NCP456R, NCP457 2 A Single Load Switch for Low Voltage Rail The NCP456R and NCP457 are power load switch with very low Ron NMOSFET controlled by external logic pin, allowing optimization of battery life, and portable device autonomy. Indeed, thanks to a best in class current consumption optimization with NMOS structure, leakage currents are drastically decreased. Offering optimized leakages isolation on the ICs connected on the battery. Output discharge path is proposed, in the NCP457 version , to eliminate residual voltages on the external components connected on output pin. Reverse voltage protection, from OUT to IN is offered in the NCP456R version. Proposed in wide input voltage range from 0.75 V to 5.5 V, and a very small CSP6 0.85 x 1.25 mm2. http://onsemi.com MARKING DIAGRAM XXAYW WLCSP6, 1.25x0.85 CASE 567GZ A Y W Features • • • • • • • • • PIN CONNECTIONS 0.75 V − 5.5 V Operating Range 24 mW N MOSFET Vbias Rail Input DC Current up to 2 A Output Auto−discharge Option Reverse Blocking Option Active High EN Pin CSP6, 0.85 x 1.25 mm2, Pitch 0.4 mm These Devices are Pb−Free and are RoHS Compliant Typical Applications • • • • • Notebooks Tablets Wireless Mobile Phones Digital Cameras Vcc = Assembly Location = Year = Work Week 1 2 A EN Gate B IN OUT C VIBAS GND Top View ORDERING INFORMATION See detailed ordering, marking and shipping information on page 12 of this data sheet. V+ LS NCP456x − NCP457 SMPS DCDC Converter B1 B2 OUT A1 A2 IN C1 Gate EN C2 Vbias GND or LDO Platform IC’n ENx EN 0 Figure 1. Typical Application Schematic © Semiconductor Components Industries, LLC, 2014 December, 2014 − Rev. 1 1 Publication Order Number: NCP456/D NCP456R, NCP457 LS NCP456x − NCP457 DCDC Converter B1 A2 C1 or LDO IN OUT Gate EN Vbias GND B2 A1 C2 Platform IC’n ENx EN 0 Figure 2. Application Schematic with Vbias Connected to IN and No Gate Delay PIN FUNCTION DESCRIPTION Pin Name Pin Number Type EN A1 INPUT IN B1 POWER Load−switch input pin. VBIAS C1 POWER External supply voltage input. GATE A2 INPUT OUT B2 POWER Load−switch output pin. GND C2 POWER Ground connection. Description Enable input, logic high turns on power switch . OUT pin slew rate control (trise). http://onsemi.com 2 NCP456R, NCP457 BLOCK DIAGRAMS IN: B1 OUT : B2 GATE : A2 Gate driver Control logic & Charge Pump EN : A1 GND : C2 VBIAS : C1 Figure 3. NCP456R Block Diagram − NCP456R Version IN: B1 OUT : B2 GATE : A2 Control logic & Charge Pump Gate driver GND : C2 VBIAS : C1 EN : A1 Figure 4. NCP457 Block Diagram − NCP457 Version http://onsemi.com 3 NCP456R, NCP457 MAXIMUM RATINGS Rating Symbol Value Unit VEN, VIN, VOUT, VBIAS, VGATE −0.3 to + 6.5 V From IN to OUT Pins: Input/Output (Note 1) NCP457 VIN, VOUT 0 to + 6.5 V From IN to OUT Pins: Input/Output (Note 1) NCP456R VIN, VOUT ±6.5 V Human Body Model (HBM) ESD Rating are (Note 2) ESD HBM 2000 V Machine Model (MM) ESD Rating are (Note 2) ESD MM 200 V Latch−up Protection (Note 3) Pins IN, OUT, EN, VBIAS and GATE LU 100 mA Maximum Junction Temperature TJ −40 to + 125 °C Storage Temperature Range TSTG −40 to + 150 °C Moisture Sensitivity (Note 4) MSL Level 1 IN, OUT, EN, VBIAS, GATE Pins: (Note 1) Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. According to JEDEC standard JESD22−A108. 2. This device series contains ESD protection and passes the following tests: Human Body Model (HBM) ±2.0 kV per JEDEC standard: JESD22−A114 for all pins. Machine Model (MM) ±250 V per JEDEC standard: JESD22−A115 for all pins. 3. Latch up Current Maximum Rating: ±100 mA per JEDEC standard: JESD78 class II. 4. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020. OPERATING CONDITIONS Symbol Parameter VIN Operational Power Supply VEN Enable Voltage Conditions Min Typ Max Unit 0.75 5.5 V 0 5.5 V Bias voltage (VBIAS ≥ best of VIN, Vout) 1.2 5.5 V TA Ambient Temperature Range −40 +85 °C CIN Decoupling input capacitor 100 nF COUT Decoupling output capacitor 100 nF RqJA Thermal Resistance Junction to Air IOUT Maximum DC current VBIAS PD 25 CSP6 (Note 5) 100 (Note 6) 0.2 °C/W 2 Power Dissipation Rating A W Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 5. The RqJA is dependent of the PCB heat dissipation and thermal via. 6. The maximum power dissipation (PD) is given by the following formula: PD + http://onsemi.com 4 T JMAX * T A R qJA NCP456R, NCP457 ELECTRICAL CHARACTERISTICS Min & Max Limits apply for TA between −40°C to +85°C for VIN and VBIAS between 0.75 V to 5.5 V (Unless otherwise noted). Typical values are referenced to TA = + 25°C, VIN = 3.3 V and VBIAS = 5 V (Unless otherwise noted). Symbol Parameter Conditions Min Typ Max Unit 24 33 mW POWER SWITCH TA = 25 °C VIN = VBIAS = 5.5 V TJ = 125°C TA = 25°C VIN = VBIAS = 3.3 V TJ = 125°C TA = 25°C VIN = VBIAS = 1.8 V RDS(on) Static drain− source on−state resistance for each rail TA = 25°C VIN = VBIAS = 1.5 V 25 26 TA = 25°C 28 TA = 25°C mW 40 42 30 TJ = 125°C VIN = 0.8 V, VBIAS = 1.2 V 35 41 TJ = 125°C VIN = 1.0 V. VBIAS = 1.2 V 34 40 TJ = 125°C TA = 25°C 33 39 TJ = 125°C VIN = VBIAS = 1.2 V RDIS 39 24 40 42 35 TJ = 125°C 45 50 Output discharge path EN = low, NCP457 220 No cap on GATE pin 0.11 Output rise time Gate capacitor = 1 nF 1.4 Gate capacitor = 10 nF 15.7 CLOAD = 1 mF, RLOAD = 25 W (Note 8) 50 ms From EN low to high to Vout = 10% of fully on− NCP456R. 10 nF gate capacitor 3 ms From EN low to high to Vout = 10% of fully on− NCP456R. 1 nF gate capacitor 300 ms From EN low to high to Vout = 10% of fully on− NCP456R. Without gate capacitor 51 ms W TIMINGS TR TF Output fall time VIN = 5 V Ten Enable time ms Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 7. Parameters are guaranteed for CLOAD and RLOAD connected to the OUT pin with respect to the ground 8. Guaranteed by design and characterization, not production tested. http://onsemi.com 5 NCP456R, NCP457 ELECTRICAL CHARACTERISTICS Min & Max Limits apply for TA between −40°C to +85°C for VIN and VBIAS between 0.75 V to 5.5 V (Unless otherwise noted). Typical values are referenced to TA = + 25°C, VIN = 3.3 V and VBIAS = 5 V (Unless otherwise noted). Symbol Parameter Conditions Min Typ Max Unit No cap on GATE pin 0.1 0.3 Output rise time Gate capacitor = 1 nF 1 Gate capacitor = 10 nF 11 Output fall time CLOAD = 1 mF, RLOAD = 25 W (Note 8) 60 From EN low to high to Vout = 10% of fully on− NCP456R. 10 nF Gate capacitor. 2.4 ms From EN low to high to Vout = 10% of fully on− NCP456R. 1 nF Gate capacitor. 230 ms From EN low to high to Vout = 10% of fully on− NCP456R. Without gate capacitor 50 No cap on GATE pin 0.06 TIMINGS TR TF VIN = 3.3 V Ten TR TF Enable time Output rise time Output fall time VIN = 1.8 V Ten TR TF Ten Enable time Output rise time Output fall time Enable time VIN = 1 V ms 120 120 ms ms Gate capacitor = 1 nF 0.6 Gate capacitor = 10 nF 6 CLOAD = 1 mF, RLOAD = 25 W (Note 8) 35 ms From EN low to high to Vout = 10% of fully on− 10 nF Gate capacitor 1.8 ms From EN low to high to Vout = 10% of fully on− 1 nF Gate capacitor 180 ms From EN low to high to Vout = 10% of fully on− NCP456R. Without gate capacitor 42 ms No cap on GATE pin 0.04 ms Gate capacitor = 1 nF 0.35 Gate capacitor = 10 nF 3.5 CLOAD = 1 mF, RLOAD = 25 W (Note 8) 20 ms From EN low to high to Vout = 10% of fully on− NCP456R. 1 nF gate capacitor 140 ms From EN low to high to Vout = 10% of fully on− NCP456R. Without gate capacitor 40 ms ms LOGIC VIH High−level input voltage VIL Low−level input voltage REN Pull down resistor 0.9 3 V 0.4 V 7 MW Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 7. Parameters are guaranteed for CLOAD and RLOAD connected to the OUT pin with respect to the ground 8. Guaranteed by design and characterization, not production tested. http://onsemi.com 6 NCP456R, NCP457 ELECTRICAL CHARACTERISTICS Min & Max Limits apply for TA between −40°C to +85°C for VIN and VBIAS between 0.75 V to 5.5 V (Unless otherwise noted). Typical values are referenced to TA = + 25°C, VIN = 3.3 V and VBIAS = 5 V (Unless otherwise noted). Symbol Parameter Conditions Min Typ Max Unit REVERSE CURRENT BLOCKING Vrev_thr Reverse threshold Vrev_hyst Reverse threshold hysteresis Trev Reverse comparator response time Vout−Vin 32 mV 50 mV Vout−Vin > Vrev_thr 2.5 ms QUIESCENT CURRENT− NCP456R IVBIAS Bias current for charge pump VBIAS = 3.3 V, EN = high 1.5 6 mA IIN IN Current consumption EN = high 0.01 0.3 mA ISTB Standby current IN EN = low, IN standby current, VIN = 3.3 V 0.01 0.3 mA ISTDVbias Standby current VBIAS VBIAS = 3.3 V EN = low 0.4 2 mA Iout_leak Output leakage current IN connected to GND, VOUT = 5 V 0.01 0.5 mA QUIESCENT CURRENT− NCP457 IVBIAS Bias current for charge pump VBIAS = 3.3 V, EN = high 1.3 5 mA IQ IN Current consumption EN = high 0.01 0.3 mA ISTB Standby current IN EN = low, IN standby current, VIN = 3.3 V 0.01 1.6 mA ISTDVbias Standby current VBIAS VBIAS = 3.3 V EN = low 0.4 2 mA Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 7. Parameters are guaranteed for CLOAD and RLOAD connected to the OUT pin with respect to the ground 8. Guaranteed by design and characterization, not production tested. http://onsemi.com 7 NCP456R, NCP457 TIMINGS Vin EN Vout TEN TR TDIS TF TON TOFF Figure 5. Enable, Rise and Fall Time http://onsemi.com 8 NCP456R, NCP457 TYPICAL CHARACTERISTICS Figure 6. RDS(on) versus Vin, Room Temperature, Vbias 5 V Figure 7. RDS(on) versus Vin, Room Temperature, Vbias Connected to Vin http://onsemi.com 9 NCP456R, NCP457 FUNCTIONAL DESCRIPTION Overview If Vbias rail is not available or used, Vbias pin and Vin pin can be connected togheter as close as possible the DUT. The NCP456R and NCP457 are high side N Channel MOSFET power distribution switch designed to isolate ICs connected on the battery or DCDC supplies in order to save energy. The part can be used with a wide range of supply from 0.75 V to 5.5 V. Output Rise Time − Gate Control Enable pin is an active high. The path is opened when EN pin is tied low (disable), forcing NMOS switch off. The IN/OUT path is activated with a minimum of VBIAS ≥ best of VIN, VOUT = 0.75 V and EN forced to high level. The NMOS is control with internal charge pump and driver. A minimum gate slew rate is internally set to avoid huge inrush current when EN is set from low to high. The default gate slew rate depends on Vin level. The higher Vin level, the longer rise time. In addition, an external capacitor can be connected between Gate pin and GND in order to slow down the gate rising. See electrical table for more details. Auto Discharge (Optional − NCP457) Cin and Cout Capacitors NMOS FET is placed between the output pin and GND, in order to discharge the application capacitor connected on OUT pin. The auto−discharge is activated when EN pin is set to low level (disable state). The discharge path ( Pull down NMOS) stays activated as long as EN pin is set at low level and VBIAS > 0.75 V. In order to limit the current across the internal discharge N−MOSFET, the typical value is set at 220 W. 100 nF external capacitors must be connected as close as possible the DUT for noise immunity and better stability. In case of input hot plug (input voltage connected with fast slew rate − few ms − it’s strongly recommended to avoid big capacitor connected on the input. That allows to avoid input over voltage transients. Enable input Reverse Blocking Control (Optional NCP456R) A reverse blocking control circuitry is embedded to eliminate leakages from OUT to IN in case of Vout>Vin. A comparator measures the dropout voltage on the switch between OUT and IN and turn off the NMOS if this voltage exceeds specified reverse voltage. This comparator is available whatever the EN pin level. VBIAS Rail The core of the IC is supplied due to VBIAS supply rail (common +5 V, 3.3 V, 1.8 V, 1.2 V ...etc). Indeed, no current consumption is used on IN pin, allowing to improve power saving of the rail that must be isolated by the power switch. APPLICATION INFORMATION Power Dissipation Demoboard Main contributor in term of junction temperature is the power dissipation of the power MOSFET. Assuming this, the power dissipation and the junction temperature in normal mode can be calculated with the following equations: The NCP456R and NCP457 integrate a 2 A rated NMOS FET, and the PCB rules must be respected to properly evacuate the heat out of the silicon. The package is a CSP and due to the low thermal resistance of the silicon, all the balls can be used to improved power dissipation. Indeed, even if the power crosses the IN / OUT pins only, all the balls around this power area should be connected to the larger PCB area. In the below PCB example (application demonstration board), all the PCB areas connected to 6 balls are enlarged. In addition vias are connected to bottom side with exactly same form factor of the other PCB side. Additional improvements can be done also by using more copper thickness and the thinner epoxy as possible. P D + R DS(on) PD RDS(on) Iout 2 (eq. 1) = Power dissipation (W) = Power MOSFET on resistance (W) = Output current (A) TJ + RD TJ RqJA TA ǒI outǓ R qJA ) T A (eq. 2) = Junction temperature (°C) = Package thermal resistance (°C/W) = Ambient temperature (°C) http://onsemi.com 10 NCP456R, NCP457 Figure 8. PCB Top View Figure 9. PCB Bottom View IN OUT NCP456x − NCP457 1 OUT_2 1 IN_2 U1 C2 C1 1μF DIODE ZENER1 C3 1nF J9 D2 DIODE ZENER1 VBIAS 1 2 Bat C4 1μF 100 k R3 EN R2 100 k Figure 10. Board Schematic http://onsemi.com 11 GND 2 GND 1μF 2 B1 B2 OUT A1 A2 IN C1 Gate EN C2 Vbias GND D1 NCP456R, NCP457 BILL OF MATERIAL Quantity Reference schem 2 IN, OUT 4 IN_2, OUT_2, VBIAS, EN 1 J9 (Bat) 3 C1, C2, C4 1 C3 1 D1, D2 2 GND2,GND 2 R2, R3 1 U1 Part description Socket, 4mm, metal, PK5 HEADER200 HEADER200-2 1uF 1nF, Not mounted TVS GND JUMPER Resistor 100k 0603 Load switch Part number B010 2.54 mm, 77313-101-06LF 2.54 mm, 77313-101-06LF GRM155R70J105KA12# GRM188R60J102ME47# ESD9x D3082F05 MC 0.063 0603 1% 100K NCP456 - 457 Manufacturer HIRSCHMANN FC FC Murata Murata ON semiconductor Harvin MULTICOMP ON semiconductor ORDERING INFORMATION Device Options Marking Package Shipping NCP456RFCCT2G Reverse Voltage Protection 56dYW WLCSP 1.25 x 0.85 mm (Pb−Free) 3000 Tape / Reel NCP457FCT2G Discharge Path 57dYW WLCSP 1.25 x 0.85 mm (Pb−Free) 3000 Tape / Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 12 NCP456R, NCP457 PACKAGE DIMENSIONS WLCSP6, 1.25x0.85 CASE 567GZ ISSUE B D PIN A1 REFERENCE 0.25 C 2X 2X ÈÈ ÈÈ 0.25 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. COPLANARITY APPLIES TO THE SPHERICAL CROWNS OF THE SOLDER BALLS. A B E DIM A A1 A2 b D E e TOP VIEW A A2 0.10 C A1 RECOMMENDED SOLDERING FOOTPRINT* 0.05 C NOTE 3 6X C SIDE VIEW 0.05 C A B SEATING PLANE PACKAGE OUTLINE 0.40 PITCH e/2 e b MILLIMETERS MIN MAX −−− 0.62 0.17 0.23 0.36 REF 0.24 0.29 1.25 BSC 0.85 BSC 0.40 BSC e A1 0.40 PITCH 1 0.03 C 2 6X 0.25 DIMENSIONS: MILLIMETERS A B C BOTTOM VIEW *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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