LINER LTC1063CJ8 Dc accurate, clock-tunable 5th order butterworth lowpass filter Datasheet

LTC1063
DC Accurate, Clock-Tunable
5th Order Butterworth
Lowpass Filter
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DESCRIPTIO
FEATURES
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Clock-Tunable Cutoff Frequency
1mV DC Offset (Typical)
80dB CMRR (Typical)
Internal or External Clock
50µVRMS Clock Feedthrough
100:1 Clock-to-Cutoff Frequency Ratio
95µVRMS Total Wideband Noise
0.01% THD at 2VRMS Output Level
50kHz Maximum Cutoff Frequency
Cascadable for Faster Roll-Off
Operates from ±2.375 to ±8V Power Supplies
Self-Clocking with 1 RC
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APPLICATI
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Audio
Strain Gauge Amplifiers
Anti-Aliasing Filters
Low Level Filtering
Digital Voltmeters
60Hz Lowpass Filters
Smoothing Filters
Reconstruction Filters
The filter cutoff frequency is controlled either by an internal or external clock. The clock-to-cutoff frequency ratio is
100:1. The on-board clock is power supply independent,
and it is programmed via an external RC. The 50µVRMS
clock feedthrough is considerably reduced over existing
monolithic filters.
The LTC1063 wideband noise is 95µVRMS, and it can
process large AC input signals with low distortion. With
±7.5V supplies, for instance, the filter handles up to
4VRMS (92dB S/N ratio) while the standard 1kHz THD is
below 0.02%; 80dB dynamic ranges (S/N +THD) is obtained with input levels between 1VRMS and 2.3VRMS.
The LTC1063 is available in 8-pin miniDIP and 16-pin SOL.
For a linear phase response, see LTC1065 data sheet.
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The LTC1063 is the first monolithic filter providing both
clock-tunability, low DC output offset and over 12-bit DC
accuracy. The frequency response of the LTC1063 closely
approximates a 5th order Butterworth polynomial. With
appropriate PCB layout techniques the output DC offset is
typically 1mV and is constant over a wide range of clock
frequencies. With ±5V supplies and ±4V input voltage
range, the CMR of the device is 80dB.
TYPICAL APPLICATI
2.5kHz 5th Order Lowpass Filter
8
2
7
3
–5V
LTC1063
0.1µF
0
VOUT
6
*19.1k
–10
5V
0.1µF
5
4
Frequency Response
10
200pF*
–20
GAIN (dB)
VIN** 1
–30
–40
–50
–60
* SELF-CLOCKING SCHEME
–70
+
** IF THE INPUT VOLTAGE CAN EXCEED V ,
CONNECT A SIGNAL DIODE BETWEEN PIN 1 AND V +.
1063 TA01
–80
–90
1
10
FREQUENCY (kHz)
100
1063 TA02
1
LTC1063
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ABSOLUTE
RATI GS
Total Supply Voltage (V + to V –) .......................... 16.5V
Power Dissipation............................................. 400mW
Voltage at Any Input .... (V – – 0.3V) ≤ VIN ≤ (V + + 0.3V)
Burn-In Voltage ...................................................... 16V
Operating Temperature Range ............... – 40°C to 85°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
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PACKAGE/ORDER I FOR ATIO
ORDER PART
NUMBER
TOP VIEW
VIN 1
8
VOS ADJ
GND 2
7
VOUT
V– 3
6
V+
CLK OUT 4
5
CLK IN
J8 PACKAGE
8-LEAD CERAMIC DIP
TOP VIEW
NC 1
16 VOS ADJ
VIN 2
15 NC
14 VOUT
GND 3
LTC1063CN8
LTC1063CJ8
LTC1063MJ8
N8 PACKAGE
8-LEAD PLASTIC DIP
V–
LTC1063CS
13 NC
NC 4
12
5
V+
NC 6
11 NC
NC 7
10 NC
9
CLK OUT 8
ORDER PART
NUMBER
CLK IN
S PACKAGE
16-LEAD PLASTIC SOL
TJMAX = 150°C, θJA = 100°C/W (J)
TJMAX = 100°C, θJA = 110°C/W (N)
TJMAX = 100°C, θJA = 85°C/W
ELECTRICAL CHARACTERISTICS
VS = ±5V, fCLK = 500kHz, fC = 5kHz, RL = 10k, TA = 25°C, unless otherwise specified.
PARAMETER
Clock-to-Cutoff Frequency Ratio (fCLK / fC)
Maximum Clock Frequency (Note 1)
Minimum Clock Frequency (Note 2)
Input Frequency Range
Filter Gain
CONDITIONS
±2.375V ≤ VS ≤ ±7.5V
VS = ±7.5V
VS = ±5V
VS = ±2.5V
±2.5V ≤ VS ≤ ±7.5V, TA < 85°C
MIN
0
VS = ±5V, fCLK = 25kHz, fC = 250Hz
fIN = 250Hz
●
VS = ±5V, fCLK = 500kHz, fC = 5kHz
fIN = 100Hz
fIN = 1kHz = 0.2fC
●
fIN = 2.5kHz = 0.5fC
●
fIN = 4kHz = 0.8fC
●
fIN = 5kHz = fC
●
fIN = 20kHz = 4fC
●
2
TYP
100 ± 0.5
5
4
3
30
MAX
UNITS
MHz
MHz
MHz
Hz
0.9fCLK
– 3.5
– 3.6
– 3.0
– 3.0
– 2.5
– 2.4
dB
dB
– 0.06
– 0.075
– 0.09
– 0.14
– 0.5
– 0.6
– 3.5
– 3.6
– 57.5
– 57.0
0
– 0.01
– 0.01
0.16
0.16
– 0.2
– 0.2
– 3.0
– 3.0
– 60.0
– 60.0
0.04
0.055
0.41
0.46
0.1
0.2
– 2.5
– 2.4
– 62.0
– 62.5
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
LTC1063
ELECTRICAL CHARACTERISTICS
VS = ±5V, fCLK = 500kHz, fC = 5kHz, RL = 10k, TA = 25°C, unless otherwise specified.
PARAMETER
Filter Gain
CONDITIONS
VS = ±2.375V, fCLK = 500kHz, fC = 5kHz
fIN = 1kHz
●
fIN = 2.5kHz
●
fIN = 4kHz
●
fIN = 5kHz
●
Clock Feedthrough
Wideband Noise (Note 3)
THD + Wideband Noise (Note 4)
Filter Output ± DC Swing
±2.375 ≤ VS ≤ ±7.5V
±2.375 ≤ VS ≤ ±7.5V, 1Hz < f < fCLK
VS = ±7.5V, fC = 20kHz, fIN = 1kHz,
1VRMS ≤ VIN ≤ 2.3VRMS
VS = ±2.375V
●
VS = ±5V
●
VS = ±7.5V
●
Input Bias Current
Dynamic Input Impedance
Output DC Offset (Note 5)
Output DC Offset Drift
Self-Clocking Frequency (fOSC)
External CLK Pin Logic Thresholds
Power Supply Current
VS = ±2.375V
VS = ±5V
VS = ±7.5V
VS = ±2.375V
VS = ±5V
VS = ±7.5V
R (Pin 4 to 5) = 20k, C (Pin 5 to GND) = 470pF
VS = ±2.375V
LTC1063CN, CS, CJ
LTC1063MJ
VS = ±5V
LTC1063CN, CS, CJ
LTC1063MJ
VS = ±7.5V
LTC1063CN, CS, CJ
LTC1063MJ
Min Logical “1”
VS = ±2.375V
Max Logical “0”
Min Logical “1”
VS = ±5V
Max Logical “0”
VS = ±7.5V
Min Logical “1”
Max Logical “0”
VS = ±2.375V, fCLK = 500kHz
LTC1063CN, CS, CJ
LTC1063MJ
VS = ±5V, fCLK = 500kHz
LTC1063CN, CS, CJ
LTC1063MJ
VS = ±7.5V, fCLK = 500kHz
LTC1063CN, CS, CJ
LTC1063MJ
MIN
TYP
MAX
– 0.066
– 0.081
– 0.24
– 0.29
– 0.6
– 0.7
– 3.5
– 3.6
0.004
0.004
0.16
0.16
– 0.2
– 0.2
– 3.0
– 3.0
50
100
–80
0.074
0.089
0.56
0.61
0.2
0.3
– 2.5
– 2.4
1.6/– 2.0
1.4/– 1.8
4.0/– 4.5
3.8/– 4.3
6.5/– 7.0
6.3/– 6.8
●
●
●
●
●
●
99
95
92
102
98
97
104
101
100
4.3/– 4.8
6.8/– 7.3
105
103
100
108
106
105
110
109
108
1.43
0.47
3
1
4.5
1.5
2.7
●
●
5.5
●
●
7.0
●
●
dB
dB
dB
dB
dB
dB
dB
dB
µVRMS
µVRMS
dB
1.7/– 2.2
10
800
2
0
–4
10
20
25
UNITS
±5
112
111
108
114
114
114
116
116
116
4.0
5.5
6.0
8
11
12
11
14.5
16.0
V
V
V
V
V
V
nA
MΩ
mV
mV
mV
µV/°C
µV/°C
µV/°C
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
3
LTC1063
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range.
Note 1: The maximum clock frequency criterion is arbitrarily defined as:
The frequency at which the filter AC response exhibits ≥ 1dB of gain
peaking.
Note 2: At limited temperature ranges (i.e., TA ≤ 50°C) the minimum clock
frequency can be as low as 10Hz. The minimum clock frequency is
arbitrarily defined as: the clock frequency at which the output DC offset
changes by more than 1mV.
Note 3: The wideband noise specification does not include the clock
feedthrough.
Note 4: To properly evaluate the filter’s harmonic distortion an inverting
output buffer is recommended as shown in the Test Circuit. An output
buffer is not necessarily needed when measuring output DC offset or
wideband noise.
Note 5: The output DC offset is optimized for ±5V supply. The output DC
offset shifts when the power supplies change; however this phenomenon
is repeatable and predictable.
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TYPICAL PERFOR A CE CHARACTERISTICS
Output Offset vs Clock,
Low Clock Rates
Self-Clocking Frequency vs R
110
Output Offset vs Clock,
Medium Clock Rates
5
50
100
45
VS = ±5V
4
40
A: TA = 25°C
B: TA = 85°C
3
VS = ±7.5V
5
4
80
R
C = 200pF
fOSC ≅ 1/RC
70
C
60
50
40
OUTPUT OFFSET (mV)
35
30
25
20
15
30
10
20
5
10
100
300
FREQUENCY (kHz)
0
500
1
–1
–2
–5
10
110
EXTERNAL CLOCK FREQUENCY (Hz)
210
10
0
0
0
–10
–10
–10
–20
–20
–50
GAIN (dB)
–40
C
A. fCLK = 0.5MHz
B. fCLK = 1MHz
C. fCLK = 2MHz
–60
A
–40
B C
D
A. fCLK = 1MHz
B. fCLK = 2MHz
C. fCLK = 3MHz
D. fCLK = 4MHz
–50
10
INPUT FREQUENCY (kHz)
100 200
1063 G04
E
A. fCLK = 1MHz
B. fCLK = 2MHz
C. fCLK = 3MHz
D. fCLK = 4MHz
E. fCLK = 5MHz
–40
–50
–70
VIN = 2.5VRMS
TA = 25°C
–80
–90
1
B C
–30
–60
VIN = 1.5VRMS
TA = 25°C
–80
–90
4
–30
–70
VIN = 750mVRMS
TA = 25°C
–80
D
A
–20
–60
–70
500
1000
EXTERNAL CLOCK FREQUENCY (kHz)
Gain vs Frequency; VS = ±7.5V
10
B
0
1063 G03
Gain vs Frequency; VS = ±5V
Gain vs Frequency; VS = ±2.5V
A
VS = ±2.5V
1063 G02
10
–30
VS = ±5V
0
–4
A
1063 G01
GAIN (dB)
2
–3
B
GAIN (dB)
R PINS 4 TO 5 (kΩ)
90
OUTPUT OFFSET (mV)
LTC1063
–90
1
10
INPUT FREQUENCY (kHz)
100 200
1063 G05
1
10
INPUT FREQUENCY (kHz)
100 200
1063 G06
LTC1063
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TYPICAL PERFOR A CE CHARACTERISTICS
THD vs Frequency;
VS = Single 5V
THD + Noise vs Input Voltage;
VS = Single 5V
1
1
1
fIN = 1kHz, TA = 25°C
5 REPRESENTATIVE UNITS
VIN = 0.75VRMS
fC = 5kHz, fCLK = 500kHz
S/N = 78dB, TA = 25°C
5 REPRESENTATIVE UNITS
THD + NOISE (%)
0.1
fIN = 1kHz, TA = 25°C
5 REPRESENTATIVE UNITS
0.1
THD (%)
THD + NOISE (%)
THD + Noise vs Input Voltage;
VS = ±5V
B
A
0.01
0.01
0.1
B
A
0.01
A. fC = 5kHz, fCLK = 0.5MHz
B. fC = 10kHz, fCLK = 1MHz
A. fC = 10kHz, fCLK = 1MHz
B. fC = 20kHz, fCLK = 2MHz
0.001
0.001
0.1
1
1
5
2
3
FREQUENCY (kHz)
INPUT (VRMS)
5
4
0.001
0.1
1
INPUT (VRMS)
1063 G08
1063 G07
1063 G09
THD + Noise vs Input Voltage;
VS = ±7.5V
THD vs Frequency; VS = ±5V
THD vs Frequency;
VS = ±7.5V
1
1
1
fIN = 1kHz, TA = 25°C
5 REPRESENTATIVE UNITS
THD (%)
0.01
VIN = 2.5VRMS
fC = 10kHz, fCLK = 1MHz
S/N = 88dB, TA = 25°C
5 REPRESENTATIVE UNITS
0.1
0.1
THD (%)
THD + NOISE (%)
VIN = 1.5VRMS
fC = 10kHz, fCLK = 1MHz
S/N = 83.5dB, TA = 25°C
5 REPRESENTATIVE UNITS
0.1
5
B
A
0.01
0.01
A. fC = 10kHz, fCLK = 1MHz
B. fC = 20kHz, fCLK = 2MHz
0.001
0.1
0.001
10
5
FREQUENCY (kHz)
0.001
1
–60
–2
PHASE
B
–100
PHASE
–140
–3
–180
–4
–5
fCLK =100kHz
fC =1kHz
–6
100
fCLK =1MHz
fC =10kHz
1k
10k
INPUT FREQUENCY (Hz)
–220
–260
100k
1063 G13
PHASE MISMATCH (±DEG)
–1
1.0
PHASE (DEG)
PASSBAND GAIN (dB)
1.1
–20
B
Power Supply Current vs
Power Supply Voltage
1.2
0
0
A
1063 G12
Phase Matching
±2.5V ≤ VS ≤ ±7.5V, TA = 25°C
0.9
10
VS = ± 7.5V
VIN = 1VRMS
fCLK = 2MHz
fC = 20kHz
–40°C
9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
8
7
25°C
6
85°C
5
4
3
2
1
0.1
0
10
5
FREQUENCY (kHz)
1063 G11
Passband Gain and Phase
vs Input Frequency
A
1
INPUT (VRMS)
1063 G10
1
5
POWER SUPPLY CURRENT (mA)
1
0 2
4
6 8 10 12 14 16 18 20 22 24
INPUT FREQUENCY (kHz)
1063 G14
0
0
2 4 6 8 10 12 14 16 18 20
TOTAL POWER SUPPLY VOLTAGE (V)
1063 G15
5
LTC1063
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TYPICAL PERFOR A CE CHARACTERISTICS
Transient Response
HORIZONTAL: 0.1ms/DIV, VERTICAL: 2V/DIV
VS = ±5V, fC = 10kHz, VIN = 1kHz ±3VP
SQUARE WAVE
1063 G16
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PI FU CTIO S
Power Supply Pins (Pins 6, 3, N Package)
The positive and negative supply pin should be bypassed
with a high quality 0.1µF ceramic capacitor. In applications
where the clock pin (5) is externally swept to provide
several cutoff frequencies, the output DC offset variation
is minimized by connecting an additional 1µF solid tantalum capacitor in parallel with the 0.1µF disc ceramic. This
technique was used to generate the graphs of the output
DC offset variation versus clock; they are illustrated in the
Typical Performance Characteristics section.
When the power supply voltage exceeds ±7V, and when V –
is applied before V +, if V+ is allowed to go below ground,
connect a signal diode between the positive supply pin and
ground to prevent latch-up (see Typical Applications).
Ground Pin (Pin 2, N Package)
The ground pin merges the internal analog and digital
ground paths. The potential of the ground pin is the
reference for the internal switched-capacitor resistors,
and the reference for the external clock. The positive input
of the internal op amp is also tied to the ground pin.
For dual supply operation, the ground pin should be
connected to a high quality AC and DC ground. A ground
plane, if possible, should be used. A poor ground will
degrade DC offset and it will increase clock feedthrough,
noise and distortion.
A small amount of AC current flows out of the ground pin
whether or not the internal oscillator is used. The fre-
6
quency of the ground current equals the frequency of the
internal or external clock. The average value of this current
is approximately 55µA, 110µA, 170µA for ±2.5V, ±5V and
±7.5V supplies respectively.
For single supply operation, the ground pin should be
preferably biased at half supply (see Typical Applications).
VOS Adjust Pin (Pin 8, N Package)
The VOS adjust pin can be used to trim any small amount
of output DC offset voltage or to introduce a desired output
DC level. The DC gain from the VOS adjust pin to the filter
output pin equals two.
Any DC voltage applied to this pin will reflect at the output
pin of the filter multiplied by two.
If the VOS adjust pin is not used, it should be shorted to the
ground pin. The DC bias current flowing into the VOS adjust
pin is typically 10pA.
Pin 8 should always be connected to an AC ground; AC
signals applied to this pin will degrade the filter response.
Input Pin (Pin 1, N Package)
Pin 1 is the filter input and it is connected to an internal
switched-capacitor resistor. If the input pin is left floating,
the filter output will saturate. The DC input impedance of
pin 1 is very high; with ±5V supplies and 1MHz clock, the
DC input impedance is typically 1GΩ. A resistor, RIN, in
series, with the input pin will not alter the value of the
LTC1063
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filter’s DC output offset (Figure 1). RIN should, however, be
limited to a maximum value (Table 1), otherwise the filter’s
passband flatness will be affected. Refer to the Applications Information section for more details.
VIN
RIN 1
8
7
2
3
V–
LTC1063
VOUT
6
V+
5 f
CLK
4
1063 F01
Figure 1.
Clock Output Pin (Pin 4, N Package)
Any external clock applied to the clock input pin appears
at the clock output pin. The duty cycle of the clock output
equals the duty cycle of the external clock applied to the
clock input pin. The clock output pin swings to the power
supply rails. When the LTC1063 is used in a self-clocking
mode, the clock of the internal oscillator appears at the
clock output pin with a 30% duty cycle. The clock output
pin can be used to drive other LTC1063s or other ICs. The
maximum capacitance, CL(MAX), the clock output pin can
drive is illustrated in Figure 3.
Table 1. RIN(MAX) vs Clock and Power Supply
200
VS = ±7.5V
VS = ±5V
VS = ±2.5V
fCLK = 4MHz
2.2k
–
–
fCLK = 3MHz
3.4k
2.9k
–
fCLK = 2MHz
fCLK = 1MHz
fCLK = 500kHz
fCLK = 100kHz
5.5k
11k
24k
120k
5k
11k
23k
120k
2.7k
9.2k
21k
110k
MAXIMUM LOAD CAPACITANCE (pF )
RIN(MAX)
Pin 7 is the filter output. This pin can typically source over
20mA and sink 2mA. Pin 7 should not drive long coax
cables, otherwise the filter’s total harmonic distortion will
degrade.
140
120
VS = ±5V
100
VS = ±7.5V
80
60
40
20
3
2
4 5 6 7 8 9 10
CLOCK FREQUENCY (MHz)
1
1063 F03
Figure 3. Maximum Load Capacitance at the Clock Output Pin
TEST CIRCUIT
Clock Input Pin (Pin 5, N Package)
An external clock when applied to pin 5 tunes the filter
cutoff frequency. The clock-to-cutoff frequency ratio is
100:1. The high (VHIGH) and low (VLOW) clock logic
threshold levels are illustrated in Table 2. Square wave
clocks with duty cycles between 30% and 50% are strongly
recommended. Sinewave clocks are not recommended.
+
Table 2. Clock Pin Threshold Levels
VIN
1
4
–
8
2
V–
VLOW
0.5V
1V
1.5V
1.6V
3V
7.2V
9V
VOUT
LT1022
3
VHIGH
1.5V
3V
4.5V
4.8V
4V
9.6V
12V
TA = 25°C
VS = ±2.5V
160
0
Output Pin (Pin 7, N Package)
POWER SUPPLY
VS = ±2.5V
VS = ±5V
VS = ±7.5V
VS = ±8V
VS = 5V, 0V
VS = 12, 0V
VS =15V, 0V
180
7
LTC1063
50k
50k
6
V+
5
0.1µF
20pF
0.1µF
CLOCK IN
1063 TC01
Figure 2. Test Circuit for THD
7
LTC1063
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APPLICATI
S I FOR ATIO
The LTC1063 features an internal oscillator which can be
tuned via an external RC. The LTC1063’s internal oscillator
is primarily intended for generation of clock frequencies
below 500kHz. The first curve of the Typical Performance
Characteristics section shows how to quickly choose the
value of the RC for a given frequency. More precisely, the
frequency of the internal oscillator is equal to:
fCLK = K/RC
For clock frequencies (fCLK) below 100kHz, K equals 1.07.
Figure 4b shows the variation of the parameter K versus
clock frequency and power supply. First choose the desired clock frequency, (fCLK < 500kHz), then through
Figure 4b pick the right value of K, set C = 200pF and solve
for R.
Note a 4pF parasitic capacitance is assumed in parallel
with the external 200pF timing capacitor. Figure 5 shows
the clock frequency variation from – 40°C to 85°C. The
200kHz clock of Example 1 will change by –1.75% at 85°C.
4
C = 200pF
3
fCLK CHANGE NORMALIZED
TO ITS 25°C VALUE (%)
Self-Clocking Operation
2
R = (1.0)/(200kHz × 204pF) = 24.5k.
VIN
8
1
7
2
3
V–
LTC1063
6
VOUT
V+
5
4
1
VS = ±7.5V
0
TA = 85°C
–1
VS = ±7.5V
–2
C
1063 F03a
Figure 4a.
–4
0
100
300
400
200
CLOCK FREQUENCY (kHz)
500
1063 F05
Figure 5. fCLK vs Temperature
For a very limited temperature range, the internal oscillator
of the LTC1063 can be used to generate clock frequencies
above 500kHz (Figures 6 and 7). The data of Figure 6 is
derived from several devices. For a given external (RC)
value, the observed device-to-device clock frequency variation was ±1% (VS = ±5V), and ±1.25% for VS = ±2.5V.
fCUTOFF = 20kHz, fCLK = 2MHz, VS = ±7.5V,
TA = 25°C, C = 10pF
from Figure 6, K = 0.575,
and,
R = (0.575)/(2MHz × 14pF) = 20.5k.
0.80
1.25
1.15
VS = ±5V
VS = ±2.5V
–3
Example 2:
R
1.20
VS = ±5V
VS = ±2.5V
Example 1: fCUTOFF = 2kHz, fCLK = 200kHz, VS = ±5V,
TA = 25°C, K = 1.0, C = 200pF
then,
TA = –40°C
FCLK = K/RC
C = 200pF
TA = 25°C
fCLK = K/RC
C = 10pF
TA = 25°C
0.75
0.70
1.10
0.65
1.00
VS = ±7.5V
K
K
1.05
0.95
0.50
VS = ±2.5V
VS = ±2.5V
0.45
0.80
0.75
VS = ±5V
0.55
0.90
0.85
VS = ±7.5V
0.60
VS = ±5V
400
100
300
500
200
INTERNAL CLOCK FREQUENCY (kHz)
0.40
0.5
1.0
2.0
2.5
1.5
CLOCK FREQUENCY (MHz)
1063 F04b
Figure 4b. fCLK vs K
8
3.0
1063 F05
Figure 6. fCLK vs K
LTC1063
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0.80
Common-Mode Rejection Ratio
fCLK = K/RC
C = 10pF
TA = 70°C
0.75
0.70
The common-mode rejection ratio is defined as the change
of the output DC offset with respect to the DC change of the
input voltage applied to the filter.
K
0.65
0.60
CMRR = 20log (∆VOS OUT /∆VIN)(dB)
VS = ±7.5V
0.55
VS = ±5V
0.50
0.45
0.40
0.5
VS = ±2.5V
1.0
2.0
2.5
1.5
CLOCK FREQUENCY (MHz)
3.0
Table 3 illustrates the common-mode rejection for three
power supplies and three temperatures. The commonmode rejection improves if the output offset is adjusted to
approximately 0V. The output offset can be adjusted via
pin 8 (N package) (see Typical Applications).
1063 F06
Figure 7. fCLK vs K
A 4pF parasitic capacitance is assumed in parallel with the
external 10pF capacitor. A ±1% clock frequency variation
from device to device can be expected. The 2MHz clock
frequency designed above will typically drift to 1.74MHz at
70°C (Figure 7).
The internal clock of the LTC1063 can be overridden by an
external clock provided that the external clock source can
drive the timing capacitor, C, which is connected from the
clock input pin to ground.
Output Offset
The DC output offset of the LTC1063 is trimmed to
typically less than ±1mV . The trimming is done at VS =
±5V. To obtain optimum DC offset performance, appropriate PC layout techniques should be used and the filter IC
should be soldered to the PC board. A socket will degrade
the output DC offset by typically 1mV. The output DC offset
is sensitive to the coupling of the clock output pin 4 (N
package) to the negative power supply pin 3 (N package).
The negative supply pin should be well decoupled. When
the surface mount package is used, all the unused pins
should be grounded.
When the power supplies are fixed, the output DC offset
should not change by more than ±100µV over 10Hz to
1MHz clock frequency variation. When the filter clock
frequency is fixed, the output DC offset will typically
change by – 4mV (2mV) when the power supply varies
from ±5V to ±7.5V (±2.5V). See Typical Performance
Characteristics.
Table 3. CMRR Data, fCLK = 100kHz
POWER SUPPLY
∆VIN
– 40°C
25°C
85°C
25°C
(VOS Nulled)
±2.5V
±1.8V
76dB
78dB
76dB
85dB
±5V
±4V
74dB
79dB
75dB
82dB
±7.5V
±6V
70dB
72dB
74dB
76dB
The above data is valid for clock frequencies up to 800kHz, 900kHz, 1MHz, for
VS = ±2.5V, ±5V, ±7.5V respectively.
Clock Feedthrough
Clock feedthrough is defined as the RMS value of the clock
frequency and its harmonics which are present at the
filter’s output pin. The clock feedthrough is tested with the
filter input grounded and it depends on the quality of the
PC board layout and power supply decoupling. Any parasitic switching transients, during the rise and fall of the
incoming clock, are not part of the clock feedthrough
specifications; their amplitude strongly depends on scope
probing techniques as well as ground quality and power
supply bypassing. For a power supply VS = ±5V, the clock
feedthrough of the LTC1063 is 50µVRMS; for VS = ±7.5V,
the clock feedthrough approaches 75µVRMS. Figure 8
shows a typical scope photo of the LTC1063 output pin
when the input pin is grounded. The filter cutoff frequency
was 1kHz, while scope bandwidth was chosen to be 1MHz
such as switching transients above the 100kHz clock
frequency will show.
Wideband Noise
The wideband noise of the filter is the RMS value of the
device’s output noise spectral density. The wideband
noise data is used to determine the operating signal-to-
9
LTC1063
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noise ratio at a given distortion level. The wideband noise
(µVRMS) is nearly independent of the value of the clock
frequency and excludes the clock feedthrough. The
LTC1063’s typical wideband noise is 95µVRMS. Figure 9
shows the same scope photo as Figure 8 but with a more
sensitive vertical scale: The clock feedthrough is imbedded in the filter’s wideband noise. The peak-to-peak
wideband noise of the filter can be clearly seen; it is
approximately 500µVP-P. Note that 500µVP-P equals the
95µVRMS wideband noise of the part, multiplied by a crest
factor or 5.25.
Aliasing
Aliasing is an inherent phenomenon of sampled data filters
and it primarily occurs when the frequency of an input
signal approaches the sampling frequency. For the
LTC1063, an input signal whose frequency is in the range
of fCLK ±6% will generate an alias signal into the filter’s
passband and stopband. Table 4 shows details.
LTC1063, fCLK = 20kHz, fC = 200kHz,
fIN = (19.6kHz, 100mVRMS)
fALIAS = (400Hz, 3.16mVRMS)
Example:
An input RC can be used to attenuate incoming signals
close to the filter clock frequency (Figure 10). A Butterworth
passband response will be maintained if the value of the
input resistor follows Table 1.
5mV/DIV
Table 4. Aliasing Data
INPUT FREQUENCY
2µs/DIV
fCLK = 100kHz, fC = 1kHz, VS = ±5V, 1MHz SCOPE BW
1063 F08
0.5mV/DIV
Figure 8. LTC1063 Output Clock Feedthrough + Noise
0.0005 fCLK
0.005 fCLK
0.01 fCLK
0.0125 fCLK
0.015 fCLK
0.0175 fCLK
0.02 fCLK
0.025 fCLK
0.03 fCLK
0.035 fCLK
0.04 fCLK
0.045 fCLK
0.05 fCLK
0.06 fCLK
0.07 fCLK
0.1
fCLK
R
VIN
C
2µs/DIV
fCLK = 100kHz, fC = 1kHz, VS = ±5V, 1MHz SCOPE BW
OUTPUT FREQUENCY
0.9995fCLK
0.995 fCLK
0.99 fCLK
0.9875fCLK
0.985 fCLK
0.9825fCLK
0.98 fCLK
0.975 fCLK
0.97 fCLK
0.965 fCLK
0.96 fCLK
0.955 fCLK
0.95 fCLK
0.94 fCLK
0.93 fCLK
0.9 fCLK
OUTPUT AMPLITUDE
REFERENCED TO
INPUT SIGNAL
8
1
7
2
V–
3
0.1µF
4
0 dB
0 dB
– 3 dB
– 10.2 dB
– 17.7 dB
– 24.3 dB
– 30 dB
– 40 dB
– 48 dB
– 54.5 dB
– 60.4 dB
– 65.5 dB
– 70.16 dB
– 78.25 dB
– 85.3 dB
– 100.3 dB
LTC1063
VOUT
6
V+
1063 F09
Figure 9. LTC1063 Output Clock Feedthrough + Noise
5
1
f
fCLK
≤
≤ CLK
20
2πRC
10
fCLK
0.1µF
1063 F10
Figure 10. Adding an Input Anti-Aliasing RC
10
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100
Group Delay
90
The group delay of the LTC1063 closely approximates the
delay of an ideal 5-pole Butterworth lowpass filter (Figure
11, Curve A). To linearize the group delay of the LTC1063
(Figure 11, Curve B), use an input resistor about six times
higher than the maximum value of RIN, shown in Table 1.
The passband response of the group delay corrected filter
approximates a 5-pole Bessel response while its transition band rolls off like a Butterworth.
(A) LTC1063
BUTTERWORTH
80
(ms)
70
(B) GROUP
DELAY
CORRECTED
60
50
40
30
20
0
1
2
3 4 5 6 7 8
INPUT FREQUENCY (kHz)
9
10
1063 F10
Figure 11. Group Delay
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TYPICAL APPLICATI
S
Adjusting VOS(OUT) for
±7.5 Supply Operation
Single 5V Supply Operation (fC = 3.4kHz)
7.5V
10k
5V
VIN
4.99k
1µF
TANT
+
1
8
2
7
0.1µF
LTC1063
3
4.53k
6
5
4
10k
LT1009
VOUT
VIN
5V
0.1µF
V–
–7.5V
13k
200pF
1063 TA03
1µF
TANT
1
8
2
7
3
LTC1063
VOUT
V+
7.5V
6
5
4
+
≅2.5mV
fCLK
0.1µF
0.1µF
*
* OPTIONAL, 1N4148
1063 TA07
Cascading Two LTC1063s for Steeper Roll-Off
VIN*
1
8
2
7
3
–5V
LTC1063
Sharing Clock for Multichannel Applications
VIN*
5V
3
–5V
0.1µF
C
LTC1063
8
2
7
3
–5V
4
LTC1063
5V
0.1µF
0.1µF
R
1
VOUT
6
5
4
0.1µF
R
7
2
6
5
4
8
1
VIN*
VOUT
6
3
0.1µF
fC ≅ (1/RC)(1/100)
WIDEBAND NOISE = 140µVRMS
ATTENUATION AT f = 2fC = 60dB
* IF THE INPUT VOLTAGE CAN EXCEED V +,
CONNECT A SIGNAL DIODE BETWEEN PIN 1 AND V +.
7
2
5
0.1µF
8
1
5V
–5V
C
LTC1063
4
VOUT
6
0.1µF
1063 TA04
* IF THE INPUT VOLTAGE CAN EXCEED V +,
CONNECT A SIGNAL DIODE BETWEEN PIN 1 AND V +.
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
5V
5
0.1µF
1063 TA05
11
LTC1063
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S
Low Noise DC Accurate Clock-Tunable Notch
R1
10k ± 0.1%
1
8
2
7
3
–5V
1µF
TANT
LTC1063
0
fCLK
0.1µF
• fNOTCH =
LT1007
+
V+
5V
6
5
4
+
–
R2
9.53k ±0.1%
0.1µF
–10
GAIN (dB)
VIN
fCLK
119.04
81Hz
–20
–30
–40
–50
• NOTCH DEPTH > 50dB
(LTC1063)VOS
• OUPUT DC OFFSET =
≅ 500µV
2
• OUTPUT NOISE = 50µVRMS
fNOTCH
10.4
=
•
f(–20dB)BW
1
fCLK = 100kHz
fn = 840Hz
–60
–70
215
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PACKAGE DESCRIPTIO
340
465
590
715
840
965 1090
INPUT FREQUENCY (Hz)
J8 Package, 8-Lead Ceramic DIP 0.200
(5.080)
MAX
0.008 – 0.018
(0.203 – 0.457)
0.015 – 0.060
(0.381 – 1.524)
0.023 – 0.045
(0.584 – 1.143)
HALF LEAD
OPTION
0.045 – 0.068
(1.143 – 1.727)
FULL LEAD
OPTION
0° – 15°
1063 TA06
0.405
(10.287)
MAX
0.005
(0.127)
MIN
8
6
7
5
0.025
(0.635)
RAD TYP
0.045 – 0.068
(1.143 – 1.727)
0.014 – 0.026
(0.360 – 0.660)
0.385 ± 0.025
(9.779 ± 0.635)
1340 1465
Dimensions in inches (millimeters) unless otherwise noted.
CORNER LEADS OPTION
(4 PLCS)
0.290 – 0.320
(7.366 – 8.128)
1215
0.220 – 0.310
(5.588 – 7.874)
0.125
3.175
0.100 ± 0.010 MIN
(2.540 ± 0.254)
1
2
3
4
NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP OR TIN PLATE LEADS.
N8 Package, 8-Lead Plastic DIP
0.300 – 0.320
(7.620 – 8.128)
0.045 – 0.065
(1.143 – 1.651)
(
+0.025
0.325 –0.015
+0.635
–0.381
8
6
5
0.250 ± 0.010
(6.350 ± 0.254)
0.125
(3.175)
MIN
0.045 ± 0.015
(1.143 ± 0.381)
)
0.100 ± 0.010
(2.540 ± 0.254)
0.020
(0.508)
MIN
1
16
0.093 – 0.104
(2.362 – 2.642)
4
3
0.398 – 0.413
(10.109 – 10.490)
S Package, 16-Lead SOL
0.010 – 0.029 × 45°
(0.254 – 0.737)
2
0.018 ± 0.003
(0.457 ± 0.076)
0.291 – 0.299
(7.391 – 7.595)
0.005
(0.127)
RAD MIN
7
0.065
(1.651)
TYP
0.009 – 0.015
(0.229 – 0.381)
8.255
0.400
(10.160)
MAX
0.130 ± 0.005
(3.302 ± 0.127)
15
14
13
12
11 10
9
0.037 – 0.045
(0.940 – 1.143)
0° – 8° TYP
SEE
NOTE
0.009 – 0.013
(0.229 – 0.330)
SEE NOTE
0.016 – 0.050
(0.406 – 1.270)
0.050
(1.270)
TYP
0.014 – 0.019
(0.356 – 0.482)
TYP
NOTE:
PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS.
12
Linear Technology Corporation
0.394 – 0.419
(10.007 – 10.643)
0.004 – 0.012
(0.102 – 0.305)
1
2
3
4
5
6
7
8
LT/GP 0493 10K REV 0
1630 McCarthy Blvd., Milpitas, CA 95035-7487
(408) 432-1900 ● FAX: (408) 434-0507 ● TELEX: 499-3977
 LINEAR TECHNOLOGY CORPORATION 1993