Holtek HT56R65 Tinypowertm a/d type with lcd 8-bit otp mcu Datasheet

TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
HT56R62/HT56R65
HT56R642/HT56R644/HT56R654/HT56R656
Revision: V1.30
Date: ��
March 6, 2013
HT56R62/HT56R65
HT56R642/HT56R644/HT56R654/HT56R656
TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
Table of Contents
Features............................................................................................................. 6
General Description.......................................................................................... 7
Selection Table.................................................................................................. 7
Block Diagram................................................................................................... 8
Pin Assignment................................................................................................. 9
Pin Description................................................................................................11
Absolute Maximum Ratings........................................................................... 13
D.C. Characteristics........................................................................................ 14
A.C. Characteristics........................................................................................ 19
ADC Characteristics....................................................................................... 20
Power-on Reset Characteristics.................................................................... 20
System Architecture....................................................................................... 21
Clocking and Pipelining.......................................................................................................... 21
Program Counter.................................................................................................................... 22
Stack...................................................................................................................................... 23
Arithmetic and Logic Unit − ALU............................................................................................ 24
Program Memory............................................................................................ 25
Structure................................................................................................................................. 25
Special Vectors...................................................................................................................... 26
Look-up Table......................................................................................................................... 27
Table Program Example......................................................................................................... 28
Data Memory................................................................................................... 29
Structure................................................................................................................................. 29
General Purpose Data Memory............................................................................................. 29
Special Purpose Data Memory.............................................................................................. 30
Display Memory..................................................................................................................... 32
Special Function Registers............................................................................ 32
Indirect Addressing Registers − IAR0, IAR1.......................................................................... 32
Memory Pointers − MP0, MP1............................................................................................... 33
Bank Pointer − BP.................................................................................................................. 34
Accumulator − ACC................................................................................................................ 34
Program Counter Low Register − PCL................................................................................... 34
Look-up Table Registers − TBLP, TBLH................................................................................. 35
Status Register − STATUS..................................................................................................... 35
Interrupt Control Registers..................................................................................................... 36
Timer/Event Counter Registers.............................................................................................. 36
Input/Output Ports and Control Registers.............................................................................. 36
Pulse Width Modulator Registers........................................................................................... 36
A/D Converter Registers – ADRL, ADRH, ADCR, ACSR....................................................... 36
Rev. 1.30
2
March 6, 2013
HT56R62/HT56R65
HT56R642/HT56R644/HT56R654/HT56R656
TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
Serial Interface Registers....................................................................................................... 37
Port A Wake-up Register − PAWU......................................................................................... 37
Pull-High Resistors − PAPU, PBPU, PDPU........................................................................... 37
Register − CLKMOD.............................................................................................................. 37
LCD/LED Registers – LCDCTRL, LEDCTRL, LCDOUT1, LCDOUT2................................... 37
Miscellaneous Register − MISC............................................................................................. 37
Input/Output Ports.......................................................................................... 38
Pull-high Resistors................................................................................................................. 38
Port A Wake-up...................................................................................................................... 38
Port A Open Drain Function................................................................................................... 38
I/O Port Control Registers...................................................................................................... 39
Pin-shared Functions............................................................................................................. 39
I/O Pin Structures................................................................................................................... 40
Programming Considerations................................................................................................. 41
LCD and LED Driver....................................................................................... 42
Display Memory..................................................................................................................... 45
LCD/LED Registers................................................................................................................ 46
LCD Reset Function............................................................................................................... 49
Clock Source.......................................................................................................................... 49
LCD Driver Output.................................................................................................................. 49
LED Driver Output.................................................................................................................. 50
LCD Voltage Source and Biasing........................................................................................... 50
Programming Considerations................................................................................................. 51
Timer/Event Counters.................................................................................... 58
Configuring the Timer/Event Counter Input Clock Source..................................................... 58
Timer Registers − TMR0, TMR1, TMR1L/TMR1H, TMR2..................................................... 59
Timer Control Registers − TMR0C, TMR1C, TMR2C............................................................ 60
Configuring the Timer Mode................................................................................................... 62
Configuring the Event Counter Mode..................................................................................... 63
Configuring the Pulse Width Measurement Mode.................................................................. 64
Programmable Frequency Divider − PFD.............................................................................. 65
Prescaler................................................................................................................................ 65
I/O Interfacing......................................................................................................................... 65
Timer/Event Counter Pins Internal Filter................................................................................ 66
Programming Considerations................................................................................................. 66
Timer Program Example........................................................................................................ 67
Pulse Width Modulator................................................................................... 68
PWM Overview...................................................................................................................... 68
8+4 PWM Mode Modulation................................................................................................... 69
PWM Output Control.............................................................................................................. 69
PWM Programming Example................................................................................................. 70
Rev. 1.30
3
March 6, 2013
HT56R62/HT56R65
HT56R642/HT56R644/HT56R654/HT56R656
TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
Analog to Digital Converter........................................................................... 71
A/D Overview......................................................................................................................... 71
A/D Converter Data Registers − ADRL, ADRH...................................................................... 71
A/D Converter Control Registers − ADCR, ACSR.................................................................. 72
A/D Input Pins........................................................................................................................ 74
Initialising the A/D Converter.................................................................................................. 74
Summary of A/D Conversion Steps........................................................................................ 75
Programming Considerations................................................................................................. 76
A/D Programming Example.................................................................................................... 77
A/D Transfer Function............................................................................................................ 79
Serial Interface Function................................................................................ 80
SPI Interface.......................................................................................................................... 80
SPI Registers......................................................................................................................... 82
SPI Control Register − SIMCTL2........................................................................................... 83
SPI Communication............................................................................................................... 85
I2C Interface........................................................................................................................... 88
I2C Control Register − SIMAR................................................................................................ 90
I2C Bus Communication......................................................................................................... 91
Peripheral Clock Output................................................................................. 95
Peripheral Clock Operation.................................................................................................... 95
Buzzer.............................................................................................................. 96
Interrupts......................................................................................................... 98
Interrupt Registers.................................................................................................................. 98
Interrupt Operation............................................................................................................... 100
Interrupt Priority.................................................................................................................... 102
External Interrupt.................................................................................................................. 102
External Peripheral Interrupt................................................................................................ 103
Timer/Event Counter Interrupt.............................................................................................. 104
A/D Interrupt......................................................................................................................... 104
SPI/I2C Interface Interrupt.................................................................................................... 104
Multi-function Interrupt......................................................................................................... 105
Real Time Clock Interrupt..................................................................................................... 105
Time Base Interrupt.............................................................................................................. 106
Programming Considerations............................................................................................... 107
Reset and Initialisation................................................................................. 107
Reset Functions................................................................................................................... 108
Reset Initial Conditions.........................................................................................................110
Oscillator........................................................................................................113
System Clock Configurations................................................................................................113
System Crystal/Ceramic Oscillator........................................................................................113
External System RC Oscillator..............................................................................................114
Internal 32K_INT Oscillator...................................................................................................115
External 32768Hz Oscillator..................................................................................................115
External Oscillator.................................................................................................................116
Rev. 1.30
4
March 6, 2013
HT56R62/HT56R65
HT56R642/HT56R644/HT56R654/HT56R656
TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
System Operating Modes..............................................................................116
Clock Sources.......................................................................................................................116
Operating Modes...................................................................................................................118
Power Down Mode and Wake-up................................................................. 121
Power Down Mode............................................................................................................... 121
Entering the Power Down Mode.......................................................................................... 121
Standby Current Considerations.......................................................................................... 121
Wake-up............................................................................................................................... 122
Low Voltage Detector − LVD........................................................................ 123
LVD Operation...................................................................................................................... 123
Watchdog Timer............................................................................................ 124
Watchdog Timer Operation.................................................................................................. 124
Clearing the Watchdog Timer............................................................................................... 125
Configuration Options.................................................................................. 126
Application Circuits...................................................................................... 127
Instruction Set............................................................................................... 129
Introduction.......................................................................................................................... 129
Instruction Timing................................................................................................................. 129
Moving and Transferring Data.............................................................................................. 129
Arithmetic Operations........................................................................................................... 129
Logical and Rotate Operation.............................................................................................. 130
Branches and Control Transfer............................................................................................ 130
Bit Operations...................................................................................................................... 130
Table Read Operations........................................................................................................ 130
Other Operations.................................................................................................................. 130
Instruction Set Summary............................................................................. 131
Table Conventions................................................................................................................ 131
Instruction Definition.................................................................................... 133
Package Information.................................................................................... 142
52-pin QFP (14mm×14mm) Outline Dimensions................................................................. 142
64-pin LQFP (7mm×7mm) Outline Dimensions................................................................... 143
100-pin LQFP (14mm×14mm) Outline Dimensions............................................................. 144
Rev. 1.30
5
March 6, 2013
HT56R62/HT56R65
HT56R642/HT56R644/HT56R654/HT56R656
TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
Features
• Operating voltage:
♦♦
fSYS=32768Hz: 2.2V~5.5V
♦♦
fSYS=4MHz: 2.2V~5.5V
♦♦
fSYS=8MHz: 3.0V~5.5V
♦♦
fSYS=12MHz: 4.5V~5.5V
• Operating current:
♦♦
fSYS=1MHz at 3V, 170µA, typ.
♦♦
fSYS=32kHz at 3V, 6µA, typ.
• OTP Program Memory: 2K×14~8K×16
• RAM Data Memory: 128×8~1152×8
• 20 to 24 bidirectional I/O lines
• TinyPower technology for low power operation
• Three pin-shared external interrupts lines
• Multiple programmable Timer/Event Counters with overflow interrupt and 7-stage prescaler
• External Crystal, RC and 32768 XTAL oscillators
• Fully integrated RC 32kHz oscillator
• Externally supplied system clock option
• Watchdog Timer function
• PFD/Buzzer for audio frequency generation
• Dual Serial Interfaces: SPI and I2C
• LCD and LED driver function
• 4 operating modes: normal, slow, idle and sleep
• 6 or 8-channel 12-bit resolution A/D converter
• 3 or 4-channel 12-bit PWM outputs
• Low voltage reset function: 2.1V, 3.15V, 4.2V
• Low voltage detect function: 2.2V, 3.3V, 4.4V
• Bit manipulation instruction
• Table read instructions
• 63 powerful instructions
• Up to 0.33µs instruction cycle with 12MHz system clock at VDD=5V
• Multiple level subroutine nesting
• All instructions executed in one or two machine cycles
• Power down and wake-up functions to reduce power consumption
• Wide range of available package types
Rev. 1.30
6
March 6, 2013
HT56R62/HT56R65
HT56R642/HT56R644/HT56R654/HT56R656
TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
General Description
These TinyPowerTM A/D Type with LCD 8-bit high performance RISC architecture microcontrollers
are specifically, designed for applications that interface directly to analog signals and which require
an LCD or LED interface. The devices include an integrated multi-channel Analog to Digital
Converter, Pulse Width Modulation outputs and an LCD/LED driver.
With their fully integrated SPI and I2C functions, designers are provided with a means of easy
communication with external peripheral hardware. The benefits of integrated A/D, LCD, and
PWM functions, in addition to low power consumption, high performance, I/O flexibility and
low-cost, provides the device with the versatility for a wide range of products in the home appliance
and industrial application areas. Some of these products could include electronic metering,
environmental monitoring, handheld instruments, electronically controlled tools, motor driving in
addition to many others.
The unique Holtek TinyPower technology also gives the devices extremely low current consumption
characteristics, an extremely important consideration in the present trend for low power battery
powered applications. The usual Holtek MCU features such as power down and wake-up functions,
oscillator options, programmable frequency divider, etc. combine to ensure user applications require
a minimum of external components.
Selection Table
Most features are common to all devices, the main feature distinguishing them are Program Memory
capacity, I/O count, stack capacity and package types. The following table summarises the main
features of each device.
Program
Data
Memory Memory
Part No.
VDD
HT56R62
2.2V~5.5V
2K×14
HT56R65
2.2V~5.5V
HT56R642 2.2V~5.5V
HT56R644
Stack
Package
Types
12-bit×6 12-bit×3
6
52QFP,
64LQFP
1
12-bit×8 12-bit×4
12
52QFP,
64LQFP,
100LQFP
1
12-bit×8 12-bit×4
8
64LQFP
1
12-bit×8 12-bit×4
1
12-bit×8 12-bit×4
LCD
128×8
20
24×4 or
25×3
2
—
8K×16
576×8
24
40×4 or
41×3
2
4K×15
384×8
24
16×16 or
24×8
1
24
32×16 or
40×8
24
48×16 or
56×8
2.2V~5.5V
4K×15
576×8
8K×16
1152×8
HT56R656 2.2V~5.5V
8K×16
1152×8
HT56R654
Timer
I/O
8-bit 16-bit
1
2
2
A/D
PWM
8
12
12
100LQFP
100LQFP
Note: 1. The devices are only available in OTP versions.
2. For devices that exist in more than one package formats, the table reflects the situation for the larger
package.
Rev. 1.30
7
March 6, 2013
HT56R62/HT56R65
HT56R642/HT56R644/HT56R654/HT56R656
TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
Block Diagram

Rev. 1.30

March 6, 2013
HT56R62/HT56R65
HT56R642/HT56R644/HT56R654/HT56R656
TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
Pin Assignment

Rev. 1.30
9
March 6, 2013
HT56R62/HT56R65
HT56R642/HT56R644/HT56R654/HT56R656
TinyPowerTM A/D Type with LCD 8-Bit OTP MCU

Rev. 1.30
10
March 6, 2013
HT56R62/HT56R65
HT56R642/HT56R644/HT56R654/HT56R656
TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
Pin Description
The following table depicts the pins common to all devices.
Pin Name
I/O
PA0/BZ
PA1/BZ
PA2
PA3/PFD
I/O
PA4 or
PA4/TMR1 or
PA4/TMR2
PA5~PA7
PB0/AN0~
PB7/AN7
or
PB0/AN0~
PB5/AN5
I/O
PD0/PWM0~
PD3/PWM3
PD4/INT0
I/O
PD5/INT1
PD6/TMR0
PD7/TMR1
Configuration
Option
Description
BZ/BZ
PFD
Bidirectional 8-bit input/output port. Each individual bit on this port can be
configured as a wake-up input using the PAWU register. Software instructions
determine if the pin is a CMOS output or Schmitt trigger input. A pull-high
resistor can be connected to each pin using the PAPU register. Pins PA0, PA1
and PA3 are shared with BZ, BZ and PFD respectively, the function of which
is chosen via configuration option. Pins PA0~PA3 can also be setup as open
drain pins using the MISC register. The HT56R642 has no shared pins with
PA4. Pin PA4 is shared with TMR1 on the HT56R62 and with TMR2 on the
HT56R65, HT56R654, HT56R656 and HT56R666.
—
Bidirectional 8-bit input/output port. Software instructions determine if the
pin is a CMOS output or Schmitt trigger input. A pull-high resistor can be
connected to each pin using the PBPU register. PB is pin-shared with the
A/D input pins. The A/D inputs are selected via software instructions. Once
selected as an A/D input, the I/O function and pull-high resistor selections are
disabled automatically. HT56R62 has six PB pins, PB0/AN0~PB5/AN5 only.
—
Bidirectional 8-bit input/output port. Software instructions determine if
the pin is a CMOS output or Schmitt trigger input. A pull-high resistor can
be connected to each pin using the PDPU register. The PWM outputs,
PWM0~PWM3, are pin shared with pins PD0~PD3, the function of which is
chosen using the PWM registers. Pins PD4~PD7 are pin-shared with INT0,
INT1, TMR0 and TMR1 respectively. HT56R62 has three PWM pins and PD7
is not available.
OSC1
OSC2
OSC1, OSC2 are connected to an external RC network or external crystal,
determined by configuration option, for the internal system clock. If the RC
I Crystal or RC or system clock option is selected, pin OSC2 can be used to measure the
EC
system clock at 1/4 frequency.
O
EC is external clock mode, we can connect OSC1 pin with external clock
source directly.
OSC3
OSC4
I
O
32768Hz
OSC3 and OSC4 are connected to a 32768Hz crystal oscillator to form a
real time clock for timing purposes and for fSUB or fSL. This 32768Hz crystal is
disabled/enabled by configuration option.
VREF
I
—
A/D reference voltage input pin
RES
I
—
Schmitt Trigger reset input. Active low
VDD
—
—
Positive power supply
VSS
—
—
Negative power supply, ground
AVDD
—
—
Analog positive power supply
AVSS
—
—
Analog negative power supply, ground
Rev. 1.30
11
March 6, 2013
HT56R62/HT56R65
HT56R642/HT56R644/HT56R654/HT56R656
TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
The following tables depict the device dependent pins.
Pin Name
I/O
Configuration
Option
Description
HT56R62
VMAX
I
—
IC maximum voltage, connect to VDD, VLCD1 or V1
VLCD1/VLCD2/V1,
C1, C2
—
—
LCD Voltage pump pins for C-type biasing.
For R-type biasing only pin VLCD1 are used.
SEG0~SEG4
SEG5/SDO
SEG6/SDI/SDA
SEG7/SCK/SCL
SEG8/SCS
SEG9/PCLK
SEG10/PINT
SEG11~SEG23
O
O
I/O
I/O
I/O
O
I/O
O
SIM
PINT
COM0~COM2
COM3/SEG24
O
—
COM0~COM2 are the LCD common outputs. A bit in the LCD Control
Register determines if pin COM3/SEG24 is configured as a segment
driver or as a common output driver.
SEG0~SEG23 are LCD driver outputs for LCD panel segments.
SEG5 is pin-shared with the SPI bus data output line, SDO.
SEG6 is pin-shared with the SPI bus data input line, SDI and the I2C Bus
data line SDA.
SEG7 is pin-shared with the SPI bus clock line, SCK and the I2C Bus
clock line SCL.
SEG8 is pin-shared with the SPI bus select line, SCS.
SEG9 is pin-shared with the Peripheral Clock line, PCLK.
SEG10 is pin-shared with the Peripheral Interrupt line, PINT.
The SEG0~SEG15 lines can be can be chosen to be either segment
drivers or CMOS outputs using control bits in the LCD control registers.
HT56R65
VMAX
I
—
IC maximum voltage, connect to VDD, VLCD1 or V1
VLCD1/VLCD2/V1,
C1, C2
—
—
LCD Voltage pump pins for C-type biasing.
For R-type biasing only pin VLCD1 are used.
SEG0~SEG15
SEG16/SDO
SEG17/SDI/SDA
SEG18/SCK/SCL
SEG19/SCS
SEG20/PCLK
SEG21/PINT
SEG22~SEG39
O
O
I/O
I/O
I/O
O
I/O
O
SIM
PINT
SEG0~SEG39 are LCD driver outputs for LCD panel segments.
SEG16 is pin-shared with the SPI bus data output line, SDO.
SEG17 is pin-shared with the SPI bus data input line, SDI and the I2C Bus
data line SDA.
SEG18 is pin-shared with the SPI bus clock line, SCK and the I2C Bus
clock line SCL.
SEG19 is pin-shared with the SPI bus select line, SCS.
SEG20 is pin-shared with the Peripheral Clock line, PCLK.
SEG21 is pin-shared with the Peripheral Interrupt line, PINT.
The SEG0~SEG23 lines can be can be chosen to be either segment
drivers or CMOS outputs using control bits in the LCD control registers.
COM0~COM2
COM3/SEG40
O
—
COM0~COM2 are the LCD common outputs. A bit in the LCD Control
Register determines if pin COM3/SEG40 is configured as a segment
driver or as a common output driver.
I
—
LCD bias pin − must less than or equal to VDD
HT56R642
VLCD
SEG0~SEG9
SEG10/SDO
SEG11/SDI/SDA
SEG12/SCK/SCL
SEG13/SCS
SEG14/PCLK
SEG15/PINT
COM15/SEG16~
COM8/SEG23
O
O
I/O
I/O
I/O
O
I/O
O
SIM
PINT
COM0~COM7
O
—
Rev. 1.30
SEG0~SEG15 are LCD driver outputs for LCD panel segments.
SEG10 is pin-shared with the SPI bus data output line, SDO.
SEG11 is pin-shared with the SPI bus data input line, SDI and the I2C Bus
data line SDA.
SEG12 is pin-shared with the SPI bus clock line, SCK and the I2C Bus
clock line SCL.
SEG13 is pin-shared with the SPI bus select line, SCS.
SEG14 is pin-shared with the Peripheral Clock line, PCLK.
SEG15 is pin-shared with the Peripheral Interrupt line, PINT.
The SEG0~SEG15 lines can be can be chosen to be either segment
drivers or CMOS outputs using control bits in the LCD control registers.
COM0~COM7 are the LCD common outputs.
12
March 6, 2013
HT56R62/HT56R65
HT56R642/HT56R644/HT56R654/HT56R656
TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
Pin Name
I/O
Configuration
Option
Description
HT56R644/HT56R654
VLCD
I
—
LCD bias pin − must less than or equal to VDD
SEG0~SEG31 are LCD driver outputs for LCD panel segments.
SEG0 is pin-shared with the SPI bus data output line, SDO.
SEG1 is pin-shared with the SPI bus data input line, SDI and the I2C Bus
data line SDA.
SEG2 is pin-shared with the SPI bus clock line, SCK and the I2C Bus
clock line SCL.
SEG3 is pin-shared with the SPI bus select line, SCS.
SEG4 is pin-shared with the Peripheral Clock line, PCLK.
SEG5 is pin-shared with the Peripheral Interrupt line, PINT.
The SEG0~SEG23 lines can be can be chosen to be either segment
drivers or CMOS outputs using control bits in the LCD control registers.
SEG0/SDO
SEG1/SDI/SDA
SEG2/SCK/SCL
SEG3/SCS
SEG4/PCLK
SEG5/PINT
SEG6~SEG31
COM15/SEG32~
COM8/SEG39
O
I/O
I/O
I/O
O
I/O
O
O
SIM
PINT
COM0~COM7
O
—
COM0~COM2 are the LCD common outputs.
I
—
LCD bias pin − must less than or equal to VDD
HT56R656
VLCD
SEG0/SDO
SEG1/SDI/SDA
SEG2/SCK/SCL
SEG3/SCS
SEG4/PCLK
SEG5/PINT
SEG6~SEG47
COM15/SEG48~
COM8/SEG55
O
I/O
I/O
I/O
O
I/O
O
O
SIM
PINT
COM0~COM7
O
—
SEG0~SEG47 are LCD driver outputs for LCD panel segments.
SEG0 is pin-shared with the SPI bus data output line, SDO.
SEG1 is pin-shared with the SPI bus data input line, SDI and the I2C Bus
data line SDA.
SEG2 is pin-shared with the SPI bus clock line, SCK and the I2C Bus
clock line SCL.
SEG3 is pin-shared with the SPI bus select line, SCS.
SEG4 is pin-shared with the Peripheral Clock line, PCLK.
SEG5 is pin-shared with the Peripheral Interrupt line, PINT.
The SEG0~SEG23 lines can be can be chosen to be either segment
drivers or CMOS outputs using control bits in the LCD control registers.
COM0~COM7 are the LCD common outputs.
Note: The Pin Description tables represents the largest package type available, therefore some of the pins and
functions may not be available on smaller package types.
Absolute Maximum Ratings
Supply Voltage ................................................................................................... VSS-0.3V~VSS+6.0V
Input Voltage ......................................................................................................VSS-0.3V~VDD+0.3V
Storage Temperature .................................................................................................... -50˚C~125˚C
Operating Temperature . ................................................................................................. -40˚C~85˚C
IOL Total ..................................................................................................................................... 80mA
IOH Total ................................................................................................................................... -80mA
Total Power Dissipation ........................................................................................................ 500mW
Note: These are stress ratings only. Stresses exceeding the range specified under "Absolute
Maximum Ratings" may cause substantial damage to the device. Functional operation of
this device at other conditions beyond those listed in the specification is not implied and
prolonged exposure to extreme conditions may affect device reliability.
Rev. 1.30
13
March 6, 2013
HT56R62/HT56R65
HT56R642/HT56R644/HT56R654/HT56R656
TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
D.C. Characteristics
HT56R62/HT56R65
Ta=25°C
Symbol
VDD
Parameter
Operating Voltage
Test Conditions
Min.
Typ.
Max.
Unit
fSYS=4MHz
2.2
—
5.5
V
— fSYS=8MHz
3.0
—
5.5
V
4.5
—
5.5
V
Conditions
VDD
fSYS=12MHz
AVDD
Analog Operating Voltage
— VREF=AVDD
3.0
—
5.0
V
IDD1
Operating Current
(Crystal OSC, RC OSC)
3V
No load, fSYS=fM=1MHz
—
170
250
µA
—
380
570
µA
IDD2
Operating Current
(Crystal OSC, RC OSC)
3V
No load, fSYS=fM=2MHz
—
240
360
µA
—
490
730
µA
IDD3
Operating Current
(Crystal OSC, RC OSC)
3V
µA
IDD4
Operating Current
(EC Mode, Filter On)
3V
IDD5
Operating Current
(EC Mode, Filter Off)
3V
IDD6
Operating Current
(Crystal OSC, RC OSC)
IDD7
IDD8
IDD9
IDD10
IDD11
IDD12
IDD13
IDD14
IDD15
IDD16
Rev. 1.30
5V
5V
—
440
660
—
900
1350
µA
—
380
570
µA
—
720
1080
µA
—
370
550
µA
—
680
1020
µA
5V No load, fSYS=fM=8MHz
—
1.8
2.7
mA
Operating Current
(Crystal OSC, RC OSC)
5V No load, fSYS=fM=12MHz
—
2.6
4.0
mA
Operating Current
(Slow Mode, fM=4MHz)
(Crystal OSC, RC OSC)
3V
—
150
220
µA
—
340
510
µA
Operating Current
(Slow Mode, fM=4MHz)
(Crystal OSC, RC OSC)
3V
—
180
270
µA
—
400
600
µA
Operating Current
(Slow Mode, fM=4MHz)
(Crystal OSC, RC OSC)
3V
—
270
400
µA
—
560
840
µA
Operating Current
(Slow Mode, fM=8MHz)
(Crystal OSC, RC OSC)
3V
—
240
360
µA
—
540
810
µA
Operating Current
(Slow Mode, fM=8MHz)
(Crystal OSC, RC OSC)
3V
—
320
480
µA
—
680
1020
µA
Operating Current
(Slow Mode, fM=8MHz)
(Crystal OSC, RC OSC)
3V
—
500
750
µA
—
1000 1500
µA
Operating Current
(fSYS=32768Hz(note 1)
or 32K_INT internal RC OSC)
3V No load, WDT off, LCD on
R type, VLCD1=VDD,
5V 1/2 bias (RBIAS=400kΩ)
Operating Current
(fSYS=32768Hz(note 1)
or 32K_INT internal RC OSC)
Operating Current
(fSYS=32768Hz(note 1)
or 32K_INT internal RC OSC)
5V
5V
5V
No load, fSYS=fM=4MHz(note 5)
No load, fSYS=fM=4MHz
No load, fSYS=fM=4MHz
No load, fSYS=fSLOW=500kHz
5V
No load, fSYS=fSLOW=1MHz
5V
No load, fSYS=fSLOW=2MHz
5V
No load, fSYS=fSLOW=1MHz
5V
No load, fSYS=fSLOW=2MHz
5V
No load, fSYS=fSLOW=4MHz
5V
(note 2)
,
—
12
18
µA
—
20
30
µA
3V No load, WDT off, LCD on(note 2),
R type, VLCD1=VDD,
5V 1/3 bias (RBIAS=600kΩ)
—
10
15
µA
—
18
27
µA
3V No load, WDT off, LCD on(note 2),
5V C type, 1/3 bias, VLCD1=3V
—
8
12
µA
—
12
18
µA
14
March 6, 2013
HT56R62/HT56R65
HT56R642/HT56R644/HT56R654/HT56R656
TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
Symbol
Parameter
Test Conditions
Conditions
VDD
Min.
Typ.
Max.
Unit
Operating Current
(fSYS=32768Hz(note 1)
or 32K_INT internal RC OSC)
3V No load, WDT off, LCD on(note 2),
5V C type, 1/2 bias, VLCD1=3V
—
8
12
µA
—
12
18
µA
Operating Current
(fSYS=32768Hz(note 1)
or 32K_INT internal RC OSC)
3V
—
6
9
µA
5V
—
10
15
µA
ISTB1
Standby Current (Sleep)
(fSYS, fSUB, fS, fLCD, fWDT=off)
3V No load, system HALT,
5V WDT off
—
0.2
1.0
µA
—
0.3
2.0
µA
3V No load, system HALT,
5V WDT on
—
1
2
µA
ISTB2
Standby Current (Sleep)
(fSYS, fLCD, fWDT=fSUB=32768Hz(note 1)
or 32K_INT RC OSC)
—
3
5
µA
Standby Current (Idle)
3V No load, system HALT,
(fSYS, fWDT=off; fS(note 3)=fSUB=32768Hz(note 1)
WDT off, LCD on(note 2),
5V
or 32K_INT RC OSC)
1/2 bias, C type, VLCD1=VDD
—
1
2
µA
—
3
5
µA
Standby Current (Idle)
3V No load, system HALT,
(fSYS, fWDT=off; fS(note 3)=fSUB=32768Hz(note 1)
WDT off, LCD on(note 2),
5V 1/3 bias, C type, VLCD1=3V
or 32K_INT RC OSC)
—
1
2
µA
—
3
5
µA
—
10
15
µA
—
18
27
µA
—
10
15
µA
—
16
24
µA
—
150
250
µA
—
350
550
µA
IDD17
IDD18
ISTB3
ISTB4
ISTB5
ISTB6
No load, LCD off, WDT off
3V No load, system HALT,
Standby Current (Idle)
WDT off, LCD on(note 2),
(note 3)
(note 1)
(fSYS, fWDT=off; fS
=fSUB=32768Hz
R type, VLCD1=VDD,
or 32K_INT RC OSC)
5V 1/2 bias (RBIAS=400kΩ)
3V No load, system HALT,
Standby Current (Idle)
WDT off, LCD on(note 2),
(note 3)
(note 1)
(fSYS, fWDT=off; fS
=fSUB=32768Hz
R type, VLCD1=VDD,
or 32K_INT RC OSC)
5V 1/3 bias (RBIAS=600kΩ)
Standby Current (Idle)
(fSYS=on, fSYS=fM=4MHz, fWDT, fLCD=off,
fS(note 3)=fSUB=32768Hz(note 1)
or 32K_INT RC OSC)
3V No load, system HALT,
WDT off, LCD off,
SPI or I2C on, PCLK on,
5V PCLK=fSYS/8
VIL1
Input Low Voltage for I/O Ports,
TMR and INT
—
—
0
—
0.3VDD
V
VIH1
Input High Voltage for I/O Ports,
TMR and INT
—
—
0.7VDD
—
VDD
V
VIL2
Input Low Voltage (RES)
—
—
0
—
0.4VDD
V
VIH2
Input High Voltage (RES)
—
—
0.9VDD
—
VDD
V
— Configuration option: 2.1V
1.98
2.1
2.22
V
— Configuration option: 3.15V
2.98
3.15
3.32
V
— Configuration option: 4.2V
3.98
4.2
4.42
V
Configuration option: 2.2V
2.08
2.2
2.32
V
— Configuration option: 3.3V
3.12
3.3
3.50
V
Configuration option: 4.4V
4.12
4.4
4.70
V
6
12
—
mA
ISTB7
VLVR
VLVD
IOL1
IOH1
IOL2
IOH2
Rev. 1.30
Low Voltage Reset Voltage
Low Voltage Detector Voltage
I/O Port Sink Current
I/O Port Source Current
LCD Common and Segment Current
LCD Common and Segment Current
3V
5V
3V
5V
3V
5V
3V
5V
VOL=0.1VDD
VOH=0.9VDD
VOL=0.1VDD
VOH=0.9VDD
15
10
25
—
mA
−2
−4
—
mA
−5
−8
—
mA
210
420
—
µA
350
700
—
µA
−80
−160
—
µA
−180 −360
—
µA
March 6, 2013
HT56R62/HT56R65
HT56R642/HT56R644/HT56R654/HT56R656
TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
Symbol
Parameter
RPH
Pull-high Resistance for I/O Ports
Test Conditions
Conditions
VDD
3V
—
5V
Min.
Typ.
Max.
Unit
20
60
100
kΩ
10
30
50
kΩ
Note: 1. 32768Hz is in slow start mode (RTCC.4=1) for the D.C. current measurement.
2. LCD waveform is in Type A condition.
3. fS is the internal clock for the Buzzer, RTC Interrupt, Time Base Interrupt and the WDT.
4. Both Timer/Event Counters are off. Timer filter is disabled for all test conditions.
5. All peripherals are in OFF condition if not mentioned at IDD, ISTB tests.
HT56R642/HT56R644/HT56R654/HT56R656
Ta=25°C
Symbol
VDD
Parameter
Operating Voltage
Test Conditions
VDD
—
Min.
Typ.
Max.
Unit
fSYS=4MHz
2.2
—
5.5
V
fSYS=8MHz
3.0
—
5.5
V
fSYS=12MHz
4.5
—
5.5
V
3.0
—
5.0
V
µA
Conditions
AVDD
Analog Operating Voltage
—
VREF=AVDD
IDD1
Operating Current
(Crystal OSC, RC OSC)
3V
5V
No load, fSYS=fM=1MHz
3V
—
170
250
—
380
570
µA
—
240
360
µA
—
490
730
µA
—
440
660
µA
—
900
1350
µA
No load, fSYS=fM=4MHz
—
380
570
µA
—
720
1080
µA
No load, fSYS=fM=4MHz
—
370
550
µA
—
680
1020
µA
IDD2
Operating Current
(Crystal OSC, RC OSC)
IDD3
Operating Current
(Crystal OSC, RC OSC)
IDD4
Operating Current
(EC Mode, Filter On)
3V
IDD5
Operating Current
(EC Mode, Filter Off)
3V
IDD6
Operating Current
(Crystal OSC, RC OSC)
5V
No load, fSYS=fM=8MHz
—
1.8
2.7
mA
IDD7
Operating Current
(Crystal OSC, RC OSC)
5V
No load, fSYS=fM=12MHz
—
2.6
4.0
mA
Operating Current
(Slow Mode, fM=4MHz)
(Crystal OSC, RC OSC)
—
150
220
µA
IDD8
—
340
510
µA
—
180
270
µA
—
400
600
µA
—
270
400
µA
—
560
840
µA
—
240
360
µA
—
540
810
µA
—
320
480
µA
—
680
1020
µA
—
500
750
µA
—
1000 1500
µA
IDD9
IDD10
IDD11
IDD12
IDD13
Rev. 1.30
Operating Current
(Slow Mode, fM=4MHz)
(Crystal OSC, RC OSC)
Operating Current
(Slow Mode, fM=4MHz)
(Crystal OSC, RC OSC)
Operating Current
(Slow Mode, fM=8MHz)
(Crystal OSC, RC OSC)
Operating Current
(Slow Mode, fM=8MHz)
(Crystal OSC, RC OSC)
Operating Current
(Slow Mode, fM=8MHz)
(Crystal OSC, RC OSC)
5V
3V
5V
5V
5V
3V
No load, fSYS=fM=2MHz
No load, fSYS=fM=4MHz(note 5)
No load, fSYS=fSLOW=500kHz
5V
3V
No load, fSYS=fSLOW=1MHz
5V
3V
No load, fSYS=fSLOW=2MHz
5V
3V
No load, fSYS=fSLOW=1MHz
5V
3V
No load, fSYS=fSLOW=2MHz
5V
3V
5V
16
No load, fSYS=fSLOW=4MHz
March 6, 2013
HT56R62/HT56R65
HT56R642/HT56R644/HT56R654/HT56R656
TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
Symbol
IDD14
IDD15
IDD16
IDD17
IDD18
IDD19
IDD20
Parameter
Operating Current
(fSYS=32768Hz(note 1)
or 32K internal RC OSC)
Operating Current
(fSYS=32768Hz(note 1)
or 32K internal RC OSC)
Operating Current
(fSYS=32768Hz(note 1)
or 32K internal RC OSC)
Operating Current
(fSYS=32768Hz(note 1)
or 32K internal RC OSC)
Operating Current
(fSYS=32768Hz(note 1)
or 32K internal RC OSC)
Test Conditions
VDD
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
Operating Current
(fSYS=32768Hz(note 1)
or 32K internal RC OSC)
3V
Operating Current
(fSYS=32768Hz(note 1)
or 32K internal RC OSC)
3V
5V
3V
Standby Current (Sleep)
(fSYS, fSUB, fS, fLCD, fWDT=off)
Standby Current (Sleep)
(fSYS, fLCD, fWDT=fSUB=32768Hz(note 1)
or 32K RC OSC)
3V
ISTB2
Standby Current (Idle)
(fSYS, fWDT=off; fS(note 3)=fSUB=32768Hz(note 1)
or 32K RC OSC)
3V
ISTB4
ISTB5
ISTB6
ISTB7
ISTB8
Rev. 1.30
Standby Current (Idle)
(fSYS, fWDT=off; fS(note 3)=fSUB=32768Hz(note 1)
or 32K RC OSC)
Standby Current (Idle)
(fSYS, fWDT=off; fS(note 3)=fSUB=32768Hz(note 1)
or 32K RC OSC)
Standby Current (Idle)
(fSYS, fWDT=off; fS(note 3)=fSUB=32768Hz(note 1)
or 32K RC OSC)
Standby Current (Idle)
(fSYS, fWDT=off; fS(note 3)=fSUB=32768Hz(note 1)
or 32K RC OSC)
Standby Current (Idle)
(fSYS, fWDT=off; fS(note 3)=fSUB=32768Hz(note 1)
or 32K RC OSC)
WDT off, LCD on(note 2),
1/5 bias (RBIAS=1MΩ),
VLCD=VDD
(note 2)
WDT off, LCD on
,
1/4 bias (RBIAS=800kΩ),
VLCD=VDD
(note 2)
WDT off, LCD on
,
1/3 bias (RBIAS=600kΩ),
VLCD=VDD
(note 2)
WDT off, LCD on
,
1/5 bias (RBIAS=100kΩ),
VLCD=VDD
(note 2)
WDT off, LCD on
,
1/4 bias (RBIAS=80kΩ),
VLCD=VDD
(note 2)
WDT off, LCD on
,
1/3 bias (RBIAS=60kΩ),
VLCD=VDD
No load, LCD off, WDT off,
5V
ISTB1
ISTB3
Conditions
5V
5V
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
17
No load, system HALT,
LCD off, WDT off
No load, system HALT,
LCD off, WDT off
No load, system HALT,
WDT off, LCD on(note 2),
1/5 bias (RBIAS=1MΩ),
VLCD=VDD
No load, system HALT,
WDT off, LCD on(note 2),
1/4 bias (RBIAS=800kΩ),
VLCD=VDD
No load, system HALT,
WDT off, LCD on(note 2),
1/3 bias (RBIAS=600kΩ),
VLCD=VDD
No load, system HALT,
WDT off, LCD on(note 2),
1/5 bias (RBIAS=100kΩ),
VLCD=VDD
No load, system HALT,
WDT off, LCD on(note 2),
1/4 bias (RBIAS=80kΩ),
VLCD=VDD
No load, system HALT,
WDT off, LCD on(note 2),
1/3 bias (RBIAS=60kΩ),
VLCD=VDD
Min.
Typ.
Max.
Unit
—
8
12
µA
—
14
21
µA
—
8
12
µA
—
14
21
µA
—
10
15
µA
—
16
24
µA
—
30
45
µA
—
50
75
µA
—
40
60
µA
—
60
90
µA
—
50
75
µA
—
80
120
µA
—
6
9
µA
—
10
15
µA
—
0.2
1.0
µA
—
0.3
2.0
µA
—
1
2
µA
—
3
5
µA
—
6
10
µA
—
10
15
µA
—
6
10
µA
—
10
15
µA
—
8
12
µA
—
12
16
µA
—
26
39
µA
—
44
66
µA
—
32
48
µA
—
54
81
µA
—
44
66
µA
—
70
105
µA
March 6, 2013
HT56R62/HT56R65
HT56R642/HT56R644/HT56R654/HT56R656
TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
Symbol
Parameter
Standby Current (Idle)
(fSYS On, fSYS=fM=4MHz, fWDT, fLCD off;
fS(note 3)=fSUB=32768Hz(note 1)
or 32K RC OSC)
ISTB9
Test Conditions
VDD
3V
5V
Conditions
No load, system HALT,
LCD off, WDT off,
SPI or I2C On, PCLK On,
PCLK=fSYS/8
Min.
Typ.
Max.
Unit
—
150
250
µA
—
350
550
µA
VIL1
Input Low Voltage for I/O Ports,
TMR and INT
—
—
0
—
0.3VDD
V
VIH1
Input High Voltage for I/O Ports,
TMR and INT
—
—
0.7VDD
—
VDD
V
VIL2
Input Low Voltage (RES)
—
—
0
—
0.4VDD
V
VIH2
Input High Voltage (RES)
—
Low Voltage Reset Voltage
VLVR
Low Voltage Detector Voltage
VLVD
IOL1
IOH1
—
I/O Port Sink Current
(PA, PB, PD; SEG, COM Level or LED
Output)
3V
I/O Port Source Current
(PA, PB, PD; SEG, COM Level or LED
Output)
3V
LCD Common and Segment Current
IOL2
—
IOH2
LCD Common and Segment Current
RPH
Pull-high Resistance for I/O Ports
—
0.9VDD
—
VDD
V
Configuration option: 4.2V
3.98
4.2
4.42
V
Configuration option: 3.15V
2.98
3.15
3.32
V
Configuration option: 2.1V
1.98
2.1
2.22
V
Configuration option: 2.2V
2.08
2.2
2.32
V
Configuration option: 3.3V
3.12
3.3
3.50
V
Configuration option: 4.4V
4.12
4.4
4.70
V
6
12
—
mA
10
25
—
mA
−2
−4
—
mA
VOL=0.1VDD
5V
VOH=0.9VDD
5V
3V
VOL=0.1VDD
5V
VOL=0.1VDD
3V
VOH=0.9VDD
5V
VOH=0.9VDD
−5
−8
—
mA
210
420
—
µA
350
700
—
µA
−80
−160
—
µA
−180 −360
—
µA
3V
—
20
60
100
kΩ
5V
—
10
30
50
kΩ
Note: 1. 32768Hz is slow start mode (RTCC.4=1) in D.C. current measurement.
2. LCD waveform is in Type A condition.
3. fS is internal clock for Buzzer, RTC, Time base and WDT.
4. Timer0/1 off. Timer filter disable in all test condition.
5. All peripherals are in OFF condition if not mentioned at IDD, ISTB tests.
Rev. 1.30
18
March 6, 2013
HT56R62/HT56R65
HT56R642/HT56R644/HT56R654/HT56R656
TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
A.C. Characteristics
Ta=25°C
Symbol
Parameter
Test Conditions
Conditions
VDD
2.2V~5.5V
fSYS
System Clock
(Crystal OSC, RC OSC)
fRTCOSC
RTC Frequency
—
3.0V~5.5V
4.5V~5.5V
—
—
2.2V~5.5V
fTIMER
Timer I/P Frequency
(TMR0/TMR1)
fRC32K
32K RC Oscillator
tRES
External Reset Low Pulse Width
—
tLVR
Low Voltage Reset Time
—
tSST1
System Start-up Timer Period
—
tSST2
System Start-up Timer Period for
XTAL or RTC oscillator
tSST3
tINT
3.0V~5.5V
—
4.5V~5.5V
Min.
Typ.
Max.
Unit
32
—
4000
kHz
32
—
8000
kHz
32
—
12000 kHz
—
32768
—
Hz
0
—
4000
kHz
0
—
8000
kHz
12000 kHz
0
—
28.8
32.0
35.2
—
1
—
—
µs
—
0.1
0.4
0.6
ms
Power-on
—
1024
—
tSYS*
—
Wake-up from Power Down
Mode
—
1024
—
tSYS*
System Start-up Timer Period for
External RC or External Clock
—
Wake-up from Power Down
Mode
—
1
2
tSYS*
Interrupt Pulse Width
—
1
—
—
µs
2.2V~5.5V After Trim
—
kHz
Note: *tSYS=1/fSYS1 or 1/fSYS2
Rev. 1.30
19
March 6, 2013
HT56R62/HT56R65
HT56R642/HT56R644/HT56R654/HT56R656
TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
ADC Characteristics
HT56R62/HT56R65
Ta=25°C
Symbol
Test Conditions
Parameter
Min. Typ.
Conditions
VDD
Max.
Unit
52QFP, 64LQFP
0
—
AVDD
V
100QFP
0
—
VREF
V
—
AVDD=5V
1.6
—
AVDD+0.1
V
—
AVDD=5V, VREF=AVDD, tAD=0.5µs
−2
—
2
LSB
ADC Integral Non-Linearity
—
AVDD=5V, VREF=AVDD, tAD=0.5µs
−4
—
4
LSB
IADC
Additional Power Consumption if A/D
Converter is Used
3V
—
0.50
0.75
mA
5V
—
1.0
1.5
mA
tAD
A/D Clock Period
—
—
0.5
—
—
µs
tADC
A/D Conversion Time
—
—
—
16
—
tAD
VAD
A/D Input Voltage
—
VREF
A/D Input Reference Voltage Range
DNL
ADC Differential Non-Linearity
INL
—
HT56R642/HT56R644/HT56R654/HT56R656
Ta=25°C
Symbol
Test Conditions
Parameter
Min. Typ.
Conditions
VDD
Max.
Unit
V
128QFP
0
—
AVDD
100QFP
0
—
VREF
V
—
AVDD=5V
1.6
—
AVDD+0.1
V
ADC Differential Non-Linearity
—
AVDD=5V, VREF=AVDD, tAD=0.5µs
−2
—
2
LSB
ADC Integral Non-Linearity
—
AVDD=5V, VREF=AVDD, tAD=0.5µs
−4
—
4
LSB
—
0.50
0.75
mA
—
1.0
1.5
mA
—
0.5
—
—
µs
—
—
16
—
tAD
VAD
A/D Input Voltage
—
VREF
A/D Input Reference Voltage Range
DNL
INL
IADC
Additional Power Consumption if A/D 3V
Converter is Used
5V
—
tAD
A/D Clock Period
—
tADC
A/D Conversion Time
—
Power-on Reset Characteristics
Ta=25°C
Symbol
Test Conditions
Parameter
Conditions
—
—
—
0.035
1
VPOR
VDD Start Voltage to Ensure Power-on Reset
—
RPOR
VDD Rise Slew Rate to Ensure Power-on Reset
—
tPOR
Minimum Time to Ensure Power-on Reset
—
VPOR=0.1V
Typ. Max. Unit
—
100
mV
—
—
V/ms
—
—
ms
Rev. 1.30
Min.
VDD
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HT56R62/HT56R65
HT56R642/HT56R644/HT56R654/HT56R656
TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
System Architecture
A key factor in the high-performance features of the Holtek range of microcontrollers is attributed
to their internal system architecture. The range of devices take advantage of the usual features found
within RISC microcontrollers providing increased speed of operation and enhanced performance.
The pipelining scheme is implemented in such a way that instruction fetching and instruction
execution are overlapped, hence instructions are effectively executed in one cycle, with the
exception of branch or call instructions. An 8-bit wide ALU is used in practically all instruction set
operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement,
branch decisions, etc. The internal data path is simplified by moving data through the Accumulator
and the ALU. Certain internal registers are implemented in the Data Memory and can be directly
or indirectly addressed. The simple addressing methods of these registers along with additional
architectural features ensure that a minimum of external components is required to provide a
functional I/O and A/D control system with maximum reliability and flexibility. This makes the
device suitable for low-cost, high-volume production for controller applications.
Clocking and Pipelining
The main system clock, derived from either a Crystal/Resonator or RC oscillator is subdivided into
four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at
the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4
clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms
one instruction cycle. Although the fetching and execution of instructions takes place in consecutive
instruction cycles, the pipelining structure of the microcontroller ensures that instructions are
effectively executed in one instruction cycle. The exception to this are instructions where the
contents of the Program Counter are changed, such as subroutine calls or jumps, in which case the
instruction will take one more instruction cycle to execute.
When the RC oscillator is used, OSC2 is free for use as a T1 phase clock synchronizing pin. This T1
phase clock has a frequency of fSYS/4 with a 1:3 high/low duty cycle.

System Clocking and Pipelining
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HT56R62/HT56R65
HT56R642/HT56R644/HT56R654/HT56R656
TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
For instructions involving branches, such as jump or call instructions, two machine cycles are
required to complete instruction execution. An extra cycle is required as the program takes one
cycle to first obtain the actual jump or call address and then another cycle to actually execute the
branch. The requirement for this extra cycle should be taken into account by programmers in timing
sensitive applications.

Instruction Fetching
Program Counter
During program execution, the Program Counter is used to keep track of the address of the next
instruction to be executed. It is automatically incremented by one each time an instruction is executed
except for instructions, such as ″JMP″ or ″CALL″ that demand a jump to a non-consecutive Program
Memory address. It must be noted that only the lower 8 bits, known as the Program Counter Low
Register, are directly addressable.
When executing instructions requiring jumps to non-consecutive addresses such as a jump
instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control
by loading the required address into the Program Counter. For conditional skip instructions, once
the condition has been met, the next instruction, which has already been fetched during the present
instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is
obtained.
The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is
available for program control and is a readable and writable register. By transferring data directly into
this register, a short program jump can be executed directly, however, as only this low byte is available
for manipulation, the jumps are limited to the present page of memory, that is 256 locations. When such
program jumps are executed it should also be noted that a dummy cycle will be inserted.
The lower byte of the Program Counter is fully accessible under program control. Manipulating the
PCL might cause program branching, so an extra cycle is needed to pre-fetch. Further information
on the PCL register can be found in the Special Function Register section.
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HT56R62/HT56R65
HT56R642/HT56R644/HT56R654/HT56R656
TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
Mode
Program Counter Bits
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
Initial Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
External Interrupt 0
0
0
0
0
0
0
0
0
0
0
1
0
0
External Interrupt 1
0
0
0
0
0
0
0
0
0
1
0
0
0
Timer/Event Counter 0 Overflow
0
0
0
0
0
0
0
0
0
1
1
0
0
Timer/Event Counter 1 Overflow
0
0
0
0
0
0
0
0
1
0
0
0
0
SPI/I2C Interrupt
0
0
0
0
0
0
0
0
1
0
1
0
0
Multi-Function Interrupt
0
0
0
0
0
0
0
0
1
1
0
0
0
@0
Program Counter + 2
Skip
Loading PCL
@6
@5
@4
@3
@2
@1
Jump, Call Branch
PC12 PC11 PC10 PC9 PC8 @7
#12
#11
#10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from Subroutine
S12
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program Counter
Note: PC12~PC8: Current Program Counter bits
@7~@0: PCL bits
#12~#0: Instruction code address bits
S12~S0: Stack register bits
For the HT56R65/HT56R654/HT56R656, the Program Counter is 13 bits wide, i.e. from b12~b0.
For the HT56R642/HT56R644, the Program Counter is 12 bits wide, i.e. from b11~b0, therefore the b12
column in the table is not applicable.
For the HT56R62, the Program Counter is 11 bits wide, i.e. from b10~b0, therefore the b12 and b11 columns
in the table are not applicable.
Stack
This is a special part of the memory which is used to save the contents of the Program Counter only.
The stack has multiple levels depending upon the device and is neither part of the data nor part of
the program space, and is neither readable nor writeable. The activated level is indexed by the Stack
Pointer, SP, and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal,
the contents of the Program Counter are pushed onto the stack. At the end of a subroutine or an
interrupt routine, signaled by a return instruction, RET or RETI, the Program Counter is restored to its
previous value from the stack. After a device reset, the Stack Pointer will point to the top of the stack.
If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but
the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI,
the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use
the structure more easily. However, when the stack is full, a CALL subroutine instruction can still
be executed which will result in a stack overflow. Precautions should be taken to avoid such cases
which might cause unpredictable program branching.
Rev. 1.30
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HT56R62/HT56R65
HT56R642/HT56R644/HT56R654/HT56R656
TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
P ro g ra m
T o p o f S ta c k
S ta c k L e v e l 1
S ta c k L e v e l 2
S ta c k
P o in te r
B o tto m
C o u n te r
S ta c k L e v e l 3
o f S ta c k
P ro g ra m
M e m o ry
S ta c k L e v e l N
Note: 6 levels of stack are available for the HT56R62, 8 levels of stack are available for the
HT56R642/ HT56R644 and 12 levels of stack are available for the HT56R65/HT56R654/
HT56R656.
Arithmetic and Logic Unit − ALU
The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic
and logic operations of the instruction set. Connected to the main microcontroller data bus, the ALU
receives related instruction codes and performs the required arithmetic or logical operations after
which the result will be placed in the specified register. As these ALU calculation or operations may
result in carry, borrow or other status changes, the status register will be correspondingly updated to
reflect these changes. The ALU supports the following functions:
• Arithmetic operations: ADD, ADDM, ADC, ADCM, SUB, SUBM, SBC, SBCM, DAA
• Logic operations: AND, OR, XOR, ANDM, ORM, XORM, CPL, CPLA
• Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA, RLC
• Increment and Decrement INCA, INC, DECA, DEC
• Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA, SDZA, CALL, RET, RETI
Rev. 1.30
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HT56R62/HT56R65
HT56R642/HT56R644/HT56R654/HT56R656
TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
Program Memory
The Program Memory is the location where the user code or program is stored. For these device the
Program Memory is an OTP type, which means it can be programmed only one time. By using the
appropriate programming tools, this OTP memory device offer users the flexibility to conveniently
debug and develop their applications while also offering a means of field programming.
Structure
The Program Memory has a capacity of 2K×14 bits to 8K×16 bits. The Program Memory is
addressed by the Program Counter and also contains data, table information and interrupt entries.
Table data, which can be setup in any location within the Program Memory, is addressed by a
separate table pointer register.

Program Memory Structure
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HT56R62/HT56R65
HT56R642/HT56R644/HT56R654/HT56R656
TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
Special Vectors
Within the Program Memory, certain locations are reserved for special usage such as reset and
interrupts.
• Location 000H
This vector is reserved for use by the device reset for program initialisation. After a device reset
is initiated, the program will jump to this location and begin execution.
• Location 004H
This vector is used by the external interrupt 0. If the external interrupt pin receives an active
edge, the program will jump to this location and begin execution if the external interrupt is
enabled and the stack is not full.
• Location 008H
This vector is used by the external interrupt 1. If the external interrupt pin receives an active
edge, the program will jump to this location and begin execution if the external interrupt is
enabled and the stack is not full.
• Location 00CH
This internal vector is used by the Timer/Event Counter 0. If a Timer/Event Counter 0 overflow
occurs, the program will jump to this location and begin execution if the timer/event counter
interrupt is enabled and the stack is not full.
• Location 010H
This internal vector is used by the Timer/Event Counter 1. If a Timer/Event Counter 1 overflow
occurs, the program will jump to this location and begin execution if the timer/event counter
interrupt is enabled and the stack is not full.
• Location 014H
This internal vector is used by the SPI/I2C interrupt. When either an SPI or I2C bus, dependent
upon which one is selected, requires data transfer, the program will jump to this location and
begin execution if the SPI/I2C interrupt is enabled and the stack is not full.
• Location 018H
This internal vector is used by the Multi-function Interrupt. The Multi-function Interrupt vector is
shared by several internal functions such as a Time Base overflow, a Real Time Clock overflow,
an A/D converter conversion completion, an active edge appearing on the External Peripheral
interrupt pin or a Timer/Event Counter 2 overflow. The program will jump to this location and
begin execution if the relevant interrupt is enabled and the stack is not full.
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HT56R62/HT56R65
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TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
Look-up Table
Any location within the Program Memory can be defined as a look-up table where programmers can
store fixed data. To use the look-up table, the table pointer must first be setup by placing the lower
order address of the look up data to be retrieved in the table pointer register, TBLP. This register
defines the lower 8-bit address of the look-up table.
After setting up the table pointer, the table data can be retrieved from the current Program Memory
page or last Program Memory page using the ″TABRDC [m]″ or ″TABRDL [m]″ instructions,
respectively. When these instructions are executed, the lower order table byte from the Program
Memory will be transferred to the user defined Data Memory register [m] as specified in the
instruction. The higher order table data byte from the Program Memory will be transferred to the
TBLH special register. Any unused bits in this transferred higher order byte will be read as ″0″.
The following diagram illustrates the addressing/data flow of the look-up table:
P ro g ra m C o u n te r
H ig h B y te
P ro g ra m
M e m o ry
T B L P
T B L H
S p e c ifie d b y [m ]
T a b le C o n te n ts H ig h B y te
Instruction
T a b le C o n te n ts L o w B y te
Table Location Bits
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
TABRDC [m] PC12 PC11 PC10 PC9 PC8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
@7
@6
@5
@4
@3
@2
@1
@0
1
1
1
1
1
Table Location
Note: PC12~PC8: Current program counter bits
@7~@0: Table Pointer TBLP bits
For the HT56R65/HT56R654/HT56R656, the Table address location is 13 bits, i.e. from
b12~b0.
For the HT56R642/HT56R644, the Table address location is 12 bits, i.e. from b11~b0.
For the HT56R62, the Table address location is 11 bits, i.e. from b10~b0.
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HT56R62/HT56R65
HT56R642/HT56R644/HT56R654/HT56R656
TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
Table Program Example
The following example shows how the table pointer and table data is defined and retrieved from the
microcontroller. This example uses raw table data located in the last page which is stored there using
the ORG statement. The value at this ORG statement is ″700H″ which refers to the start address of
the last page within the 2K Program Memory of the HT56R62. The table pointer is setup here to
have an initial value of ″06H″. This will ensure that the first data read from the data table will be
at the Program Memory address ″706H″ or 6 locations after the start of the last page. Note that the
value for the table pointer is referenced to the first address of the present page if the ″TABRDC [m]″
instruction is being used. The high byte of the table data which in this case is equal to zero will be
transferred to the TBLH register automatically when the ″TABRDL [m]″ instruction is executed.
Because the TBLH register is a read-only register and cannot be restored, care should be taken
to ensure its protection if both the main routine and Interrupt Service Routine use table read
instructions. If using the table read instructions, the Interrupt Service Routines may change the
value of the TBLH and subsequently cause errors if used again by the main routine. As a rule it is
recommended that simultaneous use of the table read instructions should be avoided. However, in
situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the
execution of any main routine table-read instructions. Note that all table related instructions require
two instruction cycles to complete their operation.
tempreg1 db ?
tempreg2 db ?
:
:
mov a,06h
mov tblp,a
:
:
tabrdl tempreg1
dec tblp
tabrdl tempreg2
; temporary register #1
; temporary register #2
; initialise table pointer - note that this address is referenced
; to the last page or present page
;
;
;
;
;
;
;
transfers value in table referenced by table pointer to tempregl
data at prog. memory address ″706H″ transferred to tempreg1 and TBLH
reduce value of table pointer by one
transfers value in table referenced by table pointer to tempreg2
data at prog.memory address ″705H″ transferred to tempreg2 and TBLH
in this example the data ″1AH″ is transferred to
tempreg1 and data ″0FH″ to register tempreg2
:
:
org 700h
; sets initial address of last page
dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh
:
:
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HT56R62/HT56R65
HT56R642/HT56R644/HT56R654/HT56R656
TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
Data Memory
The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where
temporary information is stored. Divided into three sections, the first of these is an area of RAM
where special function registers are located. These registers have fixed locations and are necessary
for correct operation of the device. Many of these registers can be read from and written to directly
under program control, however, some remain protected from user manipulation. The second area of
Data Memory is reserved for general purpose use. All locations within this area are read and write
accessible under program control. The third area is reserved for the LCD Memory. This special
area of Data Memory is mapped directly to the LCD display so data written into this memory area
will directly affect the displayed data. The addresses of the LCD Memory area overlap those in
the General Purpose Data Memory area. Switching between the different Data Memory banks is
achieved by setting the Bank Pointer to the correct value.
Structure
The Data Memory is subdivided into several banks, all of which are implemented in 8-bit wide
RAM. The Data Memory located in Bank 0 is subdivided into two sections, the Special Purpose
Data Memory and the General Purpose Data Memory.
The start address of the Data Memory for all devices is the address ″00H″. Registers which are
common to all microcontrollers, such as ACC, PCL, etc., have the same Data Memory address. The
LCD Memory is mapped into Bank. Banks 2 to 6 contain only General Purpose Data Memory for
those devices with larger Data Memory capacities. As the Special Purpose Data Memory registers
are mapped into all bank areas, they can subsequently be accessed from any bank location.

Data Memory Structure
General Purpose Data Memory
All microcontroller programs require an area of read/write memory where temporary data can be
stored and retrieved for use later. It is this area of RAM memory that is known as General Purpose
Data Memory. This area of Data Memory is fully accessible by the user program for both read and
write operations. By using the ″SET [m].i″ and ″CLR [m].i″ instructions individual bits can be set
or reset under program control giving the user a large range of flexibility for bit manipulation in the
Data Memory. For devices with larger Data Memory capacities, the General Purpose Data Memory,
in addition to being located in Bank 0, is also stored in Banks 2 to 6, the actual number of banks
present depends upon the device selected.
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HT56R62/HT56R65
HT56R642/HT56R644/HT56R654/HT56R656
TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
Special Purpose Data Memory
This area of Data Memory is where registers, necessary for the correct operation of the microcontroller,
are stored. Most of the registers are both read and write type but some are protected and are read
only, the details of which are located under the relevant Special Function Register section. Note that
for locations that are unused, any read instruction to these addresses will return the value ″00H″. The
Special Function registers are mapped into all banks and can therefore be accessed from any bank
location.
Bank Number
SPDM
HT56R62–128 Bytes
GPDM
SPDM
HT56R65–576 Bytes
GPDM
SPDM
HT56R642–384 Bytes
GPDM
SPDM
HT56R644–576 Bytes
GPDM
SPDM
HT56R654–1152 Bytes
GPDM
SPDM
HT56R656–1152 Bytes
GPDM
0
1
2
Common 00H
SA
Common 3FH
EA
3
4
5
6
x
x
x
x
x
x
x
x
SA
40H
40H
40H
x
x
x
x
EA
7FH
58H
7FH
x
Common 00H
SA
Common 3FH
EA
x
x
x
x
x
x
x
x
x
SA
40H
40H
40H
40H
x
x
x
EA
FFH
68H
FFH
FFH
x
x
x
x
x
x
x
Common 00H
SA
Common 3FH
x
x
x
x
SA
EA
40H
40H
40H
x
x
x
x
EA
FFH
5FH
FFH
x
Common 00H
SA
Common 3FH
EA
x
x
x
x
x
x
x
x
x
SA
40H
40H
40H
40H
x
x
x
EA
FFH
7FH
FFH
FFH
x
x
x
SA
Common 00H
EA
Common 3FH
SA
40H
40H
40H
40H
40H
40H
40H
EA
FFH
7FH
FFH
FFH
FFH
FFH
FFH
SA
Common 00H
EA
Common 3FH
SA
40H
40H
40H
40H
40H
40H
40H
EA
FFH
9FH
FFH
FFH
FFH
FFH
FFH
Data Memory Content
Note: SPDM: Special Purpose Data Memory
GPDM: General Purpose Data Memory
SA: Start Address
EA: End Address
x: Not implemented
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HT56R62/HT56R65
HT56R642/HT56R644/HT56R654/HT56R656
TinyPowerTM A/D Type with LCD 8-Bit OTP MCU

Special Purpose Data Memory
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HT56R62/HT56R65
HT56R642/HT56R644/HT56R654/HT56R656
TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
Display Memory
The data to be displayed on the LCD or LED display is stored in an area of fully accessible Data
Memory. By writing to this area of RAM, the display output can be directly controlled by the
application program. As this Memory exists in Bank 1, but have addresses which map into the
General Purpose Data Memory, it is necessary to first ensure that the Bank Pointer is set to the value
01H before accessing the Display Memory. The Display Memory can only be accessed indirectly
using the Memory Pointer MP1 and the indirect addressing register IAR1. When the Bank Pointer
is set to Bank 1 to access the Display Memory, if any addresses with a value less than 40H are read,
the Special Purpose Memory in Bank 0 will be accessed. Also, if the Bank Pointer is set to Bank 1,
if any addresses higher than the last address in Bank 1 are read, then a value of 00H will be returned.
Special Function Registers
To ensure successful operation of the microcontroller, certain internal registers are implemented in
the Data Memory area. These registers ensure correct operation of internal functions such as timers,
interrupts, etc., as well as external functions such as I/O data control and A/D converter operation.
The location of these registers within the Data Memory begins at the address 00H. Any unused Data
Memory locations between these special function registers and the point where the General Purpose
Memory begins is reserved for future expansion purposes, attempting to read data from these
locations will return a value of 00H.
Indirect Addressing Registers − IAR0, IAR1
The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal RAM
register space, do not actually physically exist as normal registers. The method of indirect addressing
for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in
contrast to direct memory addressing, where the actual memory address is specified. Actions on the
IAR0 and IAR1 registers will result in no actual read or write operation to these registers but rather
to the memory location specified by their corresponding Memory Pointers, MP0 or MP1. Acting as a
pair, IAR0 and MP0 can together access data from Bank 0 while the IAR1 and MP1 register pair can
access data from any bank. As the Indirect Addressing Registers are not physically implemented,
reading the Indirect Addressing Registers indirectly will return a result of ″00H″ and writing to the
registers indirectly will result in no operation.
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HT56R62/HT56R65
HT56R642/HT56R644/HT56R654/HT56R656
TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
Memory Pointers − MP0, MP1
Two Memory Pointers, known as MP0 and MP1 are provided. These Memory Pointers are
physically implemented in the Data Memory and can be manipulated in the same way as normal
registers providing a convenient way with which to address and track data. When any operation to
the relevant Indirect Addressing Registers is carried out, the actual address that the microcontroller
is directed to, is the address specified by the related Memory Pointer. MP0, together with Indirect
Addressing Register, IAR0, are used to access data from Bank 0, while MP1 and IAR1 are used to
access data from all banks.
The following example shows how to clear a section of four RAM locations already defined as
locations adres1 to adres4.
data .section ′data′
adres1 db ?
adres2 db ?
Adres3 db ?
adres4 db ?
block
db ?
code .section at 0 ′code′
org 00h
start:
mov a,04h;
mov block,a
mov a,offset adres1
;
mov mp0,a
;
loop:
clr IAR0
;
inc mp0;
sdz block ;
jmp loop
continue:
setup size of block
Accumulator loaded with first RAM address
setup memory pointer with first RAM address
clear the data at address defined by MP0
increment memory pointer
check if last memory location has been cleared
The important point to note here is that in the example shown above, no reference is made to specific
RAM addresses.
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HT56R62/HT56R65
HT56R642/HT56R644/HT56R654/HT56R656
TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
Bank Pointer − BP
The Data Memory is divided several banks, the total number of which depends upon the device
chosen. Selecting the required Data Memory area is achieved using the Bank Pointer. If data in
Bank 0 is to be accessed, then the BP register must be loaded with the value 00H, while if data in
Bank 1 is to be accessed, then the BP register must be loaded with the value 01H, and so on.
The Data Memory is initialised to Bank 0 after a reset, except for the WDT time-out reset in the
Power Down Mode, in which case, the Data Memory bank remains unaffected. It should be noted
that the Special Function Data Memory is not affected by the bank selection, which means that the
Special Function Registers can be accessed from within any bank. Directly addressing the Data
Memory will always result in Bank 0 being accessed irrespective of the value of the Bank Pointer.
Accessing data from banks other than Bank 0 must be implemented using Indirect addressing.
b 7
B P 2
B P 1
b 0
B P 0
B P 2
0
0
0
0
1
1
1
1
B P 1
0
0
1
1
0
0
1
1
B P 0
0
1
0
1
0
1
0
1
B a n k
0
1
2
3
4
5
6
N o t u s e d
N o t im p le m e n te d ,w r ite " 0 " o n ly
Bank Pointer
Accumulator − ACC
The Accumulator is central to the operation of any microcontroller and is closely related with
operations carried out by the ALU. The Accumulator is the place where all intermediate results
from the ALU are stored. Without the Accumulator it would be necessary to write the result of
each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory
resulting in higher programming and timing overheads. Data transfer operations usually involve
the temporary storage function of the Accumulator; for example, when transferring data between
one user defined register and another, it is necessary to do this by passing the data through the
Accumulator as no direct transfer between two registers is permitted.
Program Counter Low Register − PCL
To provide additional program control functions, the low byte of the Program Counter is made
accessible to programmers by locating it within the Special Purpose area of the Data Memory. By
manipulating this register, direct jumps to other program locations are easily implemented. Loading
a value directly into this PCL register will cause a jump to the specified Program Memory location,
however, as the register is only 8-bit wide, only jumps within the current Program Memory page are
permitted. When such operations are used, note that a dummy cycle will be inserted.
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HT56R642/HT56R644/HT56R654/HT56R656
TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
Look-up Table Registers − TBLP, TBLH
These two special function registers are used to control operation of the look-up table which is
stored in the Program Memory. TBLP is the table pointer and indicates the location where the table
data is located. Its value must be setup before any table read commands are executed. Its value
can be changed, for example using the ″INC″ or ″DEC″ instructions, allowing for easy table data
pointing and reading. TBLH is the location where the high order byte of the table data is stored
after a table read data instruction has been executed. Note that the lower order table data byte is
transferred to a user defined location.
Status Register − STATUS
This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag
(OV), power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/logical operation
and system management flags are used to record the status and operation of the microcontroller.
With the exception of the TO and PDF flags, bits in the status register can be altered by instructions
like most other registers. Any data written into the status register will not change the TO or PDF flag.
In addition, operations related to the status register may give different results due to the different
instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or
by executing the ″CLR WDT″ or ″HALT″ instruction. The PDF flag is affected only by executing
the ″HALT″ or ″CLR WDT″ instruction or during a system power-up.
The Z, OV, AC and C flags generally reflect the status of the latest operations.
• C is set if an operation results in a carry during an addition operation or if a borrow does not take
place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through
carry instruction.
• AC is set if an operation results in a carry out of the low nibbles in addition, or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
• Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared.
• OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
• PDF is cleared by a system power-up or executing the ″CLR WDT″ instruction. PDF is set by
executing the ″HALT″ instruction.
• TO is cleared by a system power-up or executing the ″CLR WDT″ or ″HALT″ instruction. TO is
set by a WDT time-out.

Status Register
In addition, on entering an interrupt sequence or executing a subroutine call, the status register will
not be pushed onto the stack automatically. If the contents of the status registers are important and if
the subroutine can corrupt the status register, precautions must be taken to correctly save it.
Rev. 1.30
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HT56R642/HT56R644/HT56R654/HT56R656
TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
Interrupt Control Registers
These 8-bit registers, INTC0, INTC1, MFIC, MFIC0, MFIC1 and INTEDGE, control the operation
of the device interrupt functions. By setting various bits within these registers using standard
bit manipulation instructions, the enable/disable function of each interrupt can be independently
controlled. A master interrupt bit within the INTC0 register, the EMI bit, acts like a global
enable/disable and is used to set all of the interrupt enable bits on or off. This bit is cleared when an
interrupt routine is entered to disable further interrupt and is set by executing the ″RETI″ instruction.
The INTEDGE register is used to select the active edges for the two external interrupt pins INT0
and INT1.
Timer/Event Counter Registers
The devices contain several internal 8-bit and 16-bit Timer/Event Counters, the actual amount
depends upon which device is selected. The registers TMR0, TMR1, TMR2 and the register pair
TMR1L/TMR1H are the locations where the timer values are located. These registers can also
be preloaded with fixed data to allow different time intervals to be setup. The associated control
registers, TMR0C, TMR1C and TMR2C contain the setup information for these timers, which
determines in what mode the timer is to be used as well as containing the timer on/off control
function.
Input/Output Ports and Control Registers
Within the area of Special Function Registers, the I/O registers and their associated control registers
play a prominent role. All I/O ports have a designated register correspondingly labeled as PA, PB
and PD. These labeled I/O registers are mapped to specific addresses within the Data Memory as
shown in the Data Memory table, which are used to transfer the appropriate output or input data on
that port. With each I/O port there is an associated control register labeled PAC, PBC and PDC, also
mapped to specific addresses with the Data Memory. The control register specifies which pins of that
port are set as inputs and which are set as outputs. To setup a pin as an input, the corresponding bit of
the control register must be set high, for an output it must be set low. During program initialization,
it is important to first setup the control registers to specify which pins are outputs and which are
inputs before reading data from or writing data to the I/O ports. One flexible feature of these registers
is the ability to directly program single bits using the ″SET [m].i″ and ″CLR [m].i″ instructions. The
ability to change I/O pins from output to input and vice versa by manipulating specific bits of the I/O
control registers during normal program operation is a useful feature of these devices.
Pulse Width Modulator Registers
The devices contain multiple Pulse Width Modulator outputs each with their own related independent
control register pair, known as PWM0L/PWM0H, PWM1L/PWM1H, PWM2L/PWM2H and
PWM3L/PWM3H. The 12-bit contents of each register pair, which defines the duty cycle value for
the modulation cycle of the Pulse Width Modulator, along with an enable bit are contained in these
register pairs.
A/D Converter Registers – ADRL, ADRH, ADCR, ACSR
The device contains a multiple channel 12-bit A/D converter. The correct operation of the A/D
requires the use of two data registers and two control registers. The two data registers, a high
byte data register known as ADRH, and a low byte data register known as ADRL, are the register
locations where the digital value is placed after the completion of an analog to digital conversion
cycle. Functions such as the A/D enable/disable, A/D channel selection and A/D clock frequency are
determined using the two control registers, ADCR and ACSR.
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HT56R642/HT56R644/HT56R654/HT56R656
TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
Serial Interface Registers
The device contains two serial interfaces, an SPI and an I2C interface. The SIMCTL0, SIMCTL1,
SIMCTL2 and SIMAR are the control registers for the Serial Interface function while the SIMDR is
the data register for the Serial Interface Data.
Port A Wake-up Register − PAWU
All pins on Port A have a wake-up function enable a low going edge on these pins to wake-up
the device when it is in a power down mode. The pins on Port A that are used to have a wake-up
function are selected using this resister.
Pull-High Resistors − PAPU, PBPU, PDPU
All I/O pins on Ports PA, PB and PD, if setup as inputs, can be connected to an internal pull-high
resistor. The pins which require a pull-high resistor to be connected are selected using these
registers.
Register − CLKMOD
The device operates using a dual clock system whose mode is controlled using this register. The
register controls functions such as the clock source, the idle mode enable and the division ratio for
the slow clock.
LCD/LED Registers – LCDCTRL, LEDCTRL, LCDOUT1, LCDOUT2
The device contains a fully integrated LCD/LED Driver function which can be setup in various
configurations allowing it to control a wide range of external LCD and LED panels. Most of
these options are controlled using the LCDCTRL and LEDCTRL registers. As some of the LCD
segment driving pins can also be setup to be used as CMOS outputs, two registers, LCDOUT1 and
LCDOUT2, are used to select the required function.
Miscellaneous Register − MISC
The miscellaneous register is used to control two functions. The four lower bits are used for the
Watchdog Timer control, while the highest four bits are used to select open drain outputs for pins
PA0~PA3.

PA0~PA3 Open Drain Control – MISC
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HT56R642/HT56R644/HT56R654/HT56R656
TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
Input/Output Ports
Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output
designation of every pin fully under user program control, pull-high selections for all ports and
wake-up selections on certain pins, the user is provided with an I/O structure to meet the needs of a
wide range of application possibilities.
The device provides 24 bidirectional input/output lines labeled with port names PA, PB and
PD. These I/O ports are mapped to the RAM Data Memory with specific addresses as shown in
the Special Purpose Data Memory table. All of these I/O ports can be used for input and output
operations. For input operation, these ports are non-latching, which means the inputs must be ready
at the T2 rising edge of instruction ″MOV A,[m]″, where m denotes the port address. For output
operation, all the data is latched and remains unchanged until the output latch is rewritten.
Pull-high Resistors
Many product applications require pull-high resistors for their switch inputs usually requiring the
use of an external resistor. To eliminate the need for these external resistors, all I/O pins, when
configured as an input have the capability of being connected to an internal pull-high resistor. These
pull-high resistors are selected using registers PAPU, PBPU and PDPU and are implemented using
weak PMOS transistors.
Pull-High Resistor Register – PAPU, PBPU, PDPU
Port A Wake-up
The HALT instruction forces the microcontroller into a Power Down condition which preserves
power, a feature that is important for battery and other low-power applications. Various methods
exist to wake-up the microcontroller, one of which is to change the logic condition on one of the
Port A pins from high to low. After a HALT instruction forces the microcontroller into entering a
Power Down condition, the processor will remain in a low-power state until the logic condition of
the selected wake-up pin on Port A changes from high to low. This function is especially suitable
for applications that can be woken up via external switches. Each pin on Port A can be selected
individually to have this wake-up feature using the PAWU register.
Port A Open Drain Function
All I/O pins in the device have CMOS structures, however Port A pins PA0~PA3 can also be setup
as open drain structures. This is implemented using the ODE0~ODE3 bits in the MISC register.
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HT56R62/HT56R65
HT56R642/HT56R644/HT56R654/HT56R656
TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
I/O Port Control Registers
Each I/O port has its own control register known as PAC, PBC and PDC, to control the input/output
configuration. With this control register, each CMOS output or input with or without pull-high
resistor structures can be reconfigured dynamically under software control. Each pin of the I/O
ports is directly mapped to a bit in its associated port control register. For the I/O pin to function as
an input, the corresponding bit of the control register must be written as a ″1″. This will then allow
the logic state of the input pin to be directly read by instructions. When the corresponding bit of the
control register is written as a ″0″, the I/O pin will be setup as a CMOS output. If the pin is currently
setup as an output, instructions can still be used to read the output register. However, it should be
noted that the program will in fact only read the status of the output data latch and not the actual
logic status of the output pin.
Pin-shared Functions
The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more
than one function. Limited numbers of pins can force serious design constraints on designers but by
supplying pins with multi-functions, many of these difficulties can be overcome. For some pins, the
chosen function of the multi-function I/O pins is set by configuration options while for others the
function is set by application program control.
• External Interrupt Inputs
The external interrupt pins INT0, INT1 are pin-shared with the I/O pins PD4, PD5. For
applications not requiring an external interrupt input, the pin-shared external interrupt pin can
be used as a normal I/O pin, however to do this, the external interrupt enable bits in the INTC0
register must be disabled.
• External Timer Clock Input
The external timer pins TMR0, TMR1 and TMR2 are pin-shared with I/O pins. To configure
them to operate as timer inputs, the corresponding control bits in the timer control register must
be correctly set and the pin must also be setup as an input. Note that the original I/O function will
remain even if the pin is setup to be used as an external timer input.
• PFD Output
The device contains a PFD function whose single output is pin-shared with I/O pin PA3. The
output function of this pin is chosen via a configuration option and remains fixed after the device
is programmed. Note that the corresponding bit of the port control register, PAC.3, must setup the
pin as an output to enable the PFD output. If the PAC port control register has setup the pin as an
input, then the pin will function as a normal logic input with the usual pull-high selection, even if
the PFD configuration option has been selected.
• PWM Outputs
The device contains several PWM outputs shared with pins PD0~PD3. The PWM output
functions are chosen via registers. Note that the corresponding bit of the port control register,
PDC, must setup the pin as an output to enable the PWM output. If the PDC port control register
has setup the pin as an input, then the pin will function as a normal logic input with the usual
pull-high selection, even if the PWM registers have enabled the PWM function.
• A/D Inputs
The device contains a multi-channel A/D converter inputs. All of these analog inputs are
pin-shared with I/O pins on Port B. If these pins are to be used as A/D inputs and not as normal
I/O pins then the corresponding bits in the A/D Converter Control Register, ADCR, must be
properly set. There are no configuration options associated with the A/D function. If used as I/O
pins, then full pull-high resistor register remain, however if used as A/D inputs then any pull-high
resistor selections associated with these pins will be automatically disconnected.
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HT56R62/HT56R65
HT56R642/HT56R644/HT56R654/HT56R656
TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
I/O Pin Structures
The accompanying diagrams illustrate the internal structures of some I/O pin types. As the exact
logical construction of the I/O pin will differ from these drawings, they are supplied as a guide only
to assist with the functional understanding of the I/O pins. The wide range of pin-shared structures
does not permit all types to be shown.

Generic Input/Output Structure

A/D Input/Output Structure
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HT56R62/HT56R65
HT56R642/HT56R644/HT56R654/HT56R656
TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
Programming Considerations
Within the user program, one of the first things to consider is port initialisation. After a reset, all
of the I/O data and port control registers will be set high. This means that all I/O pins will default
to an input state, the level of which depends on the other connected circuitry and whether pullhigh selections have been chosen. If the port control registers, PAC, PBC and PDC, are then
programmed to setup some pins as outputs, these output pins will have an initial high output value
unless the associated port data registers, PA, PB and PD, are first programmed. Selecting which pins
are inputs and which are outputs can be achieved byte-wide by loading the correct values into the
appropriate port control register or by programming individual bits in the port control register using
the ″SET [m].i″ and ″CLR [m].i″ instructions. Note that when using these bit control instructions, a
read-modify-write operation takes place. The microcontroller must first read in the data on the entire
port, modify it to the required new bit values and then rewrite this data back to the output ports.
Read/Write Timing
Port A has the additional capability of providing wake-up functions. When the device is in the
Power Down Mode, various methods are available to wake the device up. One of these is a high to
low transition of any of the Port A pins. Single or multiple pins on Port A can be setup to have this
function.
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HT56R62/HT56R65
HT56R642/HT56R644/HT56R654/HT56R656
TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
LCD and LED Driver
For large volume applications, which incorporate an LCD in their design, the use of a custom
display rather than a more expensive character based display reduces costs significantly. However,
the corresponding COM and SEG signals required, which vary in both amplitude and time, to drive
such a custom display require many special considerations for proper LCD operation to occur.
These devices all contain an LCD Driver function, which with their internal LCD signal generating
circuitry and various options, will automatically generate these time and amplitude varying signals
to provide a means of direct driving and easy interfacing to a range of custom LCDs.
Additionally some of the devices also include LED driver circuitry which can generated the required
signals to drive the COM and SEGMENT signals for LED panels.
All device include a wide range of options to enable LCD and LED displays of various types to be
driven. The table shows the range of options available across the device range.
Part No.
HT56R62
HT56R65
HT56R642
HT56R644
HT56R654
HT56R656
Duty
Driver No.
1/2
25×2
1/3
25×3
1/4
24×4
1/2
41×2
1/3
41×3
1/4
40×4
1/8
24×8
1/16
16×16
1/8
40×8
1/16
32×16
1/8
56×8
1/16
48×16
Bias
Bias Type
Wave Type
1/2 or 1/3
C or R
A or B
1/3, 1/4 or 1/5
R
A or B
LCD Selections
Note: 1. The HT56R62 and HT56R65 52-pin packages only have R-bias type.
2. The HT56R62 and HT56R65 devices do not have an LED driver function.
Device
HT56R642
HT56R644 HT56R654
HT56R656
LED Duty
LED Driver No.
Static
24×1
1/4
24×4
1/8
24×8
1/12
16×12
1/16
16×16
Static
40×1
1/4
40×4
1/8
40×8
1/12
32×12
1/16
32×16
Static
56×1
1/4
56×4
1/8
56×8
1/12
48×12
1/16
48×16
LED Selections
Note: The HT56R62 and HT56R65 devices do not have an LED driver function.
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TinyPowerTM A/D Type with LCD 8-Bit OTP MCU

C Type Bias Voltage Levels
V
A
(= V L C D 1 )
V
R
V M A X
V L C D 1
L C D
P o w e r S u p p ly
V
A
(= V L C D 1 )
R
B
(= V L C D 1 2 /3 )
V
V M A X
V L C D 1
R
V
B
(= V L C D 1 1 /2 )
C
(= V L C D 1 1 /3 )
L C D
P o w e r S u p p ly
R
R
L C D O n /O ff
L C D
O n /O ff
R Type Bias Voltage Levels – HT56R62/HT56R65
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HT56R642/HT56R644/HT56R654/HT56R656
TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
V L C D
V
A
(= V L C D )
V
R
L C D
P o w e r S u p p ly
B
(= V L C D 2 /3 )
V
R
C
(= V L C D 1 /3 )
R
L C D O n /O ff
V L C D
V
A
(= V L C D )
V
R
L C D
P o w e r S u p p ly
V
B
V
C
(= V L C D )
B
(= V L C D 4 /5 )
V
R
(= V L C D 3 /5 )
V
R
(= V L C D 2 /5 )
R
V
R
D
(= V L C D 1 /4 )
E
L C D
P o w e r S u p p ly
R
(= V L C D 2 /4 )
D
(= V L C D 1 /5 )
R
(= V L C D 3 /4 )
C
V
A
V L C D
V
R
L C D O n /O ff
L C D
R
O n /O ff
R Type Bias Voltage Levels – HT56R642/HT56R644/HT56R654/HT56R656
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TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
Display Memory
An area of Data Memory is especially reserved for use for the LCD/LED display data. This data area
is known as the Display Memory. Any data written here will be automatically read by the internal
display driver circuits, which will in turn automatically generate the necessary LCD or LED driving
signals. Therefore any data written into this Memory will be immediately reflected into the actual
display connected to the microcontroller.
As the Display Memory addresses overlap those of the General Purpose Data Memory, it s stored in
its own independent Bank 1 area. The Data Memory Bank to be used is chosen by using the Bank
Pointer, which is a special function register in the Data Memory, with the name, BP. To access the
Display Memory therefore requires first that Bank 1 is selected by writing a value of 01H to the BP
register. After this, the memory can then be accessed by using indirect addressing through the use of
Memory Pointer MP1. With Bank 1 selected, then using MP1 to read or write to the memory area,
starting with address 40H, will result in operations to the Display Memory. Directly addressing the
Display Memory is not applicable and will result in a data access to the Bank 0 General Purpose
Data Memory.
The accompanying Display Memory Map diagrams shows how the internal Display Memory
is mapped to the Segments and Commons of the display for the largest device, which is the
HT56R656. Display Memory Maps for devices with smaller memory capacities can be extrapolated
from these diagrams.
The accompanying waveform diagram s show the generated waveforms for a range of duty and bias
types. The huge number of permutations of available for the LCD and LED waveform types does
not permit all types to be depicted.
HT56R656 Memory Map – 56×8
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HT56R642/HT56R644/HT56R654/HT56R656
TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
HT56R656 Memory Map – 48×16
LCD/LED Registers
Control Registers in the Data Memory, are used to control the various setup features of the
LCD/LED Driver. There is one control register for the LCD function, LCDCTRL, and one for
the LED function, LEDCTRL. Various bits in these registers control functions such as duty type,
bias type, bias resistor selection as well as overall LCD enable and disable. The LEDSEL bit in
the LEDCTRL register must be first setup to determine whether the display is an LED or LCD
type. Programming this bit will determine what other options are available. The LCDEN bit in
the LCDCTRL and LEDEN bit in the LEDCTRL register, which provide the overall LCD/LED
enable/disable function, will only be effective when the device is in the Normal, Slow or Idle Mode.
If the device is in the Sleep Mode then the display will always be disabled. Bits RSEL0 and RSEL1
in the LCDCTRL register select the internal bias resistors to supply the LCD panel with the correct
bias voltages. A choice to best match the LCD panel used in the application can be selected also to
minimise bias current. The TYPE bit in the same register is used to select whether Type A or Type B
LCD control signals are used.
Two registers, LCDOUT1 and LCDOUT2 are used to determine if the output function of display
pins SEG0~SEG23 are used as segment drivers or CMOS outputs. If used as CMOS outputs then
the Display Memory is used to determine the logic level of the CMOS output pins. Note that as
only two bits are used to determine the output function of the SEG0~SEG7 and SEG8~SEG15 pins,
individual pins from these two groups of pins cannot be chosen to have either a segment or CMOS
output function. The output function of pins SEG16~SEG23 can be chosen individually to be either
a segment driver or a CMOS input.
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HT56R62/HT56R65
HT56R642/HT56R644/HT56R654/HT56R656
TinyPowerTM A/D Type with LCD 8-Bit OTP MCU

LCD Control Register – LCDCTRL for HT56R62/HT56R65

LCD Control Register – LCDCTRL for HT56R642/ HT56R644/ HT56R654/ HT56R656
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TinyPowerTM A/D Type with LCD 8-Bit OTP MCU

LED Control Register – LEDCTRL
L C D O U T 1 R e g is te r - H T 5 6 R 6 2 o n ly

L C D O U T 1 R e g is te r - H T 5 6 R 6 2 e x c e p te d

LCD Output Control Register – LCDOUT1

L C D O U T 2 R e g is te r - H T 5 6 R 6 2 o n ly
L C D O U T 2 R e g is te r - H T 5 6 R 6 2 e x c e p te d
LCD Output Control Register – LCDOUT2
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TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
LCD Reset Function
The LCD has an internal reset function that is an OR function of the inverted LCDEN bit in the
LCDCTRL register and the Sleep function. The LCD reset signal is active high. The LCDEN signal
is the inverse of the LCDEN bit in the LCDCTRL register.
Reset LCD = (Sleep Mode AND LCDEN) OR LCDEN.
LCDEN=0 and LCDEN=1 must be enabled to activate the LCDCTRL register function.
LCDEN
Sleep Mode
Reset LCD
0
Off
√
0
On
√
1
Off
x
1
On
√
LCD Reset Function
Clock Source
The LCD clock source is the internal clock signal, fSUB, divided by 8, using an internal divider
circuit. The fSUB internal clock is supplied by either the internal 32K_INT oscillator or the external
32768Hz oscillator, the choice of which is determined by a configuration option. For proper LCD
operation, this arrangement is provided to generate an ideal LCD clock source frequency of 4kHz.
fSUB Clock Source
LCD Clock Frequency
Internal 32K_INT Osc.
4kHz
External 32768Hz Osc.
4kHz
LCD Clock Source
LCD Driver Output
When the LEDSEL bit in the LEDCTRL register is cleared to zero, the COM and SEG lines will be
setup as LCD driver pins to drive the LCD display.
The number of COM and SEG outputs supplied by the LCD driver, as well as its biasing and duty
selections, are dependent upon how the LCD control bits are programmed. The Bias Type, whether
C or R type is selected using a configuration option.
If the C-type of bias is used when an internal charge pump will be enabled. Note that the C-type bias
is not available on the 52-pin QFP package type.
The nature of Liquid Crystal Displays require that only AC voltages can be applied to their pixels
as the application of DC voltages to LCD pixels may cause permanent damage. For this reason
the relative contrast of an LCD display is controlled by the actual RMS voltage applied to each
pixel, which is equal to the RMS value of the voltage on the COM pin minus the voltage applied
to the SEG pin. This differential RMS voltage must be greater than the LCD saturation voltage
for the pixel to be on and less than the threshold voltage for the pixel to be off. The requirement
to limit the DC voltage to zero and to control as many pixels as possible with a minimum number
of connections, requires that both a time and amplitude signal is generated and applied to the
application LCD. These time and amplitude varying signals are automatically generated by the LCD
driver circuits in the microcontroller. What is known as the duty determines the number of common
lines used, which are also known as backplanes or COMs. The duty, which is chosen by a control
bit to have a value of 1/2, 1/3, 1/4 etc and which equates to a COM number of 2, 3, 4 etc, therefore
defines the number of time divisions within each LCD signal frame. Two types of signal generation
are also provided, known as Type A and Type B, the required type is selected via the TYPE bit in
the LCDCTRL register. Type B offers lower frequency signals, however lower frequencies may
introduce flickering and influence display clarity.
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LED Driver Output
The LED driver uses the COM and SEG lines to drive the LED display. The number of COM and
SEG outputs supplied by the LED driver, as well as its biasing and duty selections, are dependent
upon how the LED control bits are programmed.
When the LEDSEL bit in the LEDCTRL register is set high, the COM and SEG lines will be setup
as CMOS output drivers to drive the LED display. The COM and SEG lines can be set to be either
active high or active low using bits in the LEDCTRL register. This provides 4 different timing
modes. These are COM low active, SEG low active; COM low active, SEG high active; COM high
active, SEG low active; COM high active, SEG high active. The COM and SEG lines will have a
reverse polarity when in the non-active state when the display is off. For the LED driver there are
a total of 5 different duty cycle selections which are Static, 14, 18, 112 and 116. The frame rate of
each duty cycle will be between 55Hz and 75Hz.
LCD Voltage Source and Biasing
The time and amplitude varying signals generated by the LCD Driver function require the generation
of several voltage levels for their operation. The number of voltage levels used by the signal depends
upon the value of the BIAS bit in the LCDCTRL register. The device can have either R type or C type
biasing selected via a configuration option. Selecting the C type biasing will enable an internal charge
pump whose multiplier ratio can be selected using an additional configuration option.
For R type biasing an external LCD voltage source must be supplied on pin VLCD1 to generate
the internal biasing voltages. This could be the microcontroller power supply or some other voltage
source. For the R type 1/2 bias selection, three voltage levels VSS, VA and VB are utilised. The
voltage VA is equal to the externally supplied voltage source applied to pin VLCD1. VB is generated
internally by the microcontroller and will have a value equal to VLCD1/2. For the R type 1/3 bias
selection, four voltage levels VSS, VA, VB and VC are utilised. The voltage VA is equal to VLCD1, VB is
equal to VLCD1×2/3 while VC is equal to VLCD1×1/3. In addition to selecting 1/2 or 1/3 bias, several
values of bias resistor can be chosen using bits in the LCDCTRL register. Different values of
internal bias resistors can be selected using the RSEL0 and RESEL1 bits in the LCDCTRL register.
This along with the voltage on pin VLCD1 will determine the bias current. The connection to the
VMAX pin depends upon the voltage that is applied to VLCD1. If the VDD voltage is greater than
the voltage applied to the VLCD1 pin then the VMAX pin should be connected to VDD, otherwise
the VMAX pin should be connected to pin VLCD1. Note that no external capacitors or resistors are
required to be connected if R type biasing is used.
Condition
VMAX connection
VDD > VLCD1
Connect VMAX to VDD
Otherwise
Connect VMAX to VLCD1
R Type Bias Current VMAX Connection
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For C type biasing an external LCD voltage source must also be supplied on pin VLCD1 to generate
the internal biasing voltages. The C type biasing scheme uses an internal charge pump circuit, which
in the case of the 1/3 bias selection can generate voltages higher than what is supplied on VLCD1.
This feature is useful in applications where the microcontroller supply voltage is less than the supply
voltage required by the LCD. An additional charge pump capacitor must also be connected between
pins C1 and C2 to generate the necessary voltage levels.
For the C type 1/2 bias selection, three voltage levels VSS, VA and VB are utilised. The voltage VA is
generated internally and has a value of VLCD1. VB will have a value equal to VA×0.5. For the C type
1/2 bias configuration VC is not used.
For the C type 1/3 bias selection, four voltage levels VSS, VA, VB and VC are utilised. The voltage VA
is generated internally and has a value of VLCD1×1.5. VB will have a value equal to VA×2/3 and VC
will have a value equal to VA×1/3. The connection to the VMAX pin depends upon the bias and the
voltage that is applied to VLCD, the details are shown in the table. Note that C type biasing is not
available on the 52-pin QFP package device types. On these package types, pins C1, C2 and V2 are
not provided. It is recommended that a 0.1µF capacitor is connected between the V1 pin and ground
on the 52-pin QFP package types.
It is extremely important to ensure that these charge pump generated internal voltages do not exceed
the maximum VDD voltage of 5.5V. Note that the C-type bias type is not available on the 52-pin QFP
package type.
Biasing Type
1/3 Bias
1/2 Bias
VMAX Connection
VDD>VLCD1×1.5
Connect VMAX to VDD
Otherwise
Connect VMAX to V1
VDD>VLCD1
Connect VMAX to VDD
Otherwise
Connect VMAX to VLCD1
C Type Biasing VMAX Connection
Programming Considerations
Certain precautions must be taken when programming the LCD/LED. One of these is to ensure
that the Display Memory is properly initialised after the microcontroller is powered on. Like the
General Purpose Data Memory, the contents of the Display Memory are in an unknown condition
after power-on. As the contents of the Display Memory y will be mapped into the actual display, it is
important to initialise this memory area into a known condition soon after applying power to obtain
a proper display pattern.
Consideration must also be given to the capacitive load of the actual LCD used in the application.
As the load presented to the microcontroller by LCD pixels can be generally modeled as mainly
capacitive in nature, it is important that this is not excessive, a point that is particularly true in the
case of the COM lines which may be connected to many LCD pixels. The accompanying diagram
depicts the equivalent circuit of the LCD.
One additional consideration that must be taken into account is what happens when the
microcontroller enters a Power Down condition. The LCDEN control bit in the LCDCTRL or
LEDEN bit in the LEDCTRL register permits the display to be powered off to reduce power
consumption. If this bit is zero, the driving signals to the display will cease, producing a blank
display pattern but reducing any power consumption associated with the LCD.
After Power-on, note that as the LCDEN and LEDEN bits will be cleared to zero, the display
function will be disabled.
The accompanying timing diagrams depict the display driver signals generated by the
microcontroller for various values of duty and bias. The huge range of various permutations only
permit a few types to be displayed here.
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LCD Panel Equivalent Circuit
LED 1/4 Duty, COM High Active, SEG Low Active, Display Off
LED Static Mode Normal Operation
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LED 1/4 Duty, COM High Active, SEG Low Active, Normal Operation
Note: For 1/2 Bias, VA=VLCD1, VB=VLCD1×1/2 for both R and C type.
LCD Driver Output – Type A – 1/2 Duty, 1/2 Bias
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TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
Note: For 1/2 Bias, the VA=VLCD1, VB=VLCD1×1/2 for both R and C type.
LCD Driver Output – Type A – 1/3 Duty, 1/2 Bias
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TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
Note: For 1/3 R type bias, the VA=VLCD1, VB=VLCD1×2/3 and VC=VLCD1×1/3.
For 1/3 C type bias, the VA=VLCD1×1.5, VB=VLCD1 and VC=VLCD1×1/2.
LCD Driver Output – Type A – 1/4 Duty, 1/3 Bias
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TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
Note: For 1/3 R type bias, the VA=VLCD1, VB=VLCD1×2/3 and VC=VLCD1×1/3.
For 1/3 C type bias, the VA=VLCD1×1.5, VB=VLCD1 and VC=VLCD1×1/2.
LCD Driver Output – Type A - 1/3 Duty, 1/3 Bias
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TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
Note: For 1/2 bias, the VA=VLCD1, VB=VLCD1×1/2 for both R and C type.
LCD Driver Output – Type B – 1/2 Duty, 1/2 Bias
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Timer/Event Counters
The provision of timers form an important part of any microcontroller, giving the designer a
means of carrying out time related functions. The devices contain several 8-bit and 16-bit countup timers. As each timer has three different operating modes, they can be configured to operate as a
general timer, an external event counter or as a pulse width measurement device. The provision of a
prescaler to the clock circuitry of the 8-bit Timer/Event Counter also gives added range to this timer.
There are two types of registers related to the Timer/Event Counters. The first are the registers
that contain the actual value of the Timer/Event Counter and into which an initial value can be
preloaded. Reading from these registers retrieves the contents of the Timer/Event Counter. The
second type of associated register is the Timer Control Register which defines the timer options and
determines how the Timer/Event Counter is to be used. The Timer/Event Counters can have the their
clock configured to come from an internal clock source. In addition, their clock source can also be
configured to come from an external timer pin.
Configuring the Timer/Event Counter Input Clock Source
The internal timer′s clock can originate from various sources. The system clock source is used
when the Timer/Event Counter is in the timer mode or in the pulse width measurement mode.
For the 8-bit Timer/Event Counter this internal clock source is fSYS which is also divided by a
prescaler, the division ratio of which is conditioned by the Timer Control Register, TMRnC, bits
TnPSC0~TnPSC2. For the 16-bit Timer/Event Counter this internal clock source can be chosen from
a combination of internal clocks using a configuration option and the TnS bit in the TMRnC register.
An external clock source is used when the timer is in the event counting mode, the clock source
being provided on an external timer pin TMR0, TMR1 or TMR2 depending upon which timer is
used. Depending upon the condition of the TnE bit, each high to low, or low to high transition on the
external timer pin will increment the counter by one.
Device
No. of 8-bit Timers
Timer Name
Timer Register Name
Control Register Name
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2
1
Timer/Event Counter 0
Timer/Event Counter 0
Timer/Event Counter 1
2
Timer/Event Counter 0
Timer/Event Counter2
TMR0
TMR1
TMR0
TMR0
TMR2
TMR0C
TMR1C
TMR0C
TMR0C
TMR2C
No. of 16-bit Timers
0
1
1
Timer Name
—
Timer/Event Counter 1
Timer/Event Counter 1
Timer Register Name
—
TMR1L/TMR1H
TMR1L/TMR1H
Control Register Name
—
TMR1C
TMR1C
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Timer Registers − TMR0, TMR1, TMR1L/TMR1H, TMR2
The timer registers are special function registers located in the Special Purpose Data Memory and is
the place where the actual timer value is stored. For the 8-bit Timer/Event Counters, these registers
are known as TMR0, TMR1 or TMR2. For the 16-bit Timer/Event Counter, a pair of registers are
required and are known as TMR1L/TMR1H. The value in the timer registers increases by one each
time an internal clock pulse is received or an external transition occurs on the external timer pin.
The timer will count from the initial value loaded by the preload register to the full count of FFH
for the 8-bit timer or FFFFH for the 16-bit timer at which point the timer overflows and an internal
interrupt signal is generated. The timer value will then be reset with the initial preload register value
and continue counting.
To achieve a maximum full range count of FFH for the 8-bit timer or FFFFH for the 16-bit timer,
the preload registers must first be cleared to all zeros. It should be noted that after power-on, the
preload register will be in an unknown condition. Note that if the Timer/Event Counter is switched
off and data is written to its preload registers, this data will be immediately written into the actual
timer registers. However, if the Timer/Event Counter is enabled and counting, any new data written
into the preload data registers during this period will remain in the preload registers and will only be
written into the timer registers the next time an overflow occurs.
For the 16-bit Timer/Event Counter which has both low byte and high byte timer registers, accessing
these registers is carried out in a specific way. It must be noted when using instructions to preload
data into the low byte timer register, the data will only be placed in a low byte buffer and not directly
into the low byte timer register. The actual transfer of the data into the low byte timer register is only
carried out when a write to its associated high byte timer register, namely TMR1H, is executed. On
the other hand, using instructions to preload data into the high byte timer register will result in the
data being directly written to the high byte timer register. At the same time the data in the low byte
buffer will be transferred into its associated low byte timer register. For this reason, the low byte
timer register should be written first when preloading data into the 16-bit timer registers. It must also
be noted that to read the contents of the low byte timer register, a read to the high byte timer register
must be executed first to latch the contents of the low byte timer register into its associated low byte
buffer. After this has been done, the low byte timer register can be read in the normal way. Note that
reading the low byte timer register will result in reading the previously latched contents of the low
byte buffer and not the actual contents of the low byte timer register.
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TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
Timer Control Registers − TMR0C, TMR1C, TMR2C
The flexible features of the Holtek microcontroller Timer/Event Counters enable them to operate in
three different modes, the options of which are determined by the contents of their respective control
register.
It is the Timer Control Register together with its corresponding timer registers that control the
full operation of the Timer/Event Counters. Before the timers can be used, it is essential that the
appropriate Timer Control Register is fully programmed with the right data to ensure its correct
operation, a process that is normally carried out during program initialisation.
To choose which of the three modes the timer is to operate in, either in the timer mode, the event
counting mode or the pulse width measurement mode, bits 7 and 6 of the corresponding Timer
Control Register, which are known as the bit pair TnM1/TnM0, must be set to the required
logic levels. The timer-on bit, which is bit 4 of the Timer Control Register and known as TnON,
depending upon which timer is used, provides the basic on/off control of the respective timer.
Setting the bit high allows the counter to run, clearing the bit stops the counter. For timers that have
prescalers, bits 0~2 of the Timer Control Register determine the division ratio of the input clock
prescaler. The prescaler bit settings have no effect if an external clock source is used. If the timer is
in the event count or pulse width measurement mode, the active transition edge level type is selected
by the logic level of bit 3 of the Timer Control Register which is known as TnE. An additional TnS
bit in the 16-bit Timer/Event Counter control register is used to determine the clock source for the
Timer/Event Counter.

8-bit Timer/Event Counter Structure

16-bit Timer/Event Counter Structure
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TinyPowerTM A/D Type with LCD 8-Bit OTP MCU

Timer/Event Counter Control Register – TMRnC

Timer/Event Counter Control Register – TMRnC
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Configuring the Timer Mode
In this mode, the Timer/Event Counter can be utilised to measure fixed time intervals, providing
an internal interrupt signal each time the Timer/Event Counter overflows. To operate in this mode,
the Operating Mode Select bit pair, TnM1/TnM0, in the Timer Control Register must be set to the
correct value as shown.
Bit7
Bit6
1
0
Control Register Operating Mode Select Bits for the Timer Mode
Timer Mode Timing Chart
In this mode the internal clock, fSYS, is used as the internal clock for 8-bit Timer/Event Counter 0
and fSUB or fSYS/4 is used as the internal clock for 16-bit Timer/Event Counter 1. However, the clock
source, fSYS, for the 8-bit timer is further divided by a prescaler, the value of which is determined by
the Prescaler Rate Select bits TnPSC2~TnPSC0, which are bits 2~0 in the Timer Control Register.
After the other bits in the Timer Control Register have been setup, the enable bit TnON or TnON,
which is bit 4 of the Timer Control Register, can be set high to enable the Timer/Event Counter to
run. Each time an internal clock cycle occurs, the Timer/Event Counter increments by one. When it
is full and overflows, an interrupt signal is generated and the Timer/Event Counter will reload the
value already loaded into the preload register and continue counting. The interrupt can be disabled
by ensuring that the Timer/Event Counter Interrupt Enable bit in the corresponding Interrupt Control
Register, is reset to zero.
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TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
Configuring the Event Counter Mode
In this mode, a number of externally changing logic events, occurring on the external timer pin, can
be recorded by the Timer/Event Counter. To operate in this mode, the Operating Mode Select bit
pair, TnM1/TnM0, in the Timer Control Register must be set to the correct value as shown.
Bit7
Bit6
0
1
Control Register Operating Mode Select Bits for the Event Counter Mode
Event Counter Mode Timing Chart
In this mode, the external timer pin, is used as the Timer/Event Counter clock source, however it is
not divided by the internal prescaler. After the other bits in the Timer Control Register have been
setup, the enable bit TnON, which is bit 4 of the Timer Control Register, can be set high to enable the
Timer/Event Counter to run. If the Active Edge Select bit, TnE, which is bit 3 of the Timer Control
Register, is low, the Timer/Event Counter will increment each time the external timer pin receives
a low to high transition. If the Active Edge Select bit is high, the counter will increment each time
the external timer pin receives a high to low transition. When it is full and overflows, an interrupt
signal is generated and the Timer/Event Counter will reload the value already loaded into the preload
register and continue counting. The interrupt can be disabled by ensuring that the Timer/Event
Counter Interrupt Enable bit in the corresponding Interrupt Control Register, is reset to zero.
As the external timer pin is shared with an I/O pin, to ensure that the pin is configured to operate as
an event counter input pin, two things have to happen. The first is to ensure that the Operating Mode
Select bits in the Timer Control Register place the Timer/Event Counter in the Event Counting
Mode, the second is to ensure that the port control register configures the pin as an input. It should
be noted that in the event counting mode, even if the microcontroller is in the Power Down Mode,
the Timer/Event Counter will continue to record externally changing logic events on the timer input
pin. As a result when the timer overflows it will generate a timer interrupt and corresponding wakeup source.
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Configuring the Pulse Width Measurement Mode
In this mode, the Timer/Event Counter can be utilised to measure the width of external pulses
applied to the external timer pin. To operate in this mode, the Operating Mode Select bit pair,
TnM1/TnM0, in the Timer Control Register must be set to the correct value as shown.
Bit7
Bit6
1
1
Control Register Operating Mode Select Bits for the Pulse Width Measurement Mode

Pulse Width Measure Mode Timing Chart
In this mode the internal clock, fSYS, is used as the internal clock for the 8-bit Timer/Event Counter
and fSUB or fSYS/4 is used as the internal clock for the 16-bit Timer/Event Counter. However, the clock
source, fSYS, for the 8-bit timer is further divided by a prescaler, the value of which is determined by
the Prescaler Rate Select bits TnPSC2~TnPSC0, which are bits 2~0 in the Timer Control Register.
After the other bits in the Timer Control Register have been setup, the enable bit TnON, which is bit
4 of the Timer Control Register, can be set high to enable the Timer/Event Counter, however it will
not actually start counting until an active edge is received on the external timer pin.
If the Active Edge Select bit TnE, which is bit 3 of the Timer Control Register, is low, once a high
to low transition has been received on the external timer pin, the Timer/Event Counter will start
counting until the external timer pin returns to its original high level. At this point the enable bit will
be automatically reset to zero and the Timer/Event Counter will stop counting. If the Active Edge
Select bit is high, the Timer/Event Counter will begin counting once a low to high transition has
been received on the external timer pin and stop counting when the external timer pin returns to its
original low level. As before, the enable bit will be automatically reset to zero and the Timer/Event
Counter will stop counting. It is important to note that in the Pulse Width Measurement Mode, the
enable bit is automatically reset to zero when the external control signal on the external timer pin
returns to its original level, whereas in the other two modes the enable bit can only be reset to zero
under program control.
The residual value in the Timer/Event Counter, which can now be read by the program, therefore
represents the length of the pulse received on the external timer pin. As the enable bit has now been
reset, any further transitions on the external timer pin will be ignored. Not until the enable bit is
again set high by the program can the timer begin further pulse width measurements. In this way,
single shot pulse measurements can be easily Made.
It should be noted that in this mode the Timer/Event Counter is controlled by logical transitions
on the external timer pin and not by the logic level. When the Timer/Event Counter is full and
overflows, an interrupt signal is generated and the Timer/Event Counter will reload the value already
loaded into the preload register and continue counting. The interrupt can be disabled by ensuring
that the Timer/Event Counter Interrupt Enable bit in the corresponding Interrupt Control Register, is
reset to zero.
As the external timer pin is shared with an I/O pin, to ensure that the pin is configured to operate as
a pulse width measurement pin, two things have to happen. The first is to ensure that the Operating
Mode Select bits in the Timer Control Register place the Timer/Event Counter in the Pulse Width
Measurement Mode, the second is to ensure that the port control register configures the pin as an input.
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TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
Programmable Frequency Divider − PFD
The Programmable Frequency Divider provides a means of producing a variable frequency output
suitable for applications requiring a precise frequency generator.
The PFD output is pin-shared with the I/O pin PA3. The PFD function is selected via configuration
option, however, if not selected, the pin can operate as a normal I/O pin.
The clock source for the PFD circuit can originate from either Timer/Event Counter 0 or
Timer/Event Counter 1 overflow signal selected via configuration option. The output frequency is
controlled by loading the required values into the timer registers and prescaler registers to give the
required division ratio. The timer will begin to count-up from this preload register value until full, at
which point an overflow signal is generated, causing the PFD output to change state. The timer will
then be automatically reloaded with the preload register value and continue counting-up.
For the PFD output to function, it is essential that the corresponding bit of the Port A control register
PAC bit 3 is setup as an output. If setup as an input the PFD output will not function, however, the
pin can still be used as a normal input pin. The PFD output will only be activated if bit PA3 is set
to ″1″. This output data bit is used as the on/off control bit for the PFD output. Note that the PFD
output will be low if the PA3 output data bit is cleared to ″0″.
Using this method of frequency generation, and if a crystal oscillator is used for the system clock,
very precise values of frequency can be generated.
PFD Output Control
Prescaler
Bits TnPSC0~TnPSC2 of the control register can be used to define the pre-scaling stages of the
internal clock source of the Timer/Event Counter. The Timer/Event Counter overflow signal can be
used to generate signals for the PFD and Timer Interrupt.
I/O Interfacing
The Timer/Event Counter, when configured to run in the event counter or pulse width measurement
mode, require the use of external pins for correct operation. As these pins are shared pins they must
be configured correctly to ensure they are setup for use as Timer/Event Counter inputs and not as
a normal I/O pins. This is implemented by ensuring that the mode select bits in the Timer/Event
Counter control register, select either the event counter or pulse width measurement mode.
Additionally the Port Control Register must be set high to ensure that the pin is setup as an input.
Any pull-high resistor on these pins will remain valid even if the pin is used as a Timer/Event
Counter input.
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TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
Timer/Event Counter Pins Internal Filter
The external Timer/Event Counter pins are connected to an internal filter to reduce the possibility
of unwanted event counting events or inaccurate pulse width measurements due to adverse noise or
spikes on the external Timer/Event Counter input signal. As this internal filter circuit will consume
a limited amount of power, a configuration option is provided to switch off the filter function, an
option which may be beneficial in power sensitive applications, but in which the integrity of the
input signal is high. Care must be taken when using the filter on/off configuration option as it will
be applied not only to both external Timer/Event Counter pins but also to the external interrupt input
pins. Individual Timer/Event Counter or external interrupt pins cannot be selected to have a filter
on/off function.
Programming Considerations
When configured to run in the timer mode, the internal system clock is used as the timer clock
source and is therefore synchronised with the overall operation of the microcontroller. In this mode
when the appropriate timer register is full, the microcontroller will generate an internal interrupt
signal directing the program flow to the respective internal interrupt vector. For the pulse width
measurement mode, the internal system clock is also used as the timer clock source but the timer
will only run when the correct logic condition appears on the external timer input pin. As this is
an external event and not synchronized with the internal timer clock, the microcontroller will only
see this external event when the next timer clock pulse arrives. As a result, there may be small
differences in measured values requiring programmers to take this into account during programming.
The same applies if the timer is configured to be in the event counting mode, which again is an
external event and not synchronised with the internal system or timer clock.
When the Timer/Event Counter is read, or if data is written to the preload register, the clock is
inhibited to avoid errors, however as this may result in a counting error, this should be taken into
account by the programmer. Care must be taken to ensure that the timers are properly initialised
before using them for the first time. The associated timer enable bits in the interrupt control
register must be properly set otherwise the internal interrupt associated with the timer will remain
inactive. The edge select, timer mode and clock source control bits in timer control register must
also be correctly set to ensure the timer is properly configured for the required application. It is
also important to ensure that an initial value is first loaded into the timer registers before the timer
is switched on; this is because after power-on the initial values of the timer registers are unknown.
After the timer has been initialised the timer can be turned on and off by controlling the enable bit in
the timer control register. Note that setting the timer enable bit high to turn the timer on, should only
be executed after the timer mode bits have been properly setup. Setting the timer enable bit high
together with a mode bit modification, may lead to improper timer operation if executed as a single
timer control register byte write instruction.
When the Timer/Event counter overflows, its corresponding interrupt request flag in the interrupt
control register will be set. If the timer interrupt is enabled this will in turn generate an interrupt
signal. However irrespective of whether the interrupts are enabled or not, a Timer/Event counter
overflow will also generate a wake-up signal if the device is in a Power-down condition. This
situation may occur if the Timer/Event Counter is in the Event Counting Mode and if the external
signal continues to change state. In such a case, the Timer/Event Counter will continue to count
these external events and if an overflow occurs the device will be woken up from its Power-down
condition. To prevent such a wake-up from occurring, the timer interrupt request flag should first be
set high before issuing the HALT instruction to enter the Power Down Mode.
Rev. 1.30
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Timer Program Example
This program example shows how the Timer/Event Counter registers are setup, along with how the
interrupts are enabled and managed. Note how the Timer/Event Counter is turned on, by setting bit
4 of the Timer Control Register. The Timer/Event Counter can be turned off in a similar way by
clearing the same bit. This example program sets the Timer/Event Counter to be in the timer mode,
which uses the internal system clock as the clock source.
org 04h ; external interrupt vector
reti
org 08h
; Timer/Event Counter 0 interrupt vector
jmp tmrint
; jump here when the Timer/Event Counter 0 overflows
:
org 20h
; main program internal Timer/Event Counter 0 interrupt routine
tmrint:
:
; Timer/Event Counter 0 main program placed here
:
reti
:
:
begin:
mov
mov
mov
mov
mov
mov
set
Rev. 1.30
a,09bh
tmr0,a;
a,081h
tmr0c,a
a,009h
int0c,a
tmr0c.4
; setup Timer 0 registers
; setup Timer 0 preload value
; setup Timer 0 control register
; timer mode and prescaler set to /2 setup interrupt register
; enable master interrupt and timer interrupt
; start Timer/Event Counter 0 - note mode bits must be previously setup
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TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
Pulse Width Modulator
The devices contains a series of Pulse Width Modulation, PWM, outputs. Useful for such
applications such as motor speed control, the PWM function provides an output with a fixed
frequency but with a duty cycle that can be varied by setting particular values into the corresponding
PWM register.
Part No.
Channels
PWM Mode
Output Pin
Register Names
HT56R62
3
8+4
PD0~PD2
PWM0L~PWM2L
PWM0H~PWM2H
Other Devices
4
8+4
PD0~PD3
PWM0L~PWM3L
PWM0H~PWM3H
PWM Overview
A register pair, located in the Data Memory is assigned to each Pulse Width Modulator output and
are known as the PWM registers. It is in each register pair that the 12-bit value, which represents
the overall duty cycle of one modulation cycle of the output waveform, should be placed. The
PWM registers also contain the enable/disable control bit for the PWM outputs. To increase
the PWM modulation frequency, each modulation cycle is modulated into sixteen individual
modulation sub-sections, known as the 8+4 mode. Note that it is only necessary to write the required
modulation value into the corresponding PWM register as the subdivision of the waveform into
its sub-modulation cycles is implemented automatically within the microcontroller hardware. The
PWM clock source is the system clock fSYS.
This method of dividing the original modulation cycle into a further 16 sub-cycles enables the
generation of higher PWM frequencies, which allow a wider range of applications to be served. As
long as the periods of the generated PWM pulses are less than the time constants of the load, the
PWM output will be suitable as such long time constant loads will average out the pulses of the
PWM output. The difference between what is known as the PWM cycle frequency and the PWM
modulation frequency should be understood. As the PWM clock is the system clock, fSYS, and as the
PWM value is 12-bit wide, the overall PWM cycle frequency is fSYS/4096. However, when in the
8+4 mode of operation, the PWM modulation frequency will be fSYS/256.
Rev. 1.30
PWM Modulation Frequency
PWM Cycle Frequency
PWM Cycle Duty
fSYS/256
fSYS/4096
(PWM register value)/4096
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8+4 PWM Mode Modulation
Each full PWM cycle, as it is 12-bit wide, has 4096 clock periods. However, in the 8+4 PWM
mode, each PWM cycle is subdivided into sixteen individual sub-cycles known as modulation cycle
0~modulation cycle 15, denoted as ″i″ in the table. Each one of these sixteen sub-cycles contains
256 clock cycles. In this mode, a modulation frequency increase of sixteen is achieved. The 12-bit
PWM register value, which represents the overall duty cycle of the PWM waveform, is divided
into two groups. The first group which consists of bit4~bit11 is denoted here as the DC value. The
second group which consists of bit0~bit3 is known as the AC value. In the 8+4 PWM mode, the
duty cycle value of each of the two modulation sub-cycles is shown in the following table.
Parameter
AC (0~15)
DC (Duty Cycle)
i<AC
i≥AC
Modulation cycle i
(i=0~15)
8+4 Mode Modulation Cycle Values
The accompanying diagram illustrates the waveforms associated with the 8+4 mode of PWM
operation. It is important to note how the single PWM cycle is subdivided into 16 individual
modulation cycles, numbered 0~15 and how the AC value is related to the PWM value.
PWM Output Control
The four PWM0~PWM3 outputs are shared with pins PD0~PD3. To operate as a PWM output
and not as an I/O pin, bit 0 of the relevant PWM register bit must be set high. A zero must also be
written to the corresponding bit in the PDC port control register, to ensure that the PWM0 output
pin is setup as an output. After these two initial steps have been carried out, and of course after the
required PWM 12-bit value has been written into the PWM register pair register, writing a ″1″ to
the corresponding PD data register will enable the PWM data to appear on the pin. Writing a ″0″ to
the bit will disable the PWM output function and force the output low. In this way, the Port D data
output register bits, can also be used as an on/off control for the PWM function. Note that if the
enable bit in the PWM register is set high to enable the PWM function, but a ″1″ has been written
to its corresponding bit in the PDC control register to configure the pin as an input, then the pin can
still function as a normal input line, with pull-high resistor selections.
8+4 PWM Mode
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PWM Register Pairs
PWM Programming Example
The following sample program shows how the PWM output is setup and controlled.
mov a,64h
; setup PWM0 value to 1600 decimal which is 640H
mov pwm0h,a
; setup PWM0H register value
clr pwm0l
; setup PWM0L register value
clr pdc.0
; setup pin PD0 as an output
set pwm0en
; set the PWM0 enable bit
set pd.0
; Enable the PWM0 output
:
:
:
:
clr pd.0
; PWM0 output disabled − PD0 will remain low
Rev. 1.30
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Analog to Digital Converter
The need to interface to real world analog signals is a common requirement for many electronic
systems. However, to properly process these signals by a microcontroller, they must first be
converted into digital signals by A/D converters. By integrating the A/D conversion electronic
circuitry into the microcontroller, the need for external components is reduced significantly with the
corresponding follow-on benefits of lower costs and reduced component space requirements.

A/D Converter Structure
A/D Overview
The device contains an 8-channel analog to digital converter which can directly interface to external
analog signals, such as that from sensors or other control signals and convert these signals directly
into either a 12-bit digital value.
Part No.
Input Channels Conversion Bits
Input Pins
HT56R62
6
12
PB0~PB5
Other Devices
8
12
PB0~PB7
The accompanying block diagram shows the overall internal structure of the A/D converter, together
with its associated registers.
A/D Converter Data Registers − ADRL, ADRH
The device, which has an internal 12-bit A/D converter, requires two data registers, a high byte
register, known as ADRH, and a low byte register, known as ADRL. After the conversion process
takes place, these registers can be directly read by the microcontroller to obtain the digitised
conversion value. Only the high byte register, ADRH, utilises its full 8-bit contents. The low
byte register utilises only 4 bit of its 8-bit contents as it contains only the lowest bits of the 12-bit
converted value.
In the following table, D0~D11 is the A/D conversion data result bits.
Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
ADRL
D3
D1
D0
—
—
—
—
ADRH
D11 D10 D9
D2
D8
D7
D6
D5
D4
A/D Data Registers
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TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
A/D Converter Control Registers − ADCR, ACSR
To control the function and operation of the A/D converter, two control registers known as ADCR
and ACSR are provided. These 8-bit registers define functions such as the selection of which
analog channel is connected to the internal A/D converter, which pins are used as analog inputs and
which are used as normal I/Os, the A/D clock source as well as controlling the start function and
monitoring the A/D converter end of conversion status.
The ACS2~ACS0 bits in the ADCR register define the channel number. As the device contains only
one actual analog to digital converter circuit, each of the individual 8 analog inputs must be routed
to the converter. It is the function of the ACS2~ACS0 bits in the ADCR register to determine which
analog channel is actually connected to the internal A/D converter.
The ADCR control register also contains the PCR2~PCR0 bits which determine which pins on Port
B are used as analog inputs for the A/D converter and which pins are to be used as normal I/O pins.
If the 3-bit address on PCR2~PCR0 has a value of ″111″, then all eight pins, namely AN0~AN7
will all be set as analog inputs. Note that if the PCR2~PCR0 bits are all set to zero, then all the Port
B pins will be setup as normal I/Os and the internal A/D converter circuitry will be powered off to
reduce the power consumption.

A/D Converter Control Register – ADCR
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TinyPowerTM A/D Type with LCD 8-Bit OTP MCU

A/D Converter Control Register – ACSR
The START bit in the register is used to start and reset the A/D converter. When the microcontroller
sets this bit from low to high and then low again, an analog to digital conversion cycle will be
initiated. When the START bit is brought from low to high but not low again, the EOCB bit in the
ADCR register will be set to a ″1″ and the analog to digital converter will be reset. It is the START
bit that is used to control the overall on/off operation of the internal analog to digital converter.
The EOCB bit in the ADCR register is used to indicate when the analog to digital conversion process
is complete. This bit will be automatically set to ″0″ by the microcontroller after a conversion cycle
has ended. In addition, the corresponding A/D interrupt request flag will be set in the interrupt
control register, and if the interrupts are enabled, an appropriate internal interrupt signal will be
generated. This A/D internal interrupt signal will direct the program flow to the associated A/D
internal interrupt address for processing. If the A/D internal interrupt is disabled, the microcontroller
can be used to poll the EOCB bit in the ADCR register to check whether it has been cleared as an
alternative method of detecting the end of an A/D conversion cycle.
The clock source for the A/D converter, which originates from the system clock fSYS, is first divided
by a division ratio, the value of which is determined by the ADCS2, ADCS1 and ADCS0 bits in the
ACSR register.
Controlling the on/off function of the A/D converter circuitry is implemented using the ADONB bit
in the ACSR register and the value of the PCR bits in the ADCR register. Both the ADONB bit must
cleared to ″0″ and the value of the PCR bits must have a non-zero value for the A/D converter to be
enabled.
Rev. 1.30
PCR
ADONB
0
x
Off
>0
0
On
>0
1
Off
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TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
Although the A/D clock source is determined by the system clock fSYS, and by bits ADCS2,
ADCS1 and ADCS0, there are some limitations on the maximum A/D clock source speed that can
be selected. As the minimum value of permissible A/D clock period, tAD, is 0.5µs, care must be
taken for system clock speeds in excess of 4MHz. For system clock speeds in excess of 4MHz, the
ADCS2, ADCS1 and ADCS0 bits should not be set to ″000″. Doing so will give A/D clock periods
that are less than the minimum A/D clock period which may result in inaccurate A/D conversion
values. Refer to the following table for examples, where values marked with an asterisk * show
where, depending upon the device, special care must be taken, as the values may be less than the
specified minimum A/D Clock Period.
A/D Clock Period (tAD)
ADCS2, ADCS1,
ADCS0=000
(fSYS/2)
ADCS2, ADCS1,
ADCS0=001
(fSYS/8)
ADCS2, ADCS1,
ADCS0=010
(fSYS/32)
ADCS2, ADCS1,
ADCS0=011
1MHz
2µs
8µs
32µs
Undefined
2MHz
1µs
4µs
16µs
Undefined
4MHz
500ns
2µs
8µs
Undefined
8MHz
250ns*
1µs
4µs
Undefined
12MHz
167ns*
667ns
2.67µs
Undefined
fSYS
A/D Clock Period Examples
A/D Input Pins
All of the A/D analog input pins are pin-shared with the I/O pins on Port B. Bits PCR2~PCR0 in the
ADCR register, determine whether the input pins are setup as normal Port B input/output pins or
whether they are setup as analog inputs. In this way, pins can be changed under program control to
change their function from normal I/O operation to analog inputs and vice versa. Pull-high resistors,
which are setup through register programming, apply to the input pins only when they are used as
normal I/O pins, if setup as A/D inputs the pull-high resistors will be automatically disconnected.
Note that it is not necessary to first setup the A/D pin as an input in the PBC port control register
to enable the A/D input as when the PCR2~PCR0 bits enable an A/D input, the status of the port
control register will be overridden. The A/D converter has its own power supply pins AVDD and
AVSS and a VREF reference pin. The analog input values must not be allowed to exceed the value
of VREF.
Initialising the A/D Converter
The internal A/D converter must be initialised in a special way. Each time the Port B A/D channel
selection bits are modified by the program, the A/D converter must be re-initialised. If the A/D
converter is not initialised after the channel selection bits are changed, the EOCB flag may have an
undefined value, which may produce a false end of conversion signal. To initialise the A/D converter
after the channel selection bits have changed, then, within a time frame of one to ten instruction
cycles, the START bit in the ADCR register must first be set high and then immediately cleared to
zero. This will ensure that the EOCB flag is correctly set to a high condition.
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TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
Summary of A/D Conversion Steps
The following summarises the individual steps that should be executed in order to implement an
A/D conversion process.
• Step 1
Select the required A/D conversion clock by correctly programming bits ADCS2, ADCS1 and
ADCS0 in the ACSR register.
• Step 2
Enable the A/D by clearing the ADONB in the ACSR register to zero.
• Step 3
Select which channel is to be connected to the internal A/D converter by correctly programming
the ACS2~ACS0 bits which are also contained in the ADCR register.
• Step 4
Select which pins on Port B are to be used as A/D inputs and configure them as A/D input pins
by correctly programming the PCR2~PCR0 bits in the ADCR register. Note that this step can be
combined with Step 2 into a single ADCR register programming operation.
• Step 5
If the interrupts are to be used, the interrupt control registers must be correctly configured to
ensure the A/D converter interrupt function is active. The master interrupt control bit, EMI, in the
INTC0 interrupt control register must be set to ″1″, the multi-function interrupt enable bit, EMFI,
in the INTC1 register and the A/D converter interrupt bit, EADI, in the INTC1 register must also
be set to ″1″.
• Step 6
The analog to digital conversion process can now be initialised by setting the START bit in
the ADCR register from ″0″ to ″1″ and then to ″0″ again. Note that this bit should have been
originally set to ″0″.
• Step 7
To check when the analog to digital conversion process is complete, the EOCB bit in the ADCR
register can be polled. The conversion process is complete when this bit goes low. When this
occurs the A/D data registers ADRL and ADRH can be read to obtain the conversion value. As an
alternative method if the interrupts are enabled and the stack is not full, the program can wait for
an A/D interrupt to occur.
Note: When checking for the end of the conversion process, if the method of polling the EOCB bit
in the ADCR register is used, the interrupt enable step above can be omitted.
The accompanying diagram shows graphically the various stages involved in an analog to digital
conversion process and its associated timing.
The setting up and operation of the A/D converter function is fully under the control of the
application program as there are no configuration options associated with the A/D converter. After an
A/D conversion process has been initiated by the application program, the microcontroller internal
hardware will begin to carry out the conversion, during which time the program can continue with
other functions. The time taken for the A/D conversion is 16tAD where tAD is equal to the A/D clock
period.
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TinyPowerTM A/D Type with LCD 8-Bit OTP MCU

A/D Conversion Timing
Programming Considerations
When programming, special attention must be given to the A/D channel selection bits in the ADCR
register. If these bits are all cleared to zero no external pins will be selected for use as A/D input
pins allowing the pins to be used as normal I/O pins. When this happens the power supplied to
the internal A/D circuitry will be reduced resulting in a reduction of supply current. This ability to
reduce power by turning off the internal A/D function by clearing the A/D channel selection bits
may be an important consideration in battery powered applications. The ADONB bit in the ACSR
register can also be used to power down the A/D function.
Another important programming consideration is that when the A/D channel selection bits change
value, the A/D converter must be re-initialised. This is achieved by pulsing the START bit in the
ADCR register immediately after the channel selection bits have changed state. The exception to this
is where the channel selection bits are all cleared, in which case the A/D converter is not required to
be re-initialised.
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TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
A/D Programming Example
The following two programming examples illustrate how to setup and implement an A/D
conversion. In the first example, the method of polling the EOCB bit in the ADCR register is used to
detect when the conversion cycle is complete, whereas in the second example, the A/D interrupt is
used to determine when the conversion is complete.
Example: using an EOCB polling method to detect the end of conversion
clr EADI
mov a,00000001B
mov ACSR,a
mov a,00100000B
mov ADCR,a
:
:
:
Start_conversion:
clr START
set START
clr START
Polling_EOC:
sz EOCB
jmp polling_EOC
mov a,ADRL
mov adrl_buffer,a
mov a,ADRH
mov adrh_buffer,a
:
jmp start_conversion
Rev. 1.30
; disable ADC interrupt
; select fSYS/8 as A/D clock and turn on ADONB bit
; setup ADCR register to configure Port PB0~PB3 as A/D inputs
; and select AN0 to be connected to the A/D converter
; As the Port B channel bits have changed the following
; START signal (0-1-0) must be issued instruction cycles
; reset A/D
; start A/D
;
;
;
;
;
;
;
poll the ADCR register EOCB bit to detect end
of A/D conversion
continue polling
read low byte conversion result value
save result to user defined register
read high byte conversion result value
save result to user defined register
; start next A/D conversion
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TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
Example: using the interrupt method to detect the end of conversion
clr EADI
mov a,00000001B
mov ACSR,a
mov a,00100000B
mov ADCR,a
:
:
Start_conversion:
clr START
set START
clr START
clr ADF
set EADI
set EMFI
set EMI
:
:
:
ADC_:
mov acc_stack,a
a,STATUS
mov status_stack,a
:
:
mov a,ADRL
mov adrl_buffer,a
mov a,ADRH
mov adrh_buffer,a
:
:
EXIT__ISR:
mov a,status_stack
mov STATUS,a
mov a,acc_stack
clr ADF
reti
Rev. 1.30
; disable ADC interrupt
; select fSYS/8 as A/D clock and turn on ADONB bit
; setup ADCR register to configure Port PB0~PB3 as A/D inputs
; and select AN0 to be connected to the A/D
; As the Port B channel bits have changed the
; following START signal(0-1-0) must be issued
;
;
;
;
;
;
reset A/D
start A/D
clear ADC interrupt request flag
enable ADC interrupt
enable multi-function interrupt
enable global interrupt
; ADC interrupt service routine
; save ACC to user defined memory
; save STATUS to user defined memory
;
;
;
;
read
save
read
save
low byte conversion result value
result to user defined register
high byte conversion result value
result to user defined register
; restore STATUS from user defined memory
; restore ACC from user defined memory
; clear ADC interrupt flag
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TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
A/D Transfer Function
As the device contain a 12-bit A/D converter, its full-scale converted digitised value is equal to
FFFH. Since the full-scale analog input value is equal to the VDD voltage, this gives a single bit
analog input value of VDD/4096. The diagram show the ideal transfer function between the analog
input value and the digitised output value for the A/D converter.
Note that to reduce the quantisation error, a 0.5 LSB offset is added to the A/D Converter input.
Except for the digitised zero value, the subsequent digitised values will change at a point 0.5 LSB
below where they would change without the offset, and the last full scale digitised value will change
at a point 1.5 LSB below the VDD level.

Ideal A/D Transfer Function
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TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
Serial Interface Function
The device contains a Serial Interface Function, which includes both the four line SPI interface and
the two line I2C interface types, to allow an easy method of communication with external peripheral
hardware. Having relatively simple communication protocols, these serial interface types allow
the microcontroller to interface to external SPI or I2C based hardware such as sensors, Flash or
EEPROM memory, etc. The SIM interface pins are pin-shared with other I/O pins therefore the SIM
interface function must first be selected using a configuration option. As both interface types share
the same pins and registers, the choice of whether the SPI or I2C type is used is made using a bit in
an internal register.
SPI Interface
The SPI interface is often used to communicate with external peripheral devices such as sensors,
Flash or EEPROM memory devices etc. Originally developed by Motorola, the four line SPI
interface is a synchronous serial data interface that has a relatively simple communication protocol
simplifying the programming requirements when communicating with external hardware devices.
The communication is full duplex and operates as a slave/master type, where the MCU can be
either master or slave. Although the SPI interface specification can control multiple slave devices
from a single master, here, as only a single select pin, SCS, is provided only one slave device can be
connected to the SPI bus.
SPI Master/Slave Connection

SPI Block Diagram
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SPI Interface Operation
The SPI interface is a full duplex synchronous serial data link. It is a four line interface with pin
names SDI, SDO, SCK and SCS. Pins SDI and SDO are the Serial Data Input and Serial Data
Output lines, SCK is the Serial Clock line and SCS is the Slave Select line. As the SPI interface
pins are pin-shared with normal I/O pins and with the I2C function pins, the SPI interface must
first be enabled by selecting the SIM enable configuration option and setting the correct bits in the
SIMCTL0/SIMCTL2 register. After the SPI configuration option has been configured it can also
be additionally disabled or enabled using the SIMEN bit in the SIMCTL0 register. Communication
between devices connected to the SPI interface is carried out in a slave/master mode with all data
transfer initiations being implemented by the master. The Master also controls the clock signal. As
the device only contains a single SCS pin only one slave device can be utilised.
The SPI function in this device offers the following features:
• Full duplex synchronous data transfer
• Both Master and Slave modes
• LSB first or MSB first data transmission modes
• Transmission complete flag
• Rising or falling active clock edge
• WCOL and CSEN bit enabled or disable select
The status of the SPI interface pins is determined by a number of factors such as whether the device
is in the master or slave mode and upon the condition of certain control bits such as CSEN, SIMEN
and SCS. In the table I, Z represents an input floating condition.
There are several configuration options associated with the SPI interface. One of these is to
enable the SIM function which selects the SIM pins rather than normal I/O pins. Note that if the
configuration option does not select the SIM function then the SIMEN bit in the SIMCTL0 register
will have no effect. Another two SIM configuration options determine if the CSEN and WCOL bits
are to be used.
Configuration Option
Function
SIM Function
SIM interface or I/O pins
SPI CSEN bit
Enable/Disable
SPI WCOL bit
Enable/Disable
SPI Interface Configuration Options
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SPI Registers
There are three internal registers which control the overall operation of the SPI interface. These
are the SIMDR data register and two control registers SIMCTL0 and SIMCTL2. Note that the
SIMCTL1 register is only used by the I2C interface.
The SIMDR register is used to store the data being transmitted and received. The same register is
used by both the SPI and I2C functions. Before the microcontroller writes data to the SPI bus, the
actual data to be transmitted must be placed in the SIMDR register. After the data is received from
the SPI bus, the microcontroller can read it from the SIMDR register. Any transmission or reception
of data from the SPI bus must be made via the SIMDR register.
Bit
7
6
5
4
3
2
1
0
Label
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
X
X
X
X
X
X
X
X
There are also two control registers for the SPI interface, SIMCTL0 and SIMCTL2. Note that the
SIMCTL2 register also has the name SIMAR which is used by the I2C function. The SIMCTL1
register is not used by the SPI function, only by the I2C function. Register SIMCTL0 is used to
control the enable/disable function and to set the data transmission clock frequency. Although not
connected with the SPI function, the SIMCTL0 register is also used to control the Peripheral Clock
prescaler. Register SIMCTL2 is used for other control functions such as LSB/MSB selection, write
collision flag etc.
The following gives further explanation of each SIMCTL1 register bit:
• SIMIDLE
The SIMIDLE bit is used to select if the SPI interface continues running when the device is in the
IDLE mode. Setting the bit high allows the SPI interface to maintain operation when the device
is in the Idle mode. Clearing the bit to zero disables any SPI operations when in the Idle mode.
This SPI/I2C idle mode control bit is located at CLKMOD register bit4.
• SIMEN
The SIMEN bit is the overall on/off control for the SPI interface. When the SIMEN bit is cleared
to zero to disable the SPI interface, the SDI, SDO, SCK and SCS lines will be in a floating
condition and the SPI operating current will be reduced to a minimum value. When the bit is high
the SPI interface is enabled. The SIMEN configuration option must have first enabled the SIMEN
interface for this bit to be effective. Note that when the SIMEN bit changes from low to high the
contents of the SPI control registers will be in an unknown condition and should therefore be first
initialised by the application program.
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• SIM0~SIM2
These bits setup the overall operating mode of the SIM function. As well as selecting if the I2C
or SPI function, they are used to control the SPI Master/Slave selection and the SPI Master clock
frequency. The SPI clock is a function of the system clock but can also be chosen to be sourced
from the Timer/Event Counter. If the SPI Slave Mode is selected then the clock will be supplied
by an external Master device.
SPI Master/Slave Clock Control and I2C Enable
SIM0
SIM1
SIM2
0
0
0
SPI Master, fSYS/4
0
0
1
SPI Master, fSYS/16
0
1
0
SPI Master, fSYS/64
0
1
1
SPI Master, fSUB
1
0
0
SPI Master Timer/Event Counter 0 output/2
1
0
1
SPI Slave
1
1
0
I2C mode
1
1
0
Not used
SPI Control Register − SIMCTL2
The SIMCTL2 register is also used by the I2C interface but has the name SIMAR.
• TRF
The TRF bit is the Transmit/Receive Complete flag and is set high automatically when an SPI
data transmission is completed, but must be cleared by the application program. It can be used to
generate an interrupt.
• WCOL
The WCOL bit is used to detect if a data collision has occurred. If this bit is high it means that
data has been attempted to be written to the SIMDR register during a data transfer operation.
This writing operation will be ignored if data is being transferred. The bit can be cleared by the
application program. Note that using the WCOL bit can be disabled or enabled via configuration
option.
• CSEN
The CSEN bit is used as an on/off control for the SCS pin. If this bit is low then the SCS pin will
be disabled and placed into a floating condition. If the bit is high the SCS pin will be enabled and
used as a select pin. Note that using the CSEN bit can be disabled or enabled via configuration
option.
• MLS
This is the data shift select bit and is used to select how the data is transferred, either MSB or
LSB first. Setting the bit high will select MSB first and low for LSB first.
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• CKEG and CKPOL
These two bits are used to setup the way that the clock signal outputs and inputs data on the SPI
bus. These two bits must be configured before data transfer is executed otherwise an erroneous
clock edge may be generated. The CKPOL bit determines the base condition of the clock line, if
the bit is high then the SCK line will be low when the clock is inactive. When the CKPOL bit is
low then the SCK line will be high when the clock is inactive. The CKEG bit determines active
clock edge type which depends upon the condition of CKPOL.

CKPOL
CKEG
SCKClock Signal
0
0
High Base Level Active Rising Edge
0
1
High Base Level Active Falling Edge
1
0
Low Base Level Active Falling Edge
1
1
Low Base Level Active Rising Edge

2
SPI/I C Control Register – SIMCTL0

I2C Control Register – SIMCTL1
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SPI Control Register – SIMCTL2
SPI Communication
After the SPI interface is enabled by setting the SIMEN bit high, then in the Master Mode, when
data is written to the SIMDR register, transmission/reception will begin simultaneously. When
the data transfer is complete, the TRF flag will be set automatically, but must be cleared using the
application program. In the Slave Mode, when the clock signal from the master has been received,
any data in the SIMDR register will be transmitted and any data on the SDI pin will be shifted into
the SIMDR register. The master should output an SCS signal to enable the slave device before a
clock signal is provided and slave data transfers should be enabled/disabled before/after an SCS
signal is received.
The SPI will continue to function even after a HALT instruction has been executed.

SPI Master Mode Timing
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SPI Slave Mode Timing (CKEG=0)

SPI Slave Mode Timing (CKEG=1)
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SPI Transfer Control Flowchart
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I2C Interface
The I 2C interface is used to communicate with external peripheral devices such as sensors,
EEPROM memory etc. Originally developed by Philips, it is a two line low speed serial interface
for synchronous serial data transfer. The advantage of only two lines for communication, relatively
simple communication protocol and the ability to accommodate multiple devices on the same bus
has made it an extremely popular interface type for many applications.
I2C Interface Operation
The I2C serial interface is a two line interface, a serial data line, SDA, and serial clock line, SCL. As
many devices may be connected together on the same bus, their outputs are both open drain types.
For this reason it is necessary that external pull-high resistors are connected to these outputs. Note
that no chip select line exists, as each device on the I2C bus is identified by a unique address which
will be transmitted and received on the I2C bus.
When two devices communicate with each other on the bidirectional I2C bus, one is known as the
master device and one as the slave device. Both master and slave can transmit and receive data,
however, it is the master device that has overall control of the bus. For these devices, which only
operates in slave mode, there are two methods of transferring data on the I2C bus, the slave transmit
mode and the slave receive mode.
There are several configuration options associated with the I2C interface. One of these is to enable
the function which selects the SIM pins rather than normal I/O pins. Note that if the configuration
option does not select the SIM function then the SIMEN bit in the SIMCTL0 register will have no
effect. A configuration option exists to allow a clock other than the system clock to drive the I2C
interface. Another configuration option determines the debounce time of the I2C interface. This uses
the internal clock to in effect add a debounce time to the external clock to reduce the possibility of
glitches on the clock line causing erroneous operation. The debounce time, if selected, can be chosen
to be either 1 or 2 system clocks.
SIM
Function
SIM function
interface or SEG pins
I2C clock
I2C runs without internal clock Disable/Enable
No debounce, 1 system clock; 2 system clocks
I2C debounce
I C Interface Configuration Options
2
S T A R T s ig n a l
fro m M a s te r
S e n d s la v e a d d r e s s
a n d R /W b it fr o m M a s te r
A c k n o w le d g e
fr o m s la v e
S e n d d a ta b y te
fro m M a s te r
A c k n o w le d g e
fr o m s la v e
S T O P s ig n a l
fro m M a s te r
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I2C Registers
There are three control registers associated with the I2C bus, SIMCTL0, SIMCTL1 and SIMAR and
one data register, SIMDR. The SIMDR register, which is shown in the above SPI section, is used
to store the data being transmitted and received on the I2C bus. Before the microcontroller writes
data to the I2C bus, the actual data to be transmitted must be placed in the SIMDR register. After
the data is received from the I2C bus, the microcontroller can read it from the SIMDR register. Any
transmission or reception of data from the I2C bus must be made via the SIMDR register.
Note that the SIMAR register also has the name SIMCTL2 which is used by the SPI function. Bits
SIMIDLE, SIMEN and bits SIM0~SIM2 in register SIMCTL0 are used by the I2C interface. The
SIMCTL0 register is shown in the above SPI section.
• SIMIDLE
The SIMIDLE bit is used to select if the I2C interface continues running when the device is in the
IDLE mode. Setting the bit high allows the I2C interface to maintain operation when the device is
in the Idle mode. Clearing the bit to zero disables any I2C operations when in the Idle mode.
This SPI/I2C idle mode control bit is located at CLKMOD register bit4.
• SIMEN
The SIMEN bit is the overall on/off control for the I2C interface. When the SIMEN bit is cleared
to zero to disable the I2C interface, the SDA and SCL lines will be in a floating condition and the
I2C operating current will be reduced to a minimum value. In this condition the pins can be used
as SEG functions. When the bit is high the I2C interface is enabled. The SIM configuration option
must have first enabled the SIM interface for this bit to be effective. Note that when the SIMEN
bit changes from low to high the contents of the I2C control registers will be in an unknown
condition and should therefore be first initialised by the application program
• SIM0~SIM2
These bits setup the overall operating mode of the SIM function. To select the I2C function, bits
SIM2~SIM0 should be set to the value 110.
• RXAK
The RXAK flag is the receive acknowledge flag. When the RXAK bit has been reset to zero it
means that a correct acknowledge signal has been received at the 9th clock, after 8 bits of data
have been transmitted. When in the transmit mode, the transmitter checks the RXAK bit to
determine if the receiver wishes to receive the next byte. The transmitter will therefore continue
sending out data until the RXAK bit is set high. When this occurs, the transmitter will release the
SDA line to allow the master to send a STOP signal to release the bus.
• SRW
The SRW bit is the Slave Read/Write bit. This bit determines whether the master device wishes to
transmit or receive data from the I2C bus. When the transmitted address and slave address match,
that is when the HAAS bit is set high, the device will check the SRW bit to determine whether it
should be in transmit mode or receive mode. If the SRW bit is high, the master is requesting to
read data from the bus, so the device should be in transmit mode. When the SRW bit is zero, the
master will write data to the bus, therefore the device should be in receive mode to read this data.
• TXAK
The TXAK flag is the transmit acknowledge flag. After the receipt of 8-bit of data, this bit will be
transmitted to the bus on the 9th clock. To continue receiving more data, this bit has to be reset to
zero before further data is received.
• HTX
The HTX flag is the transmit/receive mode bit. This flag should be set high to set the transmit
mode and low for the receive mode.
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• HBB
The HBB flag is the I2C busy flag. This flag will be high when the I2C bus is busy which will
occur when a START signal is detected. The flag will be reset to zero when the bus is free which
will occur when a STOP signal is detected.
• HASS
The HAAS flag is the address match flag. This flag is used to determine if the slave device
address is the same as the master transmit address. If the addresses match then this bit will be
high, if there is no match then the flag will be low.
• HCF
The HCF flag is the data transfer flag. This flag will be zero when data is being transferred. Upon
completion of an 8-bit data transfer the flag will go high and an interrupt will be generated.

I2C Block Diagram
I2C Control Register − SIMAR
The SIMAR register is also used by the SPI interface but has the name SIMCTL2.
The SIMAR register is the location where the 7-bit slave address of the microcontroller is stored.
Bits 1~7 of the SIMAR register define the microcontroller slave address. Bit 0 is not defined. When
a master device, which is connected to the I2C bus, sends out an address, which matches the slave
address in the SIMAR register, the microcontroller slave device will be selected. Note that the
SIMAR register is the same register as SIMCTL2 which is used by the SPI interface.
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I2C Bus Communication
Communication on the I2C bus requires four separate steps, a START signal, a slave device address
transmission, a data transmission and finally a STOP signal. When a START signal is placed on
the I2C bus, all devices on the bus will receive this signal and be notified of the imminent arrival
of data on the bus. The first seven bits of the data will be the slave address with the first bit being
the MSB. If the address of the microcontroller matches that of the transmitted address, the HAAS
bit in the SIMCTL1 register will be set and an I2C interrupt will be generated. After entering the
interrupt service routine, the microcontroller slave device must first check the condition of the
HAAS bit to determine whether the interrupt source originates from an address match or from the
completion of an 8-bit data transfer. During a data transfer, note that after the 7-bit slave address
has been transmitted, the following bit, which is the 8th bit, is the read/write bit whose value will be
placed in the SRW bit. This bit will be checked by the microcontroller to determine whether to go
into transmit or receive mode. Before any transfer of data to or from the I2C bus, the microcontroller
must initialise the bus, the following are steps to achieve this:
• Step 1
Write the slave address of the microcontroller to the I2C bus address register SIMAR.
• Step 2
Set the SIMEN bit in the SIMCTL0 register to ″1″ to enable the I2C bus.
• Step 3
Set the ESIM bit of the interrupt control register to enable the I2C bus interrupt.

I2C Bus Initialisation Flow Chart
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I2C Communication Timing Diagram
I2C Bus ISR Flow Chart
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Start Signal
The START signal can only be generated by the master device connected to the I2C bus and not by
the microcontroller, which is only a slave device. This START signal will be detected by all devices
connected to the I2C bus. When detected, this indicates that the I2C bus is busy and therefore the
HBB bit will be set. A START condition occurs when a high to low transition on the SDA line takes
place when the SCL line remains high.
Slave Address
The transmission of a START signal by the master will be detected by all devices on the I2C bus.
To determine which slave device the master wishes to communicate with, the address of the slave
device will be sent out immediately following the START signal. All slave devices, after receiving
this 7-bit address data, will compare it with their own 7-bit slave address. If the address sent out by
the master matches the internal address of the microcontroller slave device, then an internal I2C bus
interrupt signal will be generated. The next bit following the address, which is the 8th bit, defines
the read/write status and will be saved to the SRW bit of the SIMCTL1 register. The device will then
transmit an acknowledge bit, which is a low level, as the 9th bit. The microcontroller slave device
will also set the status flag HAAS when the addresses match.
As an I 2C bus interrupt can come from two sources, when the program enters the interrupt
subroutine, the HAAS bit should be examined to see whether the interrupt source has come from
a matching slave address or from the completion of a data byte transfer. When a slave address is
matched, the device must be placed in either the transmit mode and then write data to the SIMDR
register, or in the receive mode where it must implement a dummy read from the SIMDR register to
release the SCL line.
b 7
S A 6
b 0
S A 5
S A 4
S A 3
S A 2
S A 1
S A 0
N o t im p le m e n te d , r e a d a s " 0 "
I2C
d e v ic e s la v e a d d r e s s
I2C Slave Address Register – SIMAR
SRW Bit
The SRW bit in the SIMCTL1 register defines whether the microcontroller slave device wishes to
read data from the I2C bus or write data to the I2C bus. The microcontroller should examine this bit
to determine if it is to be a transmitter or a receiver. If the SRW bit is set to ″1″ then this indicates
that the master wishes to read data from the I2C bus, therefore the microcontroller slave device must
be setup to send data to the I2C bus as a transmitter. If the SRW bit is ″0″ then this indicates that the
master wishes to send data to the I2C bus, therefore the microcontroller slave device must be setup
to read data from the I2C bus as a receiver.
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Acknowledge Bit
After the master has transmitted a calling address, any slave device on the I 2C bus, whose
own internal address matches the calling address, must generate an acknowledge signal. This
acknowledge signal will inform the master that a slave device has accepted its calling address. If
no acknowledge signal is received by the master then a STOP signal must be transmitted by the
master to end the communication. When the HAAS bit is high, the addresses have matched and the
microcontroller slave device must check the SRW bit to determine if it is to be a transmitter or a
receiver. If the SRW bit is high, the microcontroller slave device should be setup to be a transmitter
so the HTX bit in the SIMCTL1 register should be set to ″1″ if the SRW bit is low then the
microcontroller slave device should be setup as a receiver and the HTX bit in the SIMCTL1 register
should be set to ″0″.
Data Byte
The transmitted data is 8-bit wide and is transmitted after the slave device has acknowledged receipt
of its slave address. The order of serial bit transmission is the MSB first and the LSB last. After
receipt of 8-bit of data, the receiver must transmit an acknowledge signal, level ″0″, before it can
receive the next data byte. If the transmitter does not receive an acknowledge bit signal from the
receiver, then it will release the SDA line and the master will send out a STOP signal to release
control of the I2C bus. The corresponding data will be stored in the SIMDR register. If setup as
a transmitter, the microcontroller slave device must first write the data to be transmitted into the
SIMDR register. If setup as a receiver, the microcontroller slave device must read the transmitted
data from the SIMDR register.
Data Timing Diagram
Receive Acknowledge Bit
When the receiver wishes to continue to receive the next data byte, it must generate an acknowledge
bit, known as TXAK, on the 9th clock. The microcontroller slave device, which is setup as a
transmitter will check the RXAK bit in the SIMCTL1 register to determine if it is to send another
data byte, if not then it will release the SDA line and await the receipt of a STOP signal from the
master.
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Peripheral Clock Output
The Peripheral Clock Output allows the device to supply external hardware with a clock signal
synchronised to the microcontroller clock.
Peripheral Clock Operation
As the peripheral clock output pin,, is shared with one of the LCD segment lines, the required pin
function is chosen via in SIMCTL0 register. The Peripheral Clock function is controlled using the
SIMCTL0 register. The clock source for the Peripheral Clock Output can originate from either the
Timer/Event Counter 0 divided by two or a divided ratio of the internal fSYS clock. The bit in the
SIMCTL0 register is the overall on/off control, setting the bit high enables the Peripheral Clock,
clearing it disables it. The required division ratio of the system clock is selected using the PCKPSC0
and PCKPSC1 bits in the same register. If the system enters the Sleep Mode this will disable the
Peripheral Clock output.
Peripheral Clock Block Diagram

Peripheral Clock Output Control – SIMCTL0
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Buzzer
Operating in a similar way to the Programmable Frequency Divider, the Buzzer function provides
a means of producing a variable frequency output, suitable for applications such as Piezo-buzzer
driving or other external circuits that require a precise frequency generator. The BZ and BZ pins
form a complementary pair, and are pin-shared with I/O pins, PA0 and PA1. A configuration option
is used to select from one of three buzzer options. The first option is for both pins PA0 and PA1 to be
used as normal I/Os, the second option is for both pins to be configured as BZ and BZ buzzer pins,
the third option selects only the PA0 pin to be used as a BZ buzzer pin with the PA1 pin retaining its
normal I/O pin function. Note that the BZ pin is the inverse of the BZ pin which together generate a
differential output which can supply more power to connected interfaces such as buzzers.
The buzzer is driven by the internal clock source,, which then passes through a divider, the division
ratio of which is selected by configuration options to provide a range of buzzer frequencies from
fS/22 to fS/29. The clock source that generates fS, which in turn controls the buzzer frequency, can
originate from three different sources, the 32768Hz oscillator, the 32K_INT oscillator or the System
oscillator/4, the choice of which is determined by the fS clock source configuration option. Note that
the buzzer frequency is controlled by configuration options, which select both the source clock for
the internal clock fS and the internal division ratio. There are no internal registers associated with the
buzzer frequency.
If the configuration options have selected both pins PA0 and PA1 to function as a BZ and BZ
complementary pair of buzzer outputs, then for correct buzzer operation it is essential that both pins
must be setup as outputs by setting bits PAC0 and PAC1 of the PAC port control register to zero.
The PA0 data bit in the PA data register must also be set high to enable the buzzer outputs, if set low,
both pins PA0 and PA1 will remain low. In this way the single bit PA0 of the PA register can be used
as an on/off control for both the BZ and BZ buzzer pin outputs. Note that the PA1 data bit in the PA
register has no control over the BZ buzzer pin PA1.

Buzzer Function
PA0/PA1 Pin Function Control
PAC Register
PAC0
PAC Register
PAC1
PA Data Register PA Data Register
PA0
PA1
0
0
1
x
PA0=BZ
PA1=BZ
0
0
0
x
PA0=″0″
PA1=″0″
0
1
1
x
PA0=BZ
PA1=input line
0
1
0
x
PA0=″0″
PA1=input line
1
0
x
D
PA0=input line
PA1=D
1
1
x
x
PA0=input line
PA0=input line
Output Function
″x" stands for don′t care; ″D″ stands for Data ″0″ or ″1″
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If configuration options have selected that only the PA0 pin is to function as a BZ buzzer pin, then
the PA1 pin can be used as a normal I/O pin. For the PA0 pin to function as a BZ buzzer pin, PA0
must be setup as an output by setting bit PAC0 of the PAC port control register to zero. The PA0
data bit in the PA data register must also be set high to enable the buzzer output, if set low pin PA0
will remain low. In this way the PA0 bit can be used as an on/off control for the BZ buzzer pin PA0.
If the PAC0 bit of the PAC port control register is set high, then pin PA0 can still be used as an input
even though the configuration option has configured it as a BZ buzzer output.
Note that no matter what configuration option is chosen for the buzzer, if the port control register has
setup the pin to function as an input, then this will override the configuration option selection and
force the pin to always behave as an input pin. This arrangement enables the pin to be used as both a
buzzer pin and as an input pin, so regardless of the configuration option chosen; the actual function
of the pin can be changed dynamically by the application program by programming the appropriate
port control register bit.
Buzzer Output Pin Control
Note: The above drawing shows the situation where both pins PA0 and PA1 are selected by
configuration option to be BZ and BZ buzzer pin outputs. The Port Control Register of both
pins must have already been setup as output. The data setup on pin PA1 has no effect on the
buzzer outputs.
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Interrupts
Interrupts are an important part of any microcontroller system. When an external event or an internal
function such as a Timer/Event Counter or an A/D converter requires microcontroller attention,
their corresponding interrupt will enforce a temporary suspension of the main program allowing the
microcontroller to direct attention to their respective needs. The device contains several external
interrupt and internal interrupts functions. The external interrupts are controlled by the action of the
external INT0, INT1 and PINT pins, while the internal interrupts are controlled by the Timer/Event
Counter overflows, the Time Base interrupt, the RTC interrupt, the SPI/I2C interrupt and the the A/D
converter interrupt.
Interrupt Registers
Overall interrupt control, which means interrupt enabling and request flag setting, is controlled by
the INTC0, INTC1, and MFIC/MFIC0/MFIC1 registers, which are located in the Data Memory. By
controlling the appropriate enable bits in these registers each individual interrupt can be enabled
or disabled. Also when an interrupt occurs, the corresponding request flag will be set by the
microcontroller. The global enable flag if cleared to zero will disable all interrupts.

Interrupt Control Register – INTC0
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Interrupt Control Register – INTC1

Interrupt Control Register – MFIC/MFIC0
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Interrupt Control Register – MFIC1
Interrupt Operation
A Timer/Event Counter overflow, Time Base, RTC overflow, SPI/I2C data transfer complete, an
end of A/D conversion or the external interrupt line being triggered will all generate an interrupt
request by setting their corresponding request flag. When this happens and if their appropriate
interrupt enable bit is set, the Program Counter, which stores the address of the next instruction to
be executed, will be transferred onto the stack. The Program Counter will then be loaded with a
new address which will be the value of the corresponding interrupt vector. The microcontroller will
then fetch its next instruction from this interrupt vector. The instruction at this vector will usually
be a JMP statement which will jump to another section of program which is known as the interrupt
service routine. Here is located the code to control the appropriate interrupt. The interrupt service
routine must be terminated with a RETI statement, which retrieves the original Program Counter
address from the stack and allows the microcontroller to continue with normal execution at the point
where the interrupt occurred.
The various interrupt enable bits, together with their associated request flags, are shown in the
accompanying diagram with their order of priority.
Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the EMI bit will
be cleared automatically. This will prevent any further interrupt nesting from occurring. However,
if other interrupt requests occur during this interval, although the interrupt will not be immediately
serviced, the request flag will still be recorded. If an interrupt requires immediate servicing while the
program is already in another interrupt service routine, the EMI bit should be set after entering the
routine, to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged,
even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service
is desired, the stack must be prevented from becoming full.
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Interrupt Structure
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Interrupt Priority
Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be
serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In case of
simultaneous requests, the following table shows the priority that is applied.
Interrupt Source
Priority
Vector
External Interrupt 0
1
04H
External Interrupt 1
2
08H
Timer/Event Counter 0 Overflow
3
0CH
Timer/Event Counter 1 Overflow
4
10H
SPI/I2C Interrupt
5
14H
Multi-function Interrupt
6
18H
The A/D converter interrupt, Real Time clock interrupt, Time Base interrupt and External Peripheral
interrupt all share the same interrupt vector which is 18H. Each of these interrupts have their own
own individual interrupt flag but also share the same MFF interrupt flag. The MFF flag will be
cleared by hardware once the Multi-function interrupt is serviced, however the individual interrupts
that have triggered the Multi-function interrupt need to be cleared by the application program.
External Interrupt
For an external interrupt to occur, the global interrupt enable bit, EMI, and external interrupt enable
bits, EEI0 and EEI1, must first be set. Additionally the correct interrupt edge type must be selected
using the INTEDGE register to enable the external interrupt function and to choose the trigger edge
type. An actual external interrupt will take place when the external interrupt request flag, EIF0 or
EIF1, is set, a situation that will occur when a transition, whose type is chosen by the edge select
bit, appears on the INT0 or INT1 pin. The external interrupt pins are pin-shared with the I/O pins
PD4 and PD5 and can only be configured as external interrupt pins if their corresponding external
interrupt enable bit in the INTC0 register has been set. The pin must also be setup as an input by
setting the corresponding PDC.4 and PDC.5 bits in the port control register. When the interrupt is
enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a
subroutine call to the external interrupt vector at location 04H or 08H, will take place. When the
interrupt is serviced, the external interrupt request flags, EIF0 or EIF1, will be automatically reset
and the EMI bit will be automatically cleared to disable other interrupts. Note that any pull-high
resistor selections on this pin will remain valid even if the pin is used as an external interrupt input.
The INTEDGE register is used to select the type of active edge that will trigger the external
interrupt. A choice of either rising and falling edge types can be chosen along with an option to
allow both edge types to trigger an external interrupt. Note that the INTEDGE register can also be
used to disable the external interrupt function.
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b 7
b 0
IN T 1 S 1 IN T 1 S 0 IN T 0 S 1 IN T 0 S 0
IN T 0 E d g e S e
IN T 0 S 1
IN
0
0
1
1
le c t
T 0 S 0
0
1
0
1
d is a b le
r is in g e d g e tr ig g e r
fa llin g e d g e tr ig g e r
d u a l e d g e tr ig g e r
IN T 1 E d g e S e le c t
IN T 1 S 1
IN T 1 S 0
0
0
1
0
0
1
1
1
d is a b le
r is in g e d g e tr ig g e r
fa llin g e d g e tr ig g e r
d u a l e d g e tr ig g e r
N o t im p le m e n te d , r e a d a s " 0 "
Interrupt Active Edge Register – INTEDGE
The external interrupt pins are connected to an internal filter to reduce the possibility of unwanted
external interrupts due to adverse noise or spikes on the external interrupt input signal. As this
internal filter circuit will consume a limited amount of power, a configuration option is provided
to switch off the filter function, an option which may be beneficial in power sensitive applications,
but in which the integrity of the input signal is high. Care must be taken when using the filter on/off
configuration option as it will be applied not only to both the external interrupt pins but also to the
Timer/Event Counter external input pins. Individual external interrupt or Timer/Event Counter pins
cannot be selected to have a filter on/off function.
External Peripheral Interrupt
The External Peripheral Interrupt operates in a similar way to the external interrupt and is contained
within the Multi-function interrupt.
For an external peripheral interrupt to occur, the global interrupt enable bit, EMI, external peripheral
interrupt enable bit, EPI, and Multi-function interrupt enable bit, EMFI, must first be set. An actual
external peripheral interrupt will take place when the external interrupt request flag, PEF, is set, a
situation that will occur when a negative transition, appears on the PINT pin. The external peripheral
interrupt pin is pin-shared with one of the segment pins, and is configured as a peripheral interrupt
pin via a configuration option. When the interrupt is enabled, the stack is not full and a negative
transition type appears on the external peripheral interrupt pin, a subroutine call to the Multi-function
interrupt vector at location 18H, will take place. When the external peripheral interrupt is serviced,
the EMI bit will be cleared to disable other interrupts, however only the MFF interrupt request flag
will be reset. As the PEF flag will not be automatically reset, it has to be cleared by the application
program.
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Timer/Event Counter Interrupt
For a Timer/Event Counter 0 or Timer/Event Counter 1 interrupt to occur, the global interrupt enable
bit, EMI, and the corresponding timer interrupt enable bit, ET0I or ET1I must first be set. An actual
Timer/Event Counter interrupt will take place when the Timer/Event Counter request flag, T0F or
T1F is set, a situation that will occur when the Timer/Event Counter overflows. When the interrupt
is enabled, the stack is not full and a Timer/Event Counter overflow occurs, a subroutine call to
the timer interrupt vector at location 0CH or 10H, will take place. When the interrupt is serviced,
the timer interrupt request flag, T0F or T1F, will be automatically reset and the EMI bit will be
automatically cleared to disable other interrupts.
Timer Event Counter 0 and Timer/Event Counter 1 have their own individual interrupt vectors,
however the interrupt vector for Timer/Event Counter 2 is contained within the Multi-function
Interrupt. For a Timer/Event Counter 2 interrupt to occur, the global interrupt enable bit, EMI,
Timer/Event Counter 2 interrupt enable bit, ET2I, and Multi-function interrupt enable bit, EMFI,
must first be set. An actual external peripheral interrupt will take place when the Timer/Event
Counter 2 request flag, T2F, is set, a situation that will occur when the Timer/Event Counter 2
overflows. When the interrupt is enabled, the stack is not full and the Timer/Event Counter 2
overflows, a subroutine call to the Multi-function interrupt vector at location 18H, will take place.
When the Timer/Event 2 interrupt is serviced, the EMI bit will be cleared to disable other interrupts,
however only the MFF interrupt request flag will be reset. As the T2F flag will not be automatically
reset, it has to be cleared by the application program.
A/D Interrupt
The A/D Interrupt is contained within the Multi-function Interrupt.
For an A/D Interrupt to be generated, the global interrupt enable bit, EMI, A/D Interrupt enable bit,
EADI, and Multi-function interrupt enable bit, EMFI, must first be set. An actual A/D Interrupt will
take place when the A/D Interrupt request flag, ADF, is set, a situation that will occur when the A/D
conversion process has finished. When the interrupt is enabled, the stack is not full and the A/D
conversion process has ended, a subroutine call to the Multi-function interrupt vector at location
18H, will take place. When the A/D Interrupt is serviced, the EMI bit will be cleared to disable other
interrupts, however only the MFF interrupt request flag will be reset. As the ADF flag will not be
automatically reset, it has to be cleared by the application program.
SPI/I2C Interface Interrupt
For an SPI/I2C interrupt to occur, the global interrupt enable bit, EMI, and the corresponding
interrupt enable bit, ESIM must be first set. An actual SPI/I2C interrupt will take place when the
SPI/I2C interrupt request flag, SIMF, is set, a situation that will occur when a byte of data has been
transmitted or received by the SPI/I2C interface or when an I2C address match occurs. When the
interrupt is enabled, the stack is not full and a byte of data has been transmitted or received by the
SPI/I2C interface or an I2C address match occurs, a subroutine call to the SPI/I2C interrupt vector at
location 14H, will take place. When the interrupt is serviced, the SPI/I2C request flag, SIMF will be
automatically reset and the EMI bit will be automatically cleared to disable other interrupts.
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Multi-function Interrupt
An additional interrupt known as the Multi-function interrupt is provided. Unlike the other
interrupts, this interrupt has no independent source, but rather is formed from four or five other
existing interrupt sources, namely the A/D Converter interrupt, Time Base interrupt, Real Time
Clock interrupt, External Peripheral interrupt and the Timer 2 overflow interrupt.
For a Multi-function interrupt to occur, the global interrupt enable bit, EMI, and the Multi-function
interrupt enable bit, EMFI, must first be set. An actual Multi-function interrupt will take place
when the Multi-function interrupt request flag, MFF, is set. This will occur when either a Time
Base overflow, a Real Time Clock overflow, an A/D conversion completion, an External Peripheral
Interrupt or Timer 2 overflow interrupt is generated. When the interrupt is enabled and the stack is not
full, and either one of the interrupts contained within the Multi-function interrupt occurs, a subroutine
call to the Multi-function interrupt vector at location 018H will take place. When the interrupt is
serviced, the Multi-Function request flag, MFF, will be automatically reset and the EMI bit will be
automatically cleared to disable other interrupts. However, it must be noted that the request flags
from the original source of the Multi-function interrupt, namely the Time-Base interrupt, Real Time
Clock interrupt, A/D Converter interrupt, External Peripheral interrupt or Timer 2 overflow interrupt
will not be automatically reset and must be manually reset by the application program.
Real Time Clock Interrupt
The Real Time Clock Interrupt is contained within the Multi-function Interrupt.
For a Real Time Clock interrupt to be generated, the global interrupt enable bit, EMI, Real Time
Clock interrupt enable bit, ERTI, and Multi-function interrupt enable bit, EMFI, must first be set. An
actual Real Time Clock interrupt will take place when the Real Time Clock request flag, RTF, is set,
a situation that will occur when the Real Time Clock overflows. When the interrupt is enabled, the
stack is not full and the Real Time Clock overflows, a subroutine call to the Multi-function interrupt
vector at location 18H, will take place. When the Real Time Clock interrupt is serviced, the EMI bit
will be cleared to disable other interrupts, however only the MFF interrupt request flag will be reset.
As the RTF flag will not be automatically reset, it has to be cleared by the application program.
Similar in operation to the Time Base interrupt, the purpose of the RTC interrupt is also to provide
an interrupt signal at fixed time periods. The RTC interrupt clock source originates from the internal
clock source fS. This fS input clock first passes through a divider, the division ratio of which is
selected by programming the appropriate bits in the RTCC register to obtain longer RTC interrupt
periods whose value ranges from 28/fS~215/fS. The clock source that generates fS, which in turn
controls the RTC interrupt period, can originate from three different sources, the 32768Hz oscillator,
32K_INT oscillator or the System oscillator/4, the choice of which is determine by the fS clock
source configuration option.
Note that the RTC interrupt period is controlled by both configuration options and an internal
register RTCC. A configuration option selects the source clock for the internal clock fS, and the
RTCC register bits RT2, RT1 and RT0 select the division ratio. Note that the actual division ratio
can be programmed from 28 to 215.

RTC Interrupt
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Real Time Clock Control Register – RTCC
Time Base Interrupt
The Time Base Interrupt is contained within the Multi-function Interrupt.
For a Time Base Interrupt to be generated, the global interrupt enable bit, EMI,Time Base Interrupt
enable bit, ETBI, and Multi-function interrupt enable bit, EMFI, must first be set. An actual Time
Base Interrupt will take place when the Time Base Interrupt request flag, TBF, is set, a situation that
will occur when the Time Base overflows. When the interrupt is enabled, the stack is not full and the
Time Base overflows, a subroutine call to the Multi-function interrupt vector at location 18H, will
take place. When the Time Base Interrupt is serviced, the EMI bit will be cleared to disable other
interrupts, however only the MFF interrupt request flag will be reset. As the TBF flag will not be
automatically reset, it has to be cleared by the application program.
The purpose of the Time Base function is to provide an interrupt signal at fixed time periods. The
Time Base interrupt clock source originates from the Time Base interrupt clock source originates
from the internal clock source fS. This fS input clock first passes through a divider, the division ratio
of which is selected by configuration options to provide longer Time Base interrupt periods. The
Time Base interrupt time-out period ranges from 212/fS~215/fS. The clock source that generates fS,
which in turn controls the Time Base interrupt period, can originate from three different sources, the
32768Hz oscillator, the 32K_INT internal oscillator or the System oscillator/4, the choice of which
is determine by the fS clock source configuration option.
Essentially operating as a programmable timer, when the Time Base overflows it will set a Time
Base interrupt flag which will in turn generate an Interrupt request via the Multi-function Interrupt
vector.

Time Base Interrupt
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Programming Considerations
By disabling the interrupt enable bits, a requested interrupt can be prevented from being serviced,
however, once an interrupt request flag is set, it will remain in this condition in the INTC0, INTC1
and MFIC registers until the corresponding interrupt is serviced or until the request flag is cleared by
the application program.
It is recommended that programs do not use the ″CALL subroutine″ instruction within the interrupt
subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately
in some applications. If only one stack is left and the interrupt is not well controlled, the original
control sequence will be damaged once a ″CALL subroutine″ is executed in the interrupt subroutine.
All of these interrupts have the capability of waking up the processor when in the Power Down
Mode.
Only the Program Counter is pushed onto the stack. If the contents of the status or other registers are
altered by the interrupt service program, which may corrupt the desired control sequence, then the
contents should be saved in advance.
Reset and Initialisation
A reset function is a fundamental part of any microcontroller ensuring that the device can be set
to some predetermined condition irrespective of outside parameters. The most important reset
condition is after power is first applied to the microcontroller. In this case, internal circuitry will
ensure that the microcontroller, after a short delay, will be in a well defined state and ready to
execute the first program instruction. After this power-on reset, certain important internal registers
will be set to defined states before the program commences. One of these registers is the Program
Counter, which will be reset to zero forcing the microcontroller to begin program execution from the
lowest Program Memory address.
In addition to the power-on reset, situations may arise where it is necessary to forcefully apply
a reset condition when the microcontroller is running. One example of this is where after power
has been applied and the microcontroller is already running, the RES line is forcefully pulled low.
In such a case, known as a normal operation reset, some of the microcontroller registers remain
unchanged allowing the microcontroller to proceed with normal operation after the reset line is
allowed to return high. Another type of reset is when the Watchdog Timer overflows and resets the
microcontroller. All types of reset operations result in different register conditions being setup.
Another reset exists in the form of a Low Voltage Reset, LVR, where a full reset, similar to the RES
reset is implemented in situations where the power supply voltage falls below a certain threshold.
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Reset Functions
There are five ways in which a microcontroller reset can occur, through events occurring both
internally and externally:
• Power-on Reset
The most fundamental and unavoidable reset is the one that occurs after power is first applied to
the microcontroller. As well as ensuring that the Program Memory begins execution from the first
memory address, a power-on reset also ensures that certain other registers are preset to known
conditions. All the I/O port and port control registers will power up in a high condition ensuring
that all pins will be first set to inputs.
Although the microcontroller has an internal RC reset function, if the VDD power supply rise time
is not fast enough or does not stabilise quickly at power-on, the internal reset function may be
incapable of providing proper reset operation. For this reason it is recommended that an external
RC network is connected to the RES pin, whose additional time delay will ensure that the RES pin
remains low for an extended period to allow the power supply to stabilise. During this time delay,
normal operation of the microcontroller will be inhibited. After the RES line reaches a certain
voltage value, the reset delay time tRSTD is invoked to provide an extra delay time after which
the microcontroller will begin normal operation. The abbreviation SST in the figures stands for
System Start-up Timer.
Power-On Reset Timing Chart
For most applications a resistor connected between VDD and the RES pin and a capacitor
connected between VSS and the RES pin will provide a suitable external reset circuit. Any
wiring connected to the RES pin should be kept as short as possible to minimise any stray noise
interference.
For applications that operate within an environment where more noise is present the Reset Circuit
shown is recommended.
More information regarding external reset circuits is located in Application Note HA0075E on
the Holtek website.
Note: "*" It is recommended that this component is added for added ESD protection
"**" It is recommended that this component is added in environments where power
line noise is significant
External RES Circuit
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• RES Pin Reset
This type of reset occurs when the microcontroller is already running and the RES pin is
forcefully pulled low by external hardware such as an external switch. In this case as in the case
of other reset, the Program Counter will reset to zero and program execution initiated from this
point.
RES Reset Timing Chart
• Low Voltage Reset − LVR
The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage
of the device, which is selected via a configuration option. If the supply voltage of the device
drops to within a range of 0.9V~VLVR such as might occur when changing the battery, the LVR
will automatically reset the device internally. The LVR includes the following specifications:
For a valid LVR signal, a low voltage, i.e., a voltage in the range between 0.9V~VLVR must exist
for greater than the value tLVR specified in the A.C. characteristics. If the low voltage state does
not exceed 1ms, the LVR will ignore it and will not perform a reset function. One of a range of
specified voltage values for VLVR can be selected using configuration options. The VLVR value will
be selected as a pair in conjunction with a Low Voltage Detect value.
Low Voltage Reset Timing Chart
• Watchdog Time-out Reset during Normal Operation
The Watchdog time-out Reset during normal operation is the same as a hardware RES pin reset
except that the Watchdog time-out flag TO will be set to ″1″.
WDT Time-out Reset during Normal Operation Timing Chart
• Watchdog Time-out Reset during Power Down
The Watchdog time-out Reset during Power Down is a little different from other kinds of reset.
Most of the conditions remain unchanged except that the Program Counter and the Stack Pointer
will be cleared to ″0″ and the TO flag will be set to ″1″. Refer to the A.C. Characteristics for tSST
details.
WDT Time-out Reset during Power Down Timing Chart
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Reset Initial Conditions
The different types of reset described affect the reset flags in different ways. These flags, known
as PDF and TO are located in the status register and are controlled by various microcontroller
operations, such as the Power Down function or Watchdog Timer. The reset flags are shown in the
table:
TO
PDF
RESET Conditions
0
0
RES reset during power-on
u
u
RES or LVR reset during normal operation
1
u
WDT time-out reset during normal operation
1
1
WDT time-out reset during Power Down
″u″ stands for unchanged
The following table indicates the way in which the various components of the microcontroller are
affected after a power-on reset occurs.
Item
Condition After RESET
Program Counter
Reset to zero
Interrupts
All interrupts will be disabled
WDT
Clear after reset, WDT begins counting
Timer/Event Counter
Timer Counter will be turned off
Prescaler
The Timer Counter Prescaler will be cleared
Input/Output Ports
I/O ports will be setup as inputs
Stack Pointer
Stack Pointer will point to the top of the stack
The different kinds of resets all affect the internal registers of the microcontroller in different ways.
To ensure reliable continuation of normal program execution after a reset occurs, it is important to
know what condition the microcontroller is in after a particular reset occurs. The following table
describes how each type of reset affects each of the microcontroller internal registers. Note that
where more than one package type exists the table will reflect the situation for the larger package
type.
HT56R62
Reset
(Power-on)
RES Reset
(Normal Operation)
Time-out
(Normal Operation)
Time-out
(HALT)
MP0
−xxx xxxx
−uuu uuuu
−uuu uuuu
−uuu uuuu
MP1
−xxx xxxx
−uuu uuuu
−uuu uuuu
−uuu uuuu
BP
−−−− −000
−−−− −000
−−−− −000
−−−− −uuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
PCL
0000 0000
0000 0000
0000 0000
0000 0000
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
−−xx xxxx
−−uu uuuu
−−uu uuuu
−−uu uuuu
RTCC
−−00 0111
−−00 0111
−−00 0111
−−uu uuuu
STATUS
−−00 xxxx
−−uu uuuu
−−1u uuuu
−−11 uuuu
INTC0
−000 0000
−000 0000
−000 0000
−uuu uuuu
TMR0
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR0C
00−0 1000
00−0 1000
00−0 1000
uu−u uuuu
TMR1
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
Register
TMR1C
00−0 1000
00−0 1000
00−0 1000
uu−u uuuu
PA
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
−−11 1111
−−11 1111
−−11 1111
−−uu uuuu
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Reset
(Power-on)
RES Reset
(Normal Operation)
Time-out
(Normal Operation)
Time-out
(HALT)
PBC
−−11 1111
−−11 1111
−−11 1111
−−uu uuuu
PD
−111 −111
−111 −111
−111 −111
−uuu −uuu
PDC
−111 −111
−111 −111
−111 −111
−uuu −uuu
Register
PWM0L
0000 −−−0
0000 −−−0
0000 −−−0
uuuu −−−u
PWM0H
0000 0000
0000 0000
0000 0000
uuuu uuuu
PWM1L
0000 −−−0
0000 −−−0
0000 −−−0
uuuu −−−u
PWM1H
0000 0000
0000 0000
0000 0000
uuuu uuuu
INTC1
−000 −000
−000 −000
−000 −000
−uuu −uuu
PWM2L
0000 −−−0
0000 −−−0
0000 −−−0
uuuu −−−u
PWM2H
0000 0000
0000 0000
0000 0000
uuuu uuuu
ADRL
xxxx −−−−
xxxx −−−−
xxxx −−−−
uuuu −−−−
ADRH
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
ADCR
0100 0000
0100 0000
0100 0000
uuuu uuuu
ACSR
10−− −000
10−− −000
10−− −000
uu−− −uuu
CLKMOD
0000 0x11
0000 0x11
0000 0x11
uuuu uuuu
PAWU
0000 0000
0000 0000
0000 0000
uuuu uuuu
PAPU
0000 0000
0000 0000
0000 0000
uuuu uuuu
PBPU
−−11 1111
−−11 1111
−−11 1111
−−uu uuuu
PDPU
−111 −111
−111 −111
−111 −111
−uuu −uuu
INTEDGE
−−−− 0000
−−−− 0000
−−−− 0000
−−−− uuuu
LCDCTRL
000− 0000
000− 0000
000− 0000
uuu− uuuu
LCDOUT1
−−−− −−−0
−−−− −−−0
−−−− −−−0
−−−− −−−u
LCDOUT2
0000 0000
0000 0000
0000 0000
uuuu uuuu
MISC
0000 1010
0000 1010
0000 1010
uuuu uuuu
MFIC
0000 0000
0000 0000
0000 0000
uuuu uuuu
SIMCTL0
1110 0000
1110 0000
1110 0000
uuuu uuuu
SIMCTL1
1000 00−1
1000 00−1
1000 00−1
uuuu uu−u
SIMDR
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
SIMAR/SIMCTL2
0000 0000
0000 0000
0000 0000
uuuu uuuu
Note: ″u″ stands for unchanged
″x″ stands for unknown
″−″ stands for unimplemented
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HT56R642/HT56R644/HT56R654/HT56R656
TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
HT56R65/HT56R642/HT56R644/HT56R654/HT56R656
Reset
(Power-on)
RES Reset
(Normal Operation)
Time-out
(Normal Operation)
Time-out
(HALT)
MP0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
BP
−−−− −000
−−−− −000
−−−− −000
−−−− −uuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
Register
PCL
0000 0000
0000 0000
0000 0000
0000 0000
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
RTCC
−−00 0111
−−00 0111
−−00 0111
−−uu uuuu
STATUS
−−00 xxxx
−−uu uuuu
−−1u uuuu
−−11 uuuu
INTC0
0000 0000
0000 0000
0000 0000
uuuu uuuu
TMR0
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR0C
00−0 1000
00−0 1000
00−0 1000
uu−u uuuu
TMR1H
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR1L
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR1C
0000 1−−−
0000 1−−−
0000 1−−−
uuuu u−−−
TMR2
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR2C
00−0 1000
00−0 1000
00−0 1000
uu−u uuuu
PA
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
1111 1111
1111 1111
1111 1111
uuuu uuuu
PBC
1111 1111
1111 1111
1111 1111
uuuu uuuu
PD
1111 1111
1111 1111
1111 1111
uuuu uuuu
PDC
1111 1111
1111 1111
1111 1111
uuuu uuuu
PWM0L
0000 −−−0
0000 −−−0
0000 −−−0
uuuu −−−u
PWM0H
0000 0000
0000 0000
0000 0000
uuuu uuuu
PWM1L
0000 −−−0
0000 −−−0
0000 −−−0
uuuu −−−u
PWM1H
0000 0000
0000 0000
0000 0000
uuuu uuuu
INTC1
−000 −−00
−000 −−00
−000 −−00
−uuu −−uu
PWM2L
0000 −−−0
0000 −−−0
0000 −−−0
uuuu −−−u
PWM2H
0000 0000
0000 0000
0000 0000
uuuu uuuu
PWM3L
0000 −−−0
0000 −−−0
0000 −−−0
uuuu −−−u
PWM3H
0000 0000
0000 0000
0000 0000
uuuu uuuu
ADRL
xxxx −−−−
xxxx −−−−
xxxx −−−−
uuuu −−−−
ADRH
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
ADCR
0100 0000
0100 0000
0100 0000
uuuu uuuu
ACSR
10−− −000
10−− −000
10−− −000
uu−− −uuu
CLKMOD
0000 0x11
0000 0x11
0000 0x11
uuuu uuuu
PAWU
0000 0000
0000 0000
0000 0000
uuuu uuuu
PAPU
0000 0000
0000 0000
0000 0000
uuuu uuuu
PBPU
0000 0000
0000 0000
0000 0000
uuuu uuuu
PDPU
0000 0000
0000 0000
0000 0000
uuuu uuuu
INTEDGE
−−−− 0000
−−−− 0000
−−−− 0000
−−−− uuuu
LCDCTRL
0000 0000
0000 0000
0000 0000
uuuu uuuu
LCDOUT1
−−−− −−00
−−−− −−00
−−−− −−00
−−−− −−uu
LCDOUT2
0000 0000
0000 0000
0000 0000
uuuu uuuu
MISC
0000 1010
0000 1010
0000 1010
uuuu uuuu
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TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
Reset
(Power-on)
RES Reset
(Normal Operation)
Time-out
(Normal Operation)
Time-out
(HALT)
MFIC/MFIC0
0000 0000
0000 0000
0000 0000
uuuu uuuu
MFIC1
−−−0 −−−0
−−−0 −−−0
−−−0 −−−0
−−−u −−−u
SIMCTL0
1110 0000
1110 0000
1110 0000
uuuu uuuu
SIMCTL1
1000 00−1
1000 00−1
1000 00−1
uuuu uu−u
SIMDR
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
SIMAR/SIMCTL2
0000 0000
0000 0000
0000 0000
uuuu uuuu
Register
Note: ″u″ stands for unchanged
″x″ stands for unknown
″−″ stands for unimplemented
Oscillator
Various oscillator options offer the user a wide range of functions according to their various
application requirements. Five types of system clocks can be selected while various clock source
options for the Watchdog Timer are provided for maximum flexibility. All oscillator options are
selected through the configuration options.
System Clock Configurations
There are five methods of generating the system clock, two high oscillators, two low oscillators and
an externally supplied clock. The two high oscillators are the external crystal/ceramic oscillator and
the external RC network. The two low oscillators are the fully integrated 32K_INT oscillator and
the external 32768Hz oscillator. Selecting whether the low or high oscillator is used as the system
oscillator is implemented using the HLCLK bit in the CLKMOD register. The source clock for the
high and low oscillators is chosen via configuration options. The frequency of the slow oscillator is
also determined using the SLOWC0~SLOWC2 bits in the CLKMOD register.
System Crystal/Ceramic Oscillator
After selecting the external crystal configuration option, the simple connection of a crystal across
OSC1 and OSC2, is normally all that is required to create the necessary phase shift and feedback for
oscillation, without requiring external capacitors. However, for some crystal types and frequencies,
to ensure oscillation, it may be necessary to add two small value capacitors, C1 and C2. Using a
ceramic resonator will usually require two small value capacitors, C1 and C2, to be connected as
shown for oscillation to occur. The values of C1 and C2 should be selected in consultation with the
crystal or resonator manufacturer′s specification. In most applications, resistor RP1 is not required,
however for those applications where the LVR function is not used, RP1 may be necessary to ensure
the oscillator stops running when VDD falls below its operating range. The internal oscillator circuit
contains a filter circuit to reduce the possibility of erratic operation due to noise on the oscillator
pins. An additional configuration option must be setup to configure the device according to whether
the oscillator frequency is high, defined as equal to or above 1MHz, or low, which is defined as
below 1MHz.
More information regarding oscillator applications is located on the Holtek website.
Crystal/Ceramic Oscillator
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Crystal Oscillator C1 and C2 Values
Crystal Frequency
C1
C2
12MHz
—
—
8MHz
—
—
4MHz
—
—
1MHz
—
—
455kHz (see Note 2)
10pF
10pF
Note: 1. C1 and C2 values are for guidance only.
2. XTAL mode configuration option: 455kHz.
3. RP1=5MΩ~10MΩ is recommended.
Crystal Recommended Capacitor Values
External System RC Oscillator
After selecting the correct configuration option, using the external system RC oscillator requires
that a resistor, with a value between 47kΩ and 1.5MΩ, is connected between OSC1 and VDD, and
a 470pF capacitor is connected to ground. Although this is a cost effective oscillator configuration,
the oscillation frequency can vary with VDD, temperature and process variations and is therefore
not suitable for applications where timing is critical or where accurate oscillator frequencies are
required. For the value of the external resistor ROSC refer to the Appendix section for typical RC
Oscillator vs. Temperature and VDD characteristics graphics.
Note that an internal capacitor together with the external resistor, ROSC, are the components which
determine the frequency of the oscillator. The external capacitor shown on the diagram does not
influence the frequency of oscillation. This external capacitor should be added to improve oscillator
stability if the open-drain OSC2 output is utilised in the application circuit. The internal oscillator
circuit contains a filter circuit to reduce the possibility of erratic operation due to noise on the
oscillator pins.
RC Oscillator
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TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
Internal 32K_INT Oscillator
When microcontrollers enter a power down condition, their internal clocks are normally switched
off to stop microcontroller activity and to conserve power. However, in many microcontroller
applications it may be necessary to keep some internal functions operational, such as timers,
even when the microcontroller is in the Power-down mode. To do this, the device has a 32K_INT
oscillator, which is a fully integrated free running RC oscillator with a typical period of 31.2µs at
5V, requiring no external components. It is selected via configuration option. When the device enters
the Power Down Mode, the system clock will stop running, however the 32K_INT oscillator will
continue to run if selected to keep various internal functions operational.
Internal 32K_INT Oscillator
External 32768Hz Oscillator
With a function similar to the internal 32K-INT 32KHz oscillator, that is to keep some device
functions operational during power down, this device also has an external 32768Hz oscillator. This
oscillator also remains active at all times, even when the microcontroller is in the Power-down
mode. This clock source has a fixed frequency of 32768Hz and requires a 32768Hz crystal to be
connected between pins OSC3 and OSC4.
The external resistor and capacitor components connected to the 32768Hz crystal are not necessary
to provide oscillation. For applications where precise frequencies are essential, these components
may be required to provide frequency compensation due to different crystal manufacturing
tolerances.
A configuration option selects whether the external 32768Hz oscillator or the internal 32K_INT
oscillator is selected. Selecting low frequency oscillators for use as a system oscillator is implmented
using bits in the CLKMOD register.
During power-up there is a time delay associated with the 32768Hz oscillator waiting for it to
start-up. To minimise this time delay, bit 4 of the RTCC register, known as the QOSC bit, is provided
to have a quick start-up function. During a power-up condition, this bit will be cleared to zero which
will initiate the 32768Hz oscillator quick start-up function. However, as there is additional power
consumption associated with this quick start-up function, to reduce power consumption after start-up
takes place, it is recommended that the application program should set the QOSC bit high for about
2 seconds after power-on. It should be noted that, no matter what condition the QOSC bit is set
to, the 32768Hz oscillator will always function normally, only there is more power consumption
associated with the quick start-up function.
External 32768Hz Oscillator
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TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
32768Hz Oscillator C1 and C2 Values
Crystal Frequency
C3
C4
32768Hz
8pF
10pF
Note: 1. C3 and C4 values are for guidance only.
2. RP2=5M~10MΩ is recommended.
32768 Hz Crystal Recommended Capacitor Values
External Oscillator
The system clock can also be supplied by an externally supplied clock giving users a method of
synchronising their external hardware to the microcontroller operation. This is selected using
a configuration option and supplying the clock on pin OSC1. Pin OSC2 should be left floating
if the external oscillator is used. The internal oscillator circuit contains a filter circuit to reduce
the possibility of erratic operation due to noise on the oscillator pin, however as the filter circuit
consumes a certain amount of power, a oscillator configuration option exists to turn this filter off.
Not using the internal filter should be considered in power sensitive applications and where the
externally supplied clock is of a high integrity and supplied by a low impedance source.
System Operating Modes
The devices have the ability to operate in several different modes. This range of operating modes,
known as Normal Mode, Slow Mode, Idle Mode and Sleep Mode, allow the devices to run using
a wide range of different slow and fast clock sources. The devices also possess the ability to
dynamically switch between different clocks and operating modes. With this choice of operating
functions users are provided with the flexibility to ensure they obtain optimal performance from the
device according to their application specific requirements.
Clock Sources
In discussing the system clocks for the devices, they can be seen as having a dual clock mode. These
dual clocks are what are known as a High Oscillator and the other as a Low Oscillator. The High and
Low Oscillator are the system clock sources and can be selected dynamically using the HLCLK bit
in the CLKMOD register.
The High Oscillator has the internal name fM whose source is selected using a configuration option
from a choice of either an external crystal/resonator, external RC oscillator or external clock source.
The Low Oscillator clock source, has the internal name fSL, whose source is also selected by
configuration option from a choice of either an external 32768Hz oscillator or the internal 32K_INT
oscillator. This internal fSL, fM clock, is further modified by the SLOWC0~SLOWC2 bits in the
CLKMOD register to provide the low frequency clock source fSLOW.
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TinyPowerTM A/D Type with LCD 8-Bit OTP MCU

Clock Control Register – CLKMOD
An additional sub internal clock, with the internal name fSUB, is a 32kHz clock source which can be
sourced from either the internal 32K_INT oscillator or an external 32768 Hz crystal, selected by
configuration option. Together with fSYS/4, it is used as a clock source for certain internal functions
such as the LCD driver, Watchdog Timer, Buzzer, RTC Interrupt and Time Base Interrupt. The LCD
clock source is the fSUB clock source divided by 8, giving a frequency of 4kHz. The internal clock fS,
is simply a choice of either fSUB or fSYS/4, using a configuration option.
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TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
Operating Modes
After the correct clock source configuration selections are made, overall operation of the chosen
clock is achieved using the CLKMOD register. A combination of the HLCLK and IDLEN bits in the
CLKMOD register and use of the HALT instruction determine in which mode the device will be run.
The devices can operate in the following Modes.
• Normal Mode
fM on, fSLOW on, fSYS=fM, CPU on, fS on, fLCD on/off depending upon the LCDEN bit, fWDT on/off
depending upon the WDT configuration option and WDT control register.
• Slow Mode0
fM off, fSLOW=32K_INT oscillator or the 32768Hz oscillator, fSYS=fSLOW, CPU on, fS on, fLCD on/off
depending upon the LCDEN bit, fWDT on/off depending upon the WDT configuration option and
WDT control register.
• Slow Mode1
fM on, fSLOW=fM/2~fM/64, fSYS=fSLOW, CPU on, fS on, fLCD on/off depending upon the LCDEN bit,
fWDT on/off depending upon the WDT configuration option and WDT control register.
• Idle Mode
fM, fSLOW, fSYS off, CPU off; fSUB on, fS on/off by selecting fSUB or fSYS/4, fLCD on/off depending
upon the LCDEN bit, fWDT on/off depending upon the WDT configuration option and WDT
control register.
• Sleep Mode
fM, fSLOW, fSYS, fS, fLCD off, CPU off; fSUB, fWDT on/off depending upon the WDT configuration
option and WDT control register.
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TinyPowerTM A/D Type with LCD 8-Bit OTP MCU

Dual Clock Mode Operation
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TinyPowerTM A/D Type with LCD 8-Bit OTP MCU

Dual Clock Mode Structure
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TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
Power Down Mode and Wake-up
Power Down Mode
All of the Holtek microcontrollers have the ability to enter a Power Down Mode. When the device
enters this mode, the normal operating current, will be reduced to an extremely low standby current
level. This occurs because when the device enters the Power Down Mode, the system oscillator
is stopped which reduces the power consumption to extremely low levels, however, as the device
maintains its present internal condition, it can be woken up at a later stage and continue running,
without requiring a full reset. This feature is extremely important in application areas where the
MCU must have its power supply constantly maintained to keep the device in a known condition but
where the power supply capacity is limited such as in battery applications.
Entering the Power Down Mode
There is only one way for the device to enter the Power Down Mode and that is to execute the
″HALT″ instruction in the application program. When this instruction is executed, the following will
occur:
• The system oscillator will stop running and the application program will stop at the ″HALT″
instruction.
• The Data Memory contents and registers will maintain their present condition.
• The WDT will be cleared and resume counting if the WDT clock source is selected to come from
the WDT oscillator. The WDT will stop if its clock source originates from the system clock.
• The I/O ports will maintain their present condition.
• In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,
will be cleared.
Standby Current Considerations
As the main reason for entering the Power Down Mode is to keep the current consumption of the
MCU to as low a value as possible, perhaps only in the order of several micro-amps, there are
other considerations which must also be taken into account by the circuit designer if the power
consumption is to be minimized. Special attention must be made to the I/O pins on the device. All
high-impedance input pins must be connected to either a fixed high or low level as any floating input
pins could create internal oscillations and result in increased current consumption. This also applies
to devices which have different package types, as there may be undonbed pins, which must either
be setup as outputs or if setup as inputs must have pull-high resistors connected. Care must also be
taken with the loads, which are connected to I/O pins, which are setup as outputs. These should be
placed in a condition in which minimum current is drawn or connected only to external circuits that
do not draw current, such as other CMOS inputs. Also note that additional standby current will also
be required if the configuration options have enabled the Watchdog Timer internal oscillator.
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TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
Wake-up
After the system enters the Power Down Mode, it can be woken up from one of various sources
listed as follows:
• An external reset
• An external falling edge on Port A
• A system interrupt
• A WDT overflow
If the system is woken up by an external reset, the device will experience a full system reset,
however, if the device is woken up by a WDT overflow, a Watchdog Timer reset will be initiated.
Although both of these wake-up methods will initiate a reset operation, the actual source of the
wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a
system power-up or executing the clear Watchdog Timer instructions and is set when executing the
″HALT″ instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only
resets the Program Counter and Stack Pointer, the other flags remain in their original status.
Each pin on Port A can be setup via an individual configuration option to permit a negative transition
on the pin to wake-up the system. When a Port A pin wake-up occurs, the program will resume
execution at the instruction following the ″HALT″ instruction.
If the system is woken up by an interrupt, then two possible situations may occur. The first is where
the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the
program will resume execution at the instruction following the ″HALT″ instruction. In this situation,
the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced
later when the related interrupt is finally enabled or when a stack level becomes free. The other
situation is where the related interrupt is enabled and the stack is not full, in which case the regular
interrupt response takes place. If an interrupt request flag is set to ″1″ before entering the Power
Down Mode, the wake-up function of the related interrupt will be disabled.
No matter what the source of the wake-up event is, once a wake-up situation occurs, a time period
equal to 1024 system clock periods will be required before normal system operation resumes.
However, if the wake-up has originated due to an interrupt, the actual interrupt subroutine execution
will be delayed by an additional one or more cycles. If the wake-up results in the execution of the
next instruction following the ″HALT″ instruction, this will be executed immediately after the 1024
system clock period delay has ended.
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TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
Low Voltage Detector − LVD
The Low Voltage Detect internal function provides a means for the user to monitor when the power
supply voltage falls below a certain fixed level as specified in the DC characteristics.
LVD Operation
The LVD function must be first enabled via a configuration option after which bits 3 and 5 of the
RTCC register are used to control the overall function of the LVD. Bit 3 is the enable/disable control
bit and is known as LVDC, when set low the overall function of the LVD will be disabled. Bit 5 is
the LVD detector output bit and is known as LVDO. Under normal operation, and when the power
supply voltage is above the specified VLVD value in the DC characteristic section, the LVDO bit will
remain at a zero value. If the power supply voltage should fall below this VLVD value then the LVDO
bit will change to a high value indicating a low voltage condition. Note that the LVDO bit is a readonly bit. By polling the LVDO bit in the RTCC register, the application program can therefore
determine the presence of a low voltage condition.
After power-on, or after a reset, the LVD will be switched off by clearing the LVDC bit in the RTCC
register to zero. Note that if the LVD is enabled there will be some power consumption associated
with its internal circuitry, however, by clearing the LVDC bit to zero the power can be minimised. It
is important not to confuse the LVD with the LVR function. In the LVR function an automatic reset
will be generated by the microcontroller, whereas in the LVD function only the LVDO bit will be
affected with no influence on other microcontroller functions.
There are a range of voltage values, selected using a configuration option, which can be chosen to
activate the LVD.
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Watchdog Timer
The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to
unknown locations, due to certain uncontrollable external events such as electrical noise. It operates
by providing a device reset when the Watchdog Timer counter overflows.
Watchdog Timer Operation
The Watchdog Timer clock source is provided by the internal clock, fS, which is in turn supplied by
one of two sources selected by configuration option: fSUB or fSYS/4. Note that if the Watchdog Timer
configuration option has been disabled, then any instruction relating to its operation will result in no
operation.
Most of the Watchdog Timer options, such as enable/disable, Watchdog Timer clock source and
clear instruction type are selected using configuration options. In addition to a configuration option
to enable the Watchdog Timer, there are four bits, WDTEN3~WDTEN0, in the MISC register to
offer an additional enable control of the Watchdog Timer. These bits must be set to a specific value
of 1010 to disable the Watchdog Timer. Any other values for these bits will keep the Watchdog
Timer enabled. After power on these bits will have the disabled value of 1010.
One of the WDT clock sources is the internal fSUB, which can be sourced from either the 32K_INT
internal oscillator or the 32768Hz oscillator. The 32K_INT internal oscillator has an approximate
period of 31.2µs at a supply voltage of 5V. However, it should be noted that this specified internal
clock period can vary with VDD, temperature and process variations. The 32768Hz oscillator is
supplied by an external 32768Hz crystal. The other Watchdog Timer clock source option is the
fSYS/4 clock. Whether the Watchdog Timer clock source is its own internal 32K_INT, the 32768Hz
oscillator or fSYS/4, it is divided by 213~216, using configuration option to obtain the required
Watchdog Timer time-out period. The max time out period is when the 216 option is selected. This
time-out period may vary with temperature, VDD and process variations. As the clear instruction only
resets the last stage of the divider chain, for this reason the actual division ratio and corresponding
Watchdog Timer time-out can vary by a factor of two. The exact division ratio depends upon the
residual value in the Watchdog Timer counter before the clear instruction is executed.
If the fSYS/4 clock is used as the Watchdog Timer clock source, it should be noted that when the
system enters the Power Down Mode, then the instruction clock is stopped and the Watchdog Timer
will lose its protecting purposes. For systems that operate in noisy environments, using the 32K_INT
RC oscillator is strongly recommended.

Watchdog Timer
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TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set
the status bit TO. However, if the system is in the Power Down Mode, when a Watchdog Timer
time-out occurs, the TO bit in the status register will be set and only the Program Counter and Stack
Pointer will be reset. Three methods can be adopted to clear the contents of the Watchdog Timer.
The first is an external hardware reset, which means a low level on the RES pin, the second is using
the watchdog software instructions and the third is via a ″HALT″ instruction.
Clearing the Watchdog Timer
There are two methods of using software instructions to clear the Watchdog Timer, one of which
must be chosen by configuration option. The first option is to use the single ″CLR WDT″ instruction
while the second is to use the two commands ″CLR WDT1″ and ″CLR WDT2″. For the first
option, a simple execution of ″CLR WDT″ will clear the WDT while for the second option, both
″CLR WDT1″ and ″CLR WDT2″ must both be executed to successfully clear the Watchdog Timer.
Note that for this second option, if ″CLR WDT1″ is used to clear the Watchdog Timer, successive
executions of this instruction will have no effect, only the execution of a ″CLR WDT2″ instruction
will clear the Watchdog Timer. Similarly after the ″CLR WDT2″ instruction has been executed, only
a successive ″CLR WDT1″ instruction can clear the Watchdog Timer.

Watchdog Timer Software Control – MISC
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HT56R642/HT56R644/HT56R654/HT56R656
TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
Configuration Options
Configuration options refer to certain options within the MCU that are programmed into the device
during the programming process. During the development process, these options are selected using
the HT-IDE software development tools. As these options are programmed into the device using the
hardware programming tools, once they are selected they cannot be changed later as the application
software has no control over the configuration options. All options must be defined for proper
system function, the details of which are shown in the table.
No.
Options
Oscillator Options
1
High Oscillator type selection − fM
1. External Crystal Oscillator
2. External RC Oscillator
3. Externally supplied clock − internal filter on
4. Externally supplied clock − internal filter off
2
fSUB clock selection:
1. 32768Hz External Oscillator
2. 32K_INT Internal Oscillator
3
fS clock selection: fSUB or fSYS/4
4
XTAL mode selection: 455kHz or 1M~12MHz
5
32768Hz Crystal: enable or disable
PFD Options
6
PA3: normal I/O or PFD output
7
PFD clock selection: Timer/Event Counter 0 or Timer/Event Counter 1
Buzzer Options
8
PA0/PA1: normal I/O or BZ/BZ or PA0=BZ and PA1 as normal I/O
9
Buzzer frequency: fS/22, fS/23, fS/24, fS/25, fS/26, fS/27, fS/28, fS/29
Time Base Option
10
Time base time-out period: 212/fS, 213/fS, 214/fS, 215/fS,
LCD Option
11
LCD type: R or C − HT56R62/HT56R65 only
Watchdog Options
12
Watchdog Timer function: enable or disable
13
CLRWDT instructions: 1 or 2 instructions
14
WDT time-out period: 212/fS~213/fS, 213/fS~214/fS, 214/fS~215/fS, 215/fS~216/fS
LVD/LVR Options
15
LVD function: enable or disable
16
LVR function: enable or disable
17
LVR/LVD voltage: 2.1V/2.2V or 3.15V/3.3V or 4.2V/4.4V
SPI Options
18
SIM pin enable/disable
19
SPI_WCOL: enable/disable
20
SPI_CSEN: enable/disable, used to enable/disable (1/0) software CSEN function
I2C Option
21
I2C debounce Time: no debounce, 1 system clock debounce, 2 system clock debounce
PINT Option
22
External peripheral interrupt or Segment function
Timer/Event Counter and External Interrupt Pins Filter Option
23
Interrupt and Timer/Event Counter input pins internal filter On/Off control − applies to all pins
Lock Options
24
Lock All
25
Partial Lock
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TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
Application Circuits
Application Circuit for HT56R62/HT56R65

R e s e t
C ir c u it

C r y s ta l/R e s o n a to r
S y s te m O s c illa to r

3 2 7 6 8 H z C ry s ta l
O s c illa to r

O S C 3 , O S C 4 F lo a tin g
O S C
Rev. 1.30
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R C S y s te m O s c illa to r

C ir c u it
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TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
Application Circuit for HT56R642/HT56R644/HT56R654/HT56R656

R e s e t
C ir c u it

C r y s ta l/R e s o n a to r
S y s te m O s c illa to r

3 2 7 6 8 H z C ry s ta l
O s c illa to r

R C S y s te m O s c illa to r

O S C 3 , O S C 4 F lo a tin g
O S C C ir c u it
Rev. 1.30
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TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
Instruction Set
Introduction
Central to the successful operation of any microcontroller is its instruction set, which is a set of
program instruction codes that directs the microcontroller to perform certain operations. In the case
of Holtek microcontroller, a comprehensive and flexible set of over 60 instructions is provided to
enable programmers to implement their application with the minimum of programming overheads.
For easier understanding of the various instruction codes, they have been subdivided into several
functional groupings.
Instruction Timing
Most instructions are implemented within one instruction cycle. The exceptions to this are branch,
call, or table read instructions where two instruction cycles are required. One instruction cycle is
equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions
would be implemented within 0.5μs and branch or call instructions would be implemented within
1μs. Although instructions which require one more cycle to implement are generally limited to
the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other
instructions which involve manipulation of the Program Counter Low register or PCL will also take
one more cycle to implement. As instructions which change the contents of the PCL will imply a
direct jump to that new address, one more cycle will be required. Examples of such instructions
would be “CLR PCL” or “MOV PCL, A”. For the case of skip instructions, it must be noted that if
the result of the comparison involves a skip operation then this will also take one more cycle, if no
skip is involved then only one cycle is required.
Moving and Transferring Data
The transfer of data within the microcontroller program is one of the most frequently used
operations. Making use of three kinds of MOV instructions, data can be transferred from registers to
the Accumulator and vice-versa as well as being able to move specific immediate data directly into
the Accumulator. One of the most important data transfer applications is to receive data from the
input ports and transfer data to the output ports.
Arithmetic Operations
The ability to perform certain arithmetic operations and data manipulation is a necessary feature of
most microcontroller applications. Within the Holtek microcontroller instruction set are a range of
add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care
must be taken to ensure correct handling of carry and borrow data when results exceed 255 for
addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC
and DECA provide a simple means of increasing or decreasing by a value of one of the values in the
destination specified.
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Logical and Rotate Operation
The standard logical operations such as AND, OR, XOR and CPL all have their own instruction
within the Holtek microcontroller instruction set. As with the case of most instructions involving
data manipulation, data must pass through the Accumulator which may involve additional
programming steps. In all logical data operations, the zero flag may be set if the result of the
operation is zero. Another form of logical data manipulation comes from the rotate instructions such
as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different
rotate instructions exist depending on program requirements. Rotate instructions are useful for serial
port programming applications where data can be rotated from an internal register into the Carry
bit from where it can be examined and the necessary serial bit set high or low. Another application
which rotate data operations are used is to implement multiplication and division calculations.
Branches and Control Transfer
Program branching takes the form of either jumps to specified locations using the JMP instruction
or to a subroutine using the CALL instruction. They differ in the sense that in the case of a
subroutine call, the program must return to the instruction immediately when the subroutine has
been carried out. This is done by placing a return instruction “RET” in the subroutine which will
cause the program to jump back to the address right after the CALL instruction. In the case of a JMP
instruction, the program simply jumps to the desired location. There is no requirement to jump back
to the original jumping off point as in the case of the CALL instruction. One special and extremely
useful set of branch instructions are the conditional branches. Here a decision is first made regarding
the condition of a certain data memory or individual bits. Depending upon the conditions, the
program will continue with the next instruction or skip over it and jump to the following instruction.
These instructions are the key to decision making and branching within the program perhaps
determined by the condition of certain input switches or by the condition of internal data bits.
Bit Operations
The ability to provide single bit operations on Data Memory is an extremely flexible feature of all
Holtek microcontrollers. This feature is especially useful for output port bit programming where
individual bits or port pins can be directly set high or low using either the “SET [m].i” or “CLR [m].i”
instructions respectively. The feature removes the need for programmers to first read the 8-bit output
port, manipulate the input data to ensure that other bits are not changed and then output the port with
the correct new data. This read-modify-write process is taken care of automatically when these bit
operation instructions are used.
Table Read Operations
Data storage is normally implemented by using registers. However, when working with large
amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in
the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program
Memory to be setup as a table where data can be directly stored. A set of easy to use instructions
provides the means by which this fixed data can be referenced and retrieved from the Program
Memory.
Other Operations
In addition to the above functional instructions, a range of other instructions also exist such as
the “HALT” instruction for Power-down operations and instructions to control the operation of
the Watchdog Timer for reliable program operations under extreme electric or electromagnetic
environments. For their relevant operations, refer to the functional related sections.
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TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
Instruction Set Summary
The following table depicts a summary of the instruction set categorised according to function and
can be consulted as a basic instruction reference using the following listed conventions.
Table Conventions
x: Bits immediate data
m: Data Memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Mnemonic
Description
Cycles
Flag Affected
Add Data Memory to ACC
Add ACC to Data Memory
Add immediate data to ACC
Add Data Memory to ACC with Carry
Add ACC to Data memory with Carry
Subtract immediate data from the ACC
Subtract Data Memory from ACC
Subtract Data Memory from ACC with result in Data Memory
Subtract Data Memory from ACC with Carry
Subtract Data Memory from ACC with Carry, result in Data Memory
Decimal adjust ACC for Addition with result in Data Memory
1
1Note
1
1
1Note
1
1
1Note
1
1Note
1Note
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
C
1
1
1
1Note
1Note
1Note
1
1
1
1Note
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Increment Data Memory with result in ACC
Increment Data Memory
Decrement Data Memory with result in ACC
Decrement Data Memory
1
1Note
1
1Note
Z
Z
Z
Z
Rotate Data Memory right with result in ACC
Rotate Data Memory right
Rotate Data Memory right through Carry with result in ACC
Rotate Data Memory right through Carry
Rotate Data Memory left with result in ACC
Rotate Data Memory left
Rotate Data Memory left through Carry with result in ACC
Rotate Data Memory left through Carry
1
1Note
1
1Note
1
1Note
1
1Note
None
None
C
C
None
None
C
C
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
Logical AND Data Memory to ACC
Logical OR Data Memory to ACC
Logical XOR Data Memory to ACC
Logical AND ACC to Data Memory
Logical OR ACC to Data Memory
Logical XOR ACC to Data Memory
Logical AND immediate Data to ACC
Logical OR immediate Data to ACC
Logical XOR immediate Data to ACC
Complement Data Memory
Complement Data Memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
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TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
Mnemonic
Description
Cycles
Flag Affected
Move Data Memory to ACC
Move ACC to Data Memory
Move immediate data to ACC
1
1Note
1
None
None
None
Clear bit of Data Memory
Set bit of Data Memory
1Note
1Note
None
None
Jump unconditionally
Skip if Data Memory is zero
Skip if Data Memory is zero with data movement to ACC
Skip if bit i of Data Memory is zero
Skip if bit i of Data Memory is not zero
Skip if increment Data Memory is zero
Skip if decrement Data Memory is zero
Skip if increment Data Memory is zero with result in ACC
Skip if decrement Data Memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1Note
1Note
1Note
1Note
1Note
1Note
1Note
1Note
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read table to TBLH and Data Memory
Read table (last page) to TBLH and Data Memory
2Note
2Note
None
None
No operation
Clear Data Memory
Set Data Memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of Data Memory
Swap nibbles of Data Memory with result in ACC
Enter power down mode
1
1Note
1Note
1
1
1
1Note
1
1
None
None
None
TO, PDF
TO, PDF
TO, PDF
None
None
TO, PDF
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRD [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required, if no
skip takes place only one cycle is required.
2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.
3. For the “CLR WDT1” and “CLR WDT2” instructions the TO and PDF flags may be affected by the
execution status. The TO and PDF flags are cleared after both “CLR WDT1” and “CLR WDT2”
instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged.
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TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
Instruction Definition
ADC A,[m]
Description
Operation
Affected flag(s)
ADCM A,[m]
Description
Operation
Affected flag(s)
ADD A,[m]
Description
Add Data Memory to ACC with Carry
The contents of the specified Data Memory, Accumulator and the carry flag are added.
The result is stored in the Accumulator.
ACC ← ACC + [m] + C
OV, Z, AC, C
Add ACC to Data Memory with Carry
The contents of the specified Data Memory, Accumulator and the carry flag are added.
The result is stored in the specified Data Memory.
[m] ← ACC + [m] + C
OV, Z, AC, C
Add Data Memory to ACC
The contents of the specified Data Memory and the Accumulator are added.
The result is stored in the Accumulator.
Operation
Affected flag(s)
ACC ← ACC + [m]
OV, Z, AC, C
ADD A,x
Description
Add immediate data to ACC
The contents of the Accumulator and the specified immediate data are added.
The result is stored in the Accumulator.
ACC ← ACC + x
OV, Z, AC, C
Operation
Affected flag(s)
ADDM A,[m]
Description
Operation
Affected flag(s)
AND A,[m]
Description
Operation
Affected flag(s)
AND A,x
Description
Operation
Affected flag(s)
ANDM A,[m]
Description
Operation
Affected flag(s)
Rev. 1.30
Add ACC to Data Memory
The contents of the specified Data Memory and the Accumulator are added.
The result is stored in the specified Data Memory.
[m] ← ACC + [m]
OV, Z, AC, C
Logical AND Data Memory to ACC
Data in the Accumulator and the specified Data Memory perform a bitwise logical AND
operation. The result is stored in the Accumulator.
ACC ← ACC ″AND″ [m]
Z
Logical AND immediate data to ACC
Data in the Accumulator and the specified immediate data perform a bit wise logical AND
operation. The result is stored in the Accumulator.
ACC ← ACC ″AND″ x
Z
Logical AND ACC to Data Memory
Data in the specified Data Memory and the Accumulator perform a bitwise logical AND
operation. The result is stored in the Data Memory.
[m] ← ACC ″AND″ [m]
Z
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TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
Affected flag(s)
Subroutine call
Unconditionally calls a subroutine at the specified address. The Program Counter then
increments by 1 to obtain the address of the next instruction which is then pushed onto the
stack. The specified address is then loaded and the program continues execution from this
new address. As this instruction requires an additional operation, it is a two cycle instruction.
Stack ← Program Counter + 1
Program Counter ← addr
None
CLR [m]
Description
Operation
Affected flag(s)
Clear Data Memory
Each bit of the specified Data Memory is cleared to 0.
[m] ← 00H
None
CLR [m].i
Description
Operation
Affected flag(s)
Clear bit of Data Memory
Bit i of the specified Data Memory is cleared to 0.
[m].i ← 0
None
CLR WDT
Description
Operation
Clear Watchdog Timer
The TO, PDF flags and the WDT are all cleared.
WDT cleared
TO ← 0
PDF ← 0
TO, PDF
CALL addr
Description
Operation
Affected flag(s)
CLR WDT1
Description
Operation
Affected flag(s)
CLR WDT2
Description
Operation
Affected flag(s)
CPL [m]
Description
Operation
Affected flag(s)
Rev. 1.30
Pre-clear Watchdog Timer
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in
conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have
effect. Repetitively executing this instruction without alternately executing CLR WDT2 will
have no effect.
WDT cleared
TO ← 0
PDF ← 0
TO, PDF
Pre-clear Watchdog Timer
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction
with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect.
Repetitively executing this instruction without alternately executing CLR WDT1 will have no
effect.
WDT cleared
TO ← 0
PDF ← 0
TO, PDF
Complement Data Memory
Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which
previously contained a 1 are changed to 0 and vice versa.
[m] ← [m]
Z
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TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
CPLA [m]
Description
Operation
Affected flag(s)
Complement Data Memory with result in ACC
Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which
previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in
the Accumulator and the contents of the Data Memory remain unchanged.
ACC ← [m]
Z
Affected flag(s)
Decimal-Adjust ACC for addition with result in Data Memory
Convert the contents of the Accumulator value to a BCD (Binary Coded Decimal) value
resulting from the previous addition of two BCD variables. If the low nibble is greater than 9
or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble
remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6
will be added to the high nibble. Essentially, the decimal conversion is performed by adding
00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag
may be affected by this instruction which indicates that if the original BCD sum is greater than
100, it allows multiple precision decimal addition.
[m] ← ACC + 00H or
[m] ← ACC + 06H or
[m] ← ACC + 60H or
[m] ← ACC + 66H
C
DEC [m]
Description
Operation
Affected flag(s)
Decrement Data Memory
Data in the specified Data Memory is decremented by 1.
[m] ← [m] − 1
Z
DECA [m]
Description
Decrement Data Memory with result in ACC
Data in the specified Data Memory is decremented by 1. The result is stored in the
Accumulator. The contents of the Data Memory remain unchanged.
ACC ← [m] − 1
Z
DAA [m]
Description
Operation
Operation
Affected flag(s)
Affected flag(s)
Enter power down mode
This instruction stops the program execution and turns off the system clock. The contents of
the Data Memory and registers are retained. The WDT and prescaler are cleared. The power
down flag PDF is set and the WDT time-out flag TO is cleared.
TO ← 0
PDF ← 1
TO, PDF
INC [m]
Description
Operation
Affected flag(s)
Increment Data Memory
Data in the specified Data Memory is incremented by 1.
[m] ← [m] + 1
Z
INCA [m]
Description
Increment Data Memory with result in ACC
Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator.
The contents of the Data Memory remain unchanged.
ACC ← [m] + 1
Z
HALT
Description
Operation
Operation
Affected flag(s)
Rev. 1.30
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HT56R62/HT56R65
HT56R642/HT56R644/HT56R654/HT56R656
TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
Operation
Affected flag(s)
Jump unconditionally
The contents of the Program Counter are replaced with the specified address. Program
execution then continues from this new address. As this requires the insertion of a dummy
instruction while the new address is loaded, it is a two cycle instruction.
Program Counter ← addr
None
MOV A,[m]
Description
Operation
Affected flag(s)
Move Data Memory to ACC
The contents of the specified Data Memory are copied to the Accumulator.
ACC ← [m]
None
MOV A,x
Description
Operation
Affected flag(s)
Move immediate data to ACC
The immediate data specified is loaded into the Accumulator.
ACC ← x
None
MOV [m],A
Description
Operation
Affected flag(s)
Move ACC to Data Memory
The contents of the Accumulator are copied to the specified Data Memory.
[m] ← ACC
None
NOP
Description
Operation
Affected flag(s)
No operation
No operation is performed. Execution continues with the next instruction.
No operation
None
OR A,[m]
Description
Logical OR Data Memory to ACC
Data in the Accumulator and the specified Data Memory perform a bitwise
logical OR operation. The result is stored in the Accumulator.
ACC ← ACC ″OR″ [m]
Z
JMP addr
Description
Operation
Affected flag(s)
OR A,x
Description
Operation
Affected flag(s)
ORM A,[m]
Description
Operation
Affected flag(s)
RET
Description
Operation
Affected flag(s)
Rev. 1.30
Logical OR immediate data to ACC
Data in the Accumulator and the specified immediate data perform a bitwise logical OR
operation. The result is stored in the Accumulator.
ACC ← ACC ″OR″ x
Z
Logical OR ACC to Data Memory
Data in the specified Data Memory and the Accumulator perform a bitwise logical OR
operation. The result is stored in the Data Memory.
[m] ← ACC ″OR″ [m]
Z
Return from subroutine
The Program Counter is restored from the stack. Program execution continues at the restored
address.
Program Counter ← Stack
None
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RET A,x
Description
Operation
Affected flag(s)
RETI
Description
Operation
Affected flag(s)
RL [m]
Description
Operation
Affected flag(s)
RLA [m]
Description
Operation
Affected flag(s)
RLC [m]
Description
Operation
Affected flag(s)
RLCA [m]
Description
Operation
Affected flag(s)
RR [m]
Description
Operation
Affected flag(s)
Rev. 1.30
Return from subroutine and load immediate data to ACC
The Program Counter is restored from the stack and the Accumulator loaded with the specified
immediate data. Program execution continues at the restored address.
Program Counter ← Stack
ACC ← x
None
Return from interrupt
The Program Counter is restored from the stack and the interrupts are re-enabled by setting the
EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the
RETI instruction is executed, the pending Interrupt routine will be processed before returning
to the main program.
Program Counter ← Stack
EMI ← 1
None
Rotate Data Memory left
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0.
[m].(i+1) ← [m].i; (i=0~6)
[m].0 ← [m].7
None
Rotate Data Memory left with result in ACC
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0.
The rotated result is stored in the Accumulator and the contents of the Data Memory remain
unchanged.
ACC.(i+1) ← [m].i; (i=0~6)
ACC.0 ← [m].7
None
Rotate Data Memory left through Carry
The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7
replaces the Carry bit and the original carry flag is rotated into bit 0.
[m].(i+1) ← [m].i; (i=0~6)
[m].0 ← C
C ← [m].7
C
Rotate Data Memory left through Carry with result in ACC
Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the
Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the
Accumulator and the contents of the Data Memory remain unchanged.
ACC.(i+1) ← [m].i; (i=0~6)
ACC.0 ← C
C ← [m].7
C
Rotate Data Memory right
The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7.
[m].i ← [m].(i+1); (i=0~6)
[m].7 ← [m].0
None
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RRA [m]
Description
Operation
Affected flag(s)
RRC [m]
Description
Operation
Affected flag(s)
RRCA [m]
Description
Operation
Affected flag(s)
SBC A,[m]
Description
Operation
Affected flag(s)
SBCM A,[m]
Description
Operation
Affected flag(s)
SDZ [m]
Description
Operation
Affected flag(s)
Rev. 1.30
Rotate Data Memory right with result in ACC
Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0
rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the
Data Memory remain unchanged.
ACC.i ← [m].(i+1); (i=0~6)
ACC.7 ← [m].0
None
Rotate Data Memory right through Carry
The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0
replaces the Carry bit and the original carry flag is rotated into bit 7.
[m].i ← [m].(i+1); (i=0~6)
[m].7 ← C
C ← [m].0
C
Rotate Data Memory right through Carry with result in ACC
Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces
the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the
Accumulator and the contents of the Data Memory remain unchanged.
ACC.i ← [m].(i+1); (i=0~6)
ACC.7 ← C
C ← [m].0
C
Subtract Data Memory from ACC with Carry
The contents of the specified Data Memory and the complement of the carry flag are
subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the
result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
ACC ← ACC − [m] − C
OV, Z, AC, C
Subtract Data Memory from ACC with Carry and result in Data Memory
The contents of the specified Data Memory and the complement of the carry flag are
subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the
result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
[m] ← ACC − [m] − C
OV, Z, AC, C
Skip if decrement Data Memory is 0
The contents of the specified Data Memory are first decremented by 1. If the result is 0 the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
[m] ← [m] − 1
Skip if [m]=0
None
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Affected flag(s)
Skip if decrement Data Memory is zero with result in ACC
The contents of the specified Data Memory are first decremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy
instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0,
the program proceeds with the following instruction.
ACC ← [m] − 1
Skip if ACC=0
None
SET [m]
Description
Operation
Affected flag(s)
Set Data Memory
Each bit of the specified Data Memory is set to 1.
[m] ← FFH
None
SET [m].i
Description
Operation
Affected flag(s)
Set bit of Data Memory
Bit i of the specified Data Memory is set to 1.
[m].i ← 1
None
SIZ [m]
Description
Skip if increment Data Memory is 0
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
[m] ← [m] + 1
Skip if [m]=0
None
SDZA [m]
Description
Operation
Operation
Affected flag(s)
SIZA [m]
Description
Operation
Affected flag(s)
SNZ [m].i
Description
Operation
Affected flag(s)
SUB A,[m]
Description
Operation
Affected flag(s)
Rev. 1.30
Skip if increment Data Memory is zero with result in ACC
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy
instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0 the program proceeds with the following instruction.
ACC ← [m] + 1
Skip if ACC=0
None
Skip if bit i of Data Memory is not 0
If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this
requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is 0 the program proceeds with the following instruction.
Skip if [m].i ≠ 0
None
Subtract Data Memory from ACC
The specified Data Memory is subtracted from the contents of the Accumulator. The result is
stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be
cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
ACC ← ACC − [m]
OV, Z, AC, C
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SUBM A,[m]
Description
Operation
Affected flag(s)
Subtract Data Memory from ACC with result in Data Memory
The specified Data Memory is subtracted from the contents of the Accumulator. The result is
stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be
cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
[m] ← ACC − [m]
OV, Z, AC, C
Operation
Affected flag(s)
Subtract immediate data from ACC
The immediate data specified by the code is subtracted from the contents of the Accumulator.
The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C
flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
ACC ← ACC − x
OV, Z, AC, C
SWAP [m]
Description
Operation
Affected flag(s)
Swap nibbles of Data Memory
The low-order and high-order nibbles of the specified Data Memory are interchanged.
[m].3~[m].0 ↔ [m].7~[m].4
None
SWAPA [m]
Description
Swap nibbles of Data Memory with result in ACC
The low-order and high-order nibbles of the specified Data Memory are interchanged. The
result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
ACC.3~ACC.0 ← [m].7~[m].4
ACC.7~ACC.4 ← [m].3~[m].0
None
SUB A,x
Description
Operation
Affected flag(s)
SZ [m]
Description
Operation
Affected flag(s)
SZA [m]
Description
Operation
Affected flag(s)
SZ [m].i
Description
Operation
Affected flag(s)
Rev. 1.30
Skip if Data Memory is 0
If the contents of the specified Data Memory is 0, the following instruction is skipped. As this
requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is not 0 the program proceeds with the following instruction.
Skip if [m]=0
None
Skip if Data Memory is 0 with data movement to ACC
The contents of the specified Data Memory are copied to the Accumulator. If the value is zero,
the following instruction is skipped. As this requires the insertion of a dummy instruction
while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the
program proceeds with the following instruction.
ACC ← [m]
Skip if [m]=0
None
Skip if bit i of Data Memory is 0
If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires
the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle
instruction. If the result is not 0, the program proceeds with the following instruction.
Skip if [m].i=0
None
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TABRD [m]
Description
Operation
Affected flag(s)
TABRDL [m]
Description
Operation
Affected flag(s)
XOR A,[m]
Description
Operation
Affected flag(s)
XORM A,[m]
Description
Operation
Affected flag(s)
XOR A,x
Description
Operation
Affected flag(s)
Rev. 1.30
Read table (current page) to TBLH and Data Memory
The low byte of the program code (current page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
[m] ← program code (low byte)
TBLH ← program code (high byte)
None
Read table (last page) to TBLH and Data Memory
The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved
to the specified Data Memory and the high byte moved to TBLH.
[m] ← program code (low byte)
TBLH ← program code (high byte)
None
Logical XOR Data Memory to ACC
Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR
operation. The result is stored in the Accumulator.
ACC ← ACC ″XOR″ [m]
Z
Logical XOR ACC to Data Memory
Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR
operation. The result is stored in the Data Memory.
[m] ← ACC ″XOR″ [m]
Z
Logical XOR immediate data to ACC
Data in the Accumulator and the specified immediate data perform a bitwise logical XOR
operation. The result is stored in the Accumulator.
ACC ← ACC ″XOR″ x
Z
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TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
Package Information
Note that the package information provided here is for consultation purposes only. As this
information may be updated at regular intervals users are reminded to consult the Holtek website
(http://www.holtek.com.tw/english/literature/package.pdf) for the latest version of the package
information.
52-pin QFP (14mm×14mm) Outline Dimensions
Symbol
A
B
C
D
E
F
G
H
I
J
K
α
Symbol
A
B
C
D
E
F
G
H
I
J
K
α
Rev. 1.30
Dimensions in inch
Min.
Nom.
Max.
0.681
0.547
0.681
0.547
—
—
0.098
—
—
0.029
0.004
0°
—
—
—
—
0.039
0.016
—
—
0.004
—
—
—
0.689
0.555
0.689
0.555
—
—
0.122
0.134
—
0.041
0.008
7°
Dimensions in mm
Min.
Nom.
Max.
17.30
13.90
17.30
13.90
—
—
2.50
—
—
0.73
0.10
0°
—
—
—
—
1.00
0.40
—
—
0.10
—
—
—
17.50
14.10
17.50
14.10
—
—
3.10
3.40
—
1.03
0.20
7°
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64-pin LQFP (7mm×7mm) Outline Dimensions
Symbol
A
Nom.
Max.
0.350
—
0.358
0.280
B
0.272
—
C
0.350
—
0.358
D
0.272
—
0.280
E
—
0.016
—
F
0.005
—
0.009
G
0.053
—
0.057
H
—
—
0.063
I
0.002
—
0.006
J
0.018
—
0.030
K
0.004
—
0.008
α
0°
—
7°
Symbol
Rev. 1.30
Dimensions in inch
Min.
Dimensions in mm
Min.
Nom.
Max.
A
8.90
—
9.10
B
6.90
—
7.10
C
8.90
—
9.10
D
6.90
—
7.10
E
—
0.40
—
F
0.13
—
0.23
G
1.35
—
1.45
H
—
—
1.60
0.15
I
0.05
—
J
0.45
—
0.75
K
0.09
—
0.20
α
0°
—
7°
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100-pin LQFP (14mm×14mm) Outline Dimensions
Symbol
Dimensions in inch
Min.
Nom.
Max.
A
0.626
—
0.634
B
0.547
—
0.555
C
0.626
—
0.634
D
0.547
—
0.555
E
—
0.020
—
F
—
0.008
—
G
0.053
—
0.057
H
—
—
0.063
I
—
0.004
—
J
0.018
—
0.030
K
0.004
—
0.008
α
0°
—
7°
Symbol
Rev. 1.30
Dimensions in mm
Min.
Nom.
Max.
A
15.90
—
16.10
B
13.90
—
14.10
C
15.90
—
16.10
D
13.90
—
14.10
E
—
0.50
—
F
—
0.20
—
G
1.35
—
1.45
H
—
—
1.60
I
—
0.10
—
J
0.45
—
0.75
K
0.10
—
0.20
α
0°
—
7°
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TinyPowerTM A/D Type with LCD 8-Bit OTP MCU
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor (China) Inc.
Building No.10, Xinzhu Court, (No.1 Headquarters), 4 Cuizhu Road, Songshan Lake, Dongguan, China 523808
Tel: 86-769-2626-1300
Fax: 86-769-2626-1311
Holtek Semiconductor (USA), Inc. (North America Sales Office)
46729 Fremont Blvd., Fremont, CA 94538, USA
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holtek.com
Copyright© 2013 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication.
However, Holtek assumes no responsibility arising from the use of the specifications described.
The applications mentioned herein are used solely for the purpose of illustration and Holtek makes
no warranty or representation that such applications will be suitable without further modification,
nor recommends the use of its products for application that may present a risk to human life due to
malfunction or otherwise. Holtek's products are not authorized for use as critical components in life
support devices or systems. Holtek reserves the right to alter its products without prior notification. For
the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.30
145
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