HD74HC323 8-bit Universal Shift/Storage Register (with 3-state Outputs) REJ03D0610-0200 (Previous ADE-205-489) Rev.2.00 Jan 31, 2006 Description This eight-bit universal register features multiplexed I/O ports to achieve full eight bit data handling in a single 20-pin package. HD74HC323 applications are as stacked or push-down registers, buffer storage, and accumulator registers. Two function-select inputs and two output control inputs can be used to choose the modes of operation listed in the function table. Synchronous parallel loading is accomplished by taking both function-select lines S0 and S1 high. This places the threestate outputs in a high-impedance state, which permits data that is applied on the I/O ports to be clocked into the register. Reading out of this register can be accomplished while the outputs are enabled in any mode. The clear function is synchronous, and a low level at the clear input clears the register on the next low-to-high transition of the clock. Features • • • • • • High Speed Operation: tpd (Clock to Q) = 20 ns typ (CL = 50 pF) High Output Current: Fanout of 15 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) Ordering Information Part Name Package Code (Previous Code) Package Type HD74HC323RPEL SOP-20 pin (JEDEC) Package Abbreviation PRSP0020DC-A (FP-20DBV) Taping Abbreviation (Quantity) RP EL (1,000 pcs/reel) Function Table Inputs Mode Clear Function Select S1 Clear Output Control Clock Inputs/Outputs Serial Outputs S0 G1† G2† SL SR A/QA B/QB C/QC D/QD E/QE F/QF G/QG H/QH QA’ QH’ L L X L L L X X L L L L L L L L L L L X L L X X L L L L L L L L L L Hold H L L L L X X X QA0 QB0 QC0 QD0 QE0 QF0 QG0 QH0 QA0 QH0 H X X L L L X X QA0 QB0 QC0 QD0 QE0 QF0 QG0 QH0 QA0 QH0 Shift Right H L H L L X H H QAn QBn QCn QDn QEn QFn QGn H QGn H L H L L X L L QAn QBn QCn QDn QEn QFn QGn L QGn Shift Left H H L L L H X QBn QCn QDn QEn QFn QGn QHn H QBn H H H L L L L X QBn QCn QDn QEn QFn QGn QHn L QBn L Load H H H X X X X a b c d e f g h a h a ... h = the level of the steady-state input at A through H, respectively. These data are loaded into the flip-flops while the flip-flop outputs are isolated from the input/output terminals. Rev.2.00 Jan 31, 2006 page 1 of 5 HD74HC323 Pin Arrangement Output controls S0 1 G1 2 20 VCC S0 S1 19 S1 SL 18 17 QH' G Shift left SL G2 3 G/QC 4 G/QC QH E/QE 5 E/QE H/QH 16 H/QH C/QC 6 C/QC F/QF 15 F/QF A/QA 7 A/QA D/QD 14 D/QD QA' 8 QA B/QB 13 B/QB Clear 9 Clear SR 12 Clock CK 11 Shift right SR GND 10 (Top view) Logic Diagram QH' SL H/QH G/QG F/QF E/QE D/QD C/QC B/QB CK CK CK CK CK CK A/QA CK CK CK CK SR S0 Rev.2.00 Jan 31, 2006 page 2 of 5 S1 Clear Clock QA' G1 G2 HD74HC323 Absolute Maximum Ratings Item Supply voltage range Input / Output voltage Input / Output diode current Output current VCC, GND current Power dissipation Storage temperature Symbol VCC VIN, VOUT IIK, IOK IOUT ICC or IGND PT Tstg Ratings –0.5 to 7.0 –0.5 to VCC +0.5 ±20 ±35 ±75 500 –65 to +150 Unit V V mA mA mA mW °C Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. Recommended Operating Conditions Item Supply voltage Input / Output voltage Operating temperature Symbol VCC VIN, VOUT Ta Input rise / fall time*1 Ratings 2 to 6 0 to VCC –40 to 85 0 to 1000 0 to 500 tr, tf 0 to 400 Note: Unit V V °C ns Conditions VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V 1. This item guarantees maximum limit when one input switches. Electrical Characteristics Item Input voltage Symbol VCC (V) VIH VIL Output voltage VOH VOL Off-state output current Input current IOZ Quiescent supply current ICC Iin 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 4.5 Ta = 25°C Min Typ Max 1.5 — — 3.15 — — 4.2 — — — — 0.5 — — 1.35 — — 1.8 1.9 2.0 — 4.4 4.5 — 5.9 6.0 — 4.18 — — 5.68 — — 4.18 — — 5.68 — — — 0.0 0.1 — 0.0 0.1 — 0.0 0.1 — — 0.26 6.0 4.5 6.0 6.0 — — — — — — — — 0.26 0.26 0.26 ±0.5 6.0 6.0 — — — — ±0.1 4.0 Rev.2.00 Jan 31, 2006 page 3 of 5 Ta = –40 to+85°C Unit Test Conditions Min Max 1.5 — V 3.15 — 4.2 — — 0.5 V — 1.35 — 1.8 1.9 — V Vin = VIH or VIL IOH = –20 µA 4.4 — 5.9 — 4.13 — QA to QH IOH = –6 mA 5.63 — IOH = –7.8 mA 4.13 — QA’, QH’ IOH = –4 mA 5.63 — IOH = –5.2 mA — 0.1 V Vin = VIH or VIL IOL = 20 µA — 0.1 — 0.1 — 0.33 IOL = 6 mA QA to QH IOL = 7.8 mA — 0.33 QA’, QH’ — 0.33 IOL = 4 mA — 0.33 IOL = 5.2 mA — ±5.0 µA Vin = VIH or VIL, Vout = VCC or GND — ±1.0 µA Vin = VCC or GND — 40 µA Vin = VCC or GND, Iout = 0 µA HD74HC323 Switching Characteristics (CL = 50 pF, Input tr = tf = 6 ns) Item Symbol VCC (V) Maximum clock frequency fmax Propagation delay time tPLH tPHL Output enable time tZH tZL Output disable time tHZ tLZ Output rise/fall time tTLH tTHL Input capacitance Cin 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Ta = 25°C Ta = –40 to +85°C Unit Test Conditions Min Typ Max Min Max — — 5 — 4 MHz — — 27 — 21 — — 31 — 24 — — 150 — 190 ns Clock to QA’ or QH’ — 18 30 — 38 — — 26 — 33 — — 175 — 220 ns Clock to Q — 20 35 — 44 — — 30 — 37 ns — — 150 — 190 — 14 30 — 38 — — 26 — 33 2.0 4.5 6.0 2.0 — — — — — 15 — — 150 30 26 75 — — — — 190 38 33 95 4.5 6.0 2.0 4.5 6.0 — — — — — — — 5 — — 4 — 5 15 13 60 12 10 10 — — — — — — 19 16 75 15 13 10 ns ns QA’, QH’ ns Q pF Test Circuit VCC VCC G1 G Input Pulse Generator Zout = 50 Ω See Function Table Input Pulse Generator Zout = 50 Ω Output G2 S1 1 kΩ A/QA to H/QH S0 SR Output QA' Clock Output SL Clear QH' CL = 50 pF Note : 1. CL includes probe and jig capacitance. Rev.2.00 Jan 31, 2006 page 4 of 5 CL = 50 pF S1 OPEN GND CL = 50 pF VCC TEST t PLH / t PHL S1 OPEN t ZH/ t HZ t ZL / t LZ GND VCC HD74HC323 Package Dimensions JEITA Package Code P-SOP20-7.5x12.8-1.27 RENESAS Code PRSP0020DC-A *1 Previous Code FP-20DBV MASS[Typ.] 0.52g D F 20 NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" @ DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT @ INCLUDE TRIM OFFSET. 11 HE c *2 E bp Index mark Reference Symbol Terminal cross section ( Ni/Pd/Au plating ) Dimension in Millimeters Min Nom Max D 12.80 13.2 E 7.50 A2 10 1 Z e *3 bp x A1 M 0.10 0.20 0.30 0.34 0.40 0.46 0.20 0.25 0.30 10.40 10.65 A L1 2.65 bp b1 c A c A1 θ L y 1 θ 0° HE 10.00 8° 1.27 e x 0.12 y 0.15 0.935 Z Detail F L L Rev.2.00 Jan 31, 2006 page 5 of 5 0.40 1 0.70 1.45 1.27 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. 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