NSC LM4859 Stereo 1.2w audio sub-system with 3d enhancement Datasheet

LM4859
Stereo 1.2W Audio Sub-system with 3D Enhancement
General Description
Key Specifications
The LM4859 is an integrated audio sub-system designed for
stereo cell phone applications. Operating on a 3.3V supply, it
combines a stereo speaker amplifier delivering 495mW per
channel into an 8Ω load and a stereo headphone amplifier
delivering 33mW per channel into a 32Ω load. It integrates
the audio amplifiers, volume control, mixer, power management control, and National 3D enhancement all into a single
package. In addition, the LM4859 routes and mixes the
stereo and mono inputs into 10 distinct output modes. The
LM4859 is controlled through an I2C compatible interface.
Other features include an ultra-low current shutdown mode
and thermal shutdown protection.
Boomer audio power amplifiers are designed specifically to
provide high quality output power with a minimal amount of
external components.
The LM4859 is available in a 30–bump TL package and a
28–lead LLP package.
j POUT, Stereo Loudspeakers, 4Ω, 5V,
1% THD+N (LM4859SP)
1.6W (typ)
j POUT, Stereo Loudspeakers, 8Ω, 5V,
1% THD+N
1.2W (typ)
j POUT, Stereo Headphones, 32Ω, 5V,
1% THD+N
75mW (typ)
j POUT, Stereo Loudspeakers, 8Ω, 3.3V,
1% THD+N
495mW (typ)
j POUT, Stereo Headphones, 32Ω, 3.3V,
1% THD+N
j Shutdown Current
33mW (typ)
0.06µA (typ)
Features
n
n
n
n
n
n
n
n
n
n
Stereo speaker amplifier
Stereo headphone amplifier
Independent Left, Right, and Mono volume controls
National 3D enhancement
I2C compatible interface
Ultra low shutdown current
Click and Pop Suppression circuit
10 distinct output modes
Thermal Shutdown Protection
Available in micro SMD and LLP packages
Applications
n
n
n
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Cell Phones
PDAs
Portable Gaming Devices
Internet Appliances
Portable DVD/CD/AAC/MP3 players
Boomer ® is a registered trademark of National Semiconductor Corporation.
© 2006 National Semiconductor Corporation
DS201061
www.national.com
LM4859 Stereo 1.2W Audio Sub-system with 3D Enhancement
June 2005
LM4859
Typical Application
20106101
FIGURE 1. Typical Audio Amplifier Application Circuit
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2
LM4859
Connection Diagrams
30 Bump TL Package
micro SMD Marking
20106163
Top View
XY - 2 Digit date code
TT - Die run traceability
G - Boomer Family
F1 - LM4859TL
20106108
Top View
(Bump-side down)
Order Number LM4859TL
See NS Package Number TLA30CZA
Pin Connections (TL)
Pin
Name
Pin Description
A1
RLS+
A2
VDD
Right Loudspeaker Positive Output
Power Supply
A3
SDA
Data
A4
RHP3D
Right Headphone 3D
A5
RHP
Right Headphone Output
B1
GND
Ground
B2
I2CVDD
I2C Interface Power Supply
B3
ADR
I2C Address Select
B4
LHP3D
Left Headphone 3D
B5
VDD
Power Supply
C1
RLS-
Right Loudspeaker Negative Output
C2
NC
No Connect
C3
SCL
Clock
C4
NC
No Connect
C5
GND
Ground
D1
LLS-
Left Loudspeaker Negative Output
D2
VDD
Power Supply
D3
MIN
Mono Input
D4
NC
No Connect
D5
NC
No Connect
E1
GND
Ground
E2
BYPASS
Half-supply bypass
E3
LLS3D
Left Loudspeaker 3D
E4
RIN
Right Stereo Input
E5
NC
No Connect
F1
LLS+
Left Loudspeaker Positive Output
F2
VDD
Power Supply
F3
RLS3D
Right Loudspeaker 3D
F4
LIN
Left Stereo Input
F5
LHP
Left Headphone Output
3
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LM4859
Connection Diagram
28 – Lead SP Package
20106199
Top View
Order Number LM4859SP
See NS Package Number SPA28A
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4
LM4859
Pin Connections (SP)
Pin
1
Name
Pin Description
RHP
Right Headphone Output
2
VDD
Power Supply
3
NC
No Connect
4
GND
Ground
5
NC
No Connect
6
NC
No Connect
7
LHP
Left Headphone Output
8
RIN
Right Stereo Input
9
LIN
Left Stereo Input
10
MIN
Mono Input
11
LLS3D
Left Loudspeaker 3D
12
RLS3D
Right Loudspeaker 3D
13
BYPASS
Half-supply bypass
14
VDD
Power Supply
15
LLS+
Left Loudspeaker Positive Output
16
GND
Ground
17
LLS-
Left Loudspeaker Negative Output
18
VDD
Power Supply
19
RLS-
Right Loudspeaker Negative Output
20
GND
Ground
21
RLS+
Right Loudspeaker Positive Output
22
VDD
Power Supply
23
I2CVDD
I2C Interface Power Supply
24
SDA
Data
25
ADR
I2C Address Select
26
SCL
Clock
27
RHP3D
Right Headphone 3D
28
LHP3D
Left Headphone 3D
5
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LM4859
Absolute Maximum Ratings (Notes 1, 2)
θJA (SPA28A) (Note 10)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
θJC (SPA28A)
Supply Voltage
Power Dissipation (Note 3)
Temperature Range
TMIN ≤ TA ≤ TMAX
Internally Limited
ESD Susceptibility (Note 4)
2000V
ESD Susceptibility (Note 5)
200V
Junction Temperature (TJ)
150˚C
62˚C/W
Operating Ratings
−65˚C to +150˚C
−0.3V to VDD +0.3V
Input Voltage
3˚C/W
θJA (TLA30CZA) (Note 12)
6.0V
Storage Temperature
42˚C/W
−40˚C ≤ TA ≤ +85˚C
Supply Voltage
2.7V ≤ VDD ≤ 5.5V
2.5V ≤ I2CVDD ≤ 5.5V
Thermal Resistance
Audio Amplifier Electrical Characteristics VDD = 5.0V
(Notes 1, 2)
The following specifications apply for VDD = 5.0V, unless otherwise specified. Limits apply for TA = 25˚C.
Symbol
Parameter
Conditions
LM4859
Typical
(Note 6)
IDD
ISD
PO
Supply Current
Shutdown Current
Output Power
Limits (Notes
7, 8)
Units
(Limits)
VIN = 0V, No load;
LD5 = RD5 = 0 (Note 9)
Mode 4, 9, 14
5
8
mA (max)
Mode 2, 3, 7, 8, 12, 13
13
21
mA (max)
Output mode 0 (Note 9)
0.2
3
µA (max)
LM4859SP
Speaker; THD+N = 1%;
f = 1kHz; 4Ω BTL
1.6
Speaker; THD+N = 1%;
f = 1kHz; 8Ω BTL
1.2
0.9
W (min)
Headphone; THD+N = 1%;
f = 1kHz; 32Ω SE
75
60
mW (min)
W
LD5 = RD5 = 0
THD+N
VOS
Total Harmonic Distortion Plus
Noise
Offset Voltage
Speaker; PO = 400mW;
f = 1kHz; 8Ω BTL
0.05
%
Headphone; PO = 15mW;
f = 1kHz; 32Ω SE
0.04
%
Speaker; LD5 = RD5 = 0
5
40
mV (max)
A-weighted, 0dB gain; (Note 11)
LD5 = RD5 = 0; Audio Inputs Terminated
NOUT
Output Noise
Speaker; Mode 2, 3, 7, 8
27
µV
Speaker; Mode 12, 13
38
µV
Headphone; Mode 3, 4, 8, 9
10
µV
Headphone; Mode 13, 14
14
µV
f = 217Hz; Vrip = 200mVpp; CB = 2.2µF;
0dB gain; (Note 11)
LD5 = RD5 = 0; Audio Inputs Terminated
PSRR
Power Supply Rejection Ratio
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Speaker; Mode 2, 3, 7, 8
70
Speaker; Mode 12, 13,
64
Headphone; Mode 3, 4, 8, 9
86
Headphone; Mode 13, 14
73
6
dB
54
dB (min)
dB
60
dB (min)
LM4859
Audio Amplifier Electrical Characteristics VDD = 5.0V
(Notes 1, 2) (Continued)
The following specifications apply for VDD = 5.0V, unless otherwise specified. Limits apply for TA = 25˚C.
Symbol
Parameter
Conditions
LM4859
Typical
(Note 6)
Limits (Notes
7, 8)
Units
(Limits)
LD5 = RD5 = 0
Xtalk
TWU
Crosstalk
Wake-up Time
Loudspeaker; PO = 400mW;
f = 1kHz
85
dB
Headphone; PO = 15mW;
f = 1kHz
85
dB
CD5 = 0; CB = 2.2µF
120
ms
CD5 = 1; CB = 2.2µF
230
ms
Audio Amplifier Electrical Characteristics VDD = 3.0V
(Notes 1, 2)
The following specifications apply for VDD = 3.0V, unless otherwise specified. Limits apply for TA = 25˚C.
Symbol
Parameter
Conditions
LM4859
Units
(Limits)
Typical
(Note 6)
Limits (Notes
7, 8)
4.5
7.5
mA (max)
VIN = 0V, No load;
LD5 = RD5 = 0 (Note 9)
IDD
Supply Current
Mode 2, 3, 7, 8, 12, 13
11.2
19
mA (max)
ISD
Shutdown Current
Mode 0 (Note 9)
0.06
2.5
µA (max)
Output Power
LM4859SP
Speaker; THD+N = 1%;
f = 1kHz; 4Ω BTL
530
Speaker; THD+N = 1%;
f = 1kHz; 8Ω BTL
400
320
mW (min)
Headphone; THD+N = 1%;
f = 1kHz; 32Ω SE
25
20
mW (min)
PO
PO
Output Power
Mode 4, 9, 14
mW
LD5 = RD5 = 0
THD+N
VOS
Total Harmonic Distortion Plus
Noise
Offset Voltage
Speaker; PO = 200mW;
f = 1kHz; 8Ω BTL
0.05
%
Headphone; PO = 10mW;
f = 1kHz; 32Ω SE
0.04
%
Speaker; LD5 = RD5 = 0
5
40
mV (max)
A-weighted; 0dB gain; (Note 11)
LD5 = RD5 = 0; All Inputs Terminated
NOUT
Output Noise
Speaker; Mode 2, 3, 7, 8
27
µV
Speaker; Mode 12, 13
38
µV
Headphone; Mode 3, 4, 8, 9
10
µV
Headphone; Mode 13, 14
14
µV
f = 217Hz, Vrip = 200mVpp; CB = 2.2µF;
0dB gain; (Note 11)
LD5 = RD5 = 0; All Audio Inputs
Terminated
PSRR
Power Supply Rejection Ratio
Speaker; Mode 2, 3, 7, 8
70
Speaker; Mode 12, 13,
65
Headphone; Mode 3, 4, 8, 9
87
Headphone; Mode 13, 14
75
7
dB
55
dB (min)
dB
62
dB (min)
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LM4859
Audio Amplifier Electrical Characteristics VDD = 3.0V
(Notes 1, 2) (Continued)
The following specifications apply for VDD = 3.0V, unless otherwise specified. Limits apply for TA = 25˚C.
Symbol
Parameter
Conditions
LM4859
Typical
(Note 6)
Limits (Notes
7, 8)
Units
(Limits)
LD5 = RD5 = 0
Xtalk
TWU
Crosstalk
Wake-up Time
Loudspeaker; PO = 200mW;
f = 1kHz
82
dB
Headphone; PO = 10mW;
f = 1kHz
82
dB
CD5 = 0; CB = 2.2µF
80
ms
CD5 = 1; CB = 2.2µF
140
ms
Volume Control Electrical Characteristics (Notes 1, 2)
The following specifications apply for VDD = 5.0V and VDD = 3.0V, unless otherwise specified. Limits apply for TA = 25˚C.
Symbol
Parameter
Conditions
LM4859
Typical
(Note 6)
Limits (Notes
7, 8)
maximum gain setting
6
5.5
6.5
dB (min)
dB (max)
minimum gain setting
-40.5
-41
-40
dB (min)
dB (max)
maximum gain setting
12
11.5
12.5
dB (min)
dB (max)
minimum gain setting
-34.5
-35
-34
dB (min)
dB (max)
+/-0.5
dB (max)
Stereo Volume Control Range
Mono Volume Control Range
Volume Control Step Size
1.5
Volume Control Step Size
Error
+/-0.2
Stereo Channel to Channel
Gain Mismatch
Mute Attenuation
Units
(Limits)
dB
0.3
dB
85
dB
Mode 12, Vin = 1VRMS
Headphone
maximum gain setting
33.5
25
42
kΩ (min)
kΩ (max)
minimum gain setting
100
75
125
kΩ (min)
kΩ (max)
maximum gain setting
20
15
25
kΩ (min)
kΩ (max)
minimum gain setting
98
73
123
kΩ (min)
kΩ (max)
LIN and RIN Input Impedance
MIN Input Impedance
Control Interface Electrical Characteristics (Notes 1, 2)
The following specifications apply for VDD = 5V and VDD = 3V and 2.5V ≤ I2CVDD ≤ 5.5V, unless otherwise specified. Limits
apply for TA = 25˚C.
Symbol
Parameter
Conditions
LM4859
Typical
(Note 6)
Limits (Notes
7, 8)
Units
(Limits)
t1
SCL period
2.5
µs (min)
t2
SDA Set-up Time
100
ns (min)
t3
SDA Stable Time
0
ns (min)
t4
Start Condition Time
100
ns (min)
t5
Stop Condition time
100
ns (min)
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8
(Continued)
The following specifications apply for VDD = 5V and VDD = 3V and 2.5V ≤ I2CVDD ≤ 5.5V, unless otherwise specified. Limits
apply for TA = 25˚C.
Symbol
Parameter
Conditions
LM4859
Typical
(Note 6)
Limits (Notes
7, 8)
Units
(Limits)
VIH
Digital Input High Voltage
0.7 x I2CVDD
V (min)
VIL
Digital Input Low Voltage
0.3 x I2CVDD
V (max)
Note 1: All voltages are measured with respect to the GND pin unless otherwise specified.
Note 2: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional but do not guarantee specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which
guarantee specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not guaranteed for parameters where no limit
is given, however, the typical value is a good indication of device performance.
Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature, TA. The maximum
allowable power dissipation is PDMAX = (TJMAX - TA) / θJA or the number given in Absolute Maximum Ratings, whichever is lower. For the LM4859 operating in Mode
3, 8, or 13 with VDD = 5V, 8Ω stereo loudspeakers and 32Ω stereo headphones, the total power dissipation is 1.348W. θJA = 62˚C/W.
Note 4: Human body model, 100pF discharged through a 1.5kΩ resistor.
Note 5: Machine Model, 220pF-240pF discharged through all pins.
Note 6: Typicals are measured at +25˚C and represent the parametric norm.
Note 7: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 8: Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.
Note 9: Shutdown current and supply current are measured in a normal room environment. All digital input pins are connected to I2CVDD.
Note 10: The given θJA is for an LM4859SP mounted on a PCB with a 2in2 area of 10oz printed circuit board ground plane.
Note 11: “0dB gain” refers to the volume control gain setting of MIN, LIN, and RIN set at 0dB.
Note 12: The given θJA is for an LM4859TL mounted on a PCB with a 2in2 area of 10oz printed circuit board ground plane.
External Components Description
Components
Functional Description
1.
CIN
This is the input coupling capacitor. It blocks the DC voltage and couples the input signal to the
amplifier’s input terminals. CIN also creates a high pass filter with the internal resistor Ri (Input
Impedance) at fC = 1/(2πRiCIN).
2.
CS
This is the supply bypass capacitor. It filters the supply voltage applied to the VDD pin and helps
reduce the noise at the VDD pin.
3.
CB
This is the BYPASS pin capacitor. It filters the VDD / 2 voltage and helps maintain the LM4859’s
PSRR.
4.
COUT
This is the output coupling capacitor. It blocks the DC voltage and couples the output signal to the
speaker load RL. COUT also creates a high pass filter with RL at fO = 1/(2πRLCOUT).
5.
R3D
This resistor sets the gain of the National 3D effect. Please refer to the National 3D Enhancement
section for information on selecting the value of R3D.
6.
C3D
This capacitor sets the frequency at which the National 3D effect starts to occur. Please refer to the
National 3D Enhancement section for information on selecting the value of C3D.
9
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LM4859
Control Interface Electrical Characteristics (Notes 1, 2)
LM4859
Typical Performance Characteristics
(Note 11)
LM4859SP THD+N vs Frequency
LM4859SP THD+N vs Frequency
20106155
20106156
VDD = 5V; LLS, RLS; PO = 400mW;
RL = 4Ω; Mode 7; 0dB Gain
VDD = 3V; LLS, RLS; PO = 200mW;
RL = 4Ω; Mode 7; 0dB Gain
LM4859SP THD+N vs Output Power
LM4859SP THD+N vs Output Power
20106157
20106158
VDD = 5V; LLS, RLS; f = 1kHz;
RL = 4Ω; Mode 7; 0dB Gain
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VDD = 3V; LLS, RLS; f = 1kHz;
RL = 4Ω; Mode 7; 0dB Gain
10
(Note 11)
THD+N vs Frequency
LM4859
Typical Performance Characteristics
(Continued)
THD+N vs Frequency
20106110
20106111
VDD = 5V; LLS, RLS; PO = 400mW;
RL = 8Ω; Mode 7; 0dB Gain
VDD = 3V; LLS, RLS; PO = 200mW;
RL = 8Ω; Mode 7; 0dB Gain
THD+N vs Frequency
THD+N vs Frequency
20106112
20106113
VDD = 5V; LHP, RHP; PO = 15mW;
RL = 32Ω; Mode 9; 0dB Gain
VDD = 3V; LHP, RHP; PO = 10mW;
RL = 32Ω; Mode 9; 0dB Gain
11
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LM4859
Typical Performance Characteristics
(Note 11)
THD+N vs Output Power
(Continued)
THD+N vs Output Power
20106120
20106121
VDD = 5V; LLS, RLS; f = 1kHz;
RL = 8Ω; Mode 7; 0dB Gain
VDD = 3V; LLS, RLS; f = 1kHz;
RL = 8Ω; Mode 7; 0dB Gain
THD+N vs Output Power
THD+N vs Output Power
20106122
20106123
VDD = 5V; LHP, RHP; f = 1kHz;
RL = 32Ω; Mode 9; 0dB Gain
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VDD = 3V; LHP, RHP; f = 1kHz;
RL = 32Ω; Mode 9; 0dB Gain
12
(Note 11)
PSRR vs Frequency
LM4859
Typical Performance Characteristics
(Continued)
PSRR vs Frequency
20106126
20106127
VDD = 5V; LLS, RLS; RL = 8Ω; 0db Gain;
All audio inputs terminated
Top-Mode 12, 13; Mid-Mode 2, 3; Bot-Mode 7, 8
VDD = 3V; LLS, RLS; RL = 8Ω; 0db Gain;
All audio inputs terminated
Top-Mode 12, 13; Mid-Mode 2, 3; Bot-Mode 7, 8
PSRR vs Frequency
PSRR vs Frequency
20106128
20106129
VDD = 5V; LHP, RHP; RL = 32Ω; 0db Gain;
All audio inputs terminated
Top-Mode 13, 14; Mid-Mode 3, 4; Bot-Mode 8, 9
VDD = 3V; LHP, RHP; RL = 32Ω; 0db Gain;
All audio inputs terminated
Top-Mode 13, 14; Mid-Mode 3, 4; Bot-Mode 8, 9
13
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LM4859
Typical Performance Characteristics
(Note 11)
Crosstalk vs Frequency
(Continued)
Crosstalk vs Frequency
20106134
20106135
VDD = 5V; LLS, RLS; PO = 400mW; RL = 8Ω;
Mode 7; 0db Gain; 3D off
Top-Left to Right; Bot-Right to Left
VDD = 3V; LLS, RLS; PO = 200mW; RL = 8Ω;
Mode 7; 0db Gain; 3D off
Top-Left to Right; Bot-Right to Left
Crosstalk vs Frequency
Crosstalk vs Frequency
20106136
20106137
VDD = 5V; LHP, RHP; PO = 15mW; RL = 32Ω;
Mode 9; 0db Gain; 3D off
Top-Left to Right; Bot-Right to Left
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VDD = 3V; LHP, RHP; PO = 10mW; RL = 32Ω;
Mode 9; 0db Gain; 3D off
Top-Left to Right; Bot-Right to Left
14
(Note 11)
Frequency vs Response
LM4859
Typical Performance Characteristics
(Continued)
Frequency vs Response
20106138
20106139
LLS, RLS; RL = 8Ω;
Mode 2; Full Gain
LLS, RLS; RL = 8Ω;
Mode 7; Full Gain
Frequency vs Response
Frequency vs Response
20106140
20106141
LHP, RHP; RL = 32Ω; CO = 100µF
Mode 4; Full Gain
LHP, RHP; RL = 32Ω; CO = 100µF
Mode 9; Full Gain
15
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LM4859
Typical Performance Characteristics
(Note 11)
Power Dissipation vs Output Power
Power Dissipation vs Output Power
20106146
20106145
LLS, RLS; RL = 8Ω; THD+N ≤ 1%
Top-VDD = 5V; Bot-VDD = 3V
per channel
LHP, RHP; RL = 32Ω; THD+N ≤ 1%
Top-VDD = 5V; Bot-VDD = 3V
per channel
Output Power vs Load Resistance
Output Power vs Load Resistance
20106148
20106149
LLS, RLS; RL = 8Ω;
Top-VDD = 5V, 10% THD+N; Topmid-VDD = 5V, 1% THD+N;
Botmid-VDD = 3V, 10% THD+N; Bot-VDD = 3V, 1% THD+N
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(Continued)
LHP, RHP; RL = 32Ω;
Top-VDD = 5V, 10% THD+N; Topmid-VDD = 5V, 1% THD+N;
Botmid-VDD = 3V, 10% THD+N; Bot-VDD = 3V, 1% THD+N
16
(Note 11)
Output Power vs Supply Voltage
LM4859
Typical Performance Characteristics
(Continued)
Output Power vs Supply Voltage
20106152
20106153
LLS, RLS; RL = 8Ω;
Top–10% THD+N; Bot–1% THD+N
LHP, RHP; RL = 32Ω;
Top–10% THD+N; Bot–1% THD+N
17
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LM4859
Application Information
201061F5
FIGURE 2. I2C Bus Format
201061F4
FIGURE 3. I2C Timing Diagram
TABLE 1. Chip Address
A7
A6
A5
A4
A3
A2
A1
Chip Address
1
1
1
1
1
0
EC
A0
0
ADR = 0
1
1
1
1
1
0
0
0
ADR = 1
1
1
1
1
1
0
1
0
EC - externally configured by ADR pin
TABLE 2. Control Registers
D7
D6
D5
D4
D3
D2
D1
D0
Mono Volume control
0
0
0
MD4
MD3
MD2
MD1
MD0
Left Volume control
0
1
LD5
LD4
LD3
LD2
LD1
LD0
Right Volume control
1
0
RD5
RD4
RD3
RD2
RD1
RD0
Mode control
1
1
CD5
0
CD3
CD2
CD1
CD0
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18
LM4859
Application Information
(Continued)
TABLE 3. Mono Volume Control
MD4
MD3
MD2
MD1
MD0
Gain (dB)
0
0
0
0
0
-34.5
0
0
0
0
1
-33.0
0
0
0
1
0
-31.5
0
0
0
1
1
-30.0
0
0
1
0
0
-28.5
0
0
1
0
1
-27.0
0
0
1
1
0
-25.5
0
0
1
1
1
-24.0
0
1
0
0
0
-22.5
0
1
0
0
1
-21.0
0
1
0
1
0
-19.5
0
1
0
1
1
-18.0
0
1
1
0
0
-16.5
0
1
1
0
1
-15.0
0
1
1
1
0
-13.5
0
1
1
1
1
-12.0
1
0
0
0
0
-10.5
1
0
0
0
1
-9.0
1
0
0
1
0
-7.5
1
0
0
1
1
-6.0
1
0
1
0
0
-4.5
1
0
1
0
1
-3.0
1
0
1
1
0
-1.5
1
0
1
1
1
0.0
1
1
0
0
0
1.5
1
1
0
0
1
3.0
1
1
0
1
0
4.5
1
1
0
1
1
6.0
1
1
1
0
0
7.5
1
1
1
0
1
9.0
1
1
1
1
0
10.5
1
1
1
1
1
12.0
19
www.national.com
LM4859
Application Information
(Continued)
TABLE 4. Stereo Volume Control
LD4//RD4
LD3//RD3
LD2//RD2
LD1//RD1
LD0//RD0
Gain (dB)
0
0
0
0
0
-40.5
0
0
0
0
1
-39.0
0
0
0
1
0
-37.5
0
0
0
1
1
-36.0
0
0
1
0
0
-34.5
0
0
1
0
1
-33.0
0
0
1
1
0
-31.5
0
0
1
1
1
-30.0
0
1
0
0
0
-28.5
0
1
0
0
1
-27.0
0
1
0
1
0
-25.5
0
1
0
1
1
-24.0
0
1
1
0
0
-22.5
0
1
1
0
1
-21.0
0
1
1
1
0
-19.5
0
1
1
1
1
-18.0
1
0
0
0
0
-16.5
1
0
0
0
1
-15.0
1
0
0
1
0
-13.5
1
0
0
1
1
-12.0
1
0
1
0
0
-10.5
1
0
1
0
1
-9.0
1
0
1
1
0
-7.5
1
0
1
1
1
-6.0
1
1
0
0
0
-4.5
1
1
0
0
1
-3.0
1
1
0
1
0
-1.5
1
1
0
1
1
0.0
1
1
1
0
0
1.5
1
1
1
0
1
3.0
1
1
1
1
0
4.5
1
1
1
1
1
6.0
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20
LM4859
Application Information
(Continued)
TABLE 5. Mixer and Output Mode
Mode
CD3
CD2
CD1
CD0
Loudspeaker L
Loudspeaker R
Headphone L
Headphone R
0
0
0
0
0
SD
SD
SD
SD
1
0
0
0
1
RESERVED
2
0
0
1
0
2(GM x M)
2(GM x M)
MUTE
MUTE
3
0
0
1
1
2(GM x M)
2(GM x M)
(GM x M)
(GM x M)
4
0
1
0
0
SD
SD
(GM x M)
(GM x M)
5
0
1
0
1
RESERVED
6
0
1
1
0
7
0
1
1
1
2(GL x L)
2(GR x R)
MUTE
MUTE
8
1
0
0
0
2(GL x L)
2(GR x R)
(GL x L)
(GR x R)
SD
SD
(GL x L)
(GR x R)
9
1
0
0
1
10
1
0
1
0
RESERVED
RESERVED
11
1
0
1
1
12
1
1
0
0
2(GL x L) +
2(GM x M)
2(GRx R) +
2(GM x M)
RESERVED
MUTE
MUTE
13
1
1
0
1
2(GL x L) +
2(GM x M)
2(GR x R) +
2(GM x M)
(GL x L) +
(GM x M)
(GR x R) +
(GM x M)
14
1
1
1
0
SD
SD
(GL x L) +
(GM x M)
(GR x R) +
(GM x M)
15
1
1
1
1
RESERVED
M - MIN Input Level
L - LIN Input Level
R - RIN Input Level
GM - Mono Volume Control Gain
GL - Left Stereo Volume Control Gain
GR - Right Stereo Volume Control Gain
SD - Shutdown
MUTE - Mute
TABLE 6. National 3D Enhancement
LD5
RD5
0
Loudspeaker National 3D Off
1
Loudspeaker National 3D On
0
Headphone National 3D Off
1
Headphone National 3D On
TABLE 7. Wake-up Time Select
CD5
0
Fast Wake-up Setting
1
Slow Wake-up Setting
21
www.national.com
LM4859
Application Information
both the stereo loudspeaker outputs as well as the stereo
headphone outputs, so the 3D effect can be set independently for each set of stereo outputs.
The amount of the 3D effect is set by the R3D resistor.
Decreasing the value of R3D will increase the 3D effect. The
C3D capacitor sets the low cutoff frequency of the 3D effect.
Increasing the value of C3D will decrease the low cutoff
frequency at which the 3D effect starts to occur, as shown by
Equation 1.
(Continued)
I2C COMPATIBLE INTERFACE
The LM4859 uses a serial bus, which conforms to the I2C
protocol, to control the chip’s functions with two wires: clock
(SCL) and data (SDA). The clock line is uni-directional. The
data line is bi-directional (open-collector). The maximum
clock frequency specified by the I2C standard is 400kHz. In
this discussion, the master is the controlling microcontroller
and the slave is the LM4859.
The I2C address for the LM4859 is determined using the
ADR pin. The LM4859’s two possible I2C chip addresses are
of the form 111110X10 (binary), where X1 = 0, if ADR is logic
low; and X1 = 1, if ADR is logic high. If the I2C interface is
used to address a number of chips in a system, the
LM4859’s chip address can be changed to avoid any possible address conflicts.
The bus format for the I2C interface is shown in Figure 2. The
bus format diagram is broken up into six major sections:
f3D(-3dB) = 1 / 2π(R3D)(C3D)
Activating the 3D effect will cause an increase in gain by a
multiplication factor of (1 + 9kΩ/R3D). Setting R3D to 9kΩ will
result in a gain increase by a multiplication factor of (1+
9kΩ/9kΩ) = 2 or 6dB whenever the 3D effect is activated.
The volume control can be programmed through the I2C
compatible interface to compensate for the extra 6dB increase in gain. For example, if the stereo volume control is
set at 0dB (11011 from Table 4) before the 3D effect is
activated, the volume control should be programmed to
–6dB (10111 from Table 4) immediately after the 3D effect
has been activated. Setting R3D = 20kΩ and C3D = 0.22µF
allows the LM4859 to produce a pronounced 3D effect with a
minimal increase in output noise.
The "start" signal is generated by lowering the data signal
while the clock signal is high. The start signal will alert all
devices attached to the I2C bus to check the incoming address against their own address.
The 8-bit chip address is sent next, most significant bit first.
The data is latched in on the rising edge of the clock. Each
address bit must be stable while the clock level is high.
After the last bit of the address bit is sent, the master
releases the data line high (through a pull-up resistor). Then
the master sends an acknowledge clock pulse. If the
LM4859 has received the address correctly, then it holds the
data line low during the clock pulse. If the data line is not
held low during the acknowledge clock pulse, then the master should abort the rest of the data transfer to the LM4859.
The 8 bits of data are sent next, most significant bit first.
Each data bit should be valid while the clock level is stable
high.
After the data byte is sent, the master must check for another
acknowledge to see if the LM4859 received the data.
If the master has more data bytes to send to the LM4859,
then the master can repeat the previous two steps until all
data bytes have been sent.
EXPOSED-DAP MOUNTING CONSIDERATIONS
The LM4859’s exposed-DAP (die attach paddle) package
(SP) provides a low thermal resistance between the die and
the PCB to which the part is mounted and soldered. This
allows rapid heat transfer from the die to the surrounding
PCB copper area heatsink, copper traces, ground plane, and
finally, surrounding air. The result is a low voltage audio
power amplifier that produces 1.6W dissipation in a 4Ω load
at ≤ 1% THD+N and over 1.8W in a 3Ω load at 10% THD+N.
This high power is achieved through careful consideration of
necessary thermal design. Failing to optimize thermal design
may compromise the LM4859’s high power performance and
activate unwanted, though necessary, thermal shutdown
protection.
The SP package must have its DAP soldered to a copper
pad on the PCB. The DAP’s PCB copper pad is then, ideally,
connected to a large plane of continuous unbroken copper.
This plane forms a thermal mass, heat sink, and radiation
area. Place the heat sink area on either outside plane in the
case of a two-sided or multi-layer PCB. (The heat sink area
can also be placed on an inner layer of a multi-layer board.
The thermal resistance, however, will be higher.) Connect
the DAP copper pad to the inner layer or backside copper
heat sink area with 9 (3 X 3) (SP) vias. The via diameter
should be 0.012in - 0.013in with a 1.27mm pitch. Ensure
efficient thermal conductivity by plugging and tenting the vias
with plating and solder mask, respectively.
Best thermal performance is achieved with the largest practical copper heat sink area. If the heatsink and amplifier
share the same PCB layer, a nominal 2in2 area is necessary
for 5V operation with a 4Ω load. Heatsink areas not placed
on the same PCB layer as the LM4859 should be 4in2 for the
same supply voltage and load resistance. The last two area
recommendations apply for 25˚C ambient temperature. Increase the area to compensate for ambient temperatures
above 25˚C. In all circumstances and under all conditions,
the junction temperature must be held below 150˚C to prevent activating the LM4859’s thermal shutdown protection.
An example PCB layout for the exposed-DAP SP package is
The "stop" signal ends the transfer. To signal "stop", the data
signal goes high while the clock signal is high. The data line
should be held high when not in use.
I2C INTERFACE POWER SUPPLY PIN (I2CVDD)
The LM4859’s I2C interface is powered up through the
I2CVDD pin. The LM4859’s I2C interface operates at a voltage level set by the I2CVDD pin which can be set independent to that of the main power supply pin VDD. This is ideal
whenever logic levels for the I2C interface are dictated by a
microcontroller or microprocessor that is operating at a lower
supply voltage than the main battery of a portable system.
NATIONAL 3D ENHANCEMENT
The LM4859 features a 3D audio enhancement effect that
widens the perceived soundstage from a stereo audio signal.
The 3D audio enhancement improves the apparent stereo
channel separation whenever the left and right speakers are
too close to one another, due to system size constraints or
equipment limitations.
An external RC network, shown in Figure 1, is required to
enable the 3D effect. There are separate RC networks for
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(1)
22
coupling capacitor that single supply, single-ended amplifiers
require. Eliminating an output coupling capacitor in a typical
single-ended configuration forces a single-supply amplifier’s
half-supply bias voltage across the load. This increases
internal IC power dissipation and may permanently damage
loads such as speakers.
(Continued)
shown in the Demonstration Board Layout section. Further
detailed and specific information concerning PCB layout and
fabrication and mounting an SP (LLP) is found in National
Semiconductor’s AN1187.
PCB LAYOUT AND SUPPLY REGULATION
CONSIDERATIONS FOR DRIVING 3Ω AND 4Ω LOADS
POWER DISSIPATION
Power dissipation is a major concern when designing a
successful single-ended or bridged amplifier.
A direct consequence of the increased power delivered to
the load by a bridge amplifier is higher internal power dissipation. The LM4859 has 2 sets of bridged-tied amplifier pairs
driving LLS and RLS. The maximum internal power dissipation operating in the bridge mode is twice that of a singleended amplifier. From Equation (3) and (4), assuming a 5V
power supply and an 8Ω load, the maximum power dissipation for LLS and RLS is 634mW per channel.
Power dissipated by a load is a function of the voltage swing
across the load and the load’s impedance. As load impedance decreases, load dissipation becomes increasingly dependent on the interconnect (PCB trace and wire) resistance
between the amplifier output pins and the load’s connections. Residual trace resistance causes a voltage drop,
which results in power dissipated in the trace and not in the
load as desired. For example, 0.1Ω trace resistance reduces
the output power dissipated by a 4Ω load from 1.6W to 1.5W.
The problem of decreased load dissipation is exacerbated
as load impedance decreases. Therefore, to maintain the
highest load dissipation and widest output voltage swing,
PCB traces that connect the output pins to a load must be as
wide as possible.
Poor power supply regulation adversely affects maximum
output power. A poorly regulated supply’s output voltage
decreases with increasing load current. Reduced supply
voltage causes decreased headroom, output signal clipping,
and reduced output power. Even with tightly regulated supplies, trace resistance creates the same effects as poor
supply regulation. Therefore, making the power supply
traces as wide as possible helps maintain full output voltage
swing.
(3)
PDMAX-RLS = 4(VDD)2 / (2π2 RL): Bridged
(4)
The LM4859 also has a pair of single-ended amplifiers driving LHP and RHP. The maximum internal power dissipation
for ROUT and LOUT is given by equation (5) and (6). From
Equations (5) and (6), assuming a 5V power supply and a
32Ω load, the maximum power dissipation for LOUT and
ROUT is 40mW per channel.
BRIDGE CONFIGURATION EXPLANATION
The LM4859 consists of two sets of bridged-tied amplifier
pairs that drive the left loudspeaker (LLS) and the right
loudspeaker (RLS). For this discussion, only the LLS bridgetied amplifier pair will be referred to. The LM4859 drives a
load, such as a speaker, connected between outputs, LLS+
and LLS-. In the LLS amplifier block, the output of the
amplifier that drives LLS- serves as the input to the unity gain
inverting amplifier that drives LLS+.
PDMAX-LHP = (VDD)2 / (2π2 RL): Single-ended
(5)
PDMAX-RHP = (VDD)2 / (2π2 RL): Single-ended
(6)
The maximum internal power dissipation of the LM4859
occurs during output modes 3, 8, and 13 when both loudspeaker and headphone amplifiers are simultaneously on;
and is given by Equation (7).
This results in both amplifiers producing signals identical in
magnitude, but 180˚ out of phase. Taking advantage of this
phase difference, a load is placed between LLS- and LLS+
and driven differentially (commonly referred to as ’bridge
mode’). This results in a differential or BTL gain of:
AVD = 2(Rf / Ri) = 2
PDMAX-LLS = 4(VDD)2 / (2π2 RL): Bridged
PDMAX-TOTAL =
PDMAX-LLS + PDMAX-RLS + PDMAX-LHP + PDMAX-RHP (7)
The maximum power dissipation point given by Equation (7)
must not exceed the power dissipation given by Equation
(8):
(2)
PDMAX’ = (TJMAX - TA) / θJA
Both the feedback resistor, Rf, and the input resistor, Ri, are
internally set.
Bridge mode amplifiers are different from single-ended amplifiers that drive loads connected between a single amplifier’s output and ground. For a given supply voltage, bridge
mode has a distinct advantage over the single-ended configuration: its differential output doubles the voltage swing
across the load. Theoretically, this produces four times the
output power when compared to a single-ended amplifier
under the same conditions. This increase in attainable output
power assumes that the amplifier is not current limited and
that the output signal is not clipped.
Another advantage of the differential bridge output is no net
DC voltage across the load. This is accomplished by biasing
LLS- and LLS+ outputs at half-supply. This eliminates the
(8)
The LM4859’s TJMAX = 150˚C. In the SP package, the
LM4859’s θJA is 42˚C/W. At any given ambient temperature
TA, use Equation (8) to find the maximum internal power
dissipation supported by the IC packaging. Rearranging
Equation (8) and substituting PDMAX-TOTAL for PDMAX’ results
in Equation (9). This equation gives the maximum ambient
temperature that still allows maximum stereo power dissipation without violating the LM4859’s maximum junction temperature.
TA = TJMAX - PDMAX-TOTAL θJA
23
(9)
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LM4859
Application Information
LM4859
Application Information
limited frequency response reap little improvement; by using
a large input capacitor.
The internal input resistor (Ri) and the input capacitor (Ci)
produce a high pass filter cutoff frequency that is found using
Equation (13).
(Continued)
For a typical application with a 5V power supply, stereo 8Ω
loudspeaker load, and the stereo 32Ω headphone load, the
maximum ambient temperature that allows maximum stereo
power dissipation without exceeding the maximum junction
temperature is approximately 93.4˚C for the SP package.
TJMAX = PDMAX-TOTAL θJA + TA
fc = 1 / (2πRiCi)
(10)
As an example when using a speaker with a low frequency
limit of 50Hz and Ri = 20kΩ, Ci, using Equation (13) is
0.19µF. The 0.22µF Ci shown in Figure 4 allows the LM4859
to drive high efficiency, full range speaker whose response
extends below 40Hz.
Equation (10) gives the maximum junction temperature TJMAX. If the result violates the LM4859’s 150˚C, reduce the
maximum junction temperature by reducing the power supply voltage or increasing the load resistance. Further allowance should be made for increased ambient temperatures.
The above examples assume that a device is a surface
mount part operating around the maximum power dissipation
point. Since internal power dissipation is a function of output
power, higher ambient temperatures are allowed as output
power or duty cycle decreases. If the result of Equation (7) is
greater than that of Equation (8), then decrease the supply
voltage, increase the load impedance, or reduce the ambient
temperature. If these measures are insufficient, a heat sink
can be added to reduce θJA. The heat sink can be created
using additional copper area around the package, with connections to the ground pin(s), supply pin and amplifier output
pins. External, solder attached SMT heatsinks such as the
Thermalloy 7106D can also improve power dissipation.
When adding a heat sink, the θJA is the sum of θJC, θCS, and
θSA. (θJC is the junction-to-case thermal impedance, θCS is
the case-to-sink thermal impedance, and θSA is the sink-toambient thermal impedance.) Refer to the Typical Performance Characteristics curves for power dissipation information at lower output power levels.
Output Capacitor Value Selection
Amplifying the lowest audio frequencies also requires the
use of a high value output coupling capacitor (CO in Figure
1). A high value output capacitor can be expensive and may
compromise space efficiency in portable design.
The speaker load (RL) and the output capacitor (CO) form a
high pass filter with a low cutoff frequency determined using
Equation (14).
fc = 1 / (2πRLCO)
(12)
When using a typical headphone load of RL = 32Ω with a low
frequency limit of 50Hz, CO is 99µF.
The 100µF CO shown in Figure 4 allows the LM4859 to drive
a headphone whose frequency response extends below
50Hz.
Bypass Capacitor Value Selection
Besides minimizing the input capacitor size, careful consideration should be paid to value of CB, the capacitor connected to the BYPASS pin. Since CB determines how fast
the LM4859 settles to quiescent operation, its value is critical
when minimizing turn-on pops. The slower the LM4859’s
outputs ramp to their quiescent DC voltage (nominally VDD/
2), the smaller the turn-on pop. Choosing CB equal to 2.2µF
along with a small value of Ci (in the range of 0.1µF to
0.39µF), produces a click-less and pop-less shutdown function. As discussed above, choosing Ci no larger than necessary for the desired bandwidth helps minimize clicks and
pops. CB’s value should be in the range of 5 times to 10
times the value of Ci. This ensures that output transients are
eliminated when the LM4859 transitions in and out of shutdown mode. Connecting a 2.2µF capacitor, CB, between the
BYPASS pin and ground improves the internal bias voltage’s
stability and improves the amplifier’s PSRR. The PSRR improvements increase as the bypass pin capacitor value increases. However, increasing the value of CB will increase
wake-up time. The selection of bypass capacitor value, CB,
depends on desired PSRR requirements, click and pop performance, wake-up time, system cost, and size constraints.
POWER SUPPLY BYPASSING
As with any power amplifier, proper supply bypassing is
critical for low noise performance and high power supply
rejection. Applications that employ a 5V regulator typically
use a 10µF in parallel with a 0.1µF filter capacitors to stabilize the regulator’s output, reduce noise on the supply line,
and improve the supply’s transient response. However, their
presence does not eliminate the need for a local 1.0µF
tantalum bypass capacitance connected between the
LM4859’s supply pins and ground. Keep the length of leads
and traces that connect capacitors between the LM4859’s
power supply pin and ground as short as possible.
SELECTING EXTERNAL COMPONENTS
Input Capacitor Value Selection
Amplifying the lowest audio frequencies requires a high
value input coupling capacitor (Ci in Figure 1). In many
cases, however, the speakers used in portable systems,
whether internal or external, have little ability to reproduce
signals below 50Hz. Applications using speakers with this
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(11)
24
LM4859
Application Information
(Continued)
20106102
FIGURE 4. Reference Design Board Schematic
25
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LM4859
Demonstration Board Layout
20106162
20106159
Recommended SP PCB Layout:
Silkscreen Layer
Recommended SP PCB Layout:
Top Layer
20106161
20106160
Recommended SP PCB Layout:
Mid Layer
www.national.com
Recommended SP PCB Layout:
Bottom Layer
26
LM4859
Revision History
Rev
Date
Description
1.1
6/02/05
Added Modes 9 and 14 into Mode 4
(Conditions) for the Idd under Elect.Char
tables 5V and 3V, then re-released D/S to the
WEB (per Alvin Fok). (MC)
1.2
06/06/06
Edited the micro SMD markings (per Alvin F.),
then re-released D/S to the WEB.
27
www.national.com
LM4859
Physical Dimensions
inches (millimeters) unless otherwise noted
30 Bump TL Package
Order Number LM4859TL
NS Package Number TLA30CZA
www.national.com
28
inches (millimeters) unless otherwise noted (Continued)
28 – Lead SP Package
Order Number LM4859SP
NS Package Number SPA28A
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
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WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR
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which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, and whose failure to perform when
properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result
in a significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.
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LM4859 Stereo 1.2W Audio Sub-system with 3D Enhancement
Physical Dimensions