ASAHI KASEI [AKD4584] AKD4584 AK4584 Evaluation Board Rev.A GENERAL DESCRIPTION AKD4584 is an evaluation board for the 24bit 96kHz CODEC, AK4584. The AKD4584 can evaluate A/D converter D/A converter separately in addition to loop back mode (A/D → D/A). The AKD4584 also has the digital audio interface and can achieve the interface with digital audio systems via opt-connector. Ordering guide AKD4584 --- Evaluation board for AK4584 (Cable for connecting with printer port of IBM-AT, compatible PC and control software are packed with this.) FUNCTION • DIT/DIR with optical input/output • BNC connector for an external clock input • 10pin Header for serial control mode 2.7 ~ 5.25V 4.75 ~ 5.25V GND LIN Control Data RIN 10pin Header LOUT ROUT ROM AK4584 10pin Header Opt In BNC In Opt out AK4114 Opt In Opt Out BNC out Clock Gen Figure 1. AKD4584 Block Diagram * Circuit diagram and PCB layout are attached at the end of this manual. <KM065801> 2006/06 -1- ASAHI KASEI [AKD4584] Evaluation Board Manual Analog Input / Output circuits (1) Input circuits The analog input of AK4584 inputs from J1 (RIN), J3 (LIN). J1 RIN C32 10u + RIN R16 560 J3 LIN C34 10u + LIN R19 560 Figure 2. LIN/RIN Input circuits (2) Output circuits The analog output of AK4584’s DAC outputs from J2 (ROUT), J4 (LOUT). + R15 220 J2 ROUT ROUT R17 10k R18 220 + C33 22u J4 LOUT LOUT C35 22u R20 10k Figure 3. LOUT/ROUT Output circuits * AKM assumes no responsibility for the trouble when using the above circuit examples. <KM065801> 2006/06 -2- ASAHI KASEI [AKD4584] Digital Input / Output circuits & Set-up jumper pin (1) Digital input circuits The digital input of AK4584 inputs from J7 (RX) or PORT5 (DIR). 2 VDD 5 PORT5 6 5 GND VCC GND OUT L4 47u 4 3 2 1 1 6 C37 0.1u DIR + C38 10u RX1 R39 RX JP12 470 JP13 RX J7 RX C39 R40 75 RX2 RX1 RX2 RX3 RX4 RX3 RX1-4 BNC RX4 0.1u Figure 4. Digital input circuit 1. Digital signal is input to RX1-4 pins respectively. JP12 RX1-4 JP12 RX1-4 JP12 RX1-4 JP12 RX1-4 RX1 RX1 RX1 RX1 RX2 RX2 RX2 RX2 RX3 RX3 RX3 RX3 RX4 RX4 RX4 RX4 2. Digital signal is input to RX1-4 pins via J7 (RX) and PORT5 (DIR). JP13 RX RX BNC JP13 RX RX BNC * AKM assumes no responsibility for the trouble when using the above circuit examples. <KM065801> 2006/06 -3- ASAHI KASEI [AKD4584] (2) Digital output circuits The digital output of AK4584 inputs from J6 (TX) or PORT4 (DIT). VDD 5 6 PORT4 5 6 IN VCC IF GND 4 3 2 1 DIT J6 TX T2 DA-02F TX R32 1k JP8 TX JP9 C36 0.1u R37 330 TX1 TX2 TX3 TX1 TX2 TX3 TX1-3 BNC R38 100 Figure 5. Digital output circuit 1. Digital signal is output to TX1-3 pins respectively. JP9 TX1-3 JP9 TX1-3 JP9 TX1-3 TX1 TX1 TX1 TX2 TX2 TX2 TX3 TX3 TX3 2. Digital signal is output to TX1-3 pins via J6 (TX) and PORT4 (DIT). JP8 TX TX BNC JP8 TX TX BNC * AKM assumes no responsibility for the trouble when using the above circuit examples. <KM065801> 2006/06 -4- ASAHI KASEI [AKD4584] Operation sequence 1) Set up the power supply lines. [AVDD] (Red) = 4.75 ∼ 5.25V [TVDD] (Orange) = 2.7 ∼ 5.25V [VCC] (Red) = 5.0V [VDD] (Red) = 5.0V [AGND] (Black) = 0V [DGND] (Black) = 0V : for AVDD, DVDD, PVDD of AK4584 (typ. 5.0V) : for TVDD of AK4584 (typ. 3.0V) : for logic (typ. 5.0V) : for logic (typ. 5.0V) : for analog ground : for logic ground Each supply line should be distributed from the power supply unit. 2) Set up the evaluation mode, jumper pins and DIP switches. (See the followings.) 3) Power on. The AK4584 should be reset once bringing SW1 “L” upon power-up. Evaluation mode (1) Slave mode In case of AK4584 evaluation using AK4114, it is necessary to correspond to AK4584’s and AK4114’s audio interface format. About AK4584’s audio interface format, refer to AK4584’s datasheet. About AK4114’s audio interface format, see Table2. (1-1) A/D evaluation using DIT function of AK4584 (1-2) A/D evaluation using DIT function of AK4114 (1-3) D/A evaluation using DIR function of AK4114 (1-4) All interfacing signal (MCLK, BICK, LRCK) are fed from the external circuit (1-1) A/D evaluation using DIT function of AK4584 Using J5 (EXT), PORT4 (DIT) and J6 (TX). Nothing should be connected to J7 (RX), PORT1 (DIR), PORT5 (DIR) and PORT6 (ROM). Remove the X’tal (X1). The bi-phase data is output from TX3. JP6 (EXT) should be open. JP3 XTI JP6 JP10 EXT MCLK JP11 BICK EXT JP15 SDTI DIR EXT DIR ADC ADC EXT DIR DIR JP14 LRCK <KM065801> 2006/06 -5- ASAHI KASEI [AKD4584] • Clock setting (1-1-1) Normal Speed (MCLK=256fs=11.2896MHz@fs=44.1kHz) JP4 MCLK M2 x1 BCFS LRFS x2 x4 x4 M1 JP7 x1 x1 MCKO JP5 x2 JP1 (1-1-2) Normal Speed (MCLK=512fs=22.5792MHz@fs=44.1kHz) JP4 MCLK M2 x1 BCFS LRFS x2 x4 x4 M1 JP7 x1 x1 MCKO JP5 x2 JP1 (1-1-3) Double Speed (MCLK=256fs=22.5792MHz@fs=88.2kHz) x1 JP7 LRFS x2 x4 x1 x1 M2 JP5 BCFS x4 M1 JP4 MCLK x2 JP1 MCKO • SW2 (MODE) setting (See Table 1) Normal speed and double speed are same setting. (1) When XTALE is “H”, MCLK can output from MCKO1/2 pins though AK4584 is powered down. (2) When DMCK is “H”, MCKO1 output is disabled. H 1 2 3 4 5 6 7 8 9 10 DIF0 DIF1 DIF2 OCKS0 OCKS1 CM0 TEST3 XTALE DMCK MS L <KM065801> 2006/06 -6- ASAHI KASEI [AKD4584] (1-2) A/D evaluation using DIT function of AK4114 Using X’tal (X2) and PORT2 (DIT). Nothing should be connected to J5 (EXT), J7 (RX), PORT1 (DIR), PORT5 (DIR) and PORT6 (ROM). Remove the X’tal (X1). JP6 (EXT) should be short. In normal speed and double speed mode, JP1 (MCKO), JP4 (MCLK), JP5 (BCFS) and JP7 (LRFS) should be open. JP3 XTI JP6 EXT JP10 MCLK JP11 BICK EXT DIR EXT JP15 SDTI DIR ADC ADC EXT DIR DIR JP14 LRCK • SW2 (MODE) setting (See Table 1) Normal speed and double speed are same setting. (1) Set the audio interface format of AK4114 using DIF2-0. (2) Set the master clock output of AK4114using OCKS1-0. (3) Set the PLL mode or X’tal mode of AK4114 using CM0. (4) When XTALE is “H”, MCLK can output from MCKO1/2 pins though AK4584 is powered down. (5) When DMCK is “H”, MCKO1 output is disabled. H 1 2 3 4 5 6 7 8 9 10 DIF0 DIF1 DIF2 OCKS0 OCKS1 CM0 TEST3 XTALE DMCK MS L Above figure is 24bit MSB justified, MCKO output of AK4114 is 256fs, AK4114 is X’tal mode. Using DIT of AK4114, AK4114 is set X’tal mode. <KM065801> 2006/06 -7- ASAHI KASEI [AKD4584] (1-3) D/A evaluation using DIR function of AK4114 Using PORT1 (DIR). Nothing should be connected to J7 (RX), PORT5 (DIR) and PORT6 (ROM). Remove the X’tal (X1). JP6 (EXT) should be short. In normal speed, double speed mode and quad speed mode, JP1 (MCKO), JP4 (MCLK), JP5 (BCFS) and JP7 (LRFS) should be open. JP3 XTI JP6 JP10 EXT MCLK JP11 BICK EXT JP15 SDTI DIR EXT DIR ADC ADC EXT DIR DIR JP14 LRCK • SW2 (MODE) setting (See Table 1) (1) Set the audio interface format of AK4114 using DIF2-0. (2) Set the master clock output of AK4114using OCKS1-0. (3) Set the PLL mode or X’tal mode of AK4114 using CM0. (4) When XTALE is “H”, MCLK can output from MCKO1/2 pins though AK4584 is powered down. (5) When DMCK is “H”, MCKO1 output is disabled. H 1 2 3 4 5 6 7 8 9 10 DIF0 DIF1 DIF2 OCKS0 OCKS1 CM0 TEST3 XTALE DMCK MS L Above figure is 24bit MSB justified, MCKO output of AK4114 is 256fs, AK4114 is PLL mode. In quad speed mode of AK4114, set OCKS1=“H” and OCKS0=“H”. The MCKO output of AK4114 is output 128fs. <KM065801> 2006/06 -8- ASAHI KASEI [AKD4584] (1-4) All interfacing signal (MCLK, BICK, LRCK) are fed from the external circuit Using PORT6 (ROM). Nothing should be connected to J7 (RX), PORT1 (DIR) and PORT5 (DIR). Remove the X’tal (X1). JP6 (EXT) should be short. In normal speed, double speed mode and quad speed mode, JP1 (MCKO), JP4 (MCLK), JP5 (BCFS) and JP7 (LRFS) should be open. JP3 XTI JP6 JP10 EXT MCLK JP11 BICK EXT JP15 SDTI DIR EXT DIR ADC ADC EXT DIR DIR JP14 LRCK • SW2 (MODE) setting (See Table 1) (1) When XTALE is “H”, MCLK can output from MCKO1/2 pins though AK4584 is powered down. (2) When DMCK is “H”, MCKO1 output is disabled. H 1 2 3 4 5 6 7 8 9 10 DIF0 DIF1 DIF2 OCKS0 OCKS1 CM0 TEST3 XTALE DMCK MS L <KM065801> 2006/06 -9- ASAHI KASEI [AKD4584] (2) Master Mode (2-1) A/D evaluation using DIT function of AK4584 Using X’tal (X1), PORT4 (DIT) and J6 (TX). Nothing should be connected to J7 (RX), PORT1 (DIR), PORT5 (DIR) and PORT6 (ROM). The bi-phase data is output from TX3. JP6 (EXT) should be short. In normal speed, double speed mode and quad speed mode, JP3 (XTI), JP4 (MCLK), JP5 (BCFS) and JP7 (LRFS) should be open. JP3 XTI JP6 JP10 EXT MCLK JP11 BICK EXT JP15 LRCK SDTI DIR EXT DIR ADC ADC EXT DIR DIR JP14 • Clock Setting (2-1-1) Select MCKO1 JP4 MCLK x1 x2 x4 x1 x1 M2 JP7 LRFS x4 M1 JP5 BCFS x2 JP1 MCKO (2-1-2) Select MCKO2 JP4 MCLK M2 x1 BCFS LRFS x2 x4 x4 M1 JP7 x1 x1 MCKO JP5 x2 JP1 • SW2 (MODE) setting (See Table 1) Normal speed and double speed are same setting. (1) When XTALE is “H”, MCLK can output from MCKO1/2 pins though AK4584 is powered down. (2) When DMCK is “H”, MCKO1 output is disabled. H 1 2 3 4 5 6 7 8 9 10 DIF0 DIF1 DIF2 OCKS0 OCKS1 CM0 TEST3 XTALE DMCK MS L <KM065801> 2006/06 - 10 - ASAHI KASEI [AKD4584] (2-2) D/A evaluation using DIR function of AK4584 Using PORT5 (DIR) or J7 (RX). Nothing should be connected to PORT1 (DIR) and PORT6 (ROM). JP6 (EXT) should be short. In normal speed and double speed mode, JP1 (MCKO), JP4 (MCLK), JP5 (BCFS) and JP7 (LRFS) should be open. JP3 XTI JP6 JP10 EXT MCLK JP11 BICK EXT JP15 SDTI DIR EXT DIR ADC ADC EXT DIR DIR JP14 LRCK • Clock setting (2-2-1) Select MCKO1 JP4 MCLK x1 x2 x4 x1 x1 M2 JP7 LRFS x4 M1 JP5 BCFS x2 JP1 MCKO (2-2-2) Select MCKO2 x1 JP7 LRFS x2 x4 x1 x1 M2 JP5 BCFS x4 M1 JP4 MCLK x2 JP1 MCKO • SW2 (MODE) setting (See Table 1) Normal speed, double speed and quad speed mode are same setting. (1) When XTALE is “H”, MCLK can output from MCKO1/2 pins though AK4584 is powered down. (2) When DMCK is “H”, MCKO1 output is disabled. H 1 2 3 4 5 6 7 8 9 10 DIF0 DIF1 DIF2 OCKS0 OCKS1 CM0 TEST3 XTALE DMCK MS L <KM065801> 2006/06 - 11 - ASAHI KASEI [AKD4584] DIP Switch set up [SW2] (MODE): Setting evaluation mode for AK4584 and AK4114 ON is “H”, OFF is “L”. No. 1 2 3 4 5 6 7 8 9 10 Mode 0 1 2 3 4 5 DIF2 0 0 0 0 1 1 Mode 0 1 2 3 Name ON (“H”) OFF (“L”) DIF0 AK4114 Audio Format Setting DIF1 See Table 2 DIF2 AK4114 Master Clock Output Setting OCKS0 See Table 3 OCKS1 CM0 AK4114 X’tal Mode AK4114 PLL Mode TEST3 Normally OFF XTALE MCKO1/2 Enable MCKO1/2 Disable DMCK MCKO1 Disable MCKO1 Enable M/S Master Mode Slave Mode Table 1. Setting mode for AK4584 and AK4114 DIF1 DIF0 AK4114 DAUX 0 0 24bit, MSB justified 0 1 24bit, MSB justified 1 0 24bit, MSB justified 1 1 24bit, MSB justified 0 0 24bit, MSB justified 0 1 24bit, I2S Table 2. Setting AK4114 audio interface format OCKS1 OCKS0 MCKO1 X’tal 0 0 256fs 256fs 0 1 256fs 256fs 1 0 512fs 512fs 1 1 128fs 128fs Table 3. Setting AK4114 master clock output AK4114 SDTO 16bit, LSB justified 18bit, LSB justified 20bit, LSB justified 24bit, LSB justified 24bit, MSB justified 24bit, I2S fs ∼ 96kHz ∼ 96kHz ∼ 48kHz ∼ 192kHz Other jumper pins set up 1. JP1 (GND): Analog ground and Digital ground OPEN: Separated. <Default> SHORT: Common. (The connector “DGND” can be open.) The function of the toggle SW Upper-side is “H” and lower-side is “L”. [SW1] (PDN): Power down of AK4584. Keep “H” during normal operation. [SW3] (DIR): Power down of AK4114. Keep “H” during normal operation. <KM065801> 2006/06 - 12 - ASAHI KASEI [AKD4584] Indication for LED [LED1] (INT0): Output INT0 pin of AK4584. [LED2] (INT1): Output INT1 pin of AK4584. [LED3] (ERF): Output INT0 pin of AK4114. [LED4] (DZF): Output DZF pin of AK4584. Serial Control The AK4584 can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT3 (CTRL) with PC by 10 wire flat cable packed with the AKD4584. Connect PC 10 wire flat cable 10pin Connector CSN CCLK CDTI CDTO AKD4584 10pin Header Figure 6. Connect of 10 wire flat cable <KM065801> 2006/06 - 13 - ASAHI KASEI [AKD4584] Control Software Manual Set-up of evaluation board and control software 1. Set up the AKD4584 according to previous term. 2. Connect IBM-AT compatible PC with AKD4584 by 10-line type flat cable (packed with AKD4584). Take care of the direction of 10pin header. (Please install the driver in the CD-ROM when this control software is used on Windows 2000/XP. Please refer “Installation Manual of Control Software Driver by AKM device control software”. In case of Windows95/98/ME, this installation is not needed. This control software does not operate on Windows NT.) 3. Insert the CD-ROM labeled “AKD4584 Evaluation Kit” into the CD-ROM drive. 4. Access the CD-ROM drive and double-click the icon of “akd4584.exe” to set up the control program. 5. Then please evaluate according to the follows. Operation flow Keep the following flow. 1. Set up the control program according to explanation above. 2. Click “Port Reset” button. Explanation of each buttons 1. [Port Reset]: 2. [Write default]: 3. [All Write]: 4. [Function1]: 5. [Function2]: 6. [Function3]: 7. [Function4]: 8. [Function5]: 9. [SAVE]: 10. [OPEN]: 11. [Write]: Set up the USB interface board (AKDUSBIF-A). Initialize the register of AK4584. Write all registers that is currently displayed. Dialog to write data by keyboard operation. Dialog to write data by keyboard operation. The sequence of register setting can be set and executed. The sequence that is created on [Function3] can be assigned to buttons and executed. The register setting that is created by [SAVE] function on main window can be assigned to buttons and executed. Save the current register setting. Write the saved values to all register. Dialog to write data by mouse operation. Indication of data Input data is indicated on the register map. Red letter indicates “H” or “1” and blue one indicates “L” or “0”. Blank is the part that is not defined in the datasheet. <KM065801> 2006/06 - 14 - ASAHI KASEI [AKD4584] Explanation of each dialog 1. [Write Dialog]: Dialog to write data by mouse operation There are dialogs corresponding to each register. Click the [Write] button corresponding to each register to set up the dialog. If you check the check box, data becomes “H” or “1”. If not, “L” or “0”. When writing the input data to AK4584, click [OK] button. If not, click [Cancel] button. 2. [Function1 Dialog]: Dialog to write data by keyboard operation Address Box: Data Box: Input registers address in 2 figures of hexadecimal. Input registers data in 2 figures of hexadecimal. When writing the input data to AK4584, click [OK] button. If not, click [Cancel] button. 3. [Function2 Dialog]: Dialog to evaluate GAIN/ATT This dialog corresponds to address 04H, 05H, 06H, and 07H. Address Box: Input registers address in 2 figures of hexadecimal. Start Data Box: Input starts data in 2 figures of hexadecimal. End Data Box: Input end data in 2 figures of hexadecimal. Interval Box: Data is written to AK4584 by this interval. Step Box: Data changes by this step. Mode Select Box: With checking this check box, data reaches end data, and returns to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00 Without checking this check box, data reaches end data, but does not return to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 When writing the input data to AK4584, click [OK] button. If not, click [Cancel] button. <KM065801> 2006/06 - 15 - ASAHI KASEI [AKD4584] 4. [Save] and [Open] 4-1. [Save] Save the current register setting data. The extension of file name is “akr”. (Operation flow) (1) Click [Save] Button. (2) Set the file name and push [Save] Button. The extension of file name is “akr”. 4-2. [Open] The register setting data saved by [Save] is written to AK4584. The file type is the same as [Save]. (Operation flow) (1) Click [Open] Button. (2) Select the file (*.akr) and Click [Open] Button. <KM065801> 2006/06 - 16 - ASAHI KASEI [AKD4584] 5. [Function3 Dialog] The sequence of register setting can be set and executed. (1) Click [F3] Button. (2) Set the control sequence. Set the address, Data and Interval time. Set “-1” to the address of the step where the sequence should be paused. (3) Click [Start] button. Then this sequence is executed. The sequence is paused at the step of Interval="-1". Click [START] button, the sequence restarts from the paused step. This sequence can be saved and opened by [Save] and [Open] button on the Function3 window. The extension of file name is “aks”. Figure 1. Window of [F3] <KM065801> 2006/06 - 17 - ASAHI KASEI [AKD4584] 6. [Function4 Dialog] The sequence that is created on [Function3] can be assigned to buttons and executed. When [F4] button is clicked, the window as shown in Figure 2 opens. Figure 2. [F4] window <KM065801> 2006/06 - 18 - ASAHI KASEI [AKD4584] 6-1. [OPEN] buttons on left side and [START] buttons (1) Click [OPEN] button and select the sequence file (*.aks). The sequence file name is displayed as shown in Figure 3. Figure 3. [F4] window(2) (2) Click [START] button, then the sequence is executed. 3-2. [SAVE] and [OPEN] buttons on right side [SAVE]: The sequence file names can assign be saved. The file name is *.ak4. [OPEN]: The sequence file names assign that are saved in *.ak4 are loaded. 3-3. Note (1) This function doesn't support the pause function of sequence function. (2) All files need to be in same folder used by [SAVE] and [OPEN] function on right side. (3) When the sequence is changed in [Function3], the file should be loaded again in order to reflect the change. <KM065801> 2006/06 - 19 - ASAHI KASEI [AKD4584] 7. [Function5 Dialog] The register setting that is created by [SAVE] function on main window can be assigned to buttons and executed. When [F5] button is clicked, the following window as shown in Figure 4opens. Figure 4. [F5] window 7-1. [OPEN] buttons on left side and [WRITE] button (1) Click [OPEN] button and select the register setting file (*.akr). (2) Click [WRITE] button, then the register setting is executed. 7-2. [SAVE] and [OPEN] buttons on right side [SAVE]: The register setting file names assign can be saved. The file name is *.ak5. [OPEN]: The register setting file names assign that are saved in *.ak5 are loaded. 7-3. Note (1) All files need to be in same folder used by [SAVE] and [OPEN] function on right side. (2) When the register setting is changed by [Save] Button in main window, the file should be loaded again in order to reflect the change. <KM065801> 2006/06 - 20 - ASAHI KASEI [AKD4584] MEASUREMENT RESULTS [Measurement condition] • Measurement unit : Audio Precision, System Two Cascade • MCLK : 256fs • BCLK : 64fs : 44.1kHz, 96kHz • fs : 24bit • Bit : AVDD=DVDD=TVDD=PVDD=5.0V • Power Supply • Interface : DIR/DIT • Temperature : Room [Measurement Results] Parameter ADC Analog Input Characteristics S/(N+D) (fs=44.1kHz, -0.5dB Input) (fs=96kHz, -0.5dB Input) D-Range (fs=44.1kHz, -60dB Input, A-weighted) (fs=96kHz, -60dB Input) S/N (fs=44.1kHz, A-weighted) (fs=96kHz) Interchannel Isolation DAC Analog Output Characteristics S/(N+D) (fs=44.1kHz, 0dB Output) (fs=96kHz, -0.5dB Output) D-Range (fs=44.1kHz, -60dB Output, A-weighted) (fs=96kHz, -60dB Output) S/N (fs=44.1kHz, A-weighted) (fs=96kHz) Interchannel Isolation <KM065801> Result Unit 92.0 88.3 dB dB 100.6 96.1 dB dB 101.0 96.1 110.5 dB dB dB 95.3 95.1 dB dB 105.5 100.4 dB dB 105.9 100.5 115.5 dB dB dB 2006/06 - 21 - ASAHI KASEI [AKD4584] [ADC Plot : fs=44.1kHz] AK M AK 4584 A DC THD+N vs. Input Level VDD =5.0V , fs=44.1kHz, fin=1kHz -80 -82 -84 -86 -88 -90 -92 d B F S -94 -96 -98 -100 -102 -104 -106 -108 -110 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 dB r C olo r Line Style Thick D ata Axis Blue Solid 3 D SP Anlr.TH D +N Am pl A Left las t.at2c Figure 1. THD+N vs. Input Level AK M AK 4584 A DC THD+N vs. Input Frequency VDD =5.0V , fs=44.1kHz, Input=-0.5dBr -80 -82 -84 -86 -88 -90 -92 d B F S -94 -96 -98 -100 -102 -104 -106 -108 -110 20 50 100 200 500 1k 2k 5k 10k 20k Hz C olo r Line Style Thick D ata Axis Blue Solid 3 D SP Anlr.TH D +N Am pl A Left las t.at2c Figure 2. THD+N vs. Input Frequency <KM065801> 2006/06 - 22 - ASAHI KASEI [AKD4584] AK M A K4584 ADC Linearity VDD =5.0V , fs=44.1kHz, fin=1kHz +0 -10 -20 -30 -40 d B F S -50 -60 -70 -80 -90 -100 -110 -120 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dB r C olo r Line Style Thick D ata Axis Blue Solid 3 D SP Anlr.Bandpas s A Left las t.at2c Figure 3. Linearity AK M A K4584 A DC Frequency Response VDD =5.0V , fs=44.1kHz, Input=-0.5dBr +0 -0.1 -0.2 -0.3 -0.4 d B F S -0.5 -0.6 -0.7 -0.8 -0.9 -1 20 50 100 200 500 1k 2k 5k 10k 20k Hz C olo r Line Style Thick D ata Axis Blue Solid 3 D SP Anlr.Am pl A Left las t.at2c Figure 4. Frequency Response <KM065801> 2006/06 - 23 - ASAHI KASEI [AKD4584] AK M AK 4584 A DC Crosstalk VDD =5.0V , fs=44.1kHz, Input=-0.5dBr -80 -85 -90 -95 -100 -105 d B -110 -115 -120 -125 -130 -135 -140 20 50 100 200 500 1k 2k 5k 10k 20k 5k 10k 20k Hz C olo r Line Style Thick D ata Axis Blue Blue Solid Solid 3 3 D SP Anlr.C ros s talk B D SP Anlr.C ros s talk A Left Left las t.at2c Figure 5. Crosstalk AK M AK 4584 A DC FFT P lot V DD=5.0V , fs=44.1kHz, fin=1kHz, Input=-0.5dBr +0 -20 -40 -60 d B F S -80 -100 -120 -140 -160 -180 20 50 100 200 500 1k 2k Hz C olo r Line Style Thick D ata Axis Blue Solid 3 Fft.C h.1 Am pl Le ft las t.at2c Figure 6. FFT Plot <KM065801> 2006/06 - 24 - ASAHI KASEI [AKD4584] AK M AK 4584 A DC FFT P lot VDD=5.0V, fs=44.1kHz, fin=1kHz, Input=-60dB r +0 -20 -40 -60 d B F S -80 -100 -120 -140 -160 -180 20 50 100 200 500 1k 2k 5k 10k 20k 2k 5k 10k 20k Hz C olo r Line Style Thick D ata Axis Blue Solid 3 Fft.C h.1 Am pl Le ft las t.at2c Figure 7. FFT Plot AK M AK 4584 A DC FFT P lot V DD=5.0V, fs=44.1kHz, fin=None +0 -20 -40 -60 d B F S -80 -100 -120 -140 -160 -180 20 50 100 200 500 1k Hz C olo r Line Style Thick D ata Axis Blue Solid 3 Fft.C h.1 Am pl Le ft las t.at2c Figure 8. FFT Plot <KM065801> 2006/06 - 25 - ASAHI KASEI [AKD4584] [ADC Plot : fs=96kHz] AK M AK 4584 A DC THD+N vs. Input Level VDD=5.0V, fs=96kHz, fin=1kHz -80 -82 -84 -86 -88 -90 -92 d B F S -94 -96 -98 -100 -102 -104 -106 -108 -110 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 dB r C olo r Line Style Thick D ata Axis Blue Solid 3 D SP Anlr.TH D +N Am pl A Left las t.at2c Figure 9. THD+N vs. Input Level AK M AK 4584 A DC THD+N vs. Input Frequency VDD=5.0V, fs=96kHz, Input=-0.5dB r -80 -82 -84 -86 -88 -90 -92 d B F S -94 -96 -98 -100 -102 -104 -106 -108 -110 20 50 100 200 500 1k 2k 5k 10k 20k 40k Hz C olo r Line Style Thick D ata Axis Blue Solid 3 D SP Anlr.TH D +N Am pl A Left las t.at2c Figure 10. THD+N vs. Input Frequency <KM065801> 2006/06 - 26 - ASAHI KASEI [AKD4584] AK M A K4584 ADC Linearity VDD=5.0V, fs=96kHz, fin=1kHz +0 -10 -20 -30 -40 d B F S -50 -60 -70 -80 -90 -100 -110 -120 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dB r C olo r Line Style Thick D ata Axis Blue Solid 3 D SP Anlr.Bandpas s A Left las t.at2c Figure 11. Linearity AK M A K4584 A DC Frequency Response VDD=5.0V, fs=96kHz, Input=-0.5dB r +0 -0.1 -0.2 -0.3 -0.4 d B F S -0.5 -0.6 -0.7 -0.8 -0.9 -1 20 50 100 200 500 1k 2k 5k 10k 20k 40k Hz C olo r Line Style Thick D ata Axis Blue Solid 3 D SP Anlr.Am pl A Left las t.at2c Figure 12. Frequency Response <KM065801> 2006/06 - 27 - ASAHI KASEI [AKD4584] AK M AK 4584 A DC Crosstalk VDD=5.0V, fs=96kHz, Input=-0.5dB r -80 -85 -90 -95 -100 -105 d B -110 -115 -120 -125 -130 -135 -140 20 50 100 200 500 1k 2k 5k 10k 20k 40k 5k 10k 20k 40k Hz C olo r Line Style Thick D ata Axis Blue Blue Solid Solid 3 3 D SP Anlr.C ros s talk B D SP Anlr.C ros s talk A Left Left las t.at2c Figure 13. Crosstalk AK M AK 4584 A DC FFT P lot VDD =5.0V , fs=96kHz, fin=1kHz, Input=-0.5dBr +0 -20 -40 -60 d B F S -80 -100 -120 -140 -160 -180 20 50 100 200 500 1k 2k Hz C olo r Line Style Thick D ata Axis Blue Solid 3 Fft.C h.1 Am pl Le ft las t.at2c Figure 14. FFT Plot <KM065801> 2006/06 - 28 - ASAHI KASEI [AKD4584] AK M AK 4584 A DC FFT P lot V DD=5.0V, fs=96kHz, fin=1kHz, Input=-60dBr +0 -20 -40 -60 d B F S -80 -100 -120 -140 -160 -180 20 50 100 200 500 1k 2k 5k 10k 20k 40k 5k 10k 20k 40k Hz C olo r Line Style Thick D ata Axis Blue Solid 3 Fft.C h.1 Am pl Le ft las t.at2c Figure 15. FFT Plot AK M AK 4584 A DC FFT P lot V DD=5.0V , fs=96kHz, fin=None +0 -20 -40 -60 d B F S -80 -100 -120 -140 -160 -180 20 50 100 200 500 1k 2k Hz C olo r Line Style Thick D ata Axis Blue Solid 3 Fft.C h.1 Am pl Le ft las t.at2c Figure 16. FFT Plot <KM065801> 2006/06 - 29 - ASAHI KASEI [AKD4584] [DAC Plot : fs=44.1kHz] AK M AK 4584 DA C THD+N vs. Input Level VDD =5.0V , fs=44.1kHz, fin=1kHz -80 -82 -84 -86 -88 -90 d B r -92 -94 -96 A -98 -100 -102 -104 -106 -108 -110 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBFS C olo r Line Style Thick D ata Axis Blue Solid 3 Anlr.TH D +N Am pl Left las t.at2c Figure 1. THD+N vs. Input Level AK M AK 4584 D AC THD+N vs. Input Frequency V DD=5.0V, fs=44.1kHz, Input=0dBFS -80 -82 -84 -86 -88 -90 d B r -92 -94 -96 A -98 -100 -102 -104 -106 -108 -110 20 50 100 200 500 1k 2k 5k 10k 20k Hz C olo r Line Style Thick D ata Axis Blue Solid 3 Anlr.TH D +N Am pl Left las t.at2c Figure 2. THD+N vs. Input Frequency <KM065801> 2006/06 - 30 - ASAHI KASEI [AKD4584] AK M A K4584 DAC Linearity VDD =5.0V , fs=44.1kHz, fin=1kHz +0 -10 -20 -30 -40 d B r -50 A -70 -60 -80 -90 -100 -110 -120 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBFS C olo r Line Style Thick D ata Axis Blue Solid 3 Anlr.Bandpas s Left las t.at2c Figure 3. Linearity AK M A K4584 D AC Frequency Response V DD=5.0V, fs=44.1kHz, Input=0dBFS +1 + 0.8 + 0.6 + 0.4 d B r A + 0.2 +0 -0.2 -0.4 -0.6 -0.8 -1 2k 4k 6k 8k 10k 12k 14k 16k 18k 20k Hz C olo r Line Style Thick D ata Axis Blue Solid 3 Anlr.Am pl Left las t.at2c Figure 4. Frequency Response <KM065801> 2006/06 - 31 - ASAHI KASEI [AKD4584] AK M AK 4584 DA C Crosstalk V DD=5.0V, fs=44.1kHz, Input=0dBFS -100 -102.5 -105 -107.5 -110 -112.5 d B -115 -117.5 -120 -122.5 -125 -127.5 -130 20 50 100 200 500 1k 2k 5k 10k 20k 5k 10k 20k Hz C olo r Line Style Thick D ata Axis Blue Blue Solid Solid 3 3 Anlr.C ros s talk Anlr.C ros s talk Left Left las t.at2c Figure 5. Crosstalk AK M AK 4584 D AC FFT P lot VDD =5.0V , fs=44.1kHz, fin=1kHz, Input=0dB FS +0 -20 -40 -60 d B r -80 -100 A -120 -140 -160 -180 20 50 100 200 500 1k 2k Hz C olo r Line Style Thick D ata Axis Blue Solid 3 Fft.C h.1 Am pl Le ft las t.at2c Figure 6. FFT Plot <KM065801> 2006/06 - 32 - ASAHI KASEI [AKD4584] AK M AK 4584 D AC FFT P lot VD D=5.0V , fs=44.1kHz, fin=1kHz, Input=-60dBFS +0 -20 -40 -60 d B r -80 -100 A -120 -140 -160 -180 20 50 100 200 500 1k 2k 5k 10k 20k 2k 5k 10k 20k Hz C olo r Line Style Thick D ata Axis Blue Solid 3 Fft.C h.1 Am pl Le ft las t.at2c Figure 7. FFT Plot AK M AK 4584 D AC FFT P lot V DD=5.0V, fs=44.1kHz, fin=None +0 -20 -40 -60 d B r -80 -100 A -120 -140 -160 -180 20 50 100 200 500 1k Hz C olo r Line Style Thick D ata Axis Blue Solid 3 Fft.C h.1 Am pl Le ft las t.at2c Figure 8. FFT Plot <KM065801> 2006/06 - 33 - ASAHI KASEI [AKD4584] [DAC Plot : fs=96kHz] AK M AK 4584 DA C THD+N vs. Input Level VDD=5.0V, fs=96kHz, fin=1kHz -80 -82 -84 -86 -88 -90 d B r -92 -94 -96 A -98 -100 -102 -104 -106 -108 -110 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBFS C olo r Line Style Thick D ata Axis Blue Solid 3 Anlr.TH D +N Am pl Left las t.at2c Figure 9. THD+N vs. Input Level AK M AK 4584 D AC THD+N vs. Input Frequency V DD=5.0V , fs=96kHz, Input=0dBFS -80 -82 -84 -86 -88 -90 d B r -92 -94 -96 A -98 -100 -102 -104 -106 -108 -110 20 50 100 200 500 1k 2k 5k 10k 20k 40k Hz C olo r Line Style Thick D ata Axis Blue Solid 3 Anlr.TH D +N Am pl Left las t.at2c Figure 10. THD+N vs. Input Frequency <KM065801> 2006/06 - 34 - ASAHI KASEI [AKD4584] AK M A K4584 D AC Frequency Response VDD=5.0V, fs=96kHz, fin=1kHz +0 -10 -20 -30 -40 d B r -50 A -70 -60 -80 -90 -100 -110 -120 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBFS C olo r Line Style Thick D ata Axis Blue Solid 3 Anlr.Bandpas s Left las t.at2c Figure 11. Linearity AK M A K4584 D AC Frequency Response V DD=5.0V , fs=96kHz, Input=0dBFS +1 + 0.8 + 0.6 + 0.4 d B r A + 0.2 +0 -0.2 -0.4 -0.6 -0.8 -1 2.5k 5k 7.5k 10k 12.5k 15k 17.5k 20k 22.5k 25k 27.5k 30k 32.5k 35k 37.5k 40k Hz C olo r Line Style Thick D ata Axis Blue Solid 3 Anlr.Am pl Left las t.at2c Figure 12. Frequency Response <KM065801> 2006/06 - 35 - ASAHI KASEI [AKD4584] AK M AK 4584 DA C Crosstalk V DD=5.0V , fs=96kHz, Input=0dBFS -90 -95 -100 -105 d B -110 -115 -120 -125 -130 20 50 100 200 500 1k 2k 5k 10k 20k 40k 5k 10k 20k 40k Hz C olo r Line Style Thick D ata Axis Blue Blue Solid Solid 3 3 Anlr.C ros s talk Anlr.C ros s talk Left Left las t.at2c Figure 13. Crosstalk AK M AK 4584 D AC FFT P lot VDD=5.0V, fs=96kHz, fin=1kHz, Input=0dB FS +0 -20 -40 -60 d B r -80 -100 A -120 -140 -160 -180 20 50 100 200 500 1k 2k Hz C olo r Line Style Thick D ata Axis Blue Solid 3 Fft.C h.1 Am pl Le ft las t.at2c Figure 14. FFT Plot <KM065801> 2006/06 - 36 - ASAHI KASEI [AKD4584] AK M AK 4584 D AC FFT P lot VDD =5.0V , fs=96kHz, fin=1kHz, Input=-60dBFS +0 -20 -40 -60 d B r -80 -100 A -120 -140 -160 -180 20 50 100 200 500 1k 2k 5k 10k 20k 40k 5k 10k 20k 40k Hz C olo r Line Style Thick D ata Axis Blue Solid 3 Fft.C h.1 Am pl Le ft las t.at2c Figure 15. FFT Plot AK M AK 4584 D AC FFT P lot V DD=5.0V , fs=96kHz, fin=None +0 -20 -40 -60 d B r -80 -100 A -120 -140 -160 -180 20 50 100 200 500 1k 2k Hz C olo r Line Style Thick D ata Axis Blue Solid 3 Fft.C h.1 Am pl Le ft las t.at2c Figure 16. FFT Plot <KM065801> 2006/06 - 37 - ASAHI KASEI [AKD4584] AK M AK 4584 D AC FFT P lot V DD=5.0V, fs=44.1kHz, fin=None +0 -20 -40 -60 d B r -80 -100 A -120 -140 -160 -180 20 50 100 200 500 1k 2k 5k 10k 20k 40k Hz C olo r Line Style Thick D ata Axis Blue Solid 3 Fft.C h.1 Am pl Le ft las t.at2c Figure 17. Outband Noise (fs=44.1kHz) AK M AK 4584 D AC FFT P lot V DD=5.0V , fs=96kHz, fin=None +0 -20 -40 -60 d B r -80 -100 A -120 -140 -160 -180 20 50 100 200 500 1k 2k 5k 10k 20k 50k 80k Hz C olo r Line Style Thick D ata Axis Blue Solid 3 Fft.C h.1 Am pl Le ft las t.at2c Figure 18. Outband Noise (fs=96kHz) <KM065801> 2006/06 - 38 - ASAHI KASEI [AKD4584] Revision History Date Manual Board Reason (YY/MM/DD) Revision Revision 01/11/01 KM065800 0 First Edition 06/06/26 KM065801 0 Change Contents Revised Control Software Manual IMPORTANT NOTICE • These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. • AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. • Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. • AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. • It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. <KM065801> 2006/06 - 39 - B C D E AVDD 1 R2 5.1 2 DVDD L1 (short) RIN LIN RX2 RX1 R1 5.1 1 A + C1 47u 2 VCC E E 34 35 1 + 36 37 38 1 2 CN3 AVSS VREF AVDD 34 C5 0.1u 35 C4 0.1u 36 C3 10u 37 40 R 42 41 PVSS D RX1 43 TEST1 RX2 44 U2 CN2 C2 10u RIN 1 R4 13k C6 0.1u D 1 1 TEST2 ROUT 33 2 2 RX3 LOUT 32 33 ROUT 32 LOUT 1 RX3 39 2 PDN 38 4 74HC14 2 SW1 PDN 40 41 42 U1B LIN 3 74HC14 H 3 2 + L U1A 39 1 43 44 R3 10k D1 HSU119 PVDD 1 2 CN1 3 NC RX4 4 4 PDN 5 6 C7 0.1u VCOM 31 RX4 DZF 30 30 DZF 5 PDN M/S 29 29 M/S 6 INT0 LRCK 28 28 31 2 3 + C8 2.2u VCC 1 C 1 LED1 INT0 R6 1k LED2 INT1 R8 1k 2 2 2 4 U3A 74HCT04 1 U3B 74HCT04 3 7 7 AK4584 INT1 BICK R5 100 27 4584_LRCK R7 100 2 3 4 5 6 7 8 9 27 CDTI 8 8 CDTI SDTI 26 26 CDTO 9 9 CDTO SDTO 25 25 CCLK 10 10 CCLK MCKO2 24 24 CSN 11 11 CSN MCKO1 23 23 6 5 4 3 2 1 4584_SDTI 4584_SDTO M2 19 1 RP1 47k JP1 MCKO C 4584_BICK U4 A1 A2 A3 A4 A5 A6 A7 A8 18 17 16 15 14 13 12 11 B1 B2 B3 B4 B5 B6 B7 B8 6 5 4 3 2 1 G DIR RP2 47k 74HCT245 22 TVDD C11 1 2 L2 (short) C15 + C14 47u DGND JP2 GND AGND 22 21 20 1 TVDD JP3 XTI 19 M/S DMCK XTI/MCKI 21 XTO 20 2 B 2 1 C13 10u 18 17 16 15 14 13 + 2 1 X1 11.2896MHz C10 0.1u C12 10u 12 19 18 + C9 0.1u 1 TVDD DVSS DVDD 17 TX3 16 XTALE 15 TX2 14 13 12 B TX1 TEST3 MCKO M1 CN4 Title DMCK MCKI TVDD DVDD TX3 XTALE TX2 TX1 A TEST3 A Size A3 Date: A B C D Document Number AKD4584 Rev AK4584 Tuesday, May 22, 2001 Sheet E A 1 of 4 B C D T1 TO92 1 3 L3 47u PORT1 6 6 5 5 4 3 2 1 GND VCC GND OUT DIR VOUT C17 0.1u VIN 2 + C16 47u C18 0.1u E 2 E VCC GND VCC E 1 A + C20 10u C19 0.1u C21 10u R9 470 + VD C22 0.1u 2 38 37 INT1 R AVDD 39 40 VCOM 41 AVSS 42 RX0 43 NC 44 RX1 45 TEST1 46 47 INT0 36 5 6 2 NC OCKS0 35 OCKS0 3 DIF0 OCKS1 34 OCKS1 4 TEST2 CM1 33 5 DIF1 CM0 32 6 NC PDN 31 7 DIF2 XTI 30 VCC 1 VCC R12 10k CM0 D2 HSU119 47k AK4114 C C24 5p 5 U1C 74HC14 8 9 U1D 74HC14 X2 11.2896MHz L C25 0.1u C26 5p 8 IPS1 XTO 29 9 P/SN DAUX 28 10 XTL0 MCKO2 27 11 XTL1 BICK 26 DIR_BICK 12 VIN SDTO 25 DIR_SDTI 1 6 3 OCKS0 OCKS1 CM0 TEST3 XTALE DMCK M/S H SW3 DIR 2 C 1 2 3 4 5 6 7 8 9 10 11 IPS0 LED3 ERF 1 MODE RP3 1 R11 1k 2 20 19 18 17 16 15 14 13 12 11 D U3C 74HCT04 1 SW2 R10 18k 2 1 2 3 4 5 6 7 8 9 10 RX2 VCC DIF0 DIF1 DIF2 OCKS0 OCKS1 CM0 TEST3 XTALE DMCK M/S NC RX3 U5 D 48 C23 0.47u R13 51 DAUX LRCK 24 MCKO1 23 22 DVSS DVDD C28 0.1u DIR_LRCK + 21 VOUT 20 UOUT 19 COUT 18 BOUT 17 TX1 16 15 14 TVDD 13 VCC C27 0.1u + VCC TX0 B DVSS B DIR_MCLK C29 10u C30 10u VD 5 A 6 PORT2 5 6 IN VCC IF GND DIT 4 3 2 1 A R14 1k C31 0.1u Title Size Document Number AKD4584 A3 Date: A B C D Tuesday, May 22, 2001 Rev DIR Sheet E A 2 of 4 A B C D E E E C32 10u + J1 RIN + RIN R15 220 J2 ROUT R18 220 J4 LOUT ROUT C33 22u R16 560 R17 10k D D C34 10u + J3 LIN + LIN LOUT C35 22u R19 560 C R20 10k C AVDD 2 R21 1k 1 DZF 3 TR1 RN1202 (10k,10k) 2 LED4 1 DZF B B 4 VCC D 3 CLK PR 2 8 9 5 12 U3F 13 6 12 1 CL 74HCT04 Q 11 74HCT04 U6A 74AC74 Q U3D U1F U3E 10 74HCT04 11 U1E 10 74HC14 13 74HC14 A A Title Size A3 Date: A B C D Document Number AKD4584 Rev Input/Output Tuesday, May 22, 2001 Sheet E A 3 of 4 A B C D E VDD EXT_MCLK R30 10k R23 R25 R28 470 470 470 2 3 4 5 6 7 8 9 CSN CCLK CDTI CDTO 10 9 8 7 6 1 19 R31 51 CTRL A1 A2 A3 A4 A5 A6 A7 A8 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 R24 R26 R29 18 17 16 15 14 13 12 11 100 100 100 CSN CCLK CDTI VCC E U6B 74AC74 10 10k J5 EXT G1 G2 74HCT541 JP6 EXT 12 D 11 CLK PR PORT3 10k R27 Q CL 1 2 3 4 5 R22 Q x1 9 JP4 MCLK 10 x2 11 U8 CLK RST 8 13 E U7 CDTO Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 x4 x2 x1 9 7 6 5 3 2 4 13 12 14 15 1 JP5 BCFS EXT_BICK x4 EXT_LRCK x1 JP7 LRFS 74HC4040 D D VDD 5 PORT4 6 5 IN VCC IF GND 6 TX 4 3 2 1 R32 1k DIT JP8 TX JP9 C36 0.1u TX1 TX2 TX3 SDTI TX1 TX2 TX3 R34 51 TX1-3 MCKO J6 TX T2 DA-02F R36 51 R37 330 BNC A1 A2 A3 A4 A5 A6 A7 A8 1 19 R38 100 C U9 2 3 4 5 6 7 8 9 4584_SDTO DIR_MCLK Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 18 17 16 15 14 13 12 11 R33 51 4584_SDTI DAUX 4584_MCKO MCKI R35 51 G1 G2 74HCT541 DIR C JP10 EXT_MCLK VDD 2 4584_MCKO 6 5 5 GND VCC GND OUT ADC L4 47u 4 3 2 1 MCLK DIR DIR_BICK 1 PORT5 6 EXT C37 0.1u DIR B RX JP12 470 JP13 RX J7 RX C39 R40 75 RX2 RX1 RX2 RX3 RX4 DIR_LRCK DIR B JP14 LRCK 4584_LRCK RX3 RX1-4 BNC EXT EXT_BICK RX1 R39 JP11 BICK 4584_BICK + C38 10u EXT_LRCK EXT RX4 0.1u MCLK BICK LRCK SDTI VCC SDTI VDD VCC for 74HCT541 A C48 47u + C47 0.1u C40 47u + C42 0.1u C43 0.1u ADC DIR_SDTI DIR JP15 SDTI PORT6 10 9 8 7 6 C44 0.1u C45 0.1u GND GND ROM R41 for 74HC14, 74HCT04, 74HCT245 74AC74, 74HC4040, 74HCT541 C41 0.1u DAUX 1 2 3 4 5 VCC 10k C46 0.1u A Title Size A3 Date: A B C D Document Number AKD4584 Rev LOGIC Tuesday, May 22, 2001 A Sheet E 4 of 4