ON NCP1336BDR2G Quasi-resonant current mode controller Datasheet

NCP1336A/B
Quasi-Resonant Current
Mode Controller for High
Power Universal Off-Line
Supplies
The NCP1336 hosts a high−performance circuitry aimed to
powering quasi−resonant converters. Capitalizing on a novel
valley−lockout system, the controller shifts gears and reduces the
switching frequency as the power loading becomes lighter. This
results in a stable operation despite switching events always occurring
in the drain−source valley. This system works down to the 4th valley
and toggles to a variable frequency mode beyond, ensuring an
excellent standby power performance.
The controller takes benefit of a high−voltage start−up current
source to provide a quick and lossless power−on sequence. To improve
the safety in overload situations, the controller includes an Over Power
Protection circuit which clamps the delivered power at high−line.
Safety−wise, an adjustable timer relies on the feedback voltage to
detect a fault. On version B, this fault triggers a triple−hiccup on the
VCC pin which naturally reduces the average input power drawn by
the converter. On version A, when a fault is detected, the controller is
latched−off.
Particularly well suited for adapter applications, the controller
features two latch inputs: one dedicated to Over Temperature
protection (OTP) which offers an easy means to connect a pull−down
temperature sensor like an NTC, and a second one more classical that
can be used to perform an accurate Over Voltage Protection.
Finally, a brownout pin which stops the circuit operation in presence
of a low mains condition is included.
Features
• Quasi−Resonant Peak Current−Mode Control Operation
• Valley Switching Operation with Valley−Lockout for Noise−Immune
•
•
•
•
•
•
•
•
•
•
http://onsemi.com
QUASI−RESONANT PWM
CONTROLLER FOR HIGH POWER
AC−DC WALL ADAPTERS
MARKING
DIAGRAM
14
14
1
SO−14
CASE 751AN
SUFFIX O
A
x
WL
Y
WW
G
NCP1336xG
AWLYWW
1
= Assembly Location
= A or B
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
PIN CONNECTIONS
OPP
OTP
Timer
ZCD
Ct
FB
CS
HV
OVP
BO
VCC
DRV
GND
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 25 of this data sheet.
Operation
Internal 5 ms Soft−Start
Loss−Free Adjustable Over Power Protection
Auto−Recovery or Latched Internal Output Short− Circuit Protection
Adjustable Timer for Improved Short−Circuit Protection
Overvoltage and Overtemperature Protection Inputs
Brownout Input
• Extremely Low No−Load and Standby Power
−500 mA/+800 mA Peak Current Source/Sink
• SO14 Package
Capability
• These are Pb−Free Devices
Internal Temperature Shutdown
• This Device uses Halogen−Free Molding Compound
Typical Applications
Direct Optocoupler Connection
• High Power ac−dc Converters for TVs, Set−Top Boxes etc
3 ms Blanking Delay to Ignore Leakage Ringing at
Turn−Off
• Offline Adapters for Notebooks
© Semiconductor Components Industries, LLC, 2014
April, 2014 − Rev. 2
1
Publication Order Number:
NCP1336/D
NCP1336A/B
PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
Function
1
OPP
Adjust the Over Power
Protection
A negative voltage applied to this pin reduces the internal maximum peak
current setpoint. Connecting it to an auxiliary winding through a resistor
divider thus performs Over Power compensation. If grounded, OPP is null.
Pin Description
2
OTP
Over−Temperature
Protection
Connect an NTC between this pin and GND pin. Pin 2 features an internal
current source that biases the NTC. When the NTC pulls the pin down, the
circuit permanently latches−off.
3
Timer
Timer
4
ZCD
Zero Crossing Detection
Connected to the auxiliary winding, this pin detects the core reset event.
5
Ct
Timing Capacitor
A capacitor connected to this pin acts as the timing capacitor in foldback
mode.
6
FB
Feedback Pin
Hooking an optocoupler collector to this pin will allow regulation.
7
CS
Current Sense
This pin monitors the primary peak current.
8
GND
−
Wiring a capacitor to ground helps selecting the timer duration.
This pin is the controller ground.
9
DRV
Driver Output
This pin is the driver’s output to an external MOSFET.
10
VCC
Supplies the Controller
This pin is connected to an external auxiliary voltage.
11
BO
Brownout
12
OVP
Over−Voltage Protection
13
NC
−
14
HV
High−Voltage Input
This pin is the brownout input.
By pulling this pin high, the controller can be permanently latched−off.
This pin is omitted for improved creepage.
Connected to the bulk capacitor, this pin powers the internal current source
to deliver a startup current.
OVERCURRENT PROTECTION ON NCP1336 VERSIONS
Auto−Recovery
Overcurrent protection
NCP1336 / A
Latched
Overcurrent protection
X
NCP1336 / B
X
http://onsemi.com
2
NCP1336A/B
HV−bulk
+
Vout
OPP
OTP
ZCD
+
Vin
1
14
2
13
3
12
4
11
5
10
6
9
7
8
OVP
GND
BO
NCP1336
+
GND
Figure 1. Typical Application Example
http://onsemi.com
3
NCP1336A/B
VDD
+
1st
−
HV
2nd
+
HV
−
Rpullup
FB
3rd
+
TSD
−
HV
Startup
VDD
4th
+
LOVP reset
Aux
−
PNOK
VCO
VCC
Latch
+
VCC Management
Fault
VDD
Clamp
BO Reset
ICt
DRV
1 2 34
Ct
Grand
Reset
CLK rst
−
DRV
Gate
Decimal Counter
+
Ct
Setpoint
Grand
Reset
Vdd
R
ItimerC
Q
Q
Ct
Discharge
ZCD
Timer
+
+
Demag
A & C:
Latched
−
Laux
S
10 V
ESD
Vth
S
leakage blanking
DRV
GND
Q
Q
ItimerD
−
IpFlag
S
R
Q
Q
VDD
5us Timeout
PWMReset
VCC
R
/4
+
Grand
Reset
VOVP
noise delay
+
Ipeak_min = 25% Limit
VDD
OTP
100 ns
Rsense
−
+
−
T°
SS End
VOTP
IpFlag
Ilimit
+ Vopp
OPP
IOTP
PWM Reset
Leading
Edge
Blanking
+
CS
OVP
−
−
+
−
+
HV
BO Reset
Noise Delay
VBO
+
BO
−
Ilimit
+
Soft−Start
−
IBO
Soft−Start End ? Then 1 Else 0
SS End
Figure 2. Internal Circuit Architecture
http://onsemi.com
4
NCP1336A/B
MAXIMUM RATINGS TABLE
Value
Unit
VCCmax
ICCmax
Symbol
Maximum Power Supply voltage, VCC pin, continuous voltage
Maximum current for VCC Pin
−0.3 to 28
$30
V
mA
VHVmax
IHVmax
High voltage pin (pin 14) voltage range
Pin 14 current range
−0.3 to 500
$20
V
mA
Maximum voltage on low power pins (except pin 9, pin 10 and pin 14)
Current range for low power pins (except pin 9, pin 10 and pin 14)
−0.3 to 10
$10
V
mA
−300
2
mV
mA
VCC + 1.0
V
Thermal Resistance Junction−to−Air
120
°C/W
Maximum Junction Temperature
150
°C
−60 to +150
°C
Vmax
Imax
Rating
VOPPmax
IOPPneg
Recommended maximum operating voltage on pin OPP (pin 1)
Maximum negative current into OPP pin (pin 1)
VDRV(MAX)
Maximum DRV pin voltage when DRV is in High state
RqJA
TJMAX
Storage Temperature Range
ESD Capability, HBM model (All pins except HV) (Note 1)
2
kV
ESD Capability, Machine Model (All pins except DRV) (Note 1)
200
V
ESD Capability, Machine Model (DRV pin) (Note 1)
160
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. This device series contains ESD protection rated using the following tests: Human Body Model 2000 V per JEDEC standard JESD22, Method
A114E. Machine Model Method 200 V per JEDEC standard JESD22, Method A115A.
2. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.
http://onsemi.com
5
NCP1336A/B
ELECTRICAL CHARACTERISTICS
(For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V unless otherwise noted)
Symbol
Rating
Min
Typ
Max
Unit
15
16
V
SUPPLY SECTION
VCCon
VCC increasing level at which the current source turns−off
14
VCCmin
VCC level below which output pulses are stopped
8
9
10
V
VCCreset
Internal latch reset level
−
5.5
−
V
Internal IC consumption, no output load on DRV pin (Fsw = 10 kHz)
−
1.4
2.0
mA
ICC1
ICC1light
ICC1 for a Feedback Voltage Equal to VHVCO (internal bias reduction), with CT =
220 pF (corresponding to an Fsw of about 20 kHz)
1.8
mA
ICC2
Internal IC consumption, 1 nF output load on pin 9, Fsw = 65 kHz
−
2.5
3.0
mA
ICC3
Internal IC consumption, hiccup phase (VCCmin < VCC < VCCon)
−
0.45
0.6
mA
3
6
9
mA
mA
INTERNAL STARTUP CURRENT SOURCE (TJ > 05C) (HV Pin Biased to 60 Vdc)
IC2
High−voltage current source, VCC = 10 V (Note 3)
IC1
High−voltage current source, VCC = 0
150
300
550
VTh
VCC transition level for IC1 to IC2 toggling point (IHV = 2.5 mA)
0.3
0.7
0.9
V
Ileak
Leakage current for the high voltage source, VHV(pin) = 500 Vdc
1
12
30
mA
DRIVE OUTPUT
Tr
Output voltage rise−time @ CL = 1 nF, 10%−90% of a 12 V output signal
−
40
75
ns
Tf
Output voltage fall−time @ CL = 1 nF, 10%−90% of a 12 V output signal
−
25
60
ns
Source current capability at VDRV = 2 V
−
500
−
mA
Isource
Isink
Sink current capability at VDRV = 10 V
VDRVlow
DRV pin level at VCC close to VCCmin with a 33 kW resistor to GND and a 1 nF
capacitor to GND
VDRVhigh
DRV pin level at VCC = 28 V with a 1 nF capacitor to GND (Note 3)
−
800
−
mA
7.6
−
−
V
−
−
17
V
DEMAGNETIZATION INPUT
Vth
Input threshold voltage (VZCD(pin) decreasing)
35
55
90
mV
VH
Hysteresis (VZCD(pin) increasing)
15
35
55
mV
8
−0.9
10
−0.7
12
0
V
V
VCH
VCL
Input clamp voltage
High state (IZCD(pin) = 3.0 mA)
Low state (IZCD(pin) = −2.0 mA)
Tdem
Demag propagation delay (VZCD(pin) decreasing from 4 V to −0.3 V)
−
150
250
ns
Cpar
Internal input capacitance at VZCD(pin) = 1 V
−
10
−
pF
Blanking Delay after tON
2
3
4
ms
Timeout after last demag transition
4
5.25
6.5
ms
Tblank
Tout
CURRENT COMPARATOR
−
0.02
−
mA
ILimit1
Maximum internal current setpoint – TJ = 25°C – OPP pin grounded
0.76
0.8
0.84
V
ILimit2
Maximum internal current setpoint – TJ from −40°C to 125°C – OPP pin grounded
0.744
0.8
0.856
V
22
25
28
%
−
100
160
ns
240
240
295
295
350
360
ns
IIB
Input Bias Current @ 1 V input level on CS pin
Ipeak_VCO Percentage of maximum peak current level at which VCO takes over (Note 4)
3.
4.
5.
6.
TDEL
Propagation delay from current detection to gate OFF state
TLEB
Leading Edge Blanking Duration
TJ = −5°C to +125°C
TJ = −40°C to +125°C
Minimum value for TJ = 125°C.
The peak current setpoint goes down as the load decreases. It is frozen below Ipeak_VCO (Ipeak = cst)
If negative voltage in excess to −300 mV is applied to OPP pin, the current setpoint decrease is no longer guaranteed to be linear.
NTC on OTP pin with R = 8.8 kW at 110°C.
http://onsemi.com
6
NCP1336A/B
ELECTRICAL CHARACTERISTICS
(For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V unless otherwise noted)
Symbol
Rating
Min
Typ
Max
Unit
CURRENT COMPARATOR
OPPmax
Setpoint decrease for VOPP = −300 mV (Note 5)
35
37.5
40
%
OPPs
Setpoint decrease for OPP pin shorted to ground
−
0
−
%
5
5.5
−
V
18
17.42
20
20
22
22
mA
Minimum voltage on Ct, discharge switch activated
−
−
90
mV
Recommended timing capacitor value
−
220
−
pF
16
15.5
18
18
24
24
kW
TIMING CAPACITOR
VCTmax
ICT
VCTmin
Ct
Maximum voltage on Ct capacitor, VFB < VFBT
Source current (Ct pin grounded)
TJ = −5°C to +125°C
TJ = −40°C to +125°C
FEEDBACK SECTION
Rpullup
Internal pullup resistor
TJ = −5°C to +125°C
TJ = −40°C to +125°C
Iratio
FB pin to current setpoint division ratio
3.75
4
4.25
VFBT
FB pin threshold under which the Ct capacitor is clamped to VCTMAX
0.26
0.3
0.34
V
VH2D
VH3D
VH4D
FB voltage where
1st
FB voltage where
2nd
FB voltage where
3rd
valley ends and
2nd
valley starts (VFB decreasing)
1.316
1.4
1.484
V
valley ends and
3rd
valley starts (VFB decreasing)
1.128
1.2
1.272
V
valley ends and
4th
valley starts (VFB decreasing)
0.846
0.9
0.954
V
VHVCOD
FB voltage where 4th valley ends and VCO starts (VFB decreasing)
0.752
0.8
0.848
V
VHVCOI
FB voltage where VCO ends and 4th valley starts (VFB increasing)
1.316
1.4
1.484
V
VH4I
VH3I
VH2I
FB voltage where
4th
ends and
3rd
FB voltage where
3rd
valley starts (VFB increasing)
1.504
1.6
1.696
V
ends and
2nd
FB voltage where
2nd
valley starts (VFB increasing)
1.692
1.8
1.908
V
ends and
1st
valley starts (VFB increasing)
1.88
2
2.12
V
2.79
3
3.21
V
Delay before latch confirmation (noise immunity)
15
20
25
ms
Internal source current for OTP (Note 6)
85
82
93
93
97
98
mA
−
91
−
mA
Fault detection level for OTP (Note 6)
0.76
0.8
0.84
V
Timer Level Completion
4.65
5
5.35
V
8.5
8.25
10
10
11.5
11.5
mA
PROTECTIONS
VOVP
Tlatchdel
Ilatch
Ilatch110
VOTP
VtimFault
TJ = −5°C to +125°C
TJ = −40°C to +125°C
Internal source current for OTP @ 110°C (Note 6)
ItimerC
Timer capacitor charging current
ItimerD
Timer capacitor discharging current
8.5
10
11.5
mA
TimerL
Timer length, Ctimer = 0.1 mF typical
−
50
−
ms
TSS
Soft−start duration
−
5
−
ms
TSD
Temperature shutdown
140
−
−
°C
−
40
−
°C
TSDhys
3.
4.
5.
6.
OVP level
TJ = −5°C to +125°C
TJ = −40°C to +125°C
Temperature shutdown hysteresis
Minimum value for TJ = 125°C.
The peak current setpoint goes down as the load decreases. It is frozen below Ipeak_VCO (Ipeak = cst)
If negative voltage in excess to −300 mV is applied to OPP pin, the current setpoint decrease is no longer guaranteed to be linear.
NTC on OTP pin with R = 8.8 kW at 110°C.
http://onsemi.com
7
NCP1336A/B
ELECTRICAL CHARACTERISTICS
(For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V unless otherwise noted)
Symbol
Rating
Min
Typ
Max
Unit
0.744
0.8
0.856
V
9
8.65
10
10
11
11
mA
BROWNOUT PROTECTION
3.
4.
5.
6.
VBO
Brownout level
IBO
Hysteresis Current, VBO(pin) < VBO
TJ = −5°C to +125°C
TJ = −40°C to +125°C
TBOdel
Delay before BO confirmation (noise immunity)
11
17
23
ms
IBObias
Brownout input bias current
−
0.02
−
mA
Minimum value for TJ = 125°C.
The peak current setpoint goes down as the load decreases. It is frozen below Ipeak_VCO (Ipeak = cst)
If negative voltage in excess to −300 mV is applied to OPP pin, the current setpoint decrease is no longer guaranteed to be linear.
NTC on OTP pin with R = 8.8 kW at 110°C.
http://onsemi.com
8
NCP1336A/B
APPLICATION INFORMATION
NCP1336 implements a standard current−mode
architecture operating in quasi−resonant mode. Thanks to a
novel circuitry, the controller prevents valley−jumping
instability and steadily locks out in selected valley as the
power demand goes down. Once the fourth valley is reached,
the controller continues to reduce the frequency further
down, offering excellent efficiency over a wide operating
range. Thanks to a fault timer combined to an OPP circuitry,
the controller is able to efficiently limit the output power at
high−line.
• Quasi−Resonance Current−mode operation:
implementing quasi−resonance operation in peak
current−mode control, the NCP1336 optimizes the
efficiency by switching in the valley of the MOSFET
drain−source voltage. Thanks to a novel circuitry, the
controller locks−out in a selected valley and remains
locked until the output loading significantly changes.
This behavior is obtained by monitoring the feedback
voltage. When the load becomes lighter, the feedback
setpoint changes and the controller jumps into the next
valley. It can go down to the 4th valley if necessary.
Beyond this point, the controller reduces its switching
frequency by freezing the peak current setpoint. During
quasi−resonance operation, in case of very damped
valleys, a 5 ms timer adds the missing valleys.
• Frequency reduction in light−load conditions: when
the 4th valley is left, the controller reduces the
switching frequency which naturally improves the
standby power by a reduction of all switching losses.
• Overpower protection (OPP): a negative voltage
applied on OPP pin is directly added to the internal
peak current setpoint. If this voltage is created from an
auxiliary winding with flyback polarity, a direct image
of the input voltage is subtracted from the internal
clamp, thus reducing the peak current at high line. If the
OPP pin is connected to ground no compensation is
performed.
• Internal high−voltage startup switch: reaching a low
no−load standby power represents a difficult exercise
when the controller requires an external, lossy, resistor
connected to the bulk capacitor. Thanks to an internal
•
•
•
•
•
logic, the controller disables the high−voltage current
source after startup which no longer hampers the
consumption in no−load situations.
Internal soft−start: a soft−start precludes the main
power switch from being stressed upon start−up. Its
duration is fixed and equal to 5 ms.
OTP input: thanks to an internal current source, the
controller allows the direct connection of an NTC to
ground. As soon as the pin is brought below VOTP by
the NTC, the circuit permanently latches−off. During
soft−start, the OTP comparator is masked to allow the
voltage on pin OTP to rise above VOTP.
OVP input: thanks to an internal bias resistor to
ground, the controller allows the direct connection of a
zener diode (or a resistor divider for improved
accuracy) to a monitored voltage. As soon as the pin is
brought above VOVP, the controller latches−off.
Short−circuit protection: short−circuit and especially
over−load protections are difficult to implement when a
strong leakage inductance between auxiliary and power
windings affects the transformer (where the auxiliary
winding level does not properly collapse in presence of
an output short). Here, when the internal 0.8 V
maximum peak current limit is activated, the timer
capacitor is charged. If the fault disappears, the timer
capacitor is discharged by a current equal to the
charging current. If the timer reaches completion while
the error flag is still present, the controller stops the
pulses and goes into a latch−off phase, operating in a
low−frequency burst−mode via a triple hiccup
operation. To limit the fault output power, a
divide−by−three circuitry is installed on the VCC pin
and requires 3 times a start−up sequence before
attempting to restart on version B. As soon as the fault
disappears, the SMPS resumes operation. The latch−off
phase can also be initiated, more classically, when VCC
drops below VCCmin. On version A, the fault is latched.
Brownout: the NCP1336 includes a brownout circuit
which safely stops the controller in case the input
voltage is too low. Restart occurs via a complete startup
sequence (latch reset and soft−start).
http://onsemi.com
9
NCP1336A/B
APPLICATION INFORMATION
The NCP1336 has two operating modes: quasi resonant
operation and VCO operation.
The operating mode is fixed by the FB voltage:
• Quasi−resonant operation occurs for FB voltage higher
than 0.8 V (FB decreasing) or higher than 1.6 V (FB
increasing) which correspond to high output power and
medium output power.
During quasi−resonant operation, the operating valley
(1st, 2nd, 3rd or 4th) is fixed by the FB voltage which is
compared internally to several voltage references
corresponding to the different valleys. There is a wide
hysteresis on each valley, allowing the controller to
adjust the output power by the current−mode control
without jumping between valleys. The peak current is
variable and is set by the FB voltage divided by 4.
• VCO operation occurs for FB voltage lower than 0.8 V
(FB decreasing) or lower than 1.6 V (FB increasing).
This corresponds to low output power.
During VCO operation, the peak current is fixed to 25%
of its maximum value and the frequency is variable.
The frequency is set by the end of charge of Ct
capacitor. This capacitor is charged with a constant
current source and the capacitor voltage is compared to
an internal threshold fixed by FB voltage. When this
capacitor voltage reaches the threshold the capacitor is
rapidly discharged down to 0 V and a new period start.
Startup
NCP1336 includes a high voltage startup circuitry that
derives current from the bulk line to charge the VCC
capacitor. When the power supply is first connected to the
mains outlet, the internal current source is biased and
charges up the VCC capacitor. When the voltage on this VCC
capacitor reaches the VCCon level, the current source turns
off, reducing the amount of power being dissipated. At this
time, the controller is only supplied by the VCC capacitor,
and the auxiliary supply should take over before VCC
collapses below VCCmin. Figure 3 shows the internal
arrangement of this structure:
HV
HV
+
-
IC1 or IC2
VCC
+
VCCon
VCCmin
+
GND
Figure 3. Startup Circuitry: The Current Source Brings VCC Above 15 V and Turns Off
VCC
In some fault situations, a short−circuit can purposely
occur between VCC and GND. In high line conditions (VHV
= 370 Vdc) the current delivered by the startup device will
seriously increase the junction temperature. For instance,
since IC2 equals 3 mA (the min corresponds to the highest
TJ), the device would dissipate 370 V x 3 mA = 1.11 W. To
avoid this situation, the controller includes a novel circuitry
made of two startup levels, IC1 and IC2. At power−up, as
long as VCC is below a certain level (0.7 V typ.), the source
delivers IC1 (around 300 mA typical), then, when VCC
reaches 0.7 V, the source smoothly transitions to IC2 and
delivers its nominal value. As a result, in case of
short−circuit between VCC and GND, the power dissipation
will drop to 370 V x 300 mA = 111 mW. Figure 4 portrays
this particular behavior:
Figure 4. The Dual Level Startup Current Source
http://onsemi.com
10
NCP1336A/B
The first startup period is calculated by the formula, CV
= It which implies a 22 mF x 0.9 V / 150 mA = 132 ms startup
time for the first sequence. The second sequence is obtained
by changing I to 3 mA (worst case calculation) with DV =
15 V − 0.9 V = 14.1 V, which finally leads to a second startup
time of 22 mF x 14.1 V / 3 mA = 103 ms. The total startup
time becomes 103 ms + 132 ms = 235 ms. Please note that
this calculation is approximated by the presence of the knee
in the vicinity of the transition.
As soon as VCC reaches VCCon, drive pulses are delivered
on pin 9 and the auxiliary winding increases the voltage on
the VCC pin. At the same time, the controller smoothly
ramps up the peak current to Imax (0.8 V / Rsense) which is
reached after a typical 5 ms soft−start period. As soon as the
CS voltage reaches 0.8 V = ILimit1, the internal error flag
IpFlag is asserted. When the error flag is asserted, the current
source on pin 3 is activated and charges up the capacitor
connected to this pin. If the error flag is still asserted when
the timer capacitor has reached the threshold level
VtimFault, then the controller assumes that the power
supply has really undergone a fault condition and
immediately stops all pulses to enter a safe burst operation.
Figure 5 depicts the VCC evolution during a proper startup
sequence, showing the state of the error flag:
Figure 5. An error flag gets asserted as soon as the current setpoint reaches its upper limit
(0.8 V/Rsense). Here the timer lasts 50 ms, a 100 nF capacitor being connected to pin 3.
NCP1336 Operation
The valley detection is done by monitoring the voltage of
the auxiliary winding of the transformer. The typical
detection level is fixed at 55 mV. When a valley is detected,
the decimal counter is incremented. The operating valley
(1st, 2nd, 3rd or 4th) is determined by the FB voltage. As FB
voltage decreases or increases, the valley comparators
toggle one after another to select the proper valley. The
activation of an “n” valley comparator disables the “n+1” or
“n−1” valley comparator (depending if FB increases or
decreases) and enables the corresponding “n” output of the
decimal counter. Figure 6 shows the internal arrangement of
the valley selection circuitry.
http://onsemi.com
11
NCP1336A/B
VDD
+
−
Rpullup
FB
1st
+
−
2nd
+
−
3rd
+
−
4th
VCO
VDD
ICt
Ct
Setpoint
Ct
1 2 3 4
Decimal Counter
CLK
−
+
rst
Ct
Discharge
ZCD
Laux
VFBth
DRV
+
−
10 V
ESD
Vth
DRV
Demag
Leakage
Blanking
Tblank
Time
Out
S Q
Q
R
CS Comparator
Figure 6. Valley Selection and VCO Internal Schematic
When an “n” valley is asserted by the valley selection
circuitry, the controller is locked in this valley until the FB
voltage decreases of 0.6 V (“n+1” valley activates) or
increases of 0.8 V (“n−1” valley activates). The peak current
adjusts to deliver the necessary output power (See Figure 7
and Figure 8). Each comparator has a hysteresis of 600 mV
that helps to stabilize the valley selection in case of
oscillations on FB voltage.
Figure 7. Peak Current Setpoint and Selected Valley
vs. FB Voltage when FB Voltage Decreases
http://onsemi.com
12
NCP1336A/B
Figure 8. Selected Valley According to FB State
to deliver the necessary output power. This allows achieving
very low standby power consumption.
Figure 9 shows a simulation case where the output current
of a 19 V / 60 W adapter decreases from 2.5 A to 0.5 A. No
instability is seen during the valley transitions (Figures 10,
11, 12 and 13.)
As the output load decreases (FB voltage decreases), the
valleys are incremented from the first to the fourth. When
the fourth valley is reached, if FB voltage further decreases
below 0.8 V, the controller enters VCO mode as in
NCP1351.
During VCO operation, the peak current is frozen to 25%
of maximum peak current: the switching frequency expands
Figure 9. Output Load Decreases from 2.5 A to
0.5 A at VIN = 120 Vdc for a 19 V / 60 W Adapter
http://onsemi.com
13
NCP1336A/B
Plot2
feedback in volts
2 feedback
3 vdrain
4 vct
2.20
VFB
1.80
2
1.40
1.00
600m
Plot3
vdrain in volts
300
200
Vdrain
100
3
0
−100
Plot4
vct in volts
4.00
3.00
2.00
VCt
1.00
4
0
6.41m
6.43m
6.45m
time in seconds
6.47m
6.49m
Figure 10. Zoom 1: 1st to 2nd Valley Transition
Plot2
feedback in volts
2 feedback
3 vdrain
4 vct
2.20
1.80
VFB
1.40
2
1.00
600m
Plot3
vdrain in volts
300
200
Vdrain
100
0
3
−100
Plot4
vct in volts
4.00
3.00
2.00
VCt
1.00
0
4
7.135m
7.153m
7.170m
time in seconds
7.188m
Figure 11. Zoom 2: 2nd to 3rd Valley Transition
http://onsemi.com
14
7.205m
NCP1336A/B
2 feedback
3 vdrain
4 vct
Plot2
feedback in volts
2.20
VFB
1.80
1.40
1.00
2
600m
Plot3
vdrain in volts
300
200
3
Vdrain
100
0
−100
Plot4
vct in volts
4.00
3.00
2.00
VCt
1.00
4
0
7.902m
7.917m
7.932m
time in seconds
7.946m
7.961m
Figure 12. Zoom 3: 3rd to 4th Valley Transition
Plot2
feedback in volts
2 feedback
3 vdrain
4 vct
2.20
VFB
1.80
1.40
1.00
2
600m
Plot3
vdrain in volts
300
Vdrain
200
3
100
0
−100
Plot4
vct in volts
4.00
3.00
2.00
1.00
4
0
8.24m
8.26m
8.29m
time in seconds
8.31m
8.34m
Figure 13. Zoom 4: 4th Valley to VCO Mode Transistion
http://onsemi.com
15
VCt
NCP1336A/B
Time Out
integrates a Time Out function that acts as a clock for the
decimal counter. The controller thus continues its normal
operation. To avoid having a too big step in frequency, the
time out duration is set to 5.25 ms. Figures 15 and 16 detail
the time out operation.
In case of extremely damped free oscillations, the ZCD
comparator can be unable to detect the valleys.
Consequently, the decimal counter clock is in low state and
the drive pulses stops. To avoid such situation, NCP1336
1
2
3
4
Decimal Counter
clk
ZCD
+
+
Vth
10 V
ESD
Laux
DRV
demag
Leakage
Blanking
3 ms Pulse
Vdd
5 ms Timeout
+
100 ns
Figure 14. Time Out Circuit
http://onsemi.com
16
+
-
rst
NCP1336A/B
3 Demag
4
Vth
high
14 3rd
The 3rd Valley is Validated
low
12 2nd
The 3rd Valley is Not
Detected by the ZCD Comp
high
low
high
15 ZCDcomp
The 2nd Valley is Detected
by the ZCD Comparator
low
16 TimeOut
TimeOut Adds a Pulse to Account
for the Missing 3rd Valley
high
low
17 Clk
4.79m
4.81m
4.83m
time in seconds
4.85m
4.87m
Figure 15. Time Out Operation Chronogram
Demag
3
4 Vth
18 4th
high
The 4th Valley is Validated
low
14 3rd
high
15 ZCDcomp
low
high
low
16 TimeOut
TimeOut Adds 2 Pulses to Account for
the Missing 3rd and 4th Valley
high
low
17 Clk
7.08m
7.12m
7.16m
time in seconds
7.20m
Figure 16. Time Out Operation Chronogram continued
http://onsemi.com
17
7.24m
NCP1336A/B
VCO Mode
the capacitor voltage is compared to an internal threshold
fixed by FB voltage (see Figure 6). When this capacitor
voltage reaches the threshold, the capacitor is rapidly
discharged down to 0 V and a new period start. The internal
threshold is inversely proportional to the FB voltage. The
relationship between VFBth and VFB is: VFBth = 6.5 − (10/3)
VFB. When VFB is lower than 0.3 V, Ct voltage is clamped to
VCTmax = 5.5 V. Figure 17 shows the VCO mode at works.
VCO operation occurs for FB voltage lower than 0.8 V
(FB decreasing), or lower than 1.6 V (FB increasing). This
corresponds to low output power.
During VCO operation, the peak current is fixed to 25%
of its maximum value and the frequency is variable and
expands as the output power decreases.
The frequency is set by the end of charge of Ct capacitor.
This capacitor is charged with a constant current source and
Plot3
drv in volts
Plot2
v(fbint:x1),vct in volts
Plot1
iout in amperes
1 iout
2 vct
3 v(fbint:x1)
5 drv
800m
IOUT
600m
400m
200m
1
0
Ct,
FB threshold
7.00
5.00
3
2
3.00
1.00
−1.00
30.0
DRV
20.0
10.0
0
5
−10.0
7.57m
7.78m
7.99m
time in seconds
8.20m
8.40m
Figure 17. In VCO Mode, as the Power Output Decreases the Frequency Expands
HV
Vcc
Vcc Management
S
Q
Vdd
DRV
Q
Fault
R
CS
FB/4
ItimerC
PNOK
PWM
PWM
Reset
Comparator
+
-
Timer
+
+
R
VtimFault
Q
Max Ip
IpFlag
Comparator
+
+
Ilimit + Vopp
+
OPP
Q
S
Ilimit
Figure 18. Fault Timer Schematic
http://onsemi.com
18
ItimerD
Ctimer
NCP1336A/B
Short−circuit or Overload Mode
and the PWM comparator triggers the discharge of the timer
capacitor.
If “IpFlag” and PWMreset occur at the same time, the
PWMreset signal is the strongest and the capacitor is
discharged.
Figure 18 shows the implementation of the fault timer.
When the current in the MOSFET is higher than, “Max
(0.8 V / Rsense) Ip” comparator trips and the timer capacitor is
charged by ItimerC current source. When the current comes
back within safe limits, “Max Ip” comparator becomes silent
3 v(ipflag:x1) 4 v(pwm:x1) 8 feedback 9 vtimer
3.00
2.60
2.20
1.80
VFB
1.40
vtimer in volts
plot1
feedback in volts
3.40
1.00
8
9
600m
VTimer
200m
−200m
high
plot2
IpFlag
low
high
3
PWMreset
low
6.13m
6.37m
6.60m
time in seconds
6.84m
7.08m
4
Figure 19. Timer Operating Chronograms
There can be various events that force a fault on the
primary side controller. We can split them in different
situation, each having a particular configuration:
1. The converter regulates but the auxiliary winding
collapses: this is a typical situation linked to the
usage of a constant−current / constant−voltage
(CC−CV) type of controller. If the output current
increases, the voltage feedback loop gives up and
the current loop takes over. It means that VOUT
goes low but the feedback loop is still closed
because of the output current monitoring.
Therefore, seen from the primary side, there is no
fault. However, there are numerous charger
applications where the output voltage shall not go
below a certain limit, even if the current is
controlled. To cope with this situation, the
controller features a precise under−voltage lockout
comparator biased to a VCCmin level. When this
level is crossed, whatever the other pin conditions,
pulses are stopped and the controller enters the
safe hiccup mode, trying to re−start. Figure 20
shows how the converter will behave in this
situation. If the fault goes away, the SMPS
resumes operation.
2. In the second case, the converter operates in
regulation, but the output is severely overloaded.
However, due to the bad coupling between the
power and the auxiliary windings, the controller
VCC does not go low. The peak current is pushed
to the maximum, the error flag IpFlag is
consequently asserted and the timer starts to count.
Upon completion, all pulses are stopped and
triple−startup hiccup mode is entered for
version B. If the fault goes away, the SMPS
resumes operation (Figure 21). For version A,
when the timer finishes counting, the pulses stop
and the circuit stays latched until the user cycles
down the power supply (Figure 22).
3. Another case exists where the short−circuit makes
the auxiliary level go below VCCmin. In that case,
the timer length is truncated and all pulses are
stopped. The triple hiccup fault mode is entered
and the SMPS tries to re−start. When the fault is
removed, the SMPS resumes operation.
http://onsemi.com
19
NCP1336A/B
Figure 20. First Fault Mode Case, the Auxiliary
Winding Collapses but Feedback is Still There
Figure 21. Short−Circuit Case Where Vaux Does
NOT Collapse on Version B
Figure 22. Short−Circuit Case Where Vaux Does
NOT Collapse on Version A
http://onsemi.com
20
NCP1336A/B
Figure 23. This Case is Similar to a Short−Circuit Where Vaux Does Collapse
The recurrence in hiccup mode can easily be adjusted by either reducing the timer or increasing the VCC capacitor. Figure 24
details the various time portion a hiccup is made of:
Figure 24. The Burst Period is Ensured by the VCC Capacitor Charge / Discharge Cycle
If by design we have selected a 22 mF VCC capacitor, it
becomes easy to evaluate the burst period and its duty−cycle.
This can be done by properly identifying all time events on
Figure 8 and applying the classical formula:
The total period duration is thus the sum of all these events
which leads to thiccup = 572 ms. If tfault = 50 ms, then our
burst duty−cycle equals 50 ms / (572 ms + 50 ms) ≈ 8%,
which is good. Should the user like to further decrease or, to
the contrary, increase this duty−cycle, changing the VCC
capacitor is an easy job.
t + CDV
I
• t1: I = 3 mA, ΔV= 15 V − 9 V = 6 V ³ t1 = 44 ms
• t2: I = ICC3 = 600 mA, ΔV= 15 V − 9 V = 6 V ³ t2 =
220 ms
http://onsemi.com
21
NCP1336A/B
Over Voltage / Over Temperature Protection
The OTP and OVP pins feature circuitries to protect the circuit against high temperature and high voltage (see Figure 25).
Vcc
+
VOVP
+
20 ms Filter
OVP
Vdd
Rbias
End of
Soft−start
IOTP
OTP
+
+
T°
VOTP
Figure 25. Pin Latch Circuitry
OTP
OVP
A current flows out of the OTP pin into the NTC resistor,
thus imposing a voltage on the OTP pin. When the
temperature increases, the NTC’s resistance reduces (For
example, at 110°C, RNTC = 8.8 k instead of 470 k at 25°C)
and the voltage on the OTP pin decreases until it reaches
VOTP: the comparator trips and latches−off the controller. To
reset the controller, the user must unplug and re−plug the
power supply.
During start−up and soft−start, the output of the OTP
comparator is masked to allow for the voltage on the OTP
pin to grow if a capacitor is installed across the NTC for
filtering purposes.
When VCC increases (OVP), a current starts to flow in the
zener (which much be biased externally), and the voltage on
the OVP pin starts to increase. When this voltage reaches
VOVP, the circuit immediately stops pulsing and stays
latched until the user cycles down the power supply. The
reset occurs if VCC drops below 5 V (or brownout is
detected).
Figures 26 and 27 details the operating diagrams in case
of an over temperature and an overvoltage event.
VOTP(pin)
Ambient temperature
increases
VOTP
Figure 26. Operating Diagrams in Case of an Over Temperature
http://onsemi.com
22
NCP1336A/B
VOVP(pin)
VOVP
Figure 27. Operating Diagrams in Case of an Over Voltage
Over Power Protection
The implementation of over power compensation in
NCP1336 is described by Figure 28. A negative voltage
applied on the OPP pin directly affects the precise maximum
peak current reference.
Rupper
OPP
+
Aux
ESD
Protection
Rlower
CS
0.8 V + Vopp
+
0.8 V
Leading Edge
Blanking
+
IpFlag
+
-
PWMreset
Rsense
FB/4
Figure 28. The Internal OPP Circuitry Implemented on NCP1336
By connecting the OPP pin through a resistor divider to an
auxiliary winding with flyback polarity, where a negative
voltage proportional to the input voltage appears during the
on−time, the maximum peak current setpoint is simply
decreased according to VIN, following Figure 29.
http://onsemi.com
23
NCP1336A/B
VHV
Figure 29. Peak Current Setpoint Variation vs. OPP Pin Voltage
R upper
0.25
+*
R lower
By adding a zener diode in series with the resistor divider,
the user has the choice to adjust the level at which the OPP
is applied to the power chip.
370 * (−0.2)
+ 461.5
−0.2
With Rupper = 470 kW and Rlower = 1 kW for instance, the
OPP function is performed with negligible power wasted in
the resistor divider.
Design Example
Let us assume we need a current setpoint reduction of 25%
at 370 Vdc, which corresponds to a sense voltage of 600 mV.
We thus need to apply 600 mV − 800 mV = −200 mV on
OPP pin to perform the expected compensation.
Knowing that the voltage that appears on the auxiliary
winding during the on−time is −Np,aux VIN, with Np,aux the
auxiliary to primary turn ratio of the transformer (Np,aux =
Naux/Np), we can simply calculate the ratio of the resistor
divider:
Brownout
The NCP1336 features a brownout pin to protect the
power supply against low input voltage condition. This pin
permanently monitors a fraction of the bulk voltage through
a voltage divider. When this image of bulk voltage is below
the VBO threshold, the controller stops switching. When the
bulk voltage comes back within safe limits, the circuit goes
through a new startup sequence including soft−start and
restarts switching (Figure 30). The hysteresis on brownout
pin is implemented with a low side current source sinking
10 mA when the brownout comparator is low (Vbulk <
VbulkON).
R upper
N p,auxV IN * V OPP
+*
R lower
V OPP
Assuming the turn ratio of the transformer is Np,aux = 0.25,
we obtain:
Figure 30. Brownout Operating Chronograms
http://onsemi.com
24
NCP1336A/B
HV−bulk
+
VBO
20 ms Noise Delay
Rupper
BO Reset
+
BO
BO Comp
Rlower
IBO
IBO “on” if BO Comp “low”
IBO “off” if BO Comp “high”
Figure 31. Brownout Circuitry
The following equations show how to calculate the
resistors for BO pin.
First of all, select the bulk voltage value at which the
controller must start switching (VbulkON) and the bulk
voltage for shutdown (VbulkOFF). Then use the following
equation to calculate Rupper and Rlower.
R lower +
VBO(V bulkON * V bulkOFF)
I BO(V bulkOFF * VBO)
R upper +
R lower(V bulkOFF * V BO)
VBO
Design Example
VBO = 0.8 V
IBO = 10 mA
We select: VbulkON = 120 V, VbulkOFF = 60 V
R lower +
VBO @ (V bulkON * V bulkOFF)
0.8 V @ (120 V * 60 V)
+
+ 81.1 kW
I BO @ (V bulkOFF * VBO)
10 mA @ (60 V * 0.8 V)
R upper +
R lower @ (V bulkOFF * V BO)
81.1 kW @ (60 V * 0.8 V)
+
+ 6 MW
V BO
0.8 V
ORDERING INFORMATION
Package Type
Shipping†
NCP1336ADR2G
SO−14 Less Pin 13
(Pb−Free)
2500 / Tape & Reel
NCP1336BDR2G
SO−14 Less Pin 13
(Pb−Free)
2500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
25
NCP1336A/B
PACKAGE DIMENSIONS
SOIC−14 NB, LESS PIN 13
CASE 751AN
ISSUE A
D
A
B
14
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
8
A3
E
H
L
1
0.25
M
DETAIL A
7
B
13X
M
DIM
A
A1
A3
b
D
E
e
H
h
L
M
b
0.25
C A
M
S
B
S
DETAIL A
h
A
X 45 _
M
A1
e
C
SEATING
PLANE
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.19
0.25
0.35
0.49
8.55
8.75
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0_
7_
SOLDERING FOOTPRINT*
6.50
13X
1.18
1
1.27
PITCH
13X
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
http://onsemi.com
26
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
NCP1336/D