CAT25C33/65 32K/64K-Bit SPI Serial CMOS EEPROM FEATURES ■ 1,000,000 program/erase cycles ■ 10 MHz SPI compatible ■ 100 year data tetention ■ 1.8 to 6.0 volt operation ■ Self-timed write cycle ■ Hardware and software protection ■ 8-pin DIP/SOIC and 14-pin TSSOP ■ Low power CMOS technology ■ 64-byte page write buffer ■ SPI modes (0,0 &1,1) DESCRIPTION required to access the device. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence. The CAT25C32/64 is designed with software and hardware write protection features including Block write protection. The device is available in 8-pin DIP, 8-pin SOIC, 14-pin TSSOP and 20-pin TSSOP packages. The CAT25C33/65 is a 32K/64K-Bit SPI Serial CMOS EEPROM internally organized as 4Kx8/8Kx8 bits. Catalyst’s advanced CMOS Technology substantially reduces device power requirements. The CAT25C33/ 65 features a 64-byte page write buffer. The device operates via the SPI bus serial interface and is enabled though a Chip Select (CS). In addition to the Chip Select, the clock input (SCK), data in (SI) and data out (SO) are 1 2 3 4 CS SO WP VSS 8 7 6 5 VCC HOLD SCK SI c s DIP Package (P, L, GL) 1 2 3 4 CS SO WP VSS 8 7 6 5 i D VCC HOLD SCK SI PIN FUNCTIONS Pin Name SO SCK u n TSSOP Package (U14, Y14) CS SO NC NC NC WP VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 d e BLOCK DIAGRAM VCC HOLD NC NC NC SCK SI SENSE AMPS SHIFT REGISTERS WORD ADDRESS BUFFERS SO SI CS WP HOLD SCK I/O CONTROL SPI CONTROL LOGIC BLOCK PROTECT LOGIC Function Serial Data Output Write Protect VCC +1.8V to +6.0V Power Supply VSS Ground CS Chip Select SI Serial Data Input HOLD Suspends Serial Input NC No Connect © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice XDEC COLUMN DECODERS E2PROM ARRAY DATA IN STORAGE Serial Clock WP CONTROL LOGIC it n o PIN CONFIGURATION s t r – Protect first page, last page, any 1/4 or lower 1/2 of EEPROM array temperature ranges SOIC Package (S, V, GV) a P ■ Block write protection ■ Commercial, industrial, automotive and extended HIGH VOLTAGE/ TIMING CONTROL STATUS REGISTER 1 Doc. No. 1000, Rev. H CAT25C33/65 ABSOLUTE MAXIMUM RATINGS* *COMMENT Temperature Under Bias ................. –55°C to +125°C Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Storage Temperature ....................... –65°C to +150°C Voltage on any Pin with Respect to VSS1) ................... –2.0V to +VCC +2.0V VCC with Respect to VSS ................................ –2.0V to +7.0V Package Power Dissipation Capability (Ta = 25°C) ................................... 1.0W Lead Soldering Temperature (10 secs) ............ 300°C Output Short Circuit Current(2) ........................ 100 mA a P RELIABILITY CHARACTERISTICS Symbol NEND TDR (3) (3) VZAP(3) ILTH (3)(4) Parameter Endurance Min. 100 ESD Susceptibility 2000 Latch-up 100 D.C. OPERATING CHARACTERISTICS VCC = +1.8V to +6.0V, unless otherwise specified. ICC1 ICC2 ISB(5) ILI ILO it n o Parameter Power Supply Current (Operating Write) Power Supply Current (Operating Read) Power Supply Current (Standby) Input Leakage Current Output Leakage Current c s i D Max. 1,000,000 Data Retention Symbol Typ. VIL(3) VIH(3) VOL1 VOH1 Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage VOL2 VOH2 Output Low Voltage Output High Voltage Min. -1 VCC x 0.7 d e Max. Units 10 mA 2 mA 1 µA 2 3 µA µA VCC x 0.3 VCC + 0.5 0.4 V V V V 0.2 V V VCC - 0.8 VCC-0.2 Units Cycles/Byte u n Limits Typ. s t r Years Volts mA Test Conditions VCC = 5V @ 10MHz SO=open; CS=Vss VCC = 5.0V FCLK = 10MHz CS = VCC VIN = VSS or VCC VOUT = 0V to VCC, CS = 0V 4.5V≤VCC<5.5V IOL = 3.0mA IOH = -1.6mA 1.8V≤VCC<2.7V IOL = 150µA IOH = -100µA Note: (1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) These parameter are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V. (5) Maximum standby current (ISB ) = 10µA for the Automotive and Extended Automotive temperature range. Doc. No. 1000, Rev. H 2 © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT25C33/65 PIN CAPACITANCE (1) Applicable over recommended operating range from TA=25˚C, f=1.0 MHz, VCC=+5.0V (unless otherwise noted). Symbol Test Conditions Max. Units Conditions COUT Output Capacitance (SO) 8 pF VOUT=0V CIN Input Capacitance (CS, SCK, SI, WP, HOLD) 6 pF VIN=0V A.C. CHARACTERISTICS Limits VCC = 2.5V-6.0V Vcc= 1.8V-6.0V SYMBOL PARAMETER Min. Max. Min. Max. VCC = 4.5V-5.5V Min. a P Max. UNITS Conditions tSU Data Setup Time 50 50 20 tH Data Hold Time 50 50 20 tWH SCK High Time 250 125 tWL SCK Low Time 250 125 fSCK Clock Frequency DC tLZ HOLD to Output Low Z tRI(1) Input Rise Time tFI(1) Input Fall Time tHD HOLD Setup Time 100 tCD HOLD Hold Time 100 tWC Write Cycle Time tV Output Valid from Clock Low tHO Output Hold Time tDIS Output Disable Time 250 250 75 ns tHZ HOLD to Output High Z 150 100 50 ns tCS CS High Time tCSS CS Setup Time tCSH CS Hold Time u n 50 it n o d e DC 2 c s i D 1 2 100 40 40 3 ns ns ns ns 10 MHz 50 50 ns 2 2 µs 2 2 µs 100 DC 40 ns 40 ns 10 10 5 ms 250 250 80 ns 0 0 s t r Test 0 CL = 50pF ns 500 250 200 ns 500 250 100 ns 500 250 100 ns NOTE: (1) This parameter is tested initially and after a design or process change that affects the parameter. © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 3 Doc No. 1000, Rev. H CAT25C33/65 FUNCTIONAL DESCRIPTION PIN DESCRIPTION The CAT25C33/65 supports the SPI bus data transmission protocol. The synchronous Serial Peripheral Interface (SPI) helps the CAT25C33/65 to interface directly with many of today’s popular microcontrollers. The CAT25C33/65 contains an 8-bit instruction register. (The instruction set and the operation codes are detailed in the instruction set table) SI: Serial Input SI is the serial data input pin. This pin is used to input all opcodes, byte addresses, and data to be written to the 25C33/65. Input data is latched on the rising edge of the serial clock. SO: Serial Output SO is the serial data output pin. This pin is used to transfer data out of the 25C33/65. During a read cycle, data is shifted out on the falling edge of the serial clock. After the device is selected with CS going low, the first byte will be received. The part is accessed via the SI pin, with data being clocked in on the rising edge of SCK. The first byte contains one of the six op-codes that define the operation to be performed. Figure 1. Sychronous Data Timing VIH CS d e VIL tCSS VIH VIL tH tSU VIH VALID IN SI VIL VOH SO it n o HI-Z VOL Note: Dashed Line= mode (1, 1) — — — — INSTRUCTION SET c s Instruction WREN i D WRDI RDSR WRSR READ WRITE tWL tWH SCK u n tRI tFI tV a P s t r tCS tCSH tHO tDIS HI-Z Opcode Operation 0000 0110 Enable Write Operations 0000 0100 Disable Write Operations 0000 0101 Read Status Register 0000 0001 Write Status Register 0000 0011 Read Data from Memory 0000 0010 Write Data to Memory Power-Up Timing(2)(3) Symbol Parameter Max. Units tPUR Power-up to Read Operation 1 ms tPUW Power-up to Write Operation 1 ms Note: (1) X=0 for 25010, 25020. X=A8 for 25040 (2) This parameter is tested initially and after a design or process change that affects the parameter. (3) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. Doc. No. 1000, Rev. H 4 © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT25C33/65 SCK: Serial Clock SCK is the serial clock pin. This pin is used to synchronize the communication between the microcontroller and the 25C33/65. Opcodes, byte addresses, or data present on the SI pin are latched on the rising edge of the SCK. Data on the SO pin is updated on the falling edge of the SCK. CS CS: Chip Select CS is the Chip select pin. CS low enables the CAT25C33/ 65 and CS high disables the CAT25C33/65. CS high takes the SO output pin to high impedance and forces the devices into a Standby Mode (unless an internal write operation is underway). The CAT25C33/65 draws ZERO current in the Standby mode. A high to low transition on CS is required prior to any sequence being initiated. A low to high transition on CS after a valid write sequence is what initiates an internal write cycle. WP WP: Write Protect WP is the Write Protect pin. The Write Protect pin will allow normal read/write operations when held high. When WP is tied low and the WPEN bit in the status register is set to “1”, all write operations to the status register are inhibited. WP going low while CS is still low will interrupt a write to the status register. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation to the status register. The WP pin function is blocked when the WPEN bit is set to 0. d e STATUS REGISTER 7 6 5 4 WPEN X X BP2 MEMORY PROTECTION BP2 BP1 BP0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 it n o c s i D 1 1 0 1 1 1 Non-Protection 3 u n BP1 2 a P BP0 1 0 WEL RDY MEMORY PROTECTION CAT25C33 CAT25C65 Q1 0000-03FF 0000-07FF Q2 0400-07FF 0800-0FFF Q3 0800-0BFF 1000-17FF Q3 Protected Q4 0C00-0FFF 1800-1FFF Q4 Protected H1 0000-07FF 0000-0FFF H1 Protected P0 0000-003F 0000-003F P0 Protected Pn 0FC0-0FFF 0FC0-1FFF Q1 Protected Q2 Protected s t r HOLD HOLD: Hold The HOLD pin is used to pause transmission to the CAT25C33/65 while in the middle of a serial sequence without having to re-transmit entire sequence at a later time. To pause, HOLD must be brought low while SCK is low. The SO pin is in a high impedance state during the time the part is paused, and transitions on the SI pins will be ignored. To resume communication, HOLD is brought high, while SCK is low. (HOLD should be held high any time this function is not being used.) HOLD may be tied high Pn Protected WRITE PROTECT ENABLE OPERATION WPEN WP WEL Protected Blocks Unprotected Blocks Status Register 0 X 0 Protected Protected Protected 0 X 1 Protected Writable Writable 1 Low 0 Protected Protected Protected 1 Low 1 Protected Writable Protected X High 0 Protected Protected Protected X High 1 Protected Writable Writable © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 5 Doc No. 1000, Rev. H CAT25C33/65 directly to Vcc or tied to Vcc through a resistor. Figure 9 illustrates hold timing sequence. lower half of the memory, the first page or the last page by setting these bits. Once protected the user may only STATUS REGISTER read from the protected portion of the array. These bits are non-volatile. The Status Register indicates the status of the device. The WPEN (Write Protect Enable) is an enable bit for the WP pin. The WP pin and WPEN bit in the status register control the programmable hardware write protect feature.Hardware write protection is enabled when WP is low and WPEN bit is set to high. The user cannot write to the status register (including the block protect bits and the WPEN bit) and the block protected sections in thememory array when the chip is hardware write protected. Only the sections of the memory array that are not block protected can be written. Hardware write protection is disabled when either WP pin is high or the WPEN bit is zero. The RDY (Ready) bit indicates whether the CAT25C33/ 65 is busy with a write operation. When set to 1 a write cycle is in progress and when set to 0 the device indicates it is ready. This bit is read only. The WEL (Write Enable) bit indicates the status of the write enable latch . When set to 1, the device is in a Write Enable state and when set to 0 the device is in a Write Disable state. The WEL bit can only be set by the WREN instruction and can be reset by the WRDI instruction. DEVICE OPERATION The BP0, BP1 and BP2 (Block Protect) bits indicate which blocks are currently protected. These bits are set by the user issuing the WRSR instruction. The user is allowed to protect any quarter of the memory, the Write Enable and Disable The CAT25C33/65 contains a write enable latch. This latch must be set before any write operation. The device powers Figure 2. WREN Instruction Timing CS it n o SK 0 SI 0 0 0 c s SO i D d e a P s t r u n 0 1 1 0 HIGH IMPEDANCE Note: Dashed Line= mode (1, 1) — — — — Figure 3. WRDI Instruction Timing CS SK SI SO 0 0 0 0 0 1 0 0 HIGH IMPEDANCE Note: Dashed Line= mode (1, 1) — — — — Doc. No. 1000, Rev. H 6 © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT25C33/65 and FFFh for 25C33) is reached, the address counter rolls over to 0000h allowing the read cycle to be continued indefinitely. The read operation is terminated by pulling the CS high. To read the status register, RDSR instruction should be sent. The contents of the status register are shifted out on the SO line. The status register may be read READ Sequence at any time even during a write cycle. Read sequece is The part is selected by pulling CS low. The 8-bit read illustrated in Figure 4. Reading status register is illustrated instruction is transmitted to the CAT25C33/65, followed in Figure 5. by the 16-bit address(the three Most Significant Bits are don’t care for 25C65 and four most significant bits are WRITE Sequence don't care for 25C33). After the correct read instruction The CAT25C33/65 powers up in a Write Disable state. Prior and address are sent, the data stored in the memory at to any write instructions, the WREN instruction must be the selected address is shifted out on the SO pin. The sent to CAT25C33/65. The device goes into Write enable data stored in the memory at the next address can be state by pulling the CS low and then clocking the WREN read sequentially by continuing to provide clock pulses. instruction into CAT25C33/65. The CS must be brought The internal address pointer is automatically incremented high after the WREN instruction to enable writes to the to the next higher address after each byte of data is device. shifted out. When the highest address (1FFFh for 25C65 up in a write disable state when Vcc is applied. WREN instruction will enable writes (set the latch) to the device. WRDI instruction will disable writes (reset the latch) to the device. Disabling writes will protect the device against inadvertent writes. d e Figure 4. Read Instruction Timing CS 0 1 2 3 4 5 6 7 8 9 SK it n o OPCODE SI 0 0 0 0 0 0 1 20 21 BYTE ADDRESS* 1 HIGH IMPEDANCE SO u n 10 22 23 24 25 a P 26 27 28 29 30 2 1 s t r DATA OUT 7 6 5 4 3 0 MSB *Please check the instruction set table for address c s Note: Dashed Line= mode (1, 1) — — — — i D Figure 5. RDSR Instruction Timing CS SCK SI 0 0 1 2 3 4 5 6 7 1 0 1 8 9 10 11 7 6 5 4 12 13 14 2 1 OPCODE 0 0 0 0 DATA OUT SO HIGH IMPEDANCE 3 0 MSB Note: Dashed Line= mode (1, 1) — — — — © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 7 Doc No. 1000, Rev. H CAT25C33/65 If the write operation is initiated immediately after the WREN instruction without CS being brought high, the data will not be written to the array because the write enable latch will not have been properly set. Also, for a successful write operation the address of the memory location(s) to be programmed must be outside the protected address field location selected by the block protection level. The Status Register can be read to determine if the write cycle is still in progress. If Bit 0 of the Status Register is set at 1, write cycle is in progress. If Bit 0 is set at 0, the device is ready for the next instruction. Page Write The CAT25C33/65 features page write capability. After the first initial byte the host may continue to write up to 64 bytes of data to the CAT25C33/65. After each byte of data is received, six lower order address bits are internally incremented by one; the high order bits of address will remain constant. The only restriction is that the 64 bytes must reside on the same page. If the address counter reaches the end of the page and clock continues, the counter will “roll over” to the first address of the page and overwrite any data that may have been written. The CAT25C33/65 is automatically returned to the write disable state at the completion of the write cycle. Figure 8 illustrates the page write sequence. s t r Byte Write Once the device is in a Write Enable state, the user may proceed with a write sequence by setting the CS low, issuing a write instruction via the SI line, followed by the 16-bit address (the three Most Significant Bits are don’t care for 25C65 and four most significant bits are don't care for 25C33), and then the data to be written. Programming will start after the CS is brought high. Figure 6 illustrates byte write sequence. To write to the status register, the WRSR instruction should be During an internal write cycle, all commands will be sent. Only Bit 2, Bit 3 and Bit 7 of the status register can be ignored except the RDSR (Read Status Register) written using the WRSR instruction. Figure 7 illustrates the sequence of writing to status register. instruction. Figure 6. Write Instruction Timing it n o CS 0 1 2 3 4 SK 5 6 7 8 OPCODE SI 0 0 0 0 0 0 1 0 d e u n 21 22 23 a P 24 25 26 27 28 29 30 31 DATA IN D7 D6 D5 D4 D3 D2 D1 D0 ADDRESS c s HIGH IMPEDANCE SO i D Note: Dashed Line= mode (1, 1) – – – – Figure 7. WRSR Instruction Timing CS 0 1 2 3 4 5 6 7 8 9 10 11 1 7 6 5 4 12 13 14 15 2 1 0 SCK SI 0 OPCODE 0 0 0 0 DATA IN 0 0 3 MSB SO HIGH IMPEDANCE Note: Dashed Line= mode (1, 1) — — — — Doc. No. 1000, Rev. H 8 © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT25C33/65 DESIGN CONSIDERATIONS The CAT25C33/65 powers up in a write disable state and in a low power standby mode. A WREN instruction must be issued to perform any writes to the device after power up. Also,on power up CS should be brought low to enter a ready state and receive an instruction. After a successful byte/page write or status register write the CAT25C33/65 goes into a write disable mode. CS must be set high after the proper number of clock cycles to start an internal write cycle. Access to the array during an internal write cycle is ignored and program-ming is continued. On power up, SO is in a high impedance. When powering down, the supply should be taken down to 0V, so that the CAT25C33/65 will be reset when power is ramped back up. If this is not possible, then, following a brown-out episode, the CAT25C33/65 can be reset by refreshing the contents of the Status Register (See Application Note AN10). Figure 8. Page Write Instruction Timing CS 0 1 2 3 4 5 6 7 8 21 22 d e 23 24-31 SK OPCODE SI 0 0 0 0 0 0 1 0 it n o HIGH IMPEDANCE SO Note: Dashed Line = mode (1, 1) – – – – Figure 9. HOLD Timing CS c s i D SCK HOLD u n ADDRESS Data Byte 1 32-39 24+(N-1)x8-1..24+(N-1)x8 24+Nx8-1 DATA IN Data Byte 2 tCD a P s t r Data Byte 3 Data Byte N 0 7..1 tCD tHD tHD tHZ HIGH IMPEDANCE SO tLZ Note: Dashed Line= mode (1, 1) — — — — © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 9 Doc No. 1000, Rev. H CAT25C33/65 ORDERING INFORMATION Prefix Device # Suffix 25C65 CAT Optional Company ID S Product Number 25C33: 32K 25C65: 64K -1.8 I Temperature Range Package P: PDIP S: SOIC U14: 14-pin TSSOP L: PDIP (Lead free, Halogen free) V: SOIC (Lead free, Halogen free) Y14: 14-pin TSSOP (Lead free, Halogen free) GL: PDIP (Lead-free, Halogen-free, NiPdAu lead plating) GV: SOIC, JEDEC (Lead-free, Halogen-free, NiPdAu lead plating) d e TE13 Tape & Reel s t r Operating Voltage Blank = 2.5 to 6.0V 1.8 = 1.8 to 6.0V a P Notes: (1) The device used in the above example is a 25C65SI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating Voltage, Tape & Reel) it n o u n c s i D Doc. No. 1000, Rev. H 10 © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice REVISION HISTORY Date 8/5/2004 Rev. F Reason Updated Features Updated DC Operating Characteristics table & notes 07/11/2005 G Update Reliability Characteristic Update Ordering Information 09/22/2005 H Update Pin Configuration u n d e Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: DPP ™ AE2 ™ MiniPot™ it n o a P s t r Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000. 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Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. i D Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.caalyst-semiconductor.com Publication #: Revison: Issue date: 1000 H 09/22/05