TI1 DRV8702DQRHBRQ1 Automotive half-bridge gate driver Datasheet

Order
Now
Product
Folder
Support &
Community
Tools &
Software
Technical
Documents
DRV8702D-Q1, DRV8703D-Q1
SLVSDX8 – MARCH 2017
DRV870xD-Q1 Automotive Half-Bridge Gate Driver
1 Features
2 Applications
•
•
•
•
•
AEC-Q100 Qualified for Automotive Applications
– Device Temperature Grade 1: –40°C to
+125°C Ambient Operating Temperature
Single Half-Bridge Gate Driver
– Drives Two External N-Channel MOSFETs
– Supports 100% PWM Duty Cycle
5.5- to 45-V Operating Supply-Voltage Range
PWM Control Interface
Serial Interface for Configuration (DRV8703D-Q1)
Adjustable Gate Drive For Slew-Rate Control
Supports 1.8-V, 3.3-V, and 5-V logic inputs
Current-Shunt Amplifier
Integrated PWM Current Regulation
Low-Power Sleep Mode
Small Package and Footprint
– 32-Pin VQFN
– 5 mm × 5 mm
– Wettable Flanks Package
Protection Features
– Supply Undervoltage Lockout (UVLO)
– Charge-Pump Undervoltage (CPUV) Lockout
– Overcurrent Protection (OCP)
– Gate-Driver Fault (GDF)
– Thermal Shutdown (TSD)
– Watchdog Timer (DRV8703D-Q1)
– Fault-Condition Output (nFAULT)
1
•
•
•
•
•
•
•
•
•
•
•
Fuel Pumps
Unidirectional Brushed DC Motors
Relays or Solenoids
Unipolar Loads
3 Description
The DRV870xD-Q1 family of devices is a half-bridge
gate driver that uses two external N-channel
MOSFETs targeted to drive unidirectional brushedDC motors or solenoid loads.
The PWM interface allows simple interfacing to
controller circuits. An internal sense amplifier
provides adjustable current control. The gate driver
includes circuitry to regulate the winding current using
fixed off-time PWM current chopping.
The DRV870xD-Q1 family of devices drives both
high-side and low-side FETs with a 10.5-V VGS gate
drive. The gate-drive current for all external FETs is
configurable with a single external resistor or through
the serial peripheral interface (SPI).
A low-power sleep mode is provided which shuts
down internal circuitry to achieve a very-low
quiescent-current draw.
Device Information(1)
PART NUMBER
PACKAGE
DRV8702D-Q1
VQFN (32)
DRV8703D-Q1
Gate-Drive Current
5.5 to 45 V
t(DRIVE)
DRV870xD-Q1
ISTRONG
VREF
Sense Output
nFAULT
Shunt Amplifier
HalfBridge
M
Current
Sense
Low-side
gate drive
current
IDRIVE(SNK)
ISTRONG
High-side
VGS
Current Regulation
Protection
IHOLD
t(DRIVE)
IHOLD
IDRIVE(SNK)
ISTRONG
IDRIVE(SRC)
Controller
Gate
Drive
IDRIVE(SRC)
High-side
gate drive
current
PH/EN or PWM
Half-Bridge Gate Driver
5.00 mm × 5.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
nSLEEP
BODY SIZE (NOM)
IHOLD
Low-side
VGS
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DRV8702D-Q1, DRV8703D-Q1
SLVSDX8 – MARCH 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
7
7.6 Register Maps ......................................................... 41
1
1
1
2
3
5
8
8.1 Application Information............................................ 47
8.2 Typical Application .................................................. 47
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
Power Supply Recommendations...................... 51
9.1 Bulk Capacitance Sizing ......................................... 51
10 Layout................................................................... 52
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 6
Electrical Characteristics........................................... 6
SPI Timing Requirements ....................................... 11
Switching Characteristics ........................................ 11
Typical Characteristics ............................................ 13
10.1 Layout Guidelines ................................................. 52
10.2 Layout Example .................................................... 52
11 Device and Documentation Support ................. 53
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Detailed Description ............................................ 18
7.1
7.2
7.3
7.4
7.5
Application and Implementation ........................ 47
18
19
21
39
39
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
53
53
53
53
53
53
53
12 Mechanical, Packaging, and Orderable
Information ........................................................... 54
12.1 Package Option Addendum .................................. 58
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
March 2017
*
Initial release.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8702D-Q1 DRV8703D-Q1
DRV8702D-Q1, DRV8703D-Q1
www.ti.com
SLVSDX8 – MARCH 2017
5 Pin Configuration and Functions
23
IN2
3
GND
4
VM
VDRAIN
RSVD
GND
28
27
26
25
GND
1
24
RSVD
SP
IN1
2
23
SP
22
SN
IN2
3
22
SN
21
SP
SDO
4
21
SP
20
GL
Thermal
Pad
16
GND
Not to scale
SO
GND
15
17
VREF
8
14
nSLEEP
AVDD
GND
13
17
GND
8
12
nSLEEP
DVDD
GH
11
18
MODE
7
10
SCLK
nFAULT
GH
9
18
nWDFLT
7
16
GND
SO
SH
15
19
VREF
6
14
SDI
AVDD
SH
13
19
GND
6
12
5
DVDD
nSCS
11
GL
MODE
20
10
VDS
Pad
nFAULT
5
9
IDRIVE
Thermal
VCP
GND
25
2
29
RSVD
26
IN1
CPH
VDRAIN
27
RSVD
30
VM
28
24
CPL
VCP
29
1
31
CPH
30
GND
NC
CPL
31
DRV8703D-Q1 RHB Package With Wettable Flanks
32-Pin VQFN
Top View
32
NC
32
DRV8702D-Q1 RHB Package With Wettable Flanks
32-Pin VQFN
Top View
Not to scale
Pin Functions
PIN
NAME
NO.
TYPE (1)
DESCRIPTION
DRV8702D-Q1 DRV8703D-Q1
AVDD
14
14
PWR
Analog regulator. This pin is the 5-V analog supply regulator. Bypass this pin to
ground with a 6.3-V, 1-µF ceramic capacitor.
CPH
30
30
PWR
Charge-pump switching node. Connect a 0.1-µF X7R capacitor rated for the
supply voltage (VM) between the CPH and CPL pins.
CPL
31
31
PWR
Charge-pump switching node. Connect a 0.1-µF X7R capacitor rated for the
supply voltage (VM) between the CPH and CPL pins.
DVDD
12
12
PWR
Logic regulator. This pin is the regulator for the 3.3-V logic supply. Bypass this
pin to ground with a 6.3-V, 1-µF ceramic capacitor.
GH
18
18
O
High-side gate. Connect this pin to the high-side FET gate.
GL
20
20
O
Low-side gate. Connect this pin to the low-side FET gate.
GND
1
1
PWR
Device ground. Connect this pin to the system ground.
GND
13
13
PWR
Device ground. Connect this pin to the system ground.
GND
17
17
PWR
Device ground. Connect this pin to the system ground.
GND
25
25
PWR
Device ground. Connect this pin to the system ground.
GND
4
—
PWR
Device ground. Connect this pin to the system ground.
GND
7
—
PWR
Device ground. Connect this pin to the system ground.
GND
9
—
PWR
Device ground. Connect this pin to the system ground.
IDRIVE
5
—
I
Current setting pin for the gate drive. The resistor value or voltage forced on
this pin sets the gate-drive current. For more information see the IDRIVE
Configuration section.
IN1
2
2
I
Input control pins. The logic of this pin is dependent on the MODE pin.
IN2
3
3
I
Input control pins. The logic of this pin is dependent on the MODE pin.
(1)
I = input, O = output, PWR = power, NC = no connect, OD = open-drain output
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8702D-Q1 DRV8703D-Q1
Submit Documentation Feedback
3
DRV8702D-Q1, DRV8703D-Q1
SLVSDX8 – MARCH 2017
www.ti.com
Pin Functions (continued)
PIN
TYPE (1)
NO.
NAME
DESCRIPTION
DRV8702D-Q1 DRV8703D-Q1
Mode control pin. Pull this pin to logic high for half-bridge operation without
internal current regulation. Leave this pin as no-connect for half-bridge
operation with internal current regulation. Operation of this pin is latched on
power up or when exiting sleep mode.
MODE
11
11
I
NC
32
32
NC
No connect. No internal connection
nFAULT
10
10
OD
Fault indication pin. This pin is pulled logic low when a fault condition occurs.
This pin is an open-drain output that requires an external pullup resistor.
nSCS
—
5
I
SPI chip select. This pin is the select and enable for SPI. This pin is active low.
nSLEEP
8
8
I
Device sleep mode. Pull this pin to logic low to put device into a low-power
sleep mode with the FETs in high impedance (Hi-Z). This pin is connected to
an internal pulldown resistor.
nWDFLT
—
9
OD
RSVD
26
26
RSVD
Reserved. Do not connect anything.
RSVD
24
24
RSVD
Reserved. Do not connect anything.
SCLK
—
7
I
SPI clock. This pin is for the SPI clock signal.
SDI
—
6
I
SPI input. This pin is for the SPI input signal.
SDO
—
4
OD
SH
19
19
I
High-side source. Connect this pin to the high-side FET source.
SN
22
22
I
Shunt-amplifier negative input. Connect this pin to the current-sense resistor.
SO
16
16
O
Shunt-amplifier output. The voltage on this pin is equal to the SP voltage times
AV plus an offset. Place no more than 1 nF of capacitance on this pin.
SP
21
21
I
Shunt-amplifier positive input. Connect this pin to the current-sense resistor.
SP
23
23
I
Shunt-amplifier positive input. Connect this pin to the current-sense resistor.
VCP
29
29
PWR
VDRAIN
27
27
I
High-side FET drain connection. This pin is common for the half-bridge.
VDS
6
—
I
VDS monitor setting pin. The resistor value or voltage forced on this pin sets
the VDS monitor threshold. For more information see the VDS Configuration
section.
VM
28
28
PWR
VREF
15
15
I
4
Submit Documentation Feedback
Watchdog fault indication pin. This pin is pulled logic low when a watchdog fault
condition occurs. This pin is an open-drain output that requires an external
pullup resistor.
SPI output. This pin is for the SPI output signal. This pin is an open-drain
output that requires an external pullup resistor.
Charge-pump output. Connect a 16-V, 1-µF ceramic capacitor between this pin
and the VM pin.
Power supply. Connect this pin to the motor supply voltage. Bypass this pin to
ground with a 0.1-µF ceramic plus a 10-µF (minimum) capacitor.
Current set reference input. The voltage on this pin sets the driver chopping
current.
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8702D-Q1 DRV8703D-Q1
DRV8702D-Q1, DRV8703D-Q1
www.ti.com
SLVSDX8 – MARCH 2017
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
Power supply voltage
VM
–0.3
47
V
Charge pump voltage
VCP, CPH
–0.3
VVM + 12
V
Charge pump negative switching pin
CPL
–0.3
VVM
V
Internal logic regulator voltage
DVDD
–0.3
3.8
V
Internal analog regulator voltage
AVDD
–0.3
5.75
V
Drain pin voltage
VDRAIN
–0.3
47
V
Voltage difference between supply and
VDRAIN
VM – VDRAIN
–10
10
V
Control pin voltage
IN1, IN2, nSLEEP, nFAULT, VREF, IDRIVE,
VVDS, MODE, nSCS, SCLK, SDI, SDO,
nWDFLT
–0.3
5.75
V
High-side gate pin voltage
GH
–0.3
VVM + 12
V
Low-side gate pin voltage
GL
–0.3
12
V
Continuous phase-node pin voltage
SH
–1.2
VVM + 1.2
V
Pulsed 10-µs phase-node pin voltage
SH
–2
VVM + 2
V
SP
–0.5
1
V
SN
–0.3
0.3
V
Pulsed 10-µs shunt amplifier input pin voltage
SP
–1
1
V
Shunt amplifier output pin voltage
SO
–0.3
5.75
V
Shunt amplifier output pin current
SO
0
5
mA
Maximum current, limit current with external
series resistor
VDRAIN
–2
2
mA
Open-drain output current
nFAULT, SDO, nWDFLT
0
10
mA
Gate pin source current
GH, GL
0
250
mA
Gate pin sink current
GH, GL
0
500
mA
Operating junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–65
150
°C
Continuous shunt amplifier input pin voltage
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per AEC Q100-002 (1)
V(ESD)
(1)
Electrostatic
discharge
Charged-device model (CDM), per AEC
Q100-011
UNIT
±2000
All pins
±500
Corner pins (1, 8, 9, 16, 17,
24, 25, and 32)
±750
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8702D-Q1 DRV8703D-Q1
Submit Documentation Feedback
5
DRV8702D-Q1, DRV8703D-Q1
SLVSDX8 – MARCH 2017
www.ti.com
6.3 Recommended Operating Conditions
MIN
MAX
5.5
45
V
0
5.25
V
0.3 (1)
3.6
V
100
kHz
30 (2)
mA
Power supply voltage
VCC
Logic-level input voltage
VVREF
Reference root-mean-square (rms) voltage
VREF
f(PWM)
Applied PWM signal (IN1/IN2)
IN1, IN2
IAVDD
AVDD external load current
IDVDD
DVDD external load current
30 (2)
mA
ISO
Shunt-amplifier output-current loading
5
mA
TA
Operating ambient temperature
125
°C
(1)
(2)
VM
UNIT
VVM
SO
–40
Operational at VVREF = 0 to approximately 0.3 V, but accuracy is degraded.
Power dissipation and thermal limits must be observed.
6.4 Thermal Information
DRV870xD-Q1
THERMAL METRIC
(1)
RHB (VQFN)
UNIT
32 PINS
RθJA
Junction-to-ambient thermal resistance
32.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
19.6
°C/W
RθJB
Junction-to-board thermal resistance
6.8
°C/W
ψJT
Junction-to-top characterization parameter
0.3
°C/W
ψJB
Junction-to-board characterization parameter
6.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.8
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
Over recommended operating conditions unless otherwise noted. Typical limits apply for TA = 25°C and VVM = 13.5 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLIES (VM, AVDD, DVDD)
VVM
VM operating voltage
IVM
VM operating supply current
I(SLEEP)
VM sleep mode supply current
VDVDD
Internal logic regulator voltage
VAVDD
Internal logic regulator voltage
Gate drivers functional
5.5
45
Logic functional
4.5
45
VVM = 13.5 V; nSLEEP=1
5.5
7.5
12
nSLEEP = 0, VVM = 13.5 V, TA = 25°C
14
nSLEEP = 0, VVM = 13.5 V, TA = 125°C (1)
25
2-mA load
3
3.3
3.5
30-mA load, VVM = 13.5 V
2.9
3.2
3.5
2-mA load
4.7
5
5.3
30-mA load, VVM = 13.5 V
4.6
5
5.3
VVM = 13.5 V; IVCP = 0 to 12 mA
22.5
23.5
24.5
VVM = 8 V; IVCP = 0 to 10 mA
13.7
14
14.8
VVM = 5.5 V; IVCP = 0 to 8 mA
8.9
9.1
9.5
VVM > 13.5 V
12
8 V < VVM < 13.5 V
10
5.5 V < VVM < 8 V
8
V
mA
µA
V
V
CHARGE PUMP (VCP, CPH, CPL)
VVCP
IVCP
VCP operating voltage
Charge-pump current capacity
V
mA
CONTROL INPUTS (IN1, IN2, nSLEEP, MODE, nSCS, SCLK, SDI)
VIL
Input logic-low voltage
VIH
Input logic-high voltage
(1)
6
0
0.8
V
1.5
5.25
V
Ensured by design and characterization data.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8702D-Q1 DRV8703D-Q1
DRV8702D-Q1, DRV8703D-Q1
www.ti.com
SLVSDX8 – MARCH 2017
Electrical Characteristics (continued)
Over recommended operating conditions unless otherwise noted. Typical limits apply for TA = 25°C and VVM = 13.5 V
PARAMETER
TEST CONDITIONS
Vhys
Input logic hysteresis
IIL
Input logic-low current
VIN = 0 V
IIH
Input logic-high current
VIN = 5 V
RPD
Pulldown resistance
MIN
TYP
MAX
100
mV
–5
64
UNIT
100
5
µA
70
µA
173
kΩ
CONTROL OUTPUTS (nFAULT, nWDFLT, SDO)
VOL
Output logic-low voltage
IO = 2 mA
IOZ
Output high-impedance leakage
5V pullup voltage
-2
0.1
V
2
µA
FET GATE DRIVERS (GH, SH, GL)
VVM > 13.5 V; VGSH with respect to SH
VGSH
High-side VGS gate drive (gateto-source)
VGSL
Low-side VGS gate drive (gate-to- VVM > 10.5 V
source)
VVM < 10.5 V
IDRIVE(SRC_HS)
IDRIVE(SNK_HS)
High-side peak source current
(VVM = 5.5V)
High-side peak sink current
(VVM = 5.5V)
10.5
VVM = 8 V; VGSH with respect to SH
5.7
VVM = 5.5 V; VGSH with respect to SH
3.4
6.8
VVM – 2
10
R(IDRIVE) = 33 kΩ to GND (DRV8702D) or
IDRIVE = 3’b001 (DRV8703D)
20
R(IDRIVE) = 200 kΩ to GND (DRV8702D)
or IDRIVE = 3’b010 (DRV8703D)
50
IDRIVE = 3’b011 (DRV8703D)
70
IDRIVE = 3’b100 (DRV8703D)
100
R(IDRIVE) > 2 MΩ to GND (DRV8702D) or
IDRIVE = 3’b101 (DRV8703D)
145
R(IDRIVE) = 68 kΩ to AVDD (DRV8702D)
or IDRIVE = 3’b110 (DRV8703D)
190
R(IDRIVE) = 1 kΩ to AVDD (DRV8702D) or
IDRIVE = 3’b111 (DRV8703D)
240
R(IDRIVE) < 1 kΩ to GND (DRV8702D) or
IDRIVE = 3’b000 (DRV8703D)
20
R(IDRIVE) = 33 kΩ to GND (DRV8702D) or
IDRIVE = 3’b001 (DRV8703D)
40
R(IDRIVE) = 200 kΩ to GND (DRV8702D)
or IDRIVE = 3’b010 (DRV8703D)
90
IDRIVE = 3’b011 (DRV8703D)
120
IDRIVE = 3’b100 (DRV8703D)
170
R(IDRIVE) > 2 MΩ to GND (DRV8702D) or
IDRIVE = 3’b101 (DRV8703D)
250
R(IDRIVE) = 68 kΩ to AVDD (DRV8702D)
or IDRIVE = 3’b110 (DRV8703D)
330
R(IDRIVE) = 1 kΩ to AVDD (DRV8702D) or
IDRIVE = 3’b111 (DRV8703D)
420
Product Folder Links: DRV8702D-Q1 DRV8703D-Q1
V
4
10.5
R(IDRIVE) < 1 kΩ to GND (DRV8702D) or
IDRIVE = 3’b000 (DRV8703D)
Copyright © 2017, Texas Instruments Incorporated
11.5
Submit Documentation Feedback
V
mA
mA
7
DRV8702D-Q1, DRV8703D-Q1
SLVSDX8 – MARCH 2017
www.ti.com
Electrical Characteristics (continued)
Over recommended operating conditions unless otherwise noted. Typical limits apply for TA = 25°C and VVM = 13.5 V
PARAMETER
IDRIVE(SRC_LS)
IDRIVE(SNK_LS)
IDRIVE(SRC_HS)
8
TEST CONDITIONS
Low-side peak source current
(VVM = 5.5V)
Low-side peak sink current
(VVM = 5.5V)
High-side peak source current
(VVM = 13.5V)
Submit Documentation Feedback
MIN
TYP
R(IDRIVE) < 1 kΩ to GND (DRV8702D) or
IDRIVE = 3’b000 (DRV8703D)
10
R(IDRIVE) = 33 kΩ to GND (DRV8702D) or
IDRIVE = 3’b001 (DRV8703D)
20
R(IDRIVE) = 200 kΩ to GND (DRV8702D)
or IDRIVE = 3’b010 (DRV8703D)
40
IDRIVE = 3’b011 (DRV8703D)
55
IDRIVE = 3’b100 (DRV8703D)
75
R(IDRIVE) > 2 MΩ to GND (DRV8702D) or
IDRIVE = 3’b101 (DRV8703D)
115
R(IDRIVE) = 68 kΩ to AVDD (DRV8702D)
or IDRIVE = 3’b110 (DRV8703D)
145
R(IDRIVE) = 1 kΩ to AVDD (DRV8702D) or
IDRIVE = 3’b111 (DRV8703D)
190
R(IDRIVE) < 1 kΩ to GND (DRV8702D) or
IDRIVE = 3’b000 (DRV8703D)
20
R(IDRIVE) = 33 kΩ to GND (DRV8702D) or
IDRIVE = 3’b001 (DRV8703D)
40
R(IDRIVE) = 200 kΩ to GND (DRV8702D)
or IDRIVE = 3’b010 (DRV8703D)
85
IDRIVE = 3’b011 (DRV8703D)
115
IDRIVE = 3’b100 (DRV8703D)
160
R(IDRIVE) > 2 MΩ to GND (DRV8702D) or
IDRIVE = 3’b101 (DRV8703D)
235
R(IDRIVE) = 68 kΩ to AVDD (DRV8702D)
or IDRIVE = 3’b110 (DRV8703D)
300
R(IDRIVE) = 1 kΩ to AVDD (DRV8702D) or
IDRIVE = 3’b111 (DRV8703D)
360
R(IDRIVE) < 1 kΩ to GND (DRV8702D) or
IDRIVE = 3’b000 (DRV8703D)
10
R(IDRIVE) = 33 kΩ to GND (DRV8702D) or
IDRIVE = 3’b001 (DRV8703D)
20
R(IDRIVE) = 200 kΩ to GND (DRV8702D)
or IDRIVE = 3’b010 (DRV8703D)
50
IDRIVE = 3’b011 (DRV8703D)
70
IDRIVE = 3’b100 (DRV8703D)
105
R(IDRIVE) > 2 MΩ to GND (DRV8702D) or
IDRIVE = 3’b101 (DRV8703D)
155
R(IDRIVE) = 68 kΩ to AVDD (DRV8702D)
or IDRIVE = 3’b110 (DRV8703D)
210
R(IDRIVE) = 1 kΩ to AVDD (DRV8702D) or
IDRIVE = 3’b111 (DRV8703D)
260
MAX
UNIT
mA
mA
mA
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8702D-Q1 DRV8703D-Q1
DRV8702D-Q1, DRV8703D-Q1
www.ti.com
SLVSDX8 – MARCH 2017
Electrical Characteristics (continued)
Over recommended operating conditions unless otherwise noted. Typical limits apply for TA = 25°C and VVM = 13.5 V
PARAMETER
IDRIVE(SNK_HS)
IDRIVE(SRC_LS)
IDRIVE(SNK_LS)
TEST CONDITIONS
High-side peak sink current
(VVM = 13.5V)
Low-side peak source current
(VVM = 13.5V)
Low-side peak sink current
(VVM = 13.5V)
IHOLD
FET holding current
ISTRONG
FET holdoff strong pulldown
R(OFF)
FET gate holdoff resistor
MIN
TYP
R(IDRIVE) < 1 kΩ to GND (DRV8702D) or
IDRIVE = 3’b000 (DRV8703D)
20
R(IDRIVE) = 33 kΩ to GND (DRV8702D) or
IDRIVE = 3’b001 (DRV8703D)
40
R(IDRIVE) = 200 kΩ to GND (DRV8702D)
or IDRIVE = 3’b010 (DRV8703D)
95
IDRIVE = 3’b011 (DRV8703D)
130
IDRIVE = 3’b100 (DRV8703D)
185
R(IDRIVE) > 2 MΩ to GND (DRV8702D) or
IDRIVE = 3’b101 (DRV8703D)
265
R(IDRIVE) = 68 kΩ to AVDD (DRV8702D)
or IDRIVE = 3’b110 (DRV8703D)
350
R(IDRIVE) = 1 kΩ to AVDD (DRV8702D) or
IDRIVE = 3’b111 (DRV8703D)
440
R(IDRIVE) < 1 kΩ to GND (DRV8702D) or
IDRIVE = 3’b000 (DRV8703D)
10
R(IDRIVE) = 33 kΩ to GND (DRV8702D) or
IDRIVE = 3’b001 (DRV8703D)
20
R(IDRIVE) = 200 kΩ to GND (DRV8702D)
or IDRIVE = 3’b010 (DRV8703D)
45
IDRIVE = 3’b011 (DRV8703D)
60
IDRIVE = 3’b100 (DRV8703D)
90
R(IDRIVE) > 2 MΩ to GND (DRV8702D) or
IDRIVE = 3’b101 (DRV8703D)
130
R(IDRIVE) = 68 kΩ to AVDD (DRV8702D)
or IDRIVE = 3’b110 (DRV8703D)
180
R(IDRIVE) = 1 kΩ to AVDD (DRV8702D) or
IDRIVE = 3’b111 (DRV8703D)
225
R(IDRIVE) < 1 kΩ to GND (DRV8702D) or
IDRIVE = 3’b000 (DRV8703D)
20
R(IDRIVE) = 33 kΩ to GND (DRV8702D) or
IDRIVE = 3’b001 (DRV8703D)
40
R(IDRIVE) = 200 kΩ to GND (DRV8702D)
or IDRIVE = 3’b010 (DRV8703D)
95
IDRIVE = 3’b011 (DRV8703D)
125
IDRIVE = 3’b100 (DRV8703D)
180
R(IDRIVE) > 2 MΩ to GND (DRV8702D) or
IDRIVE = 3’b101 (DRV8703D)
260
R(IDRIVE) = 68 kΩ to AVDD (DRV8702D)
or IDRIVE = 3’b110 (DRV8703D)
350
R(IDRIVE) = 1 kΩ to AVDD (DRV8702D) or
IDRIVE = 3’b111 (DRV8703D)
430
Source current after tDRIVE
10
Sink current after tDRIVE
40
GH
750
GL
1000
Pulldown GH to SH
150
Pulldown GL to GND
150
MAX
UNIT
mA
mA
mA
mA
mA
kΩ
CURRENT SHUNT AMPLIFIER AND PWM CURRENT CONTROL (SP, SN, SO, VREF)
VVREF
(2)
VREF input rms voltage
For current internal chopping
0.3 (2)
3.6
V
Operational at VVREF = 0 to approximately 0.3 V, but accuracy is degraded.
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8702D-Q1 DRV8703D-Q1
Submit Documentation Feedback
9
DRV8702D-Q1, DRV8703D-Q1
SLVSDX8 – MARCH 2017
www.ti.com
Electrical Characteristics (continued)
Over recommended operating conditions unless otherwise noted. Typical limits apply for TA = 25°C and VVM = 13.5 V
PARAMETER
RVREF
TEST CONDITIONS
DRV8702D and DRV8703D VREF_SCL =
00 (100%)
VREF input impedance
AV
Amplifier gain (DRV8703D-Q1)
Input-referred offset
VIO(DRIFT)
Drift offset
ISP
SP input current
VSO
SO pin output voltage range
C(SO)
Allowable SO pin capacitance
UNIT
MΩ
kΩ
60 < VSP < 225 mV; VSN = GND
19.3
19.8
20.3
GAIN_CS = 00; 10 < VSP < 450 mV; VSN
= GND
9.75
10
10.25
GAIN_CS = 01; 60 < VSP < 225 mV; VSN
= GND
19.3
19.8
20.3
GAIN_CS = 10; 10 < VSP < 112 mV; VSN
= GND
38.4
39.4
40.4
73
78
81
5
10
V/V
V/V
VSP = VSN = GND
(2)
MAX
175
GAIN_CS = 11; 10 < VSP < 56 mV; VSN =
GND
VIO
TYP
1
DRV8703D VREF_SCL = 2’b01, 2’b10 or
2’b11
Amplifier gain (DRV8702D-Q1)
AV
MIN
VSP = VSN = GND
10
VSP = 100 mV; VSN = GND
µV/°C
–20
AV × VOFF
mV
µA
4.5
V
1
nF
PROTECTION CIRCUITS
VM falling; UVLO2 report
V(UVLO2)
VM undervoltage lockout
V(UVLO1)
Logic undervoltage lockout
Vhys(UVLO)
VM undervoltage hysteresis
V(CP_UV)
VM rising; UVLO2 recovery
5.45
5.4
5.65
4.5
Rising to falling threshold
100
CP undervoltage hysteresis
VVM +
1.5
VCP rising; CPUV recovery
VVM +
1.55
Rising to falling threshold
V(DS_OCP)
Overcurrent protection trip level,
VDS of each external FET
(DRV8702D-Q1)
High side FETs: VDRAIN – SH
Low side FETs: SH – SP
R(VDS) < 1 kΩ to GND
0.06
R(VDS) = 33 kΩ to GND
0.12
R(VDS) = 200 kΩ to GND
0.24
R(VDS) > 2 MΩ to GND
0.48
mV
V
0.96
R(VDS) < 1 kΩ to AVDD
Overcurrent protection trip level,
VDS of each external FET
(DRV8703D-Q1)
High-side FETs: VDRAIN – SH
Low-side FETs: SH – SP
V
V
50
R(VDS) = 68 kΩ to AVDD
V
mV
VCP falling; CPUV report
Charge pump undervoltage
Vhys(CP_UV)
V(DS_OCP)
5.25
Disabled
VDS_LEVEL = 3’b000
0.06
VDS_LEVEL = 3’b001
0.145
VDS_LEVEL = 3’b010
0.17
VDS_LEVEL = 3’b011
0.2
VDS_LEVEL = 3’b100
0.12
VDS_LEVEL = 3’b101
0.24
VDS_LEVEL = 3’b110
0.48
VDS_LEVEL = 3’b111
0.96
V
V(SP_OCP)
Overcurrent protection trip level,
measured by sense amplifier
VSP with respect to GND
0.8
1
1.2
V
T(OTW)
Thermal warning temperature (1)
Die temperature TJ
120
135
145
°C
Die temperature TJ
150
(1)
TSD
Thermal shutdown temperature
Thys
Thermal shutdown hysteresis (1)
VC(GS)
10
Gate-drive clamping voltage
Submit Documentation Feedback
Die temperature TJ
°C
20
Positive clamping voltage
Negative clamping voltage
°C
16.3
17
17.8
–1
–0.7
–0.5
V
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8702D-Q1 DRV8703D-Q1
DRV8702D-Q1, DRV8703D-Q1
www.ti.com
SLVSDX8 – MARCH 2017
6.6 SPI Timing Requirements
MIN
t(CLK)
Minimum SPI clock period
t(CLKH)
NOM
MAX
UNIT
100
ms
Clock high time
50
ns
t(CLKL)
Clock low time
50
ns
tsu(SDI)
SDI input data setup time
20
ns
th(SDI)
SDI input data hold time
30
ns
th(SDO)
SDO output hold time
40
ns
tsu(SCS)
SCS setup time
50
ns
th(SCS)
SCS hold time
50
ns
t(HI_SCS)
SCS minimum high time before SCS active low
400
ns
6.7 Switching Characteristics
Over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
100
µs
POWER SUPPLIES (VM, AVDD, DVDD)
t(SLEEP)
Sleep time
nSLEEP = low to sleep mode
t(wu)
Wake-up time
nSLEEP = high to output change
1
ms
ton
Turnon time
VM > UVLO2 to output transition
1
ms
700
kHz
CHARGE PUMP (VCP, CPH, CPL)
fS(VCP)
Charge-pump switching frequency
VM > UVLO2
200
400
CONTROL INPUTS (IN1, IN2, nSLEEP, MODE, nSCS, SCLK, SDI)
tpd
Propagation delay
IN1, IN2 or PH, EN to GH or GL
500
ns
Observed t(DEAD) depends on
IDRIVE setting
240
ns
TDEAD = 2’b00; Observed t(DEAD)
depends on IDRIVE setting
120
TDEAD = 2’b01; Observed t(DEAD)
depends on IDRIVE setting
240
TDEAD = 2’b10; Observed t(DEAD)
depends on IDRIVE setting
480
TDEAD = 2’b11; Observed t(DEAD)
depends on IDRIVE setting
960
FET GATE DRIVERS (GH, GH, SH, SH, GL, GL)
t(DEAD)
t(DEAD)
t(DRIVE)
Output dead time (DRV8702D-Q1)
Output dead time (DRV8703D-Q1)
Gate drive time
ns
2.5
µs
CURRENT SHUNT AMPLIFIER AND PWM CURRENT CONTROL (SP, SN, SO, VREF)
tS
Settling time to ±1%
toff
(1)
VSP = VSN = GND to VSP = 240 mV,
VSN = GND, AV= 10; C(SO) = 200 pF
0.5
VSP = VSN = GND to VSP = 120 mV,
VSN = GND, AV= 20; C(SO) = 200 pF
1
VSP = VSN = GND to VSP = 60 mV,
VSN = GND, AV= 40; C(SO) = 200 pF
2
VSP = VSN = GND to VSP = 30 mV,
VSN = GND, AV= 80; C(SO) = 200 pF
4
PWM off-time (DRV8702D-Q1)
25
TOFF = 00
toff
PWM off-time (DRV8703D-Q1)
t(BLANK)
PWM blanking time
(1)
µs
µs
25
TOFF = 01
50
TOFF = 10
100
TOFF = 11
200
2
µs
µs
Ensured by design
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8702D-Q1 DRV8703D-Q1
Submit Documentation Feedback
11
DRV8702D-Q1, DRV8703D-Q1
SLVSDX8 – MARCH 2017
www.ti.com
Switching Characteristics (continued)
Over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PROTECTION CIRCUITS
t(UVLO)
VM UVLO falling deglitch time
t(OCP)
Overcurrent deglitch time
t(RETRY)
Overcurrent retry time
VM falling; UVLO report
10
3.7
2.8
t(WD)
Watchdog time out (DRV8703DQ1)
t(RESET)
Watchdog timer reset period
µs
4
4.3
µs
3
3.2
ms
WD_DLY = 2’b00
10
WD_DLY = 2’b01
20
WD_DLY = 2’b10
50
WD_DLY = 2’b11
100
ms
64
µs
SPI
t(SPI_READY)
SPI read after power on
VM > VUVLO1
td(SDO)
SDO output data delay time, CLK
high to SDO valid
5
CL = 20 pF
ta
SCS access time, SCS low to SDO
out of high impedance
10
ns
tdis
SCS disable time, SCS high to
SDO high impedance
10
ns
t SU_SCS
t HI_SCS
10
ms
30
ns
t HD_SCS
SCS
t CLK
SCLK
t CLKH
t CLKL
MSB in
(must be valid)
SDI
tSU_SDI
SDO
Z
LSB
tHD_SDI
t ACC
t D_SDO
Z
LSB
MSB out (is valid)
t DIS
t HD_SDO
Figure 1. SPI Slave Mode Timing Definition
12
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8702D-Q1 DRV8703D-Q1
DRV8702D-Q1, DRV8703D-Q1
www.ti.com
SLVSDX8 – MARCH 2017
1
SCS
2
3
4
X
15
16
SCLK
SDI
MSB
LSB
SDO
MSB
LSB
Receive
Latch Points
Figure 2. SPI Slave Mode Timing Diagram
8.4
8.4
8.1
8.1
7.8
7.8
Supply Current (mA)
Supply Current (mA)
6.8 Typical Characteristics
7.5
7.2
6.9
TA = 40qC
TA = 25qC
TA = 125qC
6.6
10
15
20
25
30
Supply Voltage (V)
35
40
7.5
7.2
6.9
6.6
6.3
5
VVM = 5.5 V
VVM = 13.5 V
VVM = 45 V
45
6.3
-50
-25
0
D001
Figure 3. Supply Current vs Supply Voltage (VM)
25
50
Temperature (qC)
75
100
125
D002
Figure 4. Supply Current vs Temperature
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8702D-Q1 DRV8703D-Q1
Submit Documentation Feedback
13
DRV8702D-Q1, DRV8703D-Q1
SLVSDX8 – MARCH 2017
www.ti.com
Typical Characteristics (continued)
21
21
TA = 40qC
TA = 25qC
TA = 125qC
VVM = 5.5 V
VVM = 13.5 V
VVM = 45 V
19
17
Sleep Current (PA)
Sleep Current (PA)
19
15
13
11
17
15
13
11
9
9
7
-50
7
5
10
15
20
25
30
Supply Voltage (V)
35
40
45
-25
0
D003
Figure 5. Sleep Current vs Supply Voltage (VM)
25
50
Temperature (qC)
75
100
125
D004
Figure 6. Sleep Current vs Temperature
5.1
3.4
TA = 40qC
TA = 25qC
TA = 125qC
3.35
5.05
AVDD (V)
DVDD (V)
3.3
3.25
5
3.2
4.95
TA = 40qC
TA = 25qC
TA = 125qC
3.15
3.1
4.9
5
10
15
20
25
30
Supply Voltage (V)
35
40
45
5
10
15
2-mA load
Figure 7. DVDD Regulator
40
45
D006
Figure 8. AVDD Regulator
5.1
3.24
5
3.22
4.9
4.8
AVDD (V)
3.2
DVDD (V)
35
2-mA load
3.26
3.18
3.16
3.14
4.7
4.6
4.5
4.4
3.12
4.3
TA = 40qC
TA = 25qC
TA = 125qC
3.1
TA = 40qC
TA = 25qC
TA = 125qC
4.2
4.1
3.08
5
10
15
20
25
30
Supply Voltage (V)
35
30-mA load
40
45
5
10
15
20
25
30
35
Supply Voltage (V)
D007
40
45
50
D008
30-mA load
Figure 9. DVDD Regulator
14
20
25
30
Supply Voltage (V)
D005
Submit Documentation Feedback
Figure 10. AVDD Regulator
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8702D-Q1 DRV8703D-Q1
DRV8702D-Q1, DRV8703D-Q1
www.ti.com
SLVSDX8 – MARCH 2017
Typical Characteristics (continued)
19.9
10
VVM = 5.5 V
VVM = 13.5 V
VVM = 45 V
19.84
Amplifier Gain (V/V)
Amplifier Gain (V/V)
9.98
9.96
9.94
19.78
19.72
19.66
9.92
9.9
-50
VVM = 5.5 V
VVM = 13.5 V
VVM = 45 V
-25
0
25
50
Temperature (qC)
75
100
19.6
-50
125
-25
10-V/V gain
25
50
Temperature (qC)
75
100
125
D010
19.8-V/V gain
Figure 11. Amplifier Gain
Figure 12. Amplifier Gain
40
79
VVM = 5.5 V
VVM = 13.5 V
VVM = 45 V
VVM = 5.5 V
VVM = 13.5 V
VVM = 45 V
78.8
78.6
Amplifier Gain (V/V)
39.8
Amplifier Gain (V/V)
0
D009
39.6
39.4
39.2
78.4
78.2
78
77.8
77.6
77.4
77.2
39
-50
-25
0
25
50
Temperature (qC)
75
100
77
-50
125
-25
39.4-V/V gain
Figure 13. Amplifier Gain
100
125
D012
Figure 14. Amplifier Gain
VVM = 5.5 V
VVM = 13.5 V
VVM = 45 V
0.17
VVM = 5.5 V
VVM = 13.5 V
VVM = 45 V
0.16
VDS Setting (V)
VDS Setting (V)
75
0.18
0.08
0.07
0.06
0.05
0.15
0.14
0.13
0.12
0.04
0.03
-50
25
50
Temperature (qC)
78-V/V gain
0.1
0.09
0
D011
0.11
-25
0
25
50
Temperature (qC)
75
100
VDS(OCP) = 0.06 V
125
0.1
-50
-25
0
D013
25
50
Temperature (qC)
75
100
125
D014
VDS(OCP) = 0.12 V
Figure 15. OCP Threshold Voltage
Figure 16. OCP Threshold Voltage
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8702D-Q1 DRV8703D-Q1
Submit Documentation Feedback
15
DRV8702D-Q1, DRV8703D-Q1
SLVSDX8 – MARCH 2017
www.ti.com
Typical Characteristics (continued)
0.19
0.26
VDS Setting (V)
VDS Setting (V)
0.18
0.27
VVM = 5.5 V
VVM = 13.5 V
VVM = 45 V
0.17
0.16
0.15
0.14
-50
0.25
0.24
0.23
0.22
-25
0
25
50
Temperature (qC)
75
100
0.21
-50
125
Figure 17. OCP Threshold Voltage
25
50
Temperature (qC)
75
100
125
D016
Figure 18. OCP Threshold Voltage
1
VVM = 5.5 V
VVM = 13.5 V
VVM = 45 V
VVM = 5.5 V
VVM = 13.5 V
VVM = 45 V
0.99
0.495
0.98
0.49
VDS Setting (V)
VDS Setting (V)
0
VDS(OCP) = 0.24 V
0.51
0.5
-25
D015
VDS(OCP) = 0.17 V
0.505
VVM = 5.5 V
VVM = 13.5 V
VVM = 45 V
0.485
0.48
0.475
0.47
0.97
0.96
0.95
0.465
0.46
0.94
0.455
0.45
-50
-25
0
25
50
Temperature (qC)
75
100
0.93
-50
125
VDS(OCP) = 0.48 V
0
25
50
Temperature (qC)
75
100
125
D018
VDS(OCP) = 0.86 V
Figure 19. OCP Threshold Voltage
Figure 20. OCP Threshold Voltage
300
500
3'b111
3'b110
3'b101
3'b100
3'b011
3'b010
3'b111
3'b110
450
250
3'b101
3'b100
3'b011
3'b010
400
350
IDRIVE (mA)
200
IDRIVE (mA)
-25
D017
150
100
300
250
200
150
100
50
50
0
-50
-25
0
25
50
Temperature (qC)
75
100
VVM = 5.5 V
Submit Documentation Feedback
0
-50
-25
0
D019
25
50
Temperature (qC)
75
100
125
D020
VVM = 5.5 V
Figure 21. High-Side Source Current
16
125
Figure 22. High-Side Sink Current
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8702D-Q1 DRV8703D-Q1
DRV8702D-Q1, DRV8703D-Q1
www.ti.com
SLVSDX8 – MARCH 2017
Typical Characteristics (continued)
450
250
3'b111
3'b110
3'b101
3'b100
3'b011
3'b010
3'b111
3'b110
400
200
3'b101
3'b100
3'b011
3'b010
350
IDRIVE (mA)
IDRIVE (mA)
300
150
100
250
200
150
100
50
50
0
-50
-25
0
25
50
Temperature (qC)
75
100
0
-50
125
-25
VVM = 5.5 V
25
50
Temperature (qC)
75
100
125
D022
VVM = 5.5 V
Figure 23. Low-Side Source Current
Figure 24. Low-Side Sink Current
350
550
3'b111
3'b110
300
3'b101
3'b100
3'b011
3'b010
3'b111
3'b110
500
3'b101
3'b100
3'b011
3'b010
450
400
IDRIVE (mA)
250
IDRIVE (mA)
0
D021
200
150
100
350
300
250
200
150
100
50
50
0
-50
-25
0
25
50
Temperature (qC)
75
100
0
-50
125
-25
0
D023
VVM = 13.5 V
25
50
Temperature (qC)
75
100
125
D024
VVM = 13.5 V
Figure 25. High-Side Source Current
Figure 26. High-Side Sink Current
300
550
3'b111
3'b110
3'b101
3'b100
3'b011
3'b010
3'b111
3'b110
500
250
3'b101
3'b100
3'b011
3'b010
450
400
IDRIVE (mA)
IDRIVE (mA)
200
150
100
350
300
250
200
150
100
50
50
0
-50
-25
0
25
50
Temperature (qC)
75
100
VVM = 13.5 V
125
0
-50
-25
0
D025
25
50
Temperature (qC)
75
100
125
D026
VVM = 13.5 V
Figure 27. Low-Side Source Current
Figure 28. Low-Side Sink Current
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8702D-Q1 DRV8703D-Q1
Submit Documentation Feedback
17
DRV8702D-Q1, DRV8703D-Q1
SLVSDX8 – MARCH 2017
www.ti.com
7 Detailed Description
7.1 Overview
The DRV870xD-Q1 device is an half-bridge gate driver (also called a gate controller). The device integrates FET
gate drivers to control two external NMOS FETs. The device can be powered with a supply voltage from 5.5 V to
45 V.
The device has a low-power sleep mode that is enabled using the nSLEEP pin.
The gate drive strength can be adjusted to optimize a system for a given FET size without adding external series
resistors. The IDRIVE pin allows for selection of the peak current driven into the external FET gate. Both the
high-side and low-side FETs are driven with a gate source voltage (VGS) of 10.5 V (nominal) when the VM
voltage is more than 13.5 V. At lower VM voltages, the VGS is reduced. The high-side gate drive voltage is
generated using a doubler-architecture charge pump that regulates to the VM + 10.5 V.
This device significantly reduces the component count of discrete motor-driver systems by integrating the
required FET drive circuitry into a single device. The DRV870xD-Q1 device also has protection features beyond
traditional discrete implementations including: undervoltage lockout (UVLO), overcurrent protection (OCP), gatedriver faults, and thermal shutdown (TSD).
A start-up (inrush) or running current limitation is built in using a fixed time-off current chopping scheme. The
chopping current level is set by selecting the value of the sense resistor and setting a voltage on the VREF pin.
A shunt-amplifier output provides accurate current measurements by the system controller. The SO pin outputs a
voltage that is approximately 20 times the voltage across the sense resistor on the DRV8702D-Q1 device. For
the DRV8703D-Q1, this gain is configurable.
18
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8702D-Q1 DRV8703D-Q1
DRV8702D-Q1, DRV8703D-Q1
www.ti.com
SLVSDX8 – MARCH 2017
7.2 Functional Block Diagram
VM
0.1 …F
VM
10 µF
(minimum)
VM
VM
Power
VDRAIN
1 µF
VVCP
VCP
GH
HS
CPH
Charge Pump
0.1 µF
CPL
DVDD
3.3-V LDO
AVDD
Gate Driver
Logic
1 µF
SH
5-V LDO
1 µF
M
VGLS LDO
VGLS
GL
LS
IN1
IN2
nSLEEP
Current Regulation
Control Inputs
SP
MODE
+
IDRIVE
RIDRIVE
R(SENSE)
AV
SN
±
VDS
SO
RVDS
VREF
nFAULT
Output
PAD
GND
GND
Copyright © 2017, Texas Instruments Incorporated
Figure 29. DRV8702D-Q1 Functional Block Diagram
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8702D-Q1 DRV8703D-Q1
Submit Documentation Feedback
19
DRV8702D-Q1, DRV8703D-Q1
SLVSDX8 – MARCH 2017
www.ti.com
Functional Block Diagram (continued)
VM
VM
VM
0.1 …F
10 µF
(minimum)
VM
1 µF
VCP
Power
VDRAIN
Gate Driver
VVCP
CPH
Charge Pump
GH
HS
0.1 µF
CPL
DVDD
3.3-V LDO
1 µF
Logic
AVDD
SH
5-V LDO
1 µF
VGLS LDO
VGLS
M
IN1
GL
LS
IN2
Control Inputs
nSLEEP
Current Regulation
SP
MODE
Outputs
R(SENSE)
AV
+
-
nFAULT
SN
SO
nWDFLT
VREF
SCLK
SPI
SDI
SDO
nSCS
PAD
GND
GND
Copyright © 2017, Texas Instruments Incorporated
Figure 30. DRV8703D-Q1 Functional Block Diagram
20
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8702D-Q1 DRV8703D-Q1
DRV8702D-Q1, DRV8703D-Q1
www.ti.com
SLVSDX8 – MARCH 2017
7.3 Feature Description
Table 1 and Table 2 list the recommended external components for the device.
Table 1. External Components
(1)
(2)
COMPONENT
PIN 1
PIN 2
RECOMMENDED
C(VM1)
VM
GND
0.1-µF ceramic capacitor rated for VM
C(VM2)
VM
GND
≥ 10-µF electrolytic capacitor rated for VM
C(VCP)
VCP
VM
16-V, 1-µF ceramic capacitor
C(SW)
CPH
CPL
0.1-µF X7R capacitor rated for VM
C(DVDD)
DVDD
GND
6.3-V, 1-µF ceramic capacitor
C(AVDD)
AVDD
GND
6.3-V, 1-µF ceramic capacitor
R(IDRIVE)
IDRIVE
GND
For resistor sizing, see the Typical Application section
R(VDS)
VDS
GND
For resistor sizing, see the Typical Application section
R(nFAULT)
VCC
(1)
nFAULT
≥ 10 kΩ
R(nWDFLT)
VCC (1)
nWDFLT
≥ 10 kΩ
R(SENSE)
SP
SN or GND
Optional low-side sense resistor
R(VDRAIN) (2)
VDRAIN
VM
100-Ω series resistor
The VCC pin is not a pin on the DRV870xD-Q1, but a VCC supply voltage pullup is required for open-drain outputs nFAULT. These pins
can be pulled up to either AVDD or DVDD.
The R(VDRAIN) resistor should be used between the VDRAIN and VM pins to minimize current to the VDRAIN pin if no external reserve
battery protection is implemented on the VDRAIN pin.
Table 2. External Gates
COMPONENT
GATE
DRAIN
SOURCE
RECOMMENDED
Q(HS)
GH
VM
SH
Supports FETs up to 200 nC at 40 kHz
PWM
Q(LS)
GL
SH
SP or GND
For more information, see Application
and Implementation
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8702D-Q1 DRV8703D-Q1
Submit Documentation Feedback
21
DRV8702D-Q1, DRV8703D-Q1
SLVSDX8 – MARCH 2017
www.ti.com
7.3.1 Bridge Control
The DRV870xD-Q1 device is controlled using a configurable input interface. The Logic Tables section provides
the half-bridge operation states. These tables do not consider the current control built into the DRV870xD-Q1
device. The logic operation set by the MODE pin is latched on power-up or when exiting sleep mode. Figure 31
shows the direction of the flow of current through the load when it is connected between the SH pin and GND,
and between the SH pin and VM.
VM
VM
1 Drive
2 Slow decay (brake)
1
2
1
SH
SH
2
Figure 31. Bridge Control
7.3.1.1 Logic Tables
Table 3, and Table 4 are the device logic tables. An X denotes a don’t care input or output.
NOTE
Any other input logic combinations, aside from the ones mentioned in Table 3 and
Table 4, result in an error, and the device will trigger a fault.
Table 3. DRV870xD-Q1 PWM Control Interface Without Current Regulation (MODE = 1)
nSLEEP
IN1
IN2
GH
GL
SH
AVDD/DVDD
Description
0
X
X
X
X
Hi-Z
Disabled
Sleep mode ½-bridge disabled
1
0
0
0
1
L
Enabled
½-bridge low side on
1
1
0
1
0
H
Enabled
½-bridge high side on
Table 4. DRV870xD-Q1 PWM Control Interface With Current Regulation (MODE = Hi-Z)
nSLEEP
IN1
IN2
GH
GL
SH
AVDD/DVDD
Description
0
X
X
X
X
Hi-Z
Disabled
Sleep mode ½-bridge disabled
1
0
0
0
0
Hi-Z
Enabled
½-bridge is in tri-state
1
1
0
1
0
H
Enabled
½-bridge high-side on
1
1
1
0
1
L
Enabled
½-bridge low-side on
If MODE = Hi-Z is selected, the device performs current regulation (refer to the Current Regulation section).
Having both the input (INx) pins high puts the motor in brake mode (low-side slow decay). If MODE = 1 is
selected, current regulation is disabled and must be performed externally using a MCU. With MODE = 1, the load
current recirculation occurs through the high-side FET as shown in Figure 31.
22
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8702D-Q1 DRV8703D-Q1
DRV8702D-Q1, DRV8703D-Q1
www.ti.com
SLVSDX8 – MARCH 2017
7.3.2 MODE Pin
The MODE pin of the device determines the control interface and latches on power-up or when exiting sleep
mode. Figure 32 shows an overview of the internal circuit of the MODE pin.
DVDD
+
1.35 V
±
Digital
Core
26 k
MODE
+
65 k
0.75 V
±
Figure 32. MODE Pin Block Diagram
Table 5 lists the different control interfaces that can be set via MODE pin at power-up or when exiting sleep
mode.
Table 5. MODE Pin Configuration
MODE
CONTROL INTERFACE
1
PWM control interface without current regulation
Hi-Z
PWM control interface with current regulation
During the device power-up sequence, the DVDD pin is enabled first. Then the MODE pin latches. Finally the
AVDD pin is enabled. For setting PWM control interface, TI does not recommended connecting the MODE pin to
the AVDD pin. Instead the MODE pin should be connected to an external 5-V or 3.3-V supply or to the DVDD pin
if not driven by an external microcontroller (MCU).
7.3.3 nFAULT Pin
The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. When a fault is
detected, the nFAULT line is logic low.
nFAULT
Output
Figure 33. nFAULT Block Diagram
For a 3.3-V pullup the nFAULT pin can be tied to the DVDD pin with a resistor (refer to the Application and
Implementation section). For a 5-V pullup an external 5-V supply should be used. TI does not recommended
connecting the nFAULT pin to the AVDD pin.
7.3.4 Current Regulation
The maximum current through the motor winding is regulated by a fixed off-time PWM current regulation or
current chopping. When an half-bridge is enabled, current rises through the winding at a rate dependent on the
DC voltage and inductance of the winding. When the current hits the current chopping threshold, the bridge
enters a brake (low-side slow decay) mode until the toff time expires.
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8702D-Q1 DRV8703D-Q1
Submit Documentation Feedback
23
DRV8702D-Q1, DRV8703D-Q1
SLVSDX8 – MARCH 2017
www.ti.com
NOTE
Immediately after the current is enabled, the voltage on the SP pin is ignored for a period
(t(BLANK)) before enabling the current-sense circuitry.
The PWM chopping current is set by a comparator that compares the voltage across a current-sense resistor
connected to the SP pin, multiplied by a factor of AV, with a reference voltage from the VREF pin. The factor AV
is the shunt-amplifier gain, which is 19.8 V/V for the DRV8702D-Q1 device or configurable to 10, 19.8, 39.4, or
78 V/V for the DRV8703D-Q1 device.
Use Equation 1 to calculate the chopping current (ICHOP).
VVREF VIO
I(CHOP)
A V u R(SENSE)
(1)
For example, if a 50-mΩ sense resistor and a VREF value of 3.3 V are selected, the full-scale chopping current
is 3.28 A. The AV is 19.8 V/V and VIO is assumed to be 50 mV in this example.
NOTE
If the load is connected between the SH pin and VM and current regulation is enabled
(MODE pin is Hi-Z), the low-side FET is switched on when the current flowing through the
load exceeds the ICHOP threshold. This result in an adverse effect by driving the load at
100% duty cycle because the maximum current flows through the load as the low-side
FET remains switched on for the tOFF duration. Texas Instruments recommends using the
PWM control interface without current regulation (MODE pin is 1) for this configuration to
drive the load.
For DC motors, current regulation is used to limit the start-up and stall current of the motor. If the current
regulation feature is not needed, it can be disabled by tying the VREF pin directly to the AVDD pin. If the PWM
control-interface mode without current regulation (MODE pin is 1) is selected for operation, the device does not
perform PWM current regulation or current chopping.
7.3.5 Amplifier Output (SO)
The SO pin on the DRV870xD-Q1 device outputs an analog voltage equal to the voltage across the SP and SN
pins multiplied by AV. The SO voltage is only valid for when the load is connected in the way shown in Figure 31.
Use Equation 2 to calculate the approximate current for the half-bridge.
I
VSO VIO
A V u R(SENSE)
(2)
When the SP and SN voltages are 0 V, the SO pin outputs the amplifier offset voltage, VIO. No capacitor is
required on the SO pin.
24
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8702D-Q1 DRV8703D-Q1
DRV8702D-Q1, DRV8703D-Q1
www.ti.com
SLVSDX8 – MARCH 2017
AVDD
SO (V)
AV
VIO
SP-SN (V)
Figure 34. Current Sense Amplifier Output
If the voltage across the SP and SN pins exceeds 1 V, then the DRV870xD-Q1 device flags an overcurrent
condition.
The SO pin can source up to 5 mA of current. If the pin is shorted to ground, or if this pin drives a higher current
load, the output functions as a constant-current source. The output voltage is not representative of the half-bridge
current in this state.
Drive Current (A)
I(CHOP)
Drive
Brake and Slow Decay
Drive
Brake and Slow Decay
t(DRIVE)
tOFF
t(DRIVE)
tOFF
SO (V)
VVREF
Figure 35. Current Sense Amplifier and Current Chopping Operation
During brake mode (slow decay), current is circulated through the low-side FET. Because current is not flowing
through the sense resistor, the SO pin does not represent the motor current.
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8702D-Q1 DRV8703D-Q1
Submit Documentation Feedback
25
DRV8702D-Q1, DRV8703D-Q1
SLVSDX8 – MARCH 2017
www.ti.com
7.3.5.1 SO Sample and Hold Operation
The DRV8703D-Q1 device allows the shunt amplifier to operate in a sample and hold configuration. To enable
this mode, set the SH_EN bit high through the SPI. In this mode, the shunt amplifier output is disabled to the
Hi-Z state whenever the driver is in a brake mode. Place an external capacitor on this pin.
Drive Current (A)
I(CHOP)
Drive
Brake and Slow Decay
Drive
Brake and Slow Decay
t(DRIVE)
tOFF
t(DRIVE)
tOFF
SO (V)
VVREF
SO Output Hi-Z
SO Output Hi-Z
Figure 36. Sample and Hold Operation
26
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8702D-Q1 DRV8703D-Q1
DRV8702D-Q1, DRV8703D-Q1
www.ti.com
SLVSDX8 – MARCH 2017
7.3.6 PWM Motor Gate Drivers
The DRV870xD-Q1 device has gate drivers for a single half-bridge with external NMOS FETs. Figure 37 shows a
block diagram of the predrive circuitry.
VGHS
VM
GH
IN
R(OFF)
SH
Predrive
VGLS
Logic
nSLEEP
GL
M
R(OFF)
SP
SN
R(SENSE)
Figure 37. Predrive Block Diagram
Gate drivers inside the DRV870xD-Q1 device directly drive N-Channel MOSFETs, which drive the motor current.
The high-side gate drive is supplied by the charge pump, while an internal regulator generates the low-side gate
drive.
The peak drive current of the gate drivers is adjustable through the IDRIVE pin for DRV8702D-Q1 device or the
IDRIVE register for the DRV8703D-Q1 device. Peak source currents can be set to the values listed in the FET
gate drivers section of the Electrical Characteristics table. The peak sink current is approximately two times the
peak source current. Adjusting the peak current changes the output slew rate, which also depends on the FET
input capacitance and gate charge.
Fast switching times can cause extra noise on the VM and GND pins. This additional noise can occur specifically
because of a relatively slow reverse-recovery time of the low-side body diode, when the body diode conducts
reverse-bias momentarily, similar to shoot-through. Slow switching times can cause excessive power dissipation
because the external FETs have a longer turnon and turnoff time.
When changing the state of the output, the peak current (IDRIVE) is applied for a short period (t(DRIVE)), to charge
the gate capacitance. After this time, a weak current source (IHOLD) is used to keep the gate at the desired state.
When selecting the gate drive strength for a given external FET, the selected current must be high enough to
charge fully and discharge the gate during t(DRIVE), or excessive power is dissipated in the FET.
During high-side turnon, the low-side gate is pulled low with a strong pulldown (ISTRONG). This pulldown prevents
the low-side FET QGS from charging and keeps the FET off, even when fast switching occurs at the outputs.
The gate-driver circuits include enforcement of a dead time in analog circuitry, which prevents the high-side and
low-side FETs from conducting at the same time. When the switching FETs are on, this handshaking prevents
the high-side or low-side FET from turning on until the opposite FET turns off.
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8702D-Q1 DRV8703D-Q1
Submit Documentation Feedback
27
DRV8702D-Q1, DRV8703D-Q1
SLVSDX8 – MARCH 2017
www.ti.com
tDRIVE
IHOLD
IDRIVE(SNK)
IDRIVE(SRC)
High-side
gate drive
current
ISTRONG
ISTRONG
High-side
VGS
tDRIVE
IHOLD
Low-side
gate drive
current
IHOLD
IDRIVE(SNK)
IDRIVE(SRC)
ISTRONG
Low-side
VGS
Figure 38. Gate Driver Output to Control External FETs
7.3.6.1 Miller Charge (QGD)
When a FET gate turns on, the following capacitances must be charged:
• Gate-to-source charge, QGS
• Gate-to-drain charge, QGD (Miller charge)
• Remaining QG
D
VGHS
Predrive
GH
G
SH
Gate-To-Source Charge (V)
24 V
10
25
8
20
6
15
4
10
2
5
S
10
30
20
QGD
Gate Charge (nC)
QGS
40
Drain-To-Source Charge (V)
The FET output is slewing primarily during the QGD charge.
50
Figure 39. FET Gate Charging Profile
28
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8702D-Q1 DRV8703D-Q1
DRV8702D-Q1, DRV8703D-Q1
www.ti.com
SLVSDX8 – MARCH 2017
7.3.7 IDRIVE Pin (DRV8702D-Q1 Only)
The rise and fall times of the half-bridge output (SH pin) can be adjusted by setting the IDRIVE resistor value or
forcing a voltage onto the IDRIVE pin. The FET gate voltage ramps faster if a higher IDRIVE setting is selected.
The ramp of the FET gate directly affects the rise and fall times of the half-bridge output.
Tying the IDRIVE pin to ground selects the lowest drive setting of 10-mA source and 20-mA sink. Leaving this
pin open selects the drive setting of 155-mA high side and 130-mA low side for source current, and 265-mA high
side, 260-mA low side for sink current, at a VM voltage of 13.5 V. For a detailed list of IDRIVE configurations,
see Table 6.
+
4.9 V
±
AVDD
+
190 NŸ
3.7 V
±
IDRIVE
+
310 NŸ
2.5 V
±
Digital
Core
+
1.3 V
±
+
0.1 V
±
Figure 40. IDRIVE Pin Internal Circuitry
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8702D-Q1 DRV8703D-Q1
Submit Documentation Feedback
29
DRV8702D-Q1, DRV8703D-Q1
SLVSDX8 – MARCH 2017
www.ti.com
Table 6. DRV8702D-Q1 IDRIVE Settings
IDRIVE
RESISTANCE
IDRIVE
VOLTAGE
< 1 kΩ to GND
33 kΩ ± 5% to
GND
SOURCE CURRENT
SINK CURRENT
VVM = 5.5 V
VVM = 13.5 V
VVM = 5.5 V
VVM = 13.5 V
GND
High-side: 10 mA
Low-side: 10 mA
High-side: 10 mA
Low-side: 10 mA
High-side: 20 mA
Low-side: 20 mA
High-side: 20 mA
Low-side: 20 mA
0.7 V ± 5%
High-side: 20 mA
Low-side: 20 mA
High-side: 20 mA
Low-side: 20 mA
High-side: 40 mA
Low-side: 40 mA
High-side: 40 mA
Low-side: 40 mA
CIRCUIT
IDRIVE
IDRIVE
RIDRIVE
200 kΩ ± 5% to
GND
2 V ± 5%
High-side: 50 mA
Low-side: 40 mA
High-side: 50 mA
Low-side: 45 mA
High-side: 90 mA
Low-side: 85 mA
IDRIVE
High-side: 95 mA
Low-side: 95 mA
RIDRIVE
> 2 MΩ to GND,
Hi-Z
3 V ± 5%
High-side: 145 mA
Low-side: 115 mA
High-side: 155 mA
Low-side: 130 mA
High-side: 250 mA
Low-side: 235 mA
High-side: 265 mA
Low-side: 260 mA
IDRIVE
AVDD
68 kΩ ± 5% to
AVDD
4 V ± 5%
High-side: 190 mA
Low-side: 145 mA
High-side: 210 mA
Low-side: 180 mA
High-side: 330 mA
Low-side: 300 mA
High-side: 350 mA
Low-side: 350 mA
IDRIVE
AVDD
< 1 kΩ to AVDD
30
AVDD
High-side: 240 mA
Low-side: 190 mA
Submit Documentation Feedback
High-side: 260 mA
Low-side: 225 mA
High-side: 420 mA
Low-side: 360 mA
High-side: 440 mA
Low-side:430 mA
IDRIVE
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8702D-Q1 DRV8703D-Q1
DRV8702D-Q1, DRV8703D-Q1
www.ti.com
SLVSDX8 – MARCH 2017
7.3.8 Dead Time
The dead time (t(DEAD)) is measured as the time when the SH pin is in the Hi-Z state between turning off one of
the half-bridge FETs and turning on the other. For example, the output is Hi-Z between turning off the high-side
FET and turning on the low-side FET.
The dead time consists of an inserted digital dead time and FET gate slewing. The DRV8702D-Q1 device has a
digital dead time of approximately 240 ns. The DRV8703D-Q1 device has programmable dead-time options of
120, 240, 480, 960 ns. In addition to this digital dead time, the output is Hi-Z as long as the voltage across the
GL pin to ground or GH pin to SH pin is less than the FET threshold voltage.
The total dead time is dependent on the IDRIVE resistor setting because a portion of the FET gate ramp (GH
and GL pins) includes the observable dead time.
7.3.9 Propagation Delay
The propagation delay time (tPD) is measured as the time between an input edge to an output change. This time
is composed of two parts: an input deglitcher and output slewing delay. The input deglitcher prevents noise on
the input pins from affecting the output state.
The gate drive slew rate also contributes to the delay time. For the output to change state during normal
operation, one FET must first be turned off. The FET gate is ramped down according to the IDRIVE resistor
selection, and the observed propagation delay ends when the FET gate falls below the threshold voltage.
7.3.10 Overcurrent VDS Monitor
The gate-driver circuit monitors the VDS voltage of each external FET when it is driving current. When the
voltage monitored is greater than the OCP threshold voltage (VDS(OCP)) after the OCP deglitch time has expired,
an OCP condition is detected. The VDS voltage can be adjusted by changing the resistor (R(VDS)) on the VDS pin
of the DRV8702D-Q1 device. The DRV8703D-Q1 device provides VDS voltage levels by setting the VDS
register.
VM
+
High-Side
VDS OCP
Monitor
VDRAIN
GH
±
SH
GL
+
Low-Side
VDS OCP
Monitor 1
M
±
SP
R(SENSE)
SN
Figure 41. VDS(OCP) Block Diagram
The VDS voltage on the high-side FET is measured across the VDRAIN to SH pin. The low-side VDS monitor
measures the VDS voltage across the SH to SP pins. Ensure that the SP pin is always connected to the source
of the low-side FET of half-bridge, even when the sense amplifier is not used.
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8702D-Q1 DRV8703D-Q1
Submit Documentation Feedback
31
DRV8702D-Q1, DRV8703D-Q1
SLVSDX8 – MARCH 2017
www.ti.com
7.3.11 VDS Pin (DRV8702D-Q1 Only)
The VDS pin on the DRV8702D-Q1 device is used to select the VDS threshold voltage for overcurrent detection.
Tying the VDS pin to ground selects the lowest setting of 0.06 V. Leaving this pin open selects the setting of
0.48 V. Tying the VDS pin to the AVDD the pin disables the VDS monitor. For a detailed list of VDS
configurations, see Table 7.
+
4.9 V
±
AVDD
+
190 NŸ
3.7 V
±
VDS
+
310 NŸ
2.5 V
±
Digital
Core
+
1.3 V
±
+
0.1 V
±
Figure 42. VDS Block Diagram
32
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8702D-Q1 DRV8703D-Q1
DRV8702D-Q1, DRV8703D-Q1
www.ti.com
SLVSDX8 – MARCH 2017
Table 7. VDS Pin Resistor Setting
VDS RESISTANCE
VDS VOLTAGE
OVERCURRENT
TRIP LEVEL
(VDS(OCP))
< 1 kΩ to GND
GND
0.06 V
33 kΩ ± 5% to GND
0.7 V ± 5%
0.12 V
CIRCUIT
VDS
VDS
RIDRIVE
200 kΩ ± 5% to GND
2 V ± 5%
VDS
0.24 V
RIDRIVE
> 2 MΩ to GND, Hi-Z
3 V ± 5%
0.48 V
VDS
AVDD
68 kΩ ± 5% to AVDD
4 V ± 5%
0.96 V
VDS
AVDD
< 1 kΩ to AVDD
AVDD
Disabled
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8702D-Q1 DRV8703D-Q1
VDS
Submit Documentation Feedback
33
DRV8702D-Q1, DRV8703D-Q1
SLVSDX8 – MARCH 2017
www.ti.com
7.3.12 Charge Pump
A charge pump is integrated to supply the gate drive voltage of a high-side NMOS (VGSH). The charge pump
requires a capacitor between the VM and VCP pins. Additionally, a low-ESR ceramic capacitor is required
between the CPH and CPL pins. When the VM voltage is below 13.5 V, this charge pump functions as a doubler
and generates a VVCP equal to 2 × VVM – 1.5 V if unloaded. When the VM voltage is more than 13.5 V, the
charge pump regulates VVCP such that it is equal to VVM + 10.5 V.
VM
1 F
VCP
CPH
VM
Charge
Pump
0.1 F
CPL
Figure 43. Charge Pump Block Diagram
7.3.13 Gate Drive Clamp
A clamping structure limits the gate-drive output voltage to the VC(GS) voltage to protect the power FETs from
damage. The positive voltage clamp is realized using a series of diodes. The negative voltage clamp uses the
body diodes of the internal predriver FET.
VGHS
VM
I(REVERSE)
GH
VGS > VC
IC
SH
Predriver
VGLS
VGS negative
GL
R(SENSE)
PGND
Figure 44. Gate Drive Clamp
34
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8702D-Q1 DRV8703D-Q1
DRV8702D-Q1, DRV8703D-Q1
www.ti.com
SLVSDX8 – MARCH 2017
7.3.14 Protection Circuits
The DRV870xD-Q1 device is fully protected against VM undervoltage, charge-pump undervoltage, overcurrent,
gate-driver shorts, and overtemperature events.
7.3.14.1 VM Undervoltage Lockout (UVLO2)
If the voltage on the VM pin falls below the VM undervoltage lockout threshold voltage (VUVLO2), both FETs in the
half-bridge are disabled, the charge pump is disabled, and the nFAULT pin is driven low. The VM_UVFL bit of
the DRV8703D-Q1 device is set. The operation resumes when the VM voltage rises above the UVLO2 threshold.
The nFAULT pin is released after the operation resumes but the VM_UVFL bit on the DRV8703D-Q1 device
remains set until cleared by writing to the CLR_FLT bit.
The SPI settings on the DRV8703D-Q1 device are not reset by this fault even though the output drivers are
disabled. The settings are maintained and internal logic remains active until the VM voltage falls below the logic
undervoltage threshold (VUVLO1).
7.3.14.2 Logic Undervoltage (UVLO1)
If the voltage on the VM pin falls below the logic undervoltage threshold voltage (VUVLO1), the internal logic is
reset. The operation resumes when the VM voltage rises above the UVLO1 threshold. The nFAULT pin is logic
low during this state because it is pulled low when the VM undervoltage condition occurs. Decreasing the VM
voltage below this undervoltage threshold resets the SPI settings.
7.3.14.3 VCP Undervoltage Lockout (CPUV)
If the voltage on the VCP pin falls below the threshold voltage of the charge-pump undervoltage (CPUV) lockout,
both FETs in the half-bridge are disabled and the nFAULT pin is driven low. The DRV8703D-Q1 the VCP_UVFL
bit is set. The operation resumes when the VCP voltage rises above the CPUV threshold. The nFAULT pin is
released after the operation resumes but the VCP_UVFL bit on the DRV8703D-Q1 device remains set until
cleared by writing to the CLR_FLT bit.
7.3.14.4 Overcurrent Protection (OCP)
Overcurrent is sensed by monitoring the VDS voltage drop across the external FETs. If the voltage across a
driven FET exceeds the VDS(OCP) level for longer than the OCP deglitch time, an OCP event is recognized. Both
FETs in the half-bridge are disabled, and the nFAULT pin is driven low. The OCP bit of the DRV8703D-Q1
device is set. The drive re-enables after the t(RETRY) time has passed. The nFAULT pin becomes high again after
the retry time.
If the fault condition is still present, the cycle repeats. If the fault is no longer present, normal operation resumes
and the nFAULT pin goes high. The OCP bit on the DRV8703D-Q1 remains set until cleared by writing to the
CLR_FLT bit. In addition to this FET VDS monitor, an overcurrent condition is detected if the voltage at the SP
pin exceeds VSP(OCP) and the nFAULT pin is driven low. The OCP bit in the DRV8703-Q1 device is set.
7.3.14.5 Gate Driver Fault (GDF)
The GH and GL pins are monitored such that if the voltage on the external FET gate does not increase or
decrease after the t(DRIVE) time, a gate driver fault is detected. This fault occurs if the GH or GL pins are shorted
to the GND, SH, or VM pin. Additionally, a gate-driver fault occurs if the selected IDRIVE setting is not sufficient
to turn on the external FET. Both FETs in the half-bridge are disabled, and the nFAULT pin is driven low. The
GDF bit of the DRV8703D-Q1 device is set. The driver re-enables after the OCP retry period (t(RETRY)) has
passed. The nFAULT pin is released after the operation has resumed but the GDF bit on the DRV8703D-Q1
device remains set until cleared by writing to the CLR_FLT bit.
7.3.14.6 Thermal Shutdown (TSD)
If the die temperature exceeds the TSD temperature, both FETs in the half-bridge are disabled, the charge pump
shuts down, the AVDD regulator is disabled, and the nFAULT pin is driven low. The OTSD bit of the DRV8703DQ1 device is set as well. After the die temperature falls below TSD – Thys temperature, device operation
automatically resumes. The nFAULT pin is released after the operation resumes, but the OTSD bit on the
DRV8703D-Q1 device remains set until cleared by writing to the CLR_FLT bit.
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8702D-Q1 DRV8703D-Q1
Submit Documentation Feedback
35
DRV8702D-Q1, DRV8703D-Q1
SLVSDX8 – MARCH 2017
www.ti.com
7.3.14.7 Watchdog Fault (WDFLT, DRV8703D-Q1 Only)
An MCU watchdog function can be enabled to ensure that the external controller that is instructing the
DRV8703D-Q1 device is active and in a known state. The SPI watchdog must be enabled by writing a 1 to the
WD_EN bit through the SPI (disabled by default, bit is 0). When the watchdog is enabled, an internal timer starts
to count down to an interval set by the WD_DLY bits. The register address 0x00 must be read by the MCU within
the interval set by the WD_DLY bit to reset the watchdog. If the timer is allowed to expire, the nWDFLT pin is
enabled. When the nWDFLT pin is enabled the following occurs:
• The nWDFLT pin goes low for 64 µs.
• The nFAULT pin is asserted.
• The WD_EN bit is cleared.
• The drivers are disabled.
The WDFLT bit remains asserted, and operation is halted until the CLR_FLT bit has been written to 1.
Table 8 lists the fault responses of the device under the fault conditions.
Table 8. Fault Response
36
FAULT
CONDITION
VM undervoltage
(UVLO)
VVM ≤ V(UVLOx)
(5.45 V, max)
DVDD
RECOVERY
Disabled
Operating
VVM ≥ V(UVLOx)
(5.65 V, max)
Disabled
Disabled
VCP undervoltage
(CPUV)
VVCP ≤ V(CP_UV)
(VVM + 1.5, typ)
Disabled
Operating
Operating
Operating
VVCP ≥ V(CP_UV)
(VVM + 1.5, typ)
External FET overload
(OCP)
VDS ≥ VDS(OCP)
VSP – VSN > 1 V
Disabled
Operating
Operating
Operating
t(RETRY)
Gate driver fault
(GDF)
Gate voltage unchanged after
t(DRIVE)
Disabled
Operating
Operating
Operating
t(RETRY)
Watchdog fault
(WDFLT)
Watchdog timer expires
Disabled
Operating
Operating
Operating
CLR_FLT bit
Thermal shutdown
(TSD)
TJ ≥ TSD (150°C, min)
Disabled
Disabled
Disabled
Operating
TJ ≤ TSD – Thys
(Thys is typically 20°C)
Submit Documentation Feedback
HALF-BRIDGE
CHARGE PUMP
AVDD
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8702D-Q1 DRV8703D-Q1
DRV8702D-Q1, DRV8703D-Q1
www.ti.com
SLVSDX8 – MARCH 2017
7.3.14.8 Reverse Supply Protection
The circuit in Figure 45 can be implemented to help protect the system from reverse supply conditions. This
circuit requires the following additional components:
• NMOS FET
• NPN BJT
• Diode
• 10-kΩ resistor
• 43-kΩ resistor
VM
43 kŸ
10 kŸ
0.1 µF
1 µF
Bulk
10 µF (min)
0.1 µF
CP1
CP2
VCP
VM
+
GH
SH
GL
M
SP
R(SENSE)
SN
Figure 45. Reverse Supply Protection
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8702D-Q1 DRV8703D-Q1
Submit Documentation Feedback
37
DRV8702D-Q1, DRV8703D-Q1
SLVSDX8 – MARCH 2017
www.ti.com
7.3.15 Hardware Interface
The DRV8702D-Q1 hardware interface allows the device to be configured without a SPI, however not all of the
functionality is configurable like the DRV8703D-Q1 device. The following configuration settings are fixed for the
hardware-interface device option:
• The toff value is set to 25 µs.
• Current regulation is enabled
• The VREF pin voltage is not scaled internally (100%).
• The shunt amplifier has a fixed gain of 19.8 V/V.
7.3.15.1 IDRIVE (6-level input)
The voltage or resistance on the IDRIVE pin sets the peak source and peak sink IDRIVE setting as listed in
Table 9.
Table 9. DRV8702D-Q1 IDRIVE Settings
IDRIVE
RESISTANCE
IDRIVE VOLTAGE
SOURCE CURRENT
SINK CURRENT
VVM = 5.5 V
VVM = 13.5 V
VVM = 5.5 V
VVM = 13.5 V
High-side: 10 mA
Low-side: 10 mA
High-side: 20 mA
Low-side: 20 mA
High-side: 20 mA
Low-side: 20 mA
< 1 kΩ to GND
GND
High-side: 10 mA
Low-side: 10 mA
33 kΩ ± 5% to
GND
0.7 V ± 5%
High-side: 20 mA
Low-side: 20 mA
High-side: 20 mA
Low-side: 20 mA
High-side: 40 mA
Low-side: 40 mA
High-side: 40 mA
Low-side: 40 mA
200 kΩ ± 5% to
GND
2 V ± 5%
High-side: 50 mA
Low-side: 40 mA
High-side: 50 mA
Low-side: 45 mA
High-side: 90 mA
Low-side: 85 mA
High-side: 95 mA
Low-side: 95 mA
> 2 MΩ to GND,
Hi-Z
3 V ± 5%
High-side: 145 mA
Low-side: 115 mA
High-side: 155 mA
Low-side: 130 mA
High-side: 250 mA
Low-side: 235 mA
High-side: 265 mA
Low-side: 260 mA
68 kΩ ± 5% to
AVDD
4 V ± 5%
High-side: 190 mA
Low-side: 145 mA
High-side: 210 mA
Low-side: 180 mA
High-side: 330 mA
Low-side: 300 mA
High-side: 350 mA
Low-side: 350 mA
< 1 kΩ to AVDD
AVDD
High-side: 240 mA
Low-side: 190 mA
High-side: 260 mA
Low-side: 225 mA
High-side: 420 mA
Low-side: 360 mA
High-side: 440 mA
Low-side:430 mA
7.3.15.2 VDS (6-Level Input)
This input controls the VDS monitor trip voltage as listed in Table 10.
Table 10. DRV8702D-Q1 VDS Settings
VDS RESISTANCE
38
VDS VOLTAGE
OVERCURRENT TRIP LEVEL
(VDS(OCP))
< 1 kΩ to GND
GND
0.06 V
33 kΩ ± 5% to GND
0.7 V ± 5%
0.12 V
200 kΩ ± 5% to GND
2 V ± 5%
0.24 V
0.48 V
> 2 MΩ to GND, Hi-Z
3 V ± 5%
68 kΩ ± 5% to AVDD
4 V ± 5%
0.96 V
< 1 kΩ to AVDD
AVDD
Disabled
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8702D-Q1 DRV8703D-Q1
DRV8702D-Q1, DRV8703D-Q1
www.ti.com
SLVSDX8 – MARCH 2017
7.4 Device Functional Modes
The DRV870xD-Q1 device is active unless the nSLEEP pin is brought low. In sleep mode, the charge pump is
disabled, the half-bridge FETs are disabled to the Hi-Z state, and the AVDD and DVDD regulators are disabled.
NOTE
The t(SLEEP) time must elapse after a falling edge on the nSLEEP pin before the device is
in sleep mode. The DRV870xD-Q1 device is brought out of sleep mode automatically if
the nSLEEP pin is brought high.
The t(WAKE) time must elapse before the outputs change state after wakeup.
On the DRV8703D-Q1 device, the SPI settings are reset when coming out of UVLO or exiting sleep mode.
While the nSLEEP pin is brought low, both external half-bridge FETs are disabled. The high-side gate pin, GH,
are pulled to the output node, SH, by an internal resistor and the low-side gate pin, GL, are pulled to ground.
When the VM voltage is not applied and during the power-on time (ton) the outputs are disabled using weak
pulldown resistors between the GH and SH pins and the GL and GND pins.
NOTE
The MODE pin controls the device-logic operation for phase and enable, independent halfbridge, or PWM input modes. This operation is latched on power up or when exiting sleep
mode.
7.5 Programming
7.5.1 SPI Communication
7.5.1.1 Serial Peripheral Interface (SPI)
The SPI (DRV8703D-Q1 only) is used to set device configurations, operating parameters, and read out
diagnostic information. The DRV8703D-Q1 SPI operates in slave mode. The SPI input data (SDI) word consists
of a 16-bit word, with a 5-bit command, 3 don't care bits, and 8 bits of data. The SPI output data (SDO) word
consists of 8-bit register data and the first 8 bits are don’t cares.
A
•
•
•
•
•
•
•
•
•
•
•
•
valid frame has to meet following conditions:
The clock polarity (CPOL) must be set to 0.
The clock phase (CPHA) must be set to 0.
The SCLK pin must be low when the nSCS pin goes low and when the nSCS pin goes high.
No SCLK signal can occur when the nSCS signal is in transition.
The SCLK pin must be low when the nSCS pin goes high.
The nSCS pin should be taken high for at least 500 ns between frames.
When the nSCS pin is asserted high, any signals at the SCLK and SDI pins are ignored, and the SDO pin is
in the high impedance state.
Full 16 SCLK cycles must occur.
Data is captured on the falling edge of the clock and data is driven on the rising edge of the clock.
The most-significant bit (MSB) is shifted in and out first
For a write command, if the data word sent to the SDI pin is less than or more than 16 bits, a frame error
occurs and the data word is ignored.
For a write command, the existing data in the register being written to is shifted out on the SDO pin following
the 5-bit command data
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8702D-Q1 DRV8703D-Q1
Submit Documentation Feedback
39
DRV8702D-Q1, DRV8703D-Q1
SLVSDX8 – MARCH 2017
www.ti.com
Programming (continued)
7.5.1.2 SPI Format
The SDI input-data word is 16 bits long and consists of the following format:
• 1 read or write bit, W (bit 15)
• 4 address bits, A (bits 14 through 11)
• 3 don't care bits, X (10 through 8)
• 8 data bits, D (7:0)
The SDO output-data word is 16 bits long and the first 8 bits are don’t care bits. The data word is the content of
the register being accessed.
For a write command (W0 = 0), the response word on the SDO pin is the data currently in the register being
written to.
For a read command (W0 = 1), the response word is the data currently in the register being read.
Table 11. SDI Input Data Word Format
R/W
ADDRESS
DON'T CARE
DATA
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
W0
A3
A2
A1
A0
X
X
X
D7
D6
D5
D4
D3
D2
D1
D0
Table 12. SDO Output Data Word Format
DON'T CARE
DATA
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
X
X
X
X
X
X
X
X
D7
D6
D5
D4
D3
D2
D1
D0
nSCS
SCLK
SDI
X
MSB
LSB
X
SDO
Z
MSB
LSB
Z
Capture
Point
Propagate
Point
Figure 46. SPI Transaction
The SCLK pin should be low at power-up of the device for reliable SPI transaction. If the SCLK pin cannot be
guaranteed to be low at power-up, TI recommends performing a dummy SPI-read transaction (of any register)
after power-up to ensure reliable subsequent transactions. Data read from this dummy read transaction should
be discarded.
40
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8702D-Q1 DRV8703D-Q1
DRV8702D-Q1, DRV8703D-Q1
www.ti.com
SLVSDX8 – MARCH 2017
7.6 Register Maps
DRV8703D-Q1 Memory Map
Register
Name
7
FAULT Status
FAULT
6
4
3
GDF
OCP
VM_UVFL
H_GDF
L_GDF
WDFLT
VDS and GDF
RESERVED
Main
RESERVED
IDRIVE and WD
TDEAD
VDS
5
WD_EN
VCP_UVFL
WD_DLY
Access
Type
Address
(Hex)
OTSD
OTW
R
0
L_VDS
R
1
IN2
CLR_FLT
RW
2
RW
3
RW
4
RW
5
IDRIVE
RESERVED
CHOP_IDS
0
H_VDS
IN1
VDS
TOFF
1
RESERVED
LOCK
SO_LIM
Config
2
VREF_SCL
DIS_H_VDS
SH_EN
DIS_L_VDS
GAIN_CS
Table 13. Access Type Codes
Access Type
Code
Description
R
Read
W
Write
Read Type
R
Write Type
W
7.6.1 Status Registers
The status registers are used to report warning and fault conditions. Status registers are read only registers.
Table 14 lists the memory-mapped registers for the status registers. All register offset addresses not listed in
Table 14 should be considered as reserved locations and the register contents should not be modified.
Table 14. Status Registers Summary Table
Address
Register Name
Section
0x00h
FAULT status
Go
0x01h
VDS and GDF status
Go
7.6.1.1 FAULT Status Register (address = 0x00h)
FAULT status is shown in Figure 47 and described in Table 15.
Return to Summary Table.
Read only
Figure 47. FAULT Status Register
7
FAULT
R-0b
6
WDFLT
R-0b
5
GDF
R-0b
4
OCP
R-0b
3
VM_UVFL
R-0b
2
VCP_UVFL
R-0b
1
OTSD
R-0b
0
OTW
R-0b
Table 15. FAULT Status Field Descriptions
Bit
Field
Type
Default
Description
7
FAULT
R
0b
Logic OR of the FAULT status register excluding the OTW bit
6
WDFLT
R
0b
Watchdog time-out fault
5
GDF
R
0b
Indicates gate drive fault condition
4
OCP
R
0b
Indicates VDS monitor overcurrent fault condition
3
VM_UVFL
R
0b
Indicates VM undervoltage lockout fault condition
2
VCP_UVFL
R
0b
Indicates charge-pump undervoltage fault condition
1
OTSD
R
0b
Indicates overtemperature shutdown
0
OTW
R
0b
Indicates overtemperature warning
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8702D-Q1 DRV8703D-Q1
Submit Documentation Feedback
41
DRV8702D-Q1, DRV8703D-Q1
SLVSDX8 – MARCH 2017
www.ti.com
7.6.1.2 VDS and GDF Status Register Name (address = 0x01h)
VDS and GDF status is shown in Figure 48 and described in Table 16.
Return to Summary Table.
Read only
Figure 48. VDS and GDF Status Register
7
6
5
H_GDF
R-0b
RESERVED
R-00b
4
L_GDF
R-0b
3
2
RESERVED
R-00b
1
H_VDS
R-0b
0
L_VDS
R-0b
Table 16. VDS and GDF Status Field Descriptions
Bit
Field
Type
Default
Description
7-6
RESERVED
R
00b
Reserved
5
H_GDF
R
0b
Indicates gate drive fault on the high-side FET of half-bridge
4
L_GDF
R
0b
Indicates gate drive fault on the low-side FET of half-bridge
RESERVED
R
00b
Reserved
1
H_VDS
R
0b
Indicates VDS monitor overcurrent fault on the high-side FET of
half-bridge
0
L_VDS
R
0b
Indicates VDS monitor overcurrent fault on the low-side FET of
half-bridge
3-2
7.6.2 Control Registers
The control registers are used to configure the device. Control registers are read and write capable.
Table 17 lists the memory-mapped registers for the status registers. All register offset addresses not listed in
Table 17 should be considered as reserved locations and the register contents should not be modified.
Table 17. Status Registers Summary Table
Address
42
Register Name
Section
0x02h
Main control
Go
0x03h
IDRIVE and WD control
Go
0x04h
VDS control
Go
0x05h
Config control
Go
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8702D-Q1 DRV8703D-Q1
DRV8702D-Q1, DRV8703D-Q1
www.ti.com
SLVSDX8 – MARCH 2017
7.6.2.1 Main Control Register Name (address = 0x02h)
Main control is shown in Figure 49 and described in Table 18.
Return to Summary Table.
Read and write
Figure 49. Main Control Register
7
6
5
4
LOCK
R/W-011b
RESERVED
R/W-00b
3
2
IN1
R/W-0b
1
IN2
R/W-0b
0
CLR_FLT
R/W-0b
Table 18. Main Control Field Descriptions
Bit
Field
Type
Default
Description
7-6
RESERVED
R/W
00b
Reserved
5-3
LOCK
R/W
011b
Write 110b to lock the settings by ignoring further register
changes except to address 0x02h. Writing any sequence other
than 110b has no effect when unlocked.
Write 011b to this register to unlock all registers. Writing any
sequence other than 011b has no effect when locked.
2
IN1
R/W
0b
This bit is ORed with the IN1 pin
1
IN2
R/W
0b
This bit is ORed with the IN2 pin
0
CLR_FLT
R/W
0b
Write a 1 to this bit to clear the fault bits
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8702D-Q1 DRV8703D-Q1
Submit Documentation Feedback
43
DRV8702D-Q1, DRV8703D-Q1
SLVSDX8 – MARCH 2017
www.ti.com
7.6.2.2 IDRIVE and WD Control Register Name (address = 0x03h)
IDRIVE and WD control is shown in Figure 50 and described in Table 19.
Return to Summary Table.
Read and write
Figure 50. IDRIVE and WD Register
7
6
5
WD_EN
R/W-0b
TDEAD
R/W-00b
4
3
2
1
IDRIVE
R/W-111b
WD_DLY
R/W-00b
0
Table 19. IDRIVE and WD Field Descriptions
Bit
Field
Type
Default
Description
7-6
TDEAD
R/W
00b
Dead time
00b = 120 ns
01b = 240 ns
10b = 480 ns
11b = 960 ns
5
WD_EN
R/W
0b
Time-out of the watchdog timer
4-3
WD_DLY
R/W
00b
Enables or disables the watchdog timer (disabled by default)
00b = 10 ms
01b = 20 ms
10b = 50 ms
11b = 100 ms
2-0
IDRIVE
R/W
111b
Sets the peak source current and peak sink current of the gate
drive. Table 20 lists the bit settings.
Table 20. IDRIVE Bit Settings
Bit Value
44
Source Current
Sink Current
VVM = 5.5 V
VVM = 13.5 V
VVM = 5.5 V
VVM = 13.5 V
000b
High-side: 10 mA
Low-side: 10 mA
High-side: 10 mA
Low-side: 10 mA
High-side: 20 mA
Low-side: 20 mA
High-side: 20 mA
Low-side: 20 mA
001b
High-side: 20 mA
Low-side: 20 mA
High-side: 20 mA
Low-side: 20 mA
High-side: 40 mA
Low-side: 40 mA
High-side: 40 mA
Low-side: 40 mA
010b
High-side: 50 mA
Low-side: 40 mA
High-side: 50 mA
Low-side: 45 mA
High-side: 90 mA
Low-side: 85 mA
High-side: 95 mA
Low-side: 95 mA
011b
High-side: 70 mA
Low-side: 55 mA
High-side: 70 mA
Low-side: 60 mA
High-side: 120 mA
Low-side: 115 mA
High-side: 130 mA
Low-side: 125 mA
100b
High-side: 100 mA
Low-side: 75 mA
High-side: 105 mA
Low-side: 90 mA
High-side: 170 mA
Low-side: 160 mA
High-side: 185 mA
Low-side: 180 mA
101b
High-side: 145 mA
Low-side: 115 mA
High-side: 155 mA
Low-side: 130 mA
High-side: 250 mA
Low-side: 235 mA
High-side: 265 mA
Low-side: 260 mA
110b
High-side: 190 mA
Low-side: 145 mA
High-side: 210 mA
Low-side: 180 mA
High-side: 330 mA
Low-side: 300 mA
High-side: 350 mA
Low-side: 350 mA
111b
High-side: 240 mA
Low-side: 190 mA
High-side: 260 mA
Low-side: 225 mA
High-side: 420 mA
Low-side: 360 mA
High-side: 440 mA
Low-side: 430 mA
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8702D-Q1 DRV8703D-Q1
DRV8702D-Q1, DRV8703D-Q1
www.ti.com
SLVSDX8 – MARCH 2017
7.6.2.3 VDS Control Register Name (address = 0x04h)
VDS control is shown in Figure 51 and described in Table 21.
Return to Summary Table.
Read and write
Figure 51. VDS Control Register
7
SO_LIM
R/W-0b
6
5
VDS
R/W-111b
4
3
2
RESERVED
R-00b
1
DIS_H_VDS
R/W-0b
0
DIS_L_VDS
R/W-0b
Table 21. VDS Control Field Descriptions
Bit
7
Field
Type
Default
Description
SO_LIM
R/W
0b
0b = Default operation
VDS
R/W
111b
1b = SO output is voltage-limited to 3.6 V
6-4
Sets the VDS(OCP) monitor for each FET
000b = 0.06 V
001b = 0.145 V
010b = 0.17 V
011b = 0.2 V
100b = 0.12 V
101b = 0.24 V
110b = 0.48 V
111b = 0.96 V
3-2
RESERVED
R
00b
Reserved
1
DIS_H_VDS
R/W
0b
Disables the VDS monitor on the high-side FET of half-bridge
(enabled by default)
0
DIS_L_VDS
R/W
0b
Disables the VDS monitor on the low-side FET of half-bridge
(enabled by default)
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8702D-Q1 DRV8703D-Q1
Submit Documentation Feedback
45
DRV8702D-Q1, DRV8703D-Q1
SLVSDX8 – MARCH 2017
www.ti.com
7.6.2.4 Config Control Register Name (address = 0x05h)
Config control is shown in Figure 52 and described in Table 22.
Return to Summary Table.
Read and write
Figure 52. Config Control Register
7
6
TOFF
R/W-00b
5
CHOP_IDS
R/W-0b
4
3
VREF_SCL
R/W-00b
2
SH_EN
R/W-0b
1
0
GAIN_CS
R/W-01b
Table 22. Config Control Field Descriptions
Bit
Field
Type
Default
Description
7-6
TOFF
R/W
00b
Off time for PWM current chopping
00b = 25 µs
01b = 50 µs
10b = 100 µs
11b = 200 µs
5
CHOP_IDS
R/W
0b
Disables current regulation (enabled by default)
4-3
VREF_SCL
R/W
00b
Scale factor for the VREF input
00b = 100%
01b = 75%
10b = 50%
11b = 25%
2
1-0
SH_EN
R/W
0b
Enables sample and hold operation of the shunt amplifier
(disabled by default)
GAIN_CS
R/W
01b
Shunt amplifier gain setting
00b = 10 V/V
01b = 19.8 V/V
10b = 39.4 V/V
11b = 78 V/V
46
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8702D-Q1 DRV8703D-Q1
DRV8702D-Q1, DRV8703D-Q1
www.ti.com
SLVSDX8 – MARCH 2017
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The DRV870xD-Q1 device is used in brushed-DC, solenoid, or relay-control applications. The following typical
application can be used to configure the DRV870xD-Q1 device.
8.2 Typical Application
This application features the DRV8702D-Q1 device.
VM
+
0.1 µF
0.1 µF
VM
Bulk
1 µF
26
GND
25
RSVD
27
28
VM
29
VCP
31
30
CPH
VDRAIN
GL
SH
GND
GH
23
22
21
BDC
10 mŸ
20
19
18
17
VM
SO
VREF
R1
GND
Bulk
24
+
16
10
9
15
nSLEEP
AVDD
VDS
GND
8
IDRIVE
14
7
SP
GND
(PAD)
GND
0Ÿ
GND
13
6
200 kŸ
SN
DVDD
5
IN2
MODE
4
SP
12
3
RSVD
IN1
11
2
GND
nFAULT
1
CPL
NC
32
+
VM
Bulk
R2
10 kŸ
1 µF
1 µF
Copyright © 2017, Texas Instruments Incorporated
Figure 53. DRV8702D-Q1 Typical Application Schematic
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8702D-Q1 DRV8703D-Q1
Submit Documentation Feedback
47
DRV8702D-Q1, DRV8703D-Q1
SLVSDX8 – MARCH 2017
www.ti.com
Typical Application (continued)
8.2.1 Design Requirements
For this design example, use the parameters listed in Table 23 as the input parameters.
Table 23. Design Parameters
DESIGN PARAMETER
REFERENCE
Nominal supply voltage
EXAMPLE VALUE
14 V
VM
Supply voltage range
7 V to 35 V
FET part number
CSD18502Q5B
FET total gate charge
Qg
52 nC (typical)
FET gate-to-drain charge
Qgd
8.4 nC (typical)
tr
100 to 300 ns
I(CHOP)
15 A
Target FET gate rise time
Motor current chopping level
8.2.2 Detailed Design Procedure
8.2.2.1 External FET Selection
The DRV8702D-Q1 FET support is based on the charge-pump capacity and PWM-output frequency. For a quick
calculation of FET driving capacity, use Equation 3 when drive and brake (slow decay) are the primary modes of
operation.
IVCP
Qg
f(PWM)
where
•
•
fPWM is the maximum desired PWM frequency to be applied to the DRV8702D-Q1 inputs or the current
chopping frequency, whichever is larger.
IVCP is the charge-pump capacity, which depends on the VM voltage.
The internal current chopping frequency is at most equal to the PWM frequency as shown in Equation 4.
1
f(PWM)
t off t(BLANK)
(3)
(4)
For example, if the VM voltage of a system is 7 V (IVCP = 8 mA) and uses a maximum PWM frequency of 40 kHz,
then the DRV8702D-Q1 device will support FETs with a Qg up to 200 nC.
If the application requires a forced fast decay (or alternating between drive and reverse drive), use Equation 5 to
calculate the maximum FET driving capacity.
IVCP
Qg
2 u f(PWM)
(5)
8.2.2.2 IDRIVE Configuration
The IDRIVE current is selected based on the gate charge of the FETs. The IDRIVE pin must be configured so
that the FET gates are charged entirely during the t(DRIVE) time. If the selected IDRIVE current is too low for a
given FET, then the FET may not turn on completely. TI recommends adjusting these values in-system with the
required external FETs and motor to determine the best possible setting for any application.
For FETs with a known gate-to-drain charge (Qgd) and desired rise time (tr), the IDRIVE current can be selected
based on the Equation 6.
Qgd
IDRIVE !
tr
(6)
48
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8702D-Q1 DRV8703D-Q1
DRV8702D-Q1, DRV8703D-Q1
www.ti.com
SLVSDX8 – MARCH 2017
If the gate-to-drain charge is 2.3 nC and the desired rise time is around 100 to 300 ns, use Equation 7 to
calculate the minimum IDRIVE (IDRIVE1) and Equation 8 to calculate the maximum IDRIVE (IDRIVE2).
IDRIVE1 = 8.4 nC / 100 ns = 84 mA
IDRIVE2 = 8.4 nC / 300 ns = 28 mA
(7)
(8)
Select a value for IDRIVE between 28 and 84 mA. An IDRIVE value of approximately 50 mA for the source
(approximately 100 mA sink) was selected for this application. This value requires a 200-kΩ resistor from the
IDRIVE pin to ground.
8.2.2.3 VDS Configuration
The VDS monitor is configured based on the maximum current and RDS(on) of the FETs. The VDS pin of the
DRV8702D-Q1 selects the VDS monitor trip threshold. Use Equation 3 to calculate the trip current.
V
IVDS ! VDS
RDS(on)
(9)
If the RDS(on) of the FET is 1.8 mΩ and the desired VDS trip is less than 100 A, the VVDS voltage is equal to 180
mV as shown in Equation 10.
VVDS = IVDS × RDS(on) = 100 A × 1.8 mΩ = 180 mV
(10)
Select a value for the VDS voltage that less than 180 mV. A VVDS value of 0.12 V was selected for ths
application. This value requires tying the VDS pin to ground.
8.2.2.4 Current Chopping Configuration
The chopping current is set based on the sense resistor value and the analog voltage at the VREF pin. Use
Equation 11 to calculate the current (I(CHOP)). The amplifier gain, AV, is 19.8 V/V for the DRV8702D-Q1 and VIO is
typically 2.5 mV (input referred).
VVREF VIO
I(CHOP)
A V u R(SENSE)
(11)
For example, if the desired chopping current is 15 A, select a value of 10 mΩ for R(SENSE). The value of VVREF
must therefore be 3.05 V. Add a a resistor divider from the AVDD (5 V) pin to set the VVREF at approximately 3.05
V. Select a value of 13 kΩ for and 20 kΩ for R1.
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8702D-Q1 DRV8703D-Q1
Submit Documentation Feedback
49
DRV8702D-Q1, DRV8703D-Q1
SLVSDX8 – MARCH 2017
www.ti.com
8.2.3 Application Curves
SH
SH
IN2
IN2
10-mA source
20-mA sink
10-mA source
Figure 54. SH Fall Time
SH
20-mA sink
Figure 55. SH Rise Time
SH
ILOAD
ILOAD
IN2
IN2
Figure 56. Current Profile on Motor Startup With
Regulation
Figure 57. Current Profile on Motor Startup Without
Regulation
SH
ILOAD
IN2
Figure 58. Current Regulating at 2.25 A on Motor Startup
50
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8702D-Q1 DRV8703D-Q1
DRV8702D-Q1, DRV8703D-Q1
www.ti.com
SLVSDX8 – MARCH 2017
9 Power Supply Recommendations
The DRV8702D-Q1 device is designed to operate with an input voltage supply (VM) rangefrom 5.5 V to 45 V. A
0.1-µF ceramic capacitor rated for VM must be placed as close to the DRV8702D-Q1 device as possible. Also, a
bulk capacitor valued at least 10 µF must be placed on the VM pin.
Additional bulk capacitance is required to bypass the external half-bridge FETs.
9.1 Bulk Capacitance Sizing
Bulk capacitance sizing is an important factor in motor drive system design. It is beneficial to have more bulk
capacitance, while the disadvantages are increased cost and physical size.
The amount of local capacitance needed depends on a variety of factors including:
• The highest current required by the motor system.
• The capacitance of the power supply and the ability of the power supply to source current.
• The amount of parasitic inductance between the power supply and motor system.
• The acceptable voltage ripple.
• The type of motor used (brushed DC, brushless DC, and stepper).
• The motor braking method.
The inductance between the power supply and motor drive system limits the rate that current can change from
the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands
or dumps from the motor with a change in voltage. When sufficient bulk capacitance is used, the motor voltage
remains stable, and high current can be quickly supplied.
The data sheet provides a recommended value, but system-level testing is required to determine the appropriate
sized bulk capacitor.
Parasitic Wire
Inductance
Power Supply
Motor Drive System
VM
+
+
±
Motor
Driver
GND
Local
Bulk Capacitor
IC Bypass
Capacitor
Copyright © 2016, Texas Instruments Incorporated
Figure 59. Example Setup of Motor Drive System With External Power Supply
The voltage rating for bulk capacitors should be higher than the operating voltage to provide a margin for cases
when the motor transfers energy to the supply.
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8702D-Q1 DRV8703D-Q1
Submit Documentation Feedback
51
DRV8702D-Q1, DRV8703D-Q1
SLVSDX8 – MARCH 2017
www.ti.com
10 Layout
10.1 Layout Guidelines
The VM pin should be bypassed to ground using a low-ESR ceramic bypass capacitor with a recommended
value of 0.1 µF rated for VM. This capacitor should be placed as close to the VM pin as possible with a thick
trace or ground-plane connection to the GND pin of the device. The VM pin must also be bypassed to ground
using a bulk capacitor rated for VM. This capacitor can be electrolytic and must be at least 10 µF.
A low-ESR ceramic capacitor must be placed between the CPL and CPH pins. A value of 0.1 µF rated for VM is
recommended. Place this capacitor as close to the pins as possible. A low-ESR ceramic capacitor must be
placed in between the VM and VCP pins. A value of 1 µF rated for 16 V is recommended. Place this component
as close to the pins as possible.
Bypass the AVDD and DVDD pins to ground with ceramic capacitors rated for 6.3 V. Place these bypassing
capacitors as close to the pins as possible.
Use separate traces to connect the SP and SN pins to the R(SENSE) resistor.
10.2 Layout Example
RSENSE
VM
0.1 µF
1 µF
0.1 µF
GND 25
GL
19
SH
GND 7
18
GH
nSLEEP 8
17
GND
(PPAD)
VDS 6
16
AVDD
VREF
SO
GND
15
13
MODE
DVDD
14
12
GND
nFAULT
11
9
10
1 µF
D
G
D
Bulk
SH1
1 µF
D
20
IDRIVE 5
S
S
SP
D
SN
21
GND 4
S
SP
22
GND
D
D
23
IN1 2
IN2 3
S
S
RSVD
D
24
D
G
RSVD 26
PVDD 28
VDRAIN 27
VCP 29
CPH 30
NC 32
CPL 31
GND 1
S
Figure 60. DRV8702D-Q1 Layout Example
52
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8702D-Q1 DRV8703D-Q1
DRV8702D-Q1, DRV8703D-Q1
www.ti.com
SLVSDX8 – MARCH 2017
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• Driving a Unidirectional Brushed DC Motor With Smart Gate Drive
• DRV8702-Q1 EVM User’s Guide
• DRV8703-Q1 EVM User’s Guide
• Small Footprint Motor Driver Sunroof Module Design Guide
11.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 24. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
DRV8702D-Q1
Click here
Click here
Click here
Click here
Click here
DRV8703D-Q1
Click here
Click here
Click here
Click here
Click here
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8702D-Q1 DRV8703D-Q1
Submit Documentation Feedback
53
DRV8702D-Q1, DRV8703D-Q1
SLVSDX8 – MARCH 2017
www.ti.com
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
54
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8702D-Q1 DRV8703D-Q1
DRV8702D-Q1, DRV8703D-Q1
www.ti.com
SLVSDX8 – MARCH 2017
PACKAGE OUTLINE
RHB0032N
VQFN - 0.9 mm max height
SCALE 3.000
PLASTIC QUAD FLATPACK - NO LEAD
5.1
4.9
A
B
PIN 1 INDEX AREA
5.1
4.9
0.08
0.05
SECTION A-A
A-A 30.000
TYPICAL
C
0.9 MAX
SEATING PLANE
0.05
0.00
0.08 C
2X 3.5
(0.2) TYP
3.45 0.1
9
EXPOSED
THERMAL PAD
16
28X 0.5
8
17
2X
3.5
A
33
A
SYMM
32X
24
1
32
PIN 1 ID
(OPTIONAL)
0.3
0.2
0.1
0.05
C A B
C
25
SYMM
0.5
32X
0.3
4222893/A 04/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8702D-Q1 DRV8703D-Q1
Submit Documentation Feedback
55
DRV8702D-Q1, DRV8703D-Q1
SLVSDX8 – MARCH 2017
www.ti.com
EXAMPLE BOARD LAYOUT
RHB0032N
VQFN - 0.9 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
( 3.45)
SYMM
32
25
32X (0.6)
1
24
32X (0.25)
(1.475)
28X (0.5)
33
SYMM
(4.8)
( 0.2) TYP
VIA
8
17
(R0.05)
TYP
9
(1.475)
16
(4.8)
LAND PATTERN EXAMPLE
SCALE:18X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222893/A 04/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
56
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8702D-Q1 DRV8703D-Q1
DRV8702D-Q1, DRV8703D-Q1
www.ti.com
SLVSDX8 – MARCH 2017
EXAMPLE STENCIL DESIGN
RHB0032N
VQFN - 0.9 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X ( 1.49)
(0.845)
(R0.05) TYP
32
25
32X (0.6)
1
24
32X (0.25)
28X (0.5)
(0.845)
SYMM
33
(4.8)
17
8
METAL
TYP
16
9
SYMM
(4.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 33:
75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4222893/A 04/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8702D-Q1 DRV8703D-Q1
Submit Documentation Feedback
57
DRV8702D-Q1, DRV8703D-Q1
SLVSDX8 – MARCH 2017
www.ti.com
12.1 Package Option Addendum
12.1.1 Packaging Information
Orderable Device
(1)
(2)
(3)
(4)
(5)
(6)
Status
(1)
Package
Type
Package
Drawing
Pins
Package
Qty
Eco Plan
(2)
Lead/Ball
Finish (3)
MSL Peak Temp
(4)
Op Temp (°C)
DRV8702DQRHBRQ1
PREVIEW
VQFN
RHB
32
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168
HR
-40 to 125
DRV8702DQRHBTQ1
PREVIEW
VQFN
RHB
32
250
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168
HR
-40 to 125
DRV8703DQRHBRQ1
PREVIEW
VQFN
RHB
32
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168
HR
-40 to 125
DRV8703DQRHBTQ1
PREVIEW
VQFN
RHB
32
250
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168
HR
-40 to 125
Device Marking (5) (6)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
space
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest
availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the
requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified
lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used
between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by
weight in homogeneous material)
space
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the
finish value exceeds the maximum column width.
space
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
space
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device
space
Multiple Device markings will be inside parentheses. Only on Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief
on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third
parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for
release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
58
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8702D-Q1 DRV8703D-Q1
DRV8702D-Q1, DRV8703D-Q1
www.ti.com
SLVSDX8 – MARCH 2017
12.1.2 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
B0 W
Reel
Diameter
Cavity
A0
B0
K0
W
P1
A0
Dimension designed to accommodate the component width
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1
Q2
Q1
Q2
Q3
Q4
Q3
Q4
User Direction of Feed
Pocket Quadrants
Device
Package
Type
Package
Drawing
Pins
SPQ
Reel
Diameter
(mm)
Reel
Width W1
(mm)
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
DRV8702DQRHBTQ1
VQFN
RHB
32
250
180.0
12.4
5.25
5.25
1.1
8.0
12.0
Q2
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8702D-Q1 DRV8703D-Q1
Submit Documentation Feedback
59
DRV8702D-Q1, DRV8703D-Q1
SLVSDX8 – MARCH 2017
www.ti.com
TAPE AND REEL BOX DIMENSIONS
Width (mm)
L
W
60
H
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DRV8702DQRHBTQ1
VQFN
RHB
32
250
195.0
200.0
45.0
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8702D-Q1 DRV8703D-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
4-Apr-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DRV8702DQRHBRQ1
ACTIVE
VQFN
RHB
32
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 125
8702D
DRV8702DQRHBTQ1
ACTIVE
VQFN
RHB
32
250
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 125
8702D
DRV8703DQRHBRQ1
ACTIVE
VQFN
RHB
32
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 125
8703D
DRV8703DQRHBTQ1
ACTIVE
VQFN
RHB
32
250
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 125
8703D
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
4-Apr-2017
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Mar-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DRV8702DQRHBTQ1
VQFN
RHB
32
250
180.0
12.4
5.25
5.25
1.1
8.0
12.0
Q2
DRV8703DQRHBTQ1
VQFN
RHB
32
250
180.0
12.4
5.25
5.25
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Mar-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DRV8702DQRHBTQ1
VQFN
RHB
32
250
195.0
200.0
45.0
DRV8703DQRHBTQ1
VQFN
RHB
32
250
195.0
200.0
45.0
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its
semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers
should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
TI’s published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated
circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and
services.
Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and is
accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduced
documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements
different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the
associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Buyers and others who are developing systems that incorporate TI products (collectively, “Designers”) understand and agree that Designers
remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have
full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products
used in or for Designers’ applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with
respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous
consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and
take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will
thoroughly test such applications and the functionality of such TI products as used in such applications.
TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information,
including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to
assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any
way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource
solely for this purpose and subject to the terms of this Notice.
TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI
products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,
enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically
described in the published documentation for a particular TI Resource.
Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that
include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE
TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY
RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or
endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR
REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO
ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM,
INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF
PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL,
DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN
CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949
and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.
Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such
products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards
and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must
ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in
life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.
Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all
medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.
TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s noncompliance with the terms and provisions of this Notice.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2017, Texas Instruments Incorporated