Lyontek LY612568ML-15T 5v 256k x 8 bit high speed cmos sram Datasheet

®
LY612568
5V 256K X 8 BIT HIGH SPEED CMOS SRAM
Rev. 1.0
REVISION HISTORY
Revision
Rev. 0.1
Rev. 0.2
Description
Preliminary
Revised Test Condition of ISB1/IDR
Revised VTERM to VT1 and VT2
Revised FEATURES & ORDERING INFORMATION
Lead free and green package available to Green package
available
Added packing type in ORDERING INFORMATION
Deleted TSOLDER in ABSOLUTE MAXIMUN RATINGS
Revised PACKAGE OUTLINE DIMENSION
Issue Date
Dec.6.2006
Aug.26.2009
Rev. 0.3
Rev. 1.0
Revised ORDERING INFORMATION in page 9
Revised Notes item 1 and 2 in page 3
Aug.30.2010
Aug.29.2013
1. VIH(max) = VCC + 2.0V for pulse width less than 6ns.
2. VIL(min) = VSS - 2.0V for pulse width less than 6ns.
Revised ORDERING INFORMATION
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
0
®
LY612568
5V 256K X 8 BIT HIGH SPEED CMOS SRAM
Rev. 1.0
FEATURES
GENERAL DESCRIPTION
„ Fast access time : 15/20/25ns
„ Low power consumption:
Operating current: 100/80/75mA (TYP.)
Standby current: 100µA (TYP.)
„ Single 5V power supply
„ All inputs and outputs TTL compatible
„ Fully static operation
„ Tri-state output
„ Data retention voltage : 2.0V (MIN.)
„ Green package available
„ Package : 44-pin 400 mil TSOP-II
The LY612568 is a 2,097,152-bit low power CMOS
static random access memory organized as 262,144
words by 8 bits. It is fabricated using very high
performance, high reliability CMOS technology. Its
standby current is stable within the range of
operating temperature.
The LY612568 is well designed for low power
application, and particularly well suited for battery
back-up nonvolatile memory application.
The LY612568 operates from a single power
supply of 5V and all inputs and outputs are fully TTL
compatible
PRODUCT FAMILY
Product
Family
LY612568
LY612568(E)
LY612568(I)
Operating
Temperature
0 ~ 70℃
-20 ~ 80℃
-40 ~ 85℃
Vcc Range
Speed
4.5 ~ 5.5V
4.5 ~ 5.5V
4.5 ~ 5.5V
15/20/25ns
15/20/25ns
15/20/25ns
FUNCTIONAL BLOCK DIAGRAM
PIN DESCRIPTION
Vcc
Vss
A0-A17
DECODER
DQ0-DQ7
I/O DATA
CIRCUIT
CE#
WE#
OE#
CONTROL
CIRCUIT
Power Dissipation
Standby(ISB1,TYP.) Operating(Icc,TYP.)
100µA
100/80/75mA
100µA
100/80/75mA
100µA
100/80/75mA
256Kx8
MEMORY ARRAY
SYMBOL
DESCRIPTION
A0 - A17
Address Inputs
DQ0 – DQ7
Data Inputs/Outputs
CE#
Chip Enable Inputs
WE#
Write Enable Input
OE#
Output Enable Input
VCC
Power Supply
VSS
Ground
NC
No Connection
COLUMN I/O
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
1
®
LY612568
5V 256K X 8 BIT HIGH SPEED CMOS SRAM
Rev. 1.0
PIN CONFIGURATION
NC
1
44
NC
NC
2
43
NC
A4
3
42
NC
A3
4
41
A5
5
40
A6
6
39
A7
A0
7
38
A8
37
OE#
36
DQ7
35
DQ6
34
Vss
33
Vcc
32
DQ5
CE#
8
DQ0
9
DQ1
10
Vcc
11
Vss
12
DQ2
13
LY612568
XXXXXXX
XXXX
A2
A1
DQ3
14
31
DQ4
WE#
15
30
A9
A17
16
29
A10
A16
17
28
A11
A15
18
27
A12
A14
19
26
NC
A13
20
25
NC
NC
21
24
NC
NC
22
23
NC
TSOP-II
ABSOLUTE MAXIMUN RATINGS*
PARAMETER
Voltage on VCC relative to VSS
Voltage on any other pin relative to VSS
Operating Temperature
Storage Temperature
Power Dissipation
DC Output Current
SYMBOL
VT1
VT2
TA
TSTG
PD
IOUT
RATING
-0.5 to 6.5
-0.5 to VCC+0.5
0 to 70(C grade)
-20 to 80(E grade)
-40 to 85(I grade)
-65 to 150
1
50
UNIT
V
V
℃
℃
W
mA
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
2
®
LY612568
5V 256K X 8 BIT HIGH SPEED CMOS SRAM
Rev. 1.0
TRUTH TABLE
MODE
Standby
Output Disable
Read
Write
Note:
CE#
H
L
L
L
OE#
X
H
L
X
WE#
X
H
H
L
SUPPLY CURRENT
ISB1
ICC
ICC
ICC
I/O OPERATION
High-Z
High-Z
DOUT
DIN
H = VIH, L = VIL, X = Don't care.
DC ELECTRICAL CHARACTERISTICS
SYMBOL
TEST CONDITION
PARAMETER
Supply Voltage
VCC
*1
Input High Voltage
VIH
*2
Input Low Voltage
VIL
Input Leakage Current
ILI
VCC ≧ VIN ≧ VSS
Output Leakage
VCC ≧ VOUT ≧ VSS,
ILO
Current
Output Disabled
Output High Voltage
VOH IOH = -4mA
Output Low Voltage
VOL IOL = 8mA
-15
Cycle time = Min.
Average Operating
ICC
CE# = VIL , II/O = 0mA
-20
Power supply Current
Other pins at VIH or VIL
-25
Standby Power
CE# ≧VCC - 0.2V
ISB1
Supply Current
Other pins at 0.2V or VCC-0.2V
MIN.
4.5
2.2
- 0.3
-1
TYP.
5.0
-
*4
MAX.
5.5
VCC+0.3
0.8
1
UNIT
V
V
V
µA
-1
-
1
µA
2.4
-
100
80
75
0.4
140
110
100
V
V
mA
mA
mA
-
0.1
3*
5
mA
Notes:
1. VIH(max) = VCC + 2.0V for pulse width less than 6ns.
2. VIL(min) = VSS - 2.0V for pulse width less than 6ns.
3. Over/Undershoot specifications are characterized, not 100% tested.
4. Typical values are included for reference only and are not guaranteed or tested.
Typical valued are measured at VCC = VCC(TYP.) and TA = 25℃
5. 1mA for special request
CAPACITANCE (TA = 25℃, f = 1.0MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL
CIN
CI/O
MIN.
-
Note : These parameters are guaranteed by device characterization, but not production tested.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
3
MAX
8
10
UNIT
pF
pF
®
LY612568
5V 256K X 8 BIT HIGH SPEED CMOS SRAM
Rev. 1.0
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
0.2V to VCC - 0.2V
3ns
1.5V
CL = 30pF + 1TTL, IOH/IOL = -8mA/16mA
AC ELECTRICAL CHARACTERISTICS
(1) READ CYCLE
PARAMETER
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low-Z
Output Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change
(2) WRITE CYCLE
PARAMETER
Write Cycle Time
Address Valid to End of Write
Chip Enable to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Data Hold from End of Write Time
Output Active from End of Write
Write to Output in High-Z
SYM.
tRC
tAA
tACE
tOE
tCLZ*
tOLZ*
tCHZ*
tOHZ*
tOH
SYM.
tWC
tAW
tCW
tAS
tWP
tWR
tDW
tDH
tOW*
tWHZ*
LY612568-15
MIN.
MAX.
15
15
15
7
4
0
7
7
3
-
LY612568-20
MIN.
MAX.
20
20
20
8
4
0
8
8
3
-
LY612568-25
MIN.
MAX.
25
25
25
9
4
0
9
9
3
-
UNIT
LY612568-15
MIN.
MAX.
15
12
12
0
10
0
8
0
4
8
LY612568-20
MIN.
MAX.
20
16
16
0
11
0
9
0
5
9
LY612568-25
MIN.
MAX.
25
20
20
0
12
0
10
0
6
10
UNIT
*These parameters are guaranteed by device characterization, but not production tested.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
®
LY612568
5V 256K X 8 BIT HIGH SPEED CMOS SRAM
Rev. 1.0
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled) (1,2)
tRC
Address
tAA
Dout
tOH
Previous Data Valid
Data Valid
READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5)
tRC
Address
tAA
CE#
tACE
OE#
tOE
tOH
tOHZ
tCHZ
tOLZ
tCLZ
Dout
High-Z
Data Valid
Notes :
1.WE# is high for read cycle.
2.Device is continuously selected OE# = low, CE# = low.
3.Address must be valid prior to or coincident with CE# = low,; otherwise tAA is the limiting parameter.
4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
5
High-Z
®
LY612568
5V 256K X 8 BIT HIGH SPEED CMOS SRAM
Rev. 1.0
WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6)
tWC
Address
tAW
CE#
tCW
tAS
tWP
tWR
WE#
tWHZ
Dout
TOW
High-Z
(4)
tDW
(4)
tDH
Data Valid
Din
WRITE CYCLE 2 (CE# Controlled) (1,2,5,6)
tWC
Address
tAW
CE#
tAS
tWR
tCW
tWP
WE#
tWHZ
Dout
High-Z
(4)
tDW
tDH
Data Valid
Din
Notes :
1.WE#, CE# must be high during all address transitions.
2.A write occurs during the overlap of a low CE#, low WE#.
3.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be
placed on the bus.
4.During this period, I/O pins are in the output state, and input signals must not be applied.
5.If the CE# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state.
6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
6
®
LY612568
5V 256K X 8 BIT HIGH SPEED CMOS SRAM
Rev. 1.0
DATA RETENTION CHARACTERISTICS
PARAMETER
VCC for Data Retention
Data Retention Current
Chip Disable to Data
Retention Time
Recovery Time
tRC* = Read Cycle Time
SYMBOL
TEST CONDITION
VDR CE# ≧ VCC - 0.2V
VCC = 2.0V
CE# ≧ VCC - 0.2V
IDR
Others at 0.2V or VCC-0.2V
See Data Retention
tCDR
Waveforms (below)
tR
MIN.
2.0
TYP.
-
MAX.
5.5
UNIT
V
-
0.05
2
mA
0
-
-
ns
tRC*
-
-
ns
DATA RETENTION WAVEFORM
VDR ≧ 2.0V
Vcc
Vcc(min.)
Vcc(min.)
tCDR
CE#
VIH
tR
CE# ≧ Vcc-0.2V
VIH
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
7
®
LY612568
5V 256K X 8 BIT HIGH SPEED CMOS SRAM
Rev. 1.0
PACKAGE OUTLINE DIMENSION
44-pin 400mil TSOP-Ⅱ Package Outline Dimension
SYMBOLS
A
A1
A2
b
c
D
E
E1
e
L
ZD
y
Θ
DIMENSIONS IN MILLMETERS
MIN.
NOM.
MAX.
1.20
0.05
0.10
0.15
0.95
1.00
1.05
0.30
0.45
0.12
0.21
18.212
18.415
18.618
11.506
11.760
12.014
9.957
10.160
10.363
0.800
0.40
0.50
0.60
0.805
0.076
o
o
o
3
6
0
DIMENSIONS IN MILS
MIN.
NOM.
MAX.
47.2
2.0
3.9
5.9
37.4
39.4
41.3
11.8
17.7
4.7
8.3
717
725
733
453
463
473
392
400
408
31.5
15.7
19.7
23.6
31.7
3
o
o
o
0
3
6
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
8
®
LY612568
5V 256K X 8 BIT HIGH SPEED CMOS SRAM
Rev. 1.0
ORDERING INFORMATION
Package Type
44-Pin 400mil
TSOP-II
Access Time
(Speed)(ns)
15
Temperature
Range(℃)
0℃~70℃
-20℃~80℃
-40℃~85℃
20
0℃~70℃
-20℃~80℃
-40℃~85℃
25
0℃~70℃
-20℃~80℃
-40℃~85℃
Packing
Type
Tray
LY612568ML-15
Tape Reel
LY612568ML-15T
Tray
LY612568ML-15E
Tape Reel
LY612568ML-15ET
Tray
LY612568ML-15I
Tape Reel
LY612568ML-15IT
Tray
LY612568ML-20
Tape Reel
LY612568ML-20T
Tray
LY612568ML-20E
Tape Reel
LY612568ML-20ET
Tray
LY612568ML-20I
Tape Reel
LY612568ML-20IT
Tray
LY612568ML-25
Tape Reel
LY612568ML-25T
Tray
LY612568ML-25E
Tape Reel
LY612568ML-25ET
Tray
LY612568ML-25I
Tape Reel
LY612568ML-25IT
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
9
Lyontek Item No.
®
LY612568
Rev. 1.0
5V 256K X 8 BIT HIGH SPEED CMOS SRAM
THIS PAGE IS LEFT BLANK INTENTIONALLY.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
10
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