ATMEL AT78C1501 Dvd / cd atapi controller Datasheet

Features
• Host Interface
•
•
•
•
•
•
– ATAPI Compatible (ANSI ATA-1, ATA-2, ATA-3 and ATA-4 compliant) Host Mode
– Ultra DMA Support (66 MB/sec)
– High-current (12 mA) Drivers for Direct Connection to AT Cable (slew rate
controlled)
– 256-byte Bidirectional Data FIFO to Improve Throughput
Embedded Processor
– ARM7TDMI™ RISC Processor
– Open Processor Architecture Protects Firmware Investment
– Wide Selection of Development Tools from ARM ® and Third-party Vendors
– 1-Mbyte External Flash Interface for Code/Data
– 16-Kbyte Internal SRAM for Data
Buffer Manager
– Supports SDRAM up to 32 Mbytes (16M x 16)
– DRAM Bandwidth of up to 160 Mbytes/sec (burst)
– Priority Buffer Arbiter
Read Channel Interface
– Nibble Interface Speed (code cell rate): 40 MHz (160 Mbs, DVD 5X)
– EFM (8/14) and EFM+ (8/16) Demodulation
Write Channel Interface
– Serial Interface Speed (code cell rate): DVD 2X
– EFM (8/14) and EFM+ (8/16) Modulation
– DVD-R Pre-pit Decoder with Error Detection and Correction
– DVD+RW ADIP Decoder with Error Detection and Correction
– CD-R/RW ATIP Decoder with Error Detection
Error Correction Logic
– DVD Data Block Error Detection and Correction
– DVD EDC Error Detection
– DVD IEC Header Error Detection and Correction
– All CD Formats
Lower Power Operation with 3.3V Core and 5V Tolerant I/Os
DVD/CD ATAPI
Controller
AT78C1501
Description
The Atmel AT78C1501 is a high-performance DVD/CD ATAPI Ultra DMA66 Interface
Controller, designed to interface to the AT78C1502 DVD Servo Controller, the
AT78C1503 DVD Read Channel and the AT78C1504 Automatic Laser Power Control
(ALPC). The interface controller (AT78C1501) contains ARM® and AVR® microcontrollers, buffer management, error correction code (ECC) and encoder/decoder (ENDEC)
for DVD and CD. Also included are a writeable control store for timing generation and
an on-board frequency synthesizer to generate system frequencies from one crystal.
ATA66/ATAPI66 and I2S interfaces are provided.
The major functions of the AT78C1501 include data format encoding/decoding, error
detection/correction, buffer management, ATAPI host interface and serial interface
master. The AT78C1501 also includes an embedded ARM7 RISC Core to perform all
system (drive) microprocessor functions and an embedded AVR RISC core to perform
internal data path and buffer management control.
The AT78C1501 disk formats include DVD-ROM, DVD-RAM (Read/Write), CD-ROM,
CD -R (R ea d/W rite), C D-RW (R ea d/W rite) , DVD- R (R ead /Wr ite), DVD-RW
(Read/Write), and DVD+RW (Read/Write).
Rev. 2049A–DVD–07/02
1
Figure 1. DVD System Block Diagram
DRAM
Flash
AT78C1501
ATAPI I/F
Controller
DBM
ECC
SRAM
ARM7TDMI
AT78C1502
Servo
Control
System
Power
Drivers
Sled
Focus
AT78C1503
Read
Channel
Spindle
Laser
AT78C1504
Laser Power
Controller
AT78C1507
Read
Channel Adj.
T08XX
Laser Amp
AT78C1505
Pre-amp
Table 1. DC Parameters
Symbol
Parameter
Min
Nom
Max
Units
VCC
Supply Voltage
3.0
3.3
3.6
V
ICC
Operating Current
500
mA
Note:
2
Notes
Note 1
1. Values listed are advance information and are likely to change as production silicon is characterized.
AT78C1501
2049A–DVD–07/02
AT78C1501
VDD
DA0
DA2
CSn0
CSn1
DASPn
RESETn
SCK
WS
SD
VSS
TDO
TD1
TCLK
TMS
TRSTn
GPIO15
GPIO14
GPIO13
GPIO12
VSS
AUD_FSN_LF
SCLK
VDD
SDATA
SDEN1
SDEN2
TEST_MODE
GPIO7
GPIO6
GPIO5
GPIO4
VSS
GPIO3
GPIO2
GPIO1
GPIO0
BCLK_out
WOBBLE_CLK
WOBBLE_DATA
WCLK
VSS
WRITE_DATA3
WRITE_DATA2
WRITE_DATA1
WRITE_DATA0
WRITE_GATE
WRITE
VSS
SYS_FLN_LF
SYS_FSN_VCC
ERASE
Figure 2. Pin Assignment
1
157
156
208
AT78C1501
208-lead TQFP
52
53
105
104
VSS
HOST_FSN_LF
HOST_FSN_VCC
PWRON_RSTn
SERVO_FAULT
CTRL_INT_ACK
CTRL_INT
SERVO_INT_ACK
VDD
SERVO_INT
XTAL2
XTAL1
RDATA7
RDATA6
RDATA5
RDATA4
VDD
RDATA3
RDATA2
RDATA1
RDATA0
RCLK
READ_GATE
VSS
READ
GPIO11
GPIO10
GPIO9
GPIO8
DRAM_DATA15
VDD
DRAM_DATA14
DRAM_DATA13
VSS
DRAM_DATA12
DRAM_DATA11
DRAM_DATA10
DRAM_DATA9
DRAM_DATA8
DRAM_clk
DRAM_ADDR12
DRAM_ADDR11
VSS
DRAM_ADDR9
DRAM_ADDR8
DRAM_ADDR7
DRAM_ADDR6
DRAM_ADDR5
DRAM_ADDR4
DRAM_ADDR3
DRAM_ADDR2
VSS
VSS
XA1
XA0
XD0
XD1
XD2
XD3
XD4
XD5
VSS
XD6
XD7
XD8
XD9
XD10
XD11
XD12
XD13
VSS
XD14
XD15
VDD
XCEn
XCSn0
XCSn1
XCSn2
XCSn3
XWEn0
VSS
XWEn1
DRAM_DATA0
DRAM_DATA1
DRAM_DATA2
DRAM_DATA3
DRAM_DATA4
DRAM_DATA5
DRAM_DATA6
VSS
DRAM_DATA7
SPDIF_OUT
VDD
DRAM_WEn
DRAM_CASn
DRAM_RASn
DRAM_cs_n
VSS
DRAM_ba_0
DRAM_ba_1
DRAM_ADDR10
DRAM_ADDR0
DRAM_ADDR1
VDD
VSS
PDIAGn
DA1
INTRQ
DMACKn
CSEL
IORDY
DIORn
VDD
DIOWn
DMARQ
VSS
DD15
DD0
DD14
DD1
DD13
DD2
DD12
DD3
VSS
DD11
DD4
DD10
DD5
DD9
DD6
DD8
DD7
VSS
XA19
XA18
VDD
XA17
XA16
XA15
XA14
XA13
XA12
VSS
XA11
XA10
XA9
XA8
XA7
VSS
XA6
XA5
XA4
XA3
XA2
VDD
3
2049A–DVD–07/02
Pin Definitions
General I/O Pin List
Table 1. General I/O Pin List
Pin Name
Pin #
Pin Type
XTAL1
145
I
Crystal Input
XTAL2
146
B
Crystal I/O
PWRON_RSTn
153
I
Power On Reset: This signal is used to initialize all logic in the controller including the
ARM7 and AVR cores.
TEST_MODE
181
I
RAM Test Mode: This signal is used by the chip tester to place all embedded memory
cells in BIST mode for test.
GPIO[0]
GPIO[1]
GPIO[2]
GPIO[3]
GPIO[4]
GPIO[5]
GPIO[6]
GPIO[7]
GPIO[8]
GPIO[9]
GPIO[10]
GPIO[11]
GPIO[12]
GPIO[13]
GPIO[14]
GPIO[15]
172
173
174
175
177
178
179
180
128
129
130
131
189
190
191
192
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
General Purpose I/O
BCLK_out
171
O
Processor Clock Output: This signal is the ARM7 and AVR core clock. It can be used as
the clock input to the servo chip.
SYS_FSN_VCC
158
I
System FSN VCC: This is the power supply pin for the system frequency synthesizer.
SYS_FSN_LF
159
O
System FSN Loop Filter: This signal is the loop filter pin for the system frequency
synthesizer.
HOST_FSN_VCC
154
I
Host FSN VCCc: This is the power supply pin for the host frequency synthesizer.
HOST_FSN_LF
155
O
Host FSN Loop Filter: This signal is the loop filter pin for the host frequency synthesizer.
AUD_FSN_LF
187
O
Audio FSN Loop Filter: This signal is the loop filter pin for the audio frequency synthesizer.
4
Pin Description
AT78C1501
2049A–DVD–07/02
AT78C1501
ATAPI Interface
The AT78C1501 supports the ATAPI CD-ROM specification (IDE CD-ROM Interface)
and can drive IDE signals directly. The host interface contains a 12-byte command
packet FIFO and IDE registers for transferring command and status data. The host interface also contains a data FIFO for transferring data from buffer DRAM to the host. The
host interface contains the following pins:
Table 2. ATAPI Interface I/O Pin List
Pin Name
Pin #
Pin Type
CS0-
205
I
Device Chip Select 0: Chip select signal from host to select the Command Block registers.
CS1-
204
I
Device Chip Select 1: Chip select signal from host to select the Command Block registers.
DD[15]
DD[14]
DD[13]
DD[12]
DD[11]
DD[10]
DD[9]
DD[8]
DD[7]
DD[6]
DD[5]
DD[4]
DD[3]
DD[2]
DD[1]
DD[0]
13
15
17
19
22
24
26
28
29
27
25
23
20
18
16
14
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Device Data Bus: Bidirectional data bus between the host and the device. The lower eight
bits are used for 8-bit register transfers. Data transfers are 16 bits wide.
DASP-
203
I/O
Device Active or Slave Present: This is a time-multiplexed signal that indicates that a device
is active or that Device 1 is present.
DA[2]
DA[1]
DA[0]
206
3
207
I
Device Address: This is the 3-bit binary coded address asserted by the host to access a
register or data port in the device.
5
I
DMA Acknowledge: This signal shall be used by the host in response to DMARQ- to initiate
DMA transfers.
O
DMA Request: This signal, used for DMA data transfers between the host and device, shall
be asserted by the device when it is ready to transfer data to or from the host. The direction
of data transfer is controlled by DIOR- and DIOW-. This signal is used in a handshake
manner with DMACK, i.e., the device shall wait until the host asserts DMACK, before
negating DMARQ and reasserting DMARQ, if there is more data to transfer.
O
Device Interrupt: This signal is used by the selected device to interrupt the host system.
When the nIEN bit is cleared to “0” and the device is selected, INTRQ shall be enabled
through a tristate buffer. When the nIEN bit is set to “1” or the device is not selected, the
INTRQ signal shall be in a high impedance state.
DMACK-
DMARQ-
INTRQ
11
4
Pin Description
5
2049A–DVD–07/02
Table 2. ATAPI Interface I/O Pin List (Continued)
Pin Name
DIORHDMARDYHSTROBE
IORDY
DDMARDYDSTROBE
Pin #
8
7
Pin Type
Pin Description
I
Device I/O Read: This is the strobe signal asserted by the host to read device registers or the
data port.
Host DMA Ready: This signal is a flow control signal for Ultra DMA data in bursts. This signal
is asserted by the host to indicate to the host that the device is ready to receive Ultra DMA
data in bursts. The host may negate HDMARDY- to pause an Ultra DMA data in burst.
Host Strobe: This signal is the data in strobe from the host for an Ultra DMA data out burst.
Both the rising and falling edge of HSTROBE latch the data from DD[15:0] into the device.
The host may stop generating DSTROBE edges to pause an Ultra DMA data out burst.
O
Device I/O Ready: This signal is negated to extend the host transfer cycle of any host register
access (Read or Write) when the device is not ready to respond to a data transfer request.
Device DMA Ready: This signal is a flow control signal for Ultra DMA data out bursts. This
signal is asserted by the device to indicate to the host that the device is ready to receive Ultra
DMA data out bursts. The device may negate DDMARDY- to pause an Ultra DMA data out
burst.
Device Strobe: This signal is the data in strobe from the device for an Ultra DMA data in
burst. Both the rising and falling edge of DSTROBE latch the data from DD[15:0] into the
host. The device may stop generating DSTROBE edges to pause an Ultra DMA data in burst.
DIOWSTOP
10
I
Device I/O Write: This is the strobe signal asserted by the host to write device registers or the
data port.
STOP: STOP shall be negated by the host before data is transferred in an Ultra DMA burst.
Assertion of STOP by the host during an Ultra DMA burst signals the termination of the Ultra
DMA burst.
PDIAG-
2
O
Device Passed Diagnostics: This signal shall be asserted by Device 1 to indicate to Device 0
that it has completed diagnostics.
CSEL
6
I
Cable Select: Used to select Ddevice 0 or 1.
202
I
Device Reset: This signal, referred to as hardware reset, shall be used by the host to reset
the device.
RESET-
6
AT78C1501
2049A–DVD–07/02
AT78C1501
JTAG/ICE Interface
The JTAG/ICE Interface is used as the in-circuit emulator for the ARM7TDMI Processor.
Table 3. JTAG/ICE Interface I/O Pin List
Pin Name
Disk Read Interface
Pin #
Pin Type
Pin Description
TMS
194
I
Test Mode Select
TDI
196
I
Test Data Input
TCK
195
I
Test Clock
TDO
197
O
Test Data Output
TRST
193
I
Test Reset
The Disk Read Interface connects the DVD/CD Read Channel device to the controller.
Table 4. Disk Read Interface I/O Pin List
Pin Name
Pin #
Pin Type
Pin Description
RCLK
135
I
Recovered Clock: This is the recovered data rate
clock from the read channel. This clock is used for
the sync detection logic as well as the WCS
programmable state machine.
RDATA[0]
RDATA[1]
RDATA[2]
RDATA[3]
RDATA[4]
RDATA[5]
RDATA[6]
RDATA[7]
136
137
138
139
141
142
143
144
I
I
I
I
I
I
I
I
Recovered Data: This is the recovered data from
the disk. This is used by the sync detection and
ENDEC to recover the user data on the disk.
READ
132
O
Read Mode: This signal is used to place the
ALPC in read mode.
READ_GATE
134
O
Read Gate: This signal is used by the read
channel to lock the PLL to the recovered data
instead of the synthesizer.
WOBBLE_CLK
169
I
Wobble Clock: Recovered wobble clock from read
channel. This clock is used for the ADIP, ATIP and
PRE-PIT decoder state machines. This clock is
also used to clock the WCS programmable state
machine during write operations.
WOBBLE_DATA
168
I
Wobble Data: Recovered wobble data from read
channel. This is used to decode the ADIP, ATIP
and PRE-PIT data.
7
2049A–DVD–07/02
Disk Write Interface
The Disk Write Interface connects the DVD/CD Write device to the controller.
Table 5. Disk Write Interface I/O Pin List
Pin Name
Pin Type
Pin Description
WCLK
166
I
Write Clock: Bit clock used to generate the NRZI
data stream to the ALPC. This clock originates
from the recovered wobble clock in the read
channel, which is then multiplied up to the bit rate
in the ALPC.
WRITE_DATA[0]
WRITE_DATA[1]
WRITE_DATA[2]
WRITE_DATA[3]
163
164
165
166
O
O
O
O
Write Data: This is the NRZI data stream from the
controller to the ALPC.
WRITE
161
O
Write Mode: This signal is used to place the ALPC
in write mode.
WRITE_GATE
162
O
Write Gate: This signal is used by the ALPC to
allow writing to the disk.
O
Erase Mode: This signal indicates that the ALPC
should use the erase power level between write
pulse trains. This is used for any rewritable disk
format. (DVD-RW, CD-RW, DVD+RW).
ERASE
8
Pin #
157
AT78C1501
2049A–DVD–07/02
AT78C1501
DRAM Interface
The DRAM Interface connects the controller to the buffer DRAM.
Table 6. DRAM Interface I/O Pin List
Pin Name
Pin #
Pin Type
Pin Description
DRAM_RASn
96
O
Row Address Strobe
DRAM_CASn
95
O
Column Address Strobe
DRAM_ADDR[0]
DRAM_ADDR[1]
DRAM_ADDR[2]
DRAM_ADDR[3]
DRAM_ADDR[4]
DRAM_ADDR[5]
DRAM_ADDR[6]
DRAM_ADDR[7]
DRAM_ADDR[8]
DRAM_ADDR[9]
DRAM_ADDR[10]
DRAM_ADDR[11]
DRAM_ADDR[12]
102
103
106
107
108
109
110
111
112
113
101
115
116
O
O
O
O
O
O
O
O
O
O
O
O
O
DRAM Buffer Address
DRAM_DATA[0]
DRAM_DATA[1]
DRAM_DATA[2]
DRAM_DATA[3]
DRAM_DATA[4]
DRAM_DATA[5]
DRAM_DATA[6]
DRAM_DATA[7]
DRAM_DATA[8]
DRAM_DATA[9]
DRAM_DATA[10]
DRAM_DATA[11]
DRAM_DATA[12]
DRAM_DATA[13]
DRAM_DATA[14]
DRAM_DATA[15]
83
84
85
86
87
88
89
91
118
119
120
121
122
124
125
127
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DRAM Buffer Data
DRAM_WEn
94
O
DRAM Write Strobe
DRAM_cs_n
97
O
DRAM Chip Select
DRAM_ba[0]
DRAM_ba[1]
99
100
O
O
DRAM Bank Select
DRAM_clk
117
O
DRAM Clock
9
2049A–DVD–07/02
External Memory
Interface
The External Memory Interface connects external program memory to the controller.
The DVD RAM Servo device is also connected to this bus.
Table 7. External Memory Interface I/O Pin List
Pin Name
10
Pin #
Pin Type
Pin Description
XA[0]
XA[1]
XA[2]
XA[3]
XA[4]
XA[5]
XA[6]
XA[7]
XA[8]
XA[9]
XA[10]
XA[11]
XA[12]
XA[13]
XA[14]
XA[15]
XA[16]
XA[17]
XA[18]
XA[19]
55
54
51
50
49
48
47
45
44
43
42
41
39
38
37
36
35
34
32
31
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
External Address Bus: Address bus for external
memory banks
XD[0]
XD[1]
XD[2]
XD[3]
XD[4]
XD[5]
XD[6]
XD[7]
XD[8]
XD[9]
XD[10]
XD[11]
XD[12]
XD[13]
XD[14]
XD[15]
56
57
58
59
60
61
63
64
65
66
67
68
69
70
72
73
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
External Data Bus
XCSn[0]
XCSn[1]
XCSn[2]
XCSn[3]
76
77
78
79
O
O
O
O
External Chip Select
XWEn[0]
XWEn[1]
80
82
O
O
External Write Enable
XOEn
75
O
External Output Enable
AT78C1501
2049A–DVD–07/02
AT78C1501
Servo Interface
The Servo Interface connects the servo device to the controller.
Table 8. Servo Interface I/O Pin List
Pin Name
Serial Interface
Pin #
Pin Type
Pin Description
SERVO_INT
147
I
Servo Interrupt Input: Interrupt signal from the
servo to the controller
SERVO_INT_ACK
149
O
Servo Interrupt Acknowledge: Interrupt
acknowledge from the controller to the servo
CTRL_INT
150
O
Controller Interrupt Output: Interrupt signal from
the controller to the servo
CTRL_INT_ACK
151
I
Controller Interrupt Acknowledge: Interrupt
acknowledge from the servo to the controller
SERVO_FAULT
152
I
Servo Fault: Indicates that some kind of fault has
occurred in the servo or read channel. This is
used to gate off any disk write functions.
The Serial Interface connects all slave devices to the controller.
Table 9. Serial Interface I/O Pin List
Pin Name
I2S Audio Interface
Pin #
Pin Type
Pin Description
SCLK
186
O
Serial Clock
SDATA
184
I/O
Serial Data
SDEN1
183
O
Serial Enable 1
SDEN2
182
O
Serial Enable 2
The I2S Audio Interface is a serial interface for external audio devices.
Table 10. I2S Audio Interface I/O Pin List
Pin Name
Sony® Philips® Digital
Audio Interface
Pin #
Pin Type
Pin Description
SCK
201
O
Serial Clock
WS
200
O
Word Select
SD
100
O
Serial Data
The Sony Philips Digital Audio Interface is a standard digital interface for external audio
devices.
Table 11. Sony Philips Digital Audio Interface I/O Pin List
Pin Name
SPDIF_OUT
Pin #
Pin Type
92
O
Pin Description
Sony Philips Digital Interface
11
2049A–DVD–07/02
Figure 3. Functional Pinout
AT78C1501
SYSTEM
ATAPI
MEMORY
JTAG
SERIAL
PORT
12
XTAL1
XTAL2
PWRON_RSTn
SYS_FSN_VCC
SYS_FSN_LF
HOST_FSN_VCC
HOST_FSN_LF
AUD_FSN_LF
TEST_MODE
CS[1:0]
DA[2:0]
DIORDIOWDD[16:0]
DMARQDMACKIORDY
DASPPDIAGCSEL
RESET-
XA[19:0]
XD[15:0]
XCSn[3:0]
XWEn[1:0]
XOEn
TMS
TDI
TCK
TDO
TRST
SCLK
SDATA
SDEN[1:0]
GPIO[15:0]
RCLK
RDATA[7:0]
READ
READ_GATE
WOBBLE_CLK
WOBBLE_DATA
WCLK
WDATA[3:0]
WRITE
WRITE_GATE
ERASE
GENERAL
PURPOSE
READ
CHANNEL
ALPC
DRAM_ADDR[12:0]
DRAM_DATA[15:0]
DRAM_CASn
DRAM_RASn
DRAM_WEn
DRAM_ba[1:0]
DRAM_CSn
DRAM_clk
SDRAM
SERVO_INT
SERVO_INT_ACK
CTRL_INT
CTRL_INT_ACK
SERVO_FAULT
SERVO
SCK
WS
SD
I2S
AUDIO
SPDIF_OUT
DIGITAL
AUDIO
AT78C1501
2049A–DVD–07/02
AT78C1501
Figure 4. AT78C1501 Block Diagram
Program
FLASH
External
Memory
I/F
(MMU)
ARM7TDMI
Processor
SRAM
AMBA
Bridge
Test I/F
Controller
AVR Code
DPRAM
Interrupt
Controller
Decoder
Advanced
System Bus
AT78C1502
SERVO
Advanced
Peripheral Bus
Serial
Bus
Serial I/F
DRAM
Refresh
Control
AVR Code
DPRAM
AVR
Processor
(Buffer MGR)
Ultra DMA
66 MHz
AT78C1503
Read
Channel
DRAM
Access
Control
ATAPI
Packet
FIFO
DRAM
Copy
Control
Host IDE
ATAPI I/F
Host
Data
FIFO
Disk Formatter/
WCS Timing
Engine
Buffer
Arbiter
&
DRAM
I/F
Buffer
SDRAM
Disk
Read I/F
DVD/CD
ENDEC
AT78C1504
ALPC
Timer/
Counter
ECC
Bypass
FIFO
Disk
Write I/F
DVD/CD
ECC
Engine
13
2049A–DVD–07/02
Atmel Headquarters
Atmel Operations
Corporate Headquarters
Memory
2325 Orchard Parkway
San Jose, CA 95131
TEL 1(408) 441-0311
FAX 1(408) 487-2600
Europe
Atmel Sarl
Route des Arsenaux 41
Case Postale 80
CH-1705 Fribourg
Switzerland
TEL (41) 26-426-5555
FAX (41) 26-426-5500
Asia
Room 1219
Chinachem Golden Plaza
77 Mody Road Tsimhatsui
East Kowloon
Hong Kong
TEL (852) 2721-9778
FAX (852) 2722-1369
Japan
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
TEL (81) 3-3523-3551
FAX (81) 3-3523-7581
2325 Orchard Parkway
San Jose, CA 95131
TEL 1(408) 441-0311
FAX 1(408) 436-4314
RF/Automotive
Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
TEL (49) 71-31-67-0
FAX (49) 71-31-67-2340
Microcontrollers
2325 Orchard Parkway
San Jose, CA 95131
TEL 1(408) 441-0311
FAX 1(408) 436-4314
La Chantrerie
BP 70602
44306 Nantes Cedex 3, France
TEL (33) 2-40-18-18-18
FAX (33) 2-40-18-19-60
ASIC/ASSP/Smart Cards
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TEL 1(719) 576-3300
FAX 1(719) 540-1759
Biometrics/Imaging/Hi-Rel MPU/
High Speed Converters/RF Datacom
Avenue de Rochepleine
BP 123
38521 Saint-Egreve Cedex, France
TEL (33) 4-76-58-30-00
FAX (33) 4-76-58-34-80
Zone Industrielle
13106 Rousset Cedex, France
TEL (33) 4-42-53-60-00
FAX (33) 4-42-53-60-01
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TEL 1(719) 576-3300
FAX 1(719) 540-1759
Scottish Enterprise Technology Park
Maxwell Building
East Kilbride G75 0QR, Scotland
TEL (44) 1355-803-000
FAX (44) 1355-242-743
e-mail
[email protected]
Web Site
http://www.atmel.com
© Atmel Corporation 2002.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does
not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted
by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical
components in life support devices or systems.
ATMEL ® and AVR ® are the registered trademarks of Atmel. ARM ® is the registered trademark of ARM Limited.
ARM7TDMI ™ is the trademark of ARM Limited. Sony ® is a registered trademerk of Sony Corporation. Philips ®
is a registered trademark of Koninklijke Philips Electronics N.V.
Other terms and product names may be trademarks of others.
Printed on recycled paper.
2049A–DVD–07/02
Atmel Headquarters
Atmel Operations
Corporate Headquarters
Memory
2325 Orchard Parkway
San Jose, CA 95131
TEL 1(408) 441-0311
FAX 1(408) 487-2600
Europe
Atmel Sarl
Route des Arsenaux 41
Case Postale 80
CH-1705 Fribourg
Switzerland
TEL (41) 26-426-5555
FAX (41) 26-426-5500
Asia
Room 1219
Chinachem Golden Plaza
77 Mody Road Tsimhatsui
East Kowloon
Hong Kong
TEL (852) 2721-9778
FAX (852) 2722-1369
Japan
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
TEL (81) 3-3523-3551
FAX (81) 3-3523-7581
2325 Orchard Parkway
San Jose, CA 95131
TEL 1(408) 441-0311
FAX 1(408) 436-4314
RF/Automotive
Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
TEL (49) 71-31-67-0
FAX (49) 71-31-67-2340
Microcontrollers
2325 Orchard Parkway
San Jose, CA 95131
TEL 1(408) 441-0311
FAX 1(408) 436-4314
La Chantrerie
BP 70602
44306 Nantes Cedex 3, France
TEL (33) 2-40-18-18-18
FAX (33) 2-40-18-19-60
ASIC/ASSP/Smart Cards
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TEL 1(719) 576-3300
FAX 1(719) 540-1759
Biometrics/Imaging/Hi-Rel MPU/
High Speed Converters/RF Datacom
Avenue de Rochepleine
BP 123
38521 Saint-Egreve Cedex, France
TEL (33) 4-76-58-30-00
FAX (33) 4-76-58-34-80
Zone Industrielle
13106 Rousset Cedex, France
TEL (33) 4-42-53-60-00
FAX (33) 4-42-53-60-01
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TEL 1(719) 576-3300
FAX 1(719) 540-1759
Scottish Enterprise Technology Park
Maxwell Building
East Kilbride G75 0QR, Scotland
TEL (44) 1355-803-000
FAX (44) 1355-242-743
e-mail
[email protected]
Web Site
http://www.atmel.com
© Atmel Corporation 2002.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does
not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted
by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical
components in life support devices or systems.
Printed on recycled paper.
2049A–DVD–07/02