ISSI IS41C8200 2m x 8 (16-mbit) dynamic ram with edo page mode Datasheet

IS41C8200
IS41LV8200
ISSI
®
2M x 8 (16-MBIT) DYNAMIC RAM
WITH EDO PAGE MODE
JUNE 2001
FEATURES
DESCRIPTION
• Extended Data-Out (EDO) Page Mode access cycle
• TTL compatible inputs and outputs
• Refresh Interval:
-- 2,048 cycles/32 ms
• Refresh Mode: RAS-Only,
CAS-before-RAS (CBR), and Hidden
• Single power supply:
5V±10% or 3.3V ± 10%
• Byte Write and Byte Read operation via two CAS
The ISSI IS41C8200 and IS41LV8200 are 2,097,152 x 8-bit highperformance CMOS Dynamic Random Access Memory.
These devices offer an accelarated cycle access called
EDO Page Mode. EDO Page Mode allows 2,048 random
accesses within a single row with access cycle time as
short as 20 ns per 4-bit word.
These features make the IS41C8200 and IS41LV8200
ideally suited for high-bandwidth graphics, digital signal
processing, high-performance computing systems, and
peripheral applications.
The IS41C8200 and IS41LV8200 are packaged in 28-pin
300-mil SOJ with JEDEC standard pinouts.
• Industrial temperature range -40°C to 85°C
PRODUCT SERIES OVERVIEW
Part No.
Refresh
Voltage
IS41C8200
2K
5V ± 10%
IS41LV8200
2K
3.3V ± 10%
PIN CONFIGURATION
28 Pin SOJ
VCC
1
28
GND
I/O0
2
27
I/O7
I/O1
3
26
I/O6
I/O2
4
25
I/O5
I/O3
5
24
I/O4
WE
6
23
CAS
RAS
7
22
OE
NC
8
21
A10
9
A0
A1
KEY TIMING PARAMETERS
Parameter
-50
-60
Unit
RAS Access Time (tRAC)
50
60
ns
CAS Access Time (tCAC)
13
15
ns
Column Address Access Time (tAA)
25
30
ns
EDO Page Mode Cycle Time (tPC)
20
25
ns
Read/Write Cycle Time (tRC)
84
104
ns
PIN DESCRIPTIONS
A0-A10
Address Inputs
I/O0-7
Data Inputs/Outputs
A9
WE
Write Enable
20
A8
OE
Output Enable
10
19
A7
RAS
Row Address Strobe
11
18
A6
CAS
Column Address Strobe
A2
12
17
A5
A3
13
16
A4
Vcc
Power
VCC
14
15
GND
GND
Ground
NC
No Connection
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
06/22/01
1
IS41C8200
IS41LV8200
ISSI
®
FUNCTIONAL BLOCK DIAGRAM
OE
WE
CAS
CAS
CONTROL
LOGIC
WE
CONTROL
LOGIC
CAS
WE
OE
CONTROL
LOGIC
OE
RAS
CLOCK
GENERATOR
RAS
DATA I/O BUS
COLUMN DECODER
SENSE AMPLIFIERS
ADDRESS
BUFFERS
A0-A10
ROW DECODER
REFRESH
COUNTER
DATA I/O BUFFERS
RAS
I/O0-I/O7
MEMORY ARRAY
2,097,152 x 8
TRUTH TABLE
Function
Standby
Read
Write: Word (Early Write)
Read-Write
EDO Page-Mode Read
1st Cycle:
2nd Cycle:
EDO Page-Mode Write
1st Cycle:
2nd Cycle:
EDO Page-Mode
1st Cycle:
Read-Write
2nd Cycle:
Hidden Refresh
Read
Write(1)
RAS-Only Refresh
CBR Refresh
RAS
H
L
L
L
L
L
L
L
L
L
L→H→L
L→H→L
L
H→L
CAS
H
L
L
L
H→L
H→L
H→L
H→L
H→L
H→L
L
L
H
L
WE
X
H
L
H→L
H
H
L
L
H→L
H→L
H
L
X
X
OE
X
L
X
L→H
L
L
X
X
L→H
L→H
L
X
X
X
Address tR/tC
X
ROW/COL
ROW/COL
ROW/COL
ROW/COL
NA/COL
ROW/COL
NA/COL
ROW/COL
NA/COL
ROW/COL
ROW/COL
ROW/NA
X
I/O
High-Z
DOUT
DIN
DOUT, DIN
DOUT
DOUT
DIN
DIN
DOUT, DIN
DOUT, DIN
DOUT
DOUT
High-Z
High-Z
Note:
1. EARLY WRITE only.
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
06/22/01
IS41C8200
IS41LV8200
ISSI
®
Functional Description
Auto Refresh Cycle
The IS41C8200 and IS41LV8200 are CMOS DRAMs
optimized for high-speed bandwidth, low power applications.
During READ or WRITE cycles, each bit is uniquely
addressed through the 11 address bits. These are entered
11 bits (A0-A10) at a time. The row address is latched by
the Row Address Strobe (RAS). The column address is
latched by the Column Address Strobe (CAS). RAS is
used to latch the first nine bits and CAS is used the latter
ten bits.
To retain data, 2,048 refresh cycles are required in each
32 ms period. There are two ways to refresh the memory:
Memory Cycle
A memory cycle is initiated by bring RAS LOW and it is
terminated by returning both RAS and CAS HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum tRAS time has expired. A new
cycle must not be initiated until the minimum precharge
time tRP, tCP has elapsed.
Read Cycle
A read cycle is initiated by the falling edge of CAS or OE,
whichever occurs last, while holding WE HIGH. The
column address must be held for a minimum time specified
by tAR. Data Out becomes valid only when tRAC, tAA, tCAC
and tOEA are all satisfied. As a result, the access time is
dependent on the timing relationships between these
parameters.
1. By clocking each of the 2,048 row addresses (A0
through A10) with RAS at least once every 32 ms. Any
read, write, read-modify-write or RAS-only cycle refreshes
the addressed row.
2. Using a CAS-before-RAS refresh cycle. CAS-before-RAS
refresh is activated by the falling edge of RAS, while
holding CAS LOW. In CAS-before-RAS refresh cycle,
an internal 9-bit counter provides the row addresses
and the external address inputs are ignored.
CAS-before-RAS is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Power-On
After application of the VCC supply, an initial pause of
200 µs is required followed by a minimum of eight
initialization cycles (any combination of cycles containing a RAS signal).
During power-on, it is recommended that RAS track with
VCC or be held at a valid VIH to avoid current surges.
Write Cycle
A write cycle is initiated by the falling edge of CAS and
WE, whichever occurs last. The input data must be valid
at or before the falling edge of CAS or WE, whichever
occurs last.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
06/22/01
3
IS41C8200
IS41LV8200
ISSI
®
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Parameters
Rating
Unit
VT
Voltage on Any Pin Relative to GND
5V
3.3V
–1.0 to +7.0
–0.5 to +4.6
V
VCC
Supply Voltage
5V
3.3V
–1.0 to +7.0
–0.5 to +4.6
V
IOUT
Output Current
50
mA
PD
Power Dissipation
1
W
TA
Commercial Operation Temperature
Industrial Operation Temperature
0 to +70
-40 to +85
°C
TSTG
Storage Temperature
–55 to +125
°C
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.)
Symbol
Parameter
VCC
Supply Voltage
VIH
Input High Voltage
VIL
Input Low Voltage
TA
Commercial Ambient Temperature
Industrial Ambient Temperature
5V
3.3V
5V
3.3V
5V
3.3V
Min.
Typ.
Max.
Unit
4.5
3.0
2.4
2.0
–1.0
–0.3
0
-40
5.0
3.3
—
—
—
—
—
—
5.5
3.6
VCC + 1.0
VCC + 0.3
0.8
0.8
70
85
V
V
V
°C
°C
CAPACITANCE(1,2)
Symbol
CIN1
CIN2
CIO
Parameter
Input Capacitance: A0-A10(A11)
Input Capacitance: RAS, CAS, WE, OE
Data Input/Output Capacitance: I/O0-I/O3
Max.
Unit
5
7
7
pF
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz.
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
06/22/01
IS41C8200
IS41LV8200
ISSI
®
ELECTRICAL CHARACTERISTICS(1)
(Recommended Operating Conditions unless otherwise noted.)
Symbol Parameter
Test Condition
IIL
Input Leakage Current
IIO
V CC
Min.
Max.
Unit
Any input 0V ≤ VIN ≤ Vcc
Other inputs not under test = 0V
–5
5
µA
Output Leakage Current
Output is disabled (Hi-Z)
0V ≤ VOUT ≤ Vcc
–5
5
µA
VOH
Output High Voltage Level
IOH = –5.0 mA, Vcc = 5V
IOH = –2.0 mA, Vcc = 3.3V
2.4
—
V
VOL
Output Low Voltage Level
IOL = 4.2 mA, Vcc = 5V
IOL = 2 mA, Vcc = 3.3V
—
0.4
V
ICC1
Standby Current: TTL
RAS, CAS ≥ VIH
5V
3.3V
5V
3.3V
2
0.5
3
2
mA
—
—
—
5V
3.3V
—
—
1
0.5
mA
Commercial
Industrial
Speed
ICC2
Standby Current: CMOS
RAS, CAS ≥ VCC – 0.2V
ICC3
Operating Current:
Random Read/Write(2,3,4)
Average Power Supply Current
RAS, CAS,
Address Cycling, tRC = tRC (min.)
-50
-60
—
—
120
110
mA
ICC4
Operating Current:
EDO Page Mode(2,3,4)
Average Power Supply Current
RAS= VIL, CAS ≥ VIH
tRC = tRC (min.)
-50
-60
—
—
90
80
mA
ICC5
Refresh Current:
RAS-Only(2,3)
Average Power Supply Current
RAS Cycling, CAS ≥ VIH
tRC = tRC (min.)
-50
-60
—
—
120
110
mA
ICC6
Refresh Current:
CBR(2,3,5)
Average Power Supply Current
RAS, CAS Cycling
tRC = tRC (min.)
-50
-60
—
—
120
110
mA
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each EDO Page cycle.
5. Enables on-chip refresh and address counters.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
06/22/01
5
IS41C8200
IS41LV8200
ISSI
®
AC CHARACTERISTICS(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
-50
Symbol
Parameter
t RC
t RAC
t CAC
t AA
t RAS
t RP
t CAS
t CP
t CSH
t RCD
t ASR
t RAH
t ASC
t CAH
t AR
Random READ or WRITE Cycle Time
Access Time from RAS(6, 7)
Access Time from CAS(6, 8, 15)
Access Time from Column-Address(6)
RAS Pulse Width
RAS Precharge Time
CAS Pulse Width(23)
CAS Precharge Time(9)
CAS Hold Time (21)
RAS to CAS Delay Time(10, 20)
Row-Address Setup Time
Row-Address Hold Time
Column-Address Setup Time(20)
Column-Address Hold Time(20)
Column-Address Hold Time
(referenced to RAS)
RAS to Column-Address Delay Time(11)
Column-Address to RAS Lead Time
RAS to CAS Precharge Time
RAS Hold Time
RAS Hold Time from CAS Precharge
CAS to Output in Low-Z(15, 24)
CAS to RAS Precharge Time(21)
Output Disable Time(19, 24)
Output Enable Time(15, 16)
Output Enable Data Delay (Write)
OE HIGH Hold Time from CAS HIGH
OE HIGH Pulse Width
OE LOW to CAS HIGH Setup Time
Read Command Setup Time(17, 20)
Read Command Hold Time
(referenced to RAS)(12)
Read Command Hold Time
(referenced to CAS)(12, 17, 21)
Write Command Hold Time(17)
Write Command Hold Time
(referenced to RAS)(17)
Write Command Pulse Width(17)
WE Pulse Widths to Disable Outputs
t RAD
t RAL
t RPC
t RSH
t RHCP
t CLZ
t CRP
t OD
tOE
tOED
t OEHC
tOEP
tOES
t RCS
t RRH
t RCH
t WCH
t WCR
tWP
tWPZ
6
-60
Min.
Max.
Min.
Max.
Units
84
—
—
—
50
30
8
9
38
12
0
8
0
8
30
—
50
13
25
10K
—
10K
—
—
37
—
—
—
—
—
104
—
—
—
60
40
10
9
40
14
0
10
0
10
40
—
60
15
30
10K
—
10K
—
—
45
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
25
5
8
30
0
5
3
—
12
5
10
5
0
0
25
—
—
—
—
—
—
15
12
—
—
—
—
—
—
12
30
5
10
35
0
5
3
—
15
5
10
5
0
0
30
—
—
—
—
—
—
15
15
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
—
0
—
ns
8
40
—
—
10
50
—
—
ns
ns
8
7
—
—
10
7
—
—
ns
ns
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
06/22/01
IS41C8200
IS41LV8200
ISSI
®
AC CHARACTERISTICS (Continued)(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
-50
Symbol
Parameter
tRWL
Write Command to RAS Lead Time
tCWL
-60
Min.
Max.
Min.
Max.
Units
13
—
15
—
ns
Write Command to CAS Lead Time(17, 21)
8
—
10
—
ns
tWCS
Write Command Setup Time(14, 17, 20)
0
—
0
—
ns
t DHR
Data-in Hold Time (referenced to RAS)
39
—
39
—
ns
t ACH
Column-Address Setup Time to CAS
Precharge during WRITE Cycle
OE Hold Time from WE during
READ-MODIFY-WRITE cycle(18)
Data-In Setup Time(15, 22)
Data-In Hold Time(15, 22)
READ-MODIFY-WRITE Cycle Time
RAS to WE Delay Time during
READ-MODIFY-WRITE Cycle(14)
CAS to WE Delay Time(14, 20)
Column-Address to WE Delay Time(14)
EDO Page Mode READ or WRITE
Cycle Time
RAS Pulse Width in EDO Page Mode
Access Time from CAS Precharge(15)
READ-WRITE Cycle Time(24)
Data Output Hold after CAS LOW
Output Buffer Turn-Off Delay from
CAS or RAS(13,15,19, 24)
Output Disable Delay from WE
CAS Setup Time (CBR REFRESH)(20, 25)
CAS Hold Time (CBR REFRESH)( 21, 25)
OE Setup Time prior to RAS during
HIDDEN REFRESH Cycle
Auto Refresh Period
2,048 Cycles
Transition Time (Rise or Fall)(2, 3)
15
—
15
—
ns
8
—
10
—
ns
0
8
108
64
—
—
—
—
0
10
133
77
—
—
—
—
ns
ns
ns
ns
26
39
20
—
—
—
32
47
25
—
—
—
ns
ns
ns
50
—
56
5
0
100K
30
—
—
12
60
—
68
5
0
100K
35
—
—
15
ns
ns
ns
ns
ns
3
5
8
0
10
—
—
—
3
5
10
0
10
—
—
—
ns
ns
ns
ns
—
1
32
50
—
1
32
50
ms
ns
tOEH
t DS
t DH
t RWC
t RWD
t CWD
tAWD
t PC
tRASP
tCPA
tPRWC
tCOH
tOFF
tWHZ
t CSR
t CHR
tORD
tREF
tT
(17)
AC TEST CONDITIONS
Output load: Two TTL Loads and 50 pF (Vcc = 5.0V ±10%)
One TTL Load and 50 pF (Vcc = 3.3V ±10%)
Input timing reference levels: VIH = 2.4V, VIL = 0.8V (Vcc = 5.0V ±10%);
VIH = 2.0V, VIL = 0.8V (Vcc = 3.3V ±10%)
Output timing reference levels: VOH = 2.0V, VOL = 0.8V (Vcc = 5V ±10%, 3.3V ±10%)
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
06/22/01
7
IS41C8200
IS41LV8200
ISSI
®
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between VIH and
VIL (or between VIL and VIH) and assume to be 1 ns for all inputs.
3. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in a
monotonic manner.
4. If CAS and RAS = VIH, data output is High-Z.
5. If CAS = VIL, data output may contain data from the last valid READ cycle.
6. Measured with a load equivalent to one TTL gate and 50 pF.
7. Assumes that tRCD - tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase by the
amount that tRCD exceeds the value shown.
8. Assumes that tRCD • tRCD (MAX).
9. If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear the data
output buffer, CAS and RAS must be pulsed for tCP.
10. Operation with the tRCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD is
greater than the specified tRCD (MAX) limit, access time is controlled exclusively by tCAC.
11. Operation within the tRAD (MAX) limit ensures that tRCD (MAX) can be met. tRAD (MAX) is specified as a reference point only; if tRAD is
greater than the specified tRAD (MAX) limit, access time is controlled exclusively by tAA.
12. Either tRCH or tRRH must be satisfied for a READ cycle.
13. tOFF (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL.
14. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If tWCS • tWCS
(MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If tRWD • tRWD (MIN),
tAWD • tAWD (MIN) and tCWD • tCWD (MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from the selected
cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back to VIH) is
indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle.
15. Output parameter (I/O) is referenced to corresponding CAS input.
16. During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a LATE
WRITE or READ-MODIFY-WRITE is not possible.
17. Write command is defined as WE going low.
18. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (OE HIGH during WRITE cycle) in order to ensure
that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS remains LOW and
OE is taken back to LOW after tOEH is met.
19. The I/Os are in open during READ cycles once tOD or tOFF occur.
20. Determined by falling edge of CAS.
21. Determined by rising edge of CAS.
22. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or
READ-MODIFY-WRITE cycles.
23. CAS must meet minimum pulse width.
24. The 3 ns minimum is a parameter guaranteed by design.
25. Enables on-chip refresh and address counters.
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
06/22/01
IS41C8200
IS41LV8200
ISSI
®
READ CYCLE
tRC
tRAS
tRP
RAS
tCSH
tCRP
tRSH
tCAS tCLCH
tRCD
tRRH
CAS
tAR
tRAD
tASR
ADDRESS
tRAH
tRAL
tCAH
tASC
Row
Column
Row
tRCS
tRCH
WE
tAA
tRAC
tCAC
tCLC
I/O
tOFF(1)
Open
Open
Valid Data
tOE
tOD
OE
tOES
Don’t Care
Note:
1. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
06/22/01
9
IS41C8200
IS41LV8200
ISSI
®
READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE CYCLES)
tRWC
tRAS
tRP
RAS
tCSH
tCRP
tRSH
tCAS tCLCH
tRCD
CAS
tAR
tRAD
tRAH
tASR
tRAL
tCAH
tASC
tACH
ADDRESS
Row
Column
Row
tRWD
tCWL
tRWL
tCWD
tRCS
tAWD
tWP
WE
tAA
tRAC
tCAC
tCLZ
I/O
tDS
Open
Valid DOUT
tOE
tOD
tDH
Valid DIN
Open
tOEH
OE
Don’t Care
10
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
06/22/01
IS41C8200
IS41LV8200
ISSI
®
EARLY WRITE CYCLE (OE = DON'T CARE)
tRC
tRAS
tRP
RAS
tCSH
tCRP
tRSH
tCAS tCLCH
tRCD
CAS
tAR
tRAD
tASR
ADDRESS
tRAH
tRAL
tCAH
tACH
tASC
Row
Column
Row
tCWL
tRWL
tWCR
tWCS
tWCH
tWP
WE
tDHR
tDS
I/O
tDH
Valid Data
Don’t Care
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
06/22/01
11
IS41C8200
IS41LV8200
ISSI
®
EDO-PAGE-MODE READ CYCLE
tRASP
tRP
RAS
tCSH
tCRP
tCAS,
tCLCH
tRCD
tPC(1)
tCAS,
tCLCH
tCP
tCP
tRSH
tCAS,
tCLCH
tCP
CAS
tAR
tRAD
tASR
ADDRESS
tASC
tCAH tASC
Row
Column
tRAL
tCAH
tCAH tASC
Column
Column
Row
tRAH
tRRH
tRCS
tRCH
WE
tAA
tRAC
tCAC
tCLZ
I/O
Open
tAA
tCPA
tCAC
tCOH
Valid Data
tOE
tOES
tAA
tCPA
tCAC
tCLZ
tOFF
Valid Data
tOEHC
Valid Data
Open
tOE
tOD
tOES
tOD
OE
tOEP
Don’t Care
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
06/22/01
IS41C8200
IS41LV8200
ISSI
®
EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles)
tRASP
tRP
RAS
tCSH
tCRP
tCAS, tCLCH
tRCD
tCP
tPC / tPRWC(1)
tCAS, tCLCH
tRSH
tCAS, tCLCH
tCP
tCP
CAS
tASR
tRAH
ADDRESS
tAR
tRAD
tASC
tCAH
Row
tASC
tCAH
Column
tRWD
tRCS
tRAL
tCAH
tASC
Column
tCWL
tWP
Column
tRWL
tCWL
tWP
tCWL
tWP
tAWD
tCWD
Row
tAWD
tCWD
tAWD
tCWD
WE
tAA
tAA
tCPA
tDH
tDS
tRAC
tCAC
tCLZ
I/O
Open
tAA
tCPA
tDH
tDS
tCAC
tCLZ
DOUT
DIN
tOE
tCAC
tCLZ
DOUT
tOD
DIN
DOUT
tOD
tOE
tDH
tDS
Open
DIN
tOD
tOE
tOEH
OE
Don’t Care
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
06/22/01
13
IS41C8200
IS41LV8200
ISSI
®
EDO-PAGE-MODE EARLY-WRITE CYCLE
tRASP
tRP
RAS
tCSH
tCRP
tPC
tCAS,
tCLCH
tRCD
tCAS,
tCLCH
tCP
tCP
tRSH
tCAS,
tCLCH
tCP
CAS
tAR
tACH
tCAH tASC
tRAD
tASR
ADDRESS
tASC
Row
Column
tRAH
tACH
tRAL
tCAH
tACH
tCAH tASC
Column
tCWL
tWCS
Column
tCWL
tWCS
tWCH
tCWL
tWCS
tWCH
tWCH
tWP
tWP
Row
tWP
WE
tWCR
tDHR
tRWL
tDS
tDS
tDH
I/O
Valid Data
tDS
tDH
Valid Data
tDH
Valid Data
OE
Don’t Care
14
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
06/22/01
IS41C8200
IS41LV8200
ISSI
®
EDO-PAGE-MODE READ-EARLY-WRITE CYCLE
tRASP
tRP
RAS
tCSH
tPC
tPC
tCRP
tCAS
tRCD
tCAS
tCP
tRSH
tCAS
tCP
tCP
CAS
tASR
tRAH
ADDRESS
tAR
tRAD
tASC
Row
tCAH
tASC
tCAH
Column (A)
tASC
Column (B)
tRCS
tACH
tRAL
tCAH
Column (N)
Row
tRCH
tWCS
tWCH
WE
tAA
tCPA
tCAC
tRAC
tCAC
tAA
tWHZ
tCOH
I/O
Open
Valid Data (A)
tDS
Valid Data (B)
tDH
DIN
Open
tOE
OE
Don’t Care
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
06/22/01
15
IS41C8200
IS41LV8200
ISSI
®
AC WAVEFORMS
READ CYCLE (With WE-Controlled Disable)
RAS
tCSH
tCRP
tRCD
tCP
tCAS
CAS
tAR
tRAD
tASR
tRAH
ADDRESS
tCAH
tASC
Row
tASC
Column
Column
tRCS
tRCH
tRCS
WE
tAA
tRAC
tCAC
tCLZ
Open
I/O
tWHZ
tCLZ
Valid Data
Open
tOE
tOD
OE
Don’t Care
RAS-ONLY REFRESH CYCLE (OE, WE = DON'T CARE)
tRC
tRAS
tRP
RAS
tCRP
tRPC
CAS
tASR
ADDRESS
I/O
tRAH
Row
Row
Open
Don’t Care
16
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
06/22/01
IS41C8200
IS41LV8200
ISSI
®
CBR REFRESH CYCLE (Addresses; WE, OE = DON'T CARE)
tRP
tRAS
tRP
tRAS
RAS
tCHR
tRPC
tCP
tCHR
tRPC
tCSR
tCSR
CAS
Open
I/O
Don’t Care
HIDDEN REFRESH CYCLE(1) (WE = HIGH; OE = LOW)
tRAS
tRP
tRAS
RAS
tCRP
tRCD
tRSH
tCHR
CAS
tAR
tRAD
tRAH tASC
tASR
ADDRESS
Row
tRAL
tCAH
Column
tAA
tRAC
tOFF(2)
tCAC
tCLZ
I/O
Open
Valid Data
tOE
Open
tOD
tORD
OE
Don’t Care
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
06/22/01
17
IS41C8200
IS41LV8200
ISSI
ORDERING INFORMATION
ORDERING INFORMATION
Commercial Range: 0°° C to 70°° C
Voltage: 5V
Industrial Range: -40°° C to 85°C
Voltage: 5V
Speed (ns) Order Part No.
Package
Speed (ns) Order Part No.
Package
50
IS41C8200-50J
300-mil SOJ
50
IS41C8200-50JI
300-mil SOJ
60
IS41C8200-60J
300-mil SOJ
60
IS41C8200-60JI
300-mil SOJ
Voltage: 3.3V
Speed (ns) Order Part No.
®
Voltage: 3.3V
Package
Speed (ns) Order Part No.
Package
50
IS41LV8200-50J
300-mil SOJ
50
IS41LV8200-50JI
300-mil SOJ
60
IS41LV8200-60J
300-mil SOJ
60
IS41LV8200-60JI
300-mil SOJ
ISSI
®
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Tel: 1-800-379-4774
Fax: (408) 588-0806
E-mail: [email protected]
www.issi.com
18
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
06/22/01