PRELIMINARY Integrated Circuit Systems, Inc. ICS840004I FEMTOCLOCKS™CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER GENERAL DESCRIPTION FEATURES The ICS840004I is a 4 output LVCMOS/LVTTL Synthesizer optimized to generate Fibre Channel HiPerClockS™ reference clock frequencies and is a member of the HiPerClocksTM family of high performance clock solutions from ICS. Using a 26.5625MHz, 18pF parallel resonant crystal, the following frequencies can be generated based on the 2 frequency select pins (F_SEL1:0): 212.5MHz, 159.375MHz, 156.25MHz, 106.25MHz, and 53.125MHz. The ICS840004I uses ICS’ 3rd generation low phase noise VCO technology and can achieve 1ps or lower typical random rms phase jitter, easily meeting Fibre Channel jitter requirements. The ICS840004I is packaged in a small 20-pin TSSOP package. • Four LVCMOS/LVTTL outputs, 15Ω typical output impedance ICS • Selectable crystal oscillator interface or LVCMOS single-ended input • Supports the following input frequencies: 212.5MHz, 159.375MHz, 156.25MHz, 106.25MHz and 53.125MHz • RMS phase jitter @ 212.5MHz(2.55MHz - 20MHz): 0.49ps (typical) • Output supply modes: Core/Output 3.3V/3.3V 3.3V/2.5V 2.5V/2.5V • -40°C to 85°C ambient operating temperature FREQUENCY SELECT FUNCTION TABLE Input Frequency (MHz) 26.5625 F_SEL1 0 Inputs M Divider F_SEL0 Value 0 24 N Divider Value 3 M/N Ratio Value 8 Output Frequency Range (MHz) 212.5 26.5625 0 1 24 4 6 159.375 26.5625 1 0 24 6 4 106.25 26.5625 1 1 24 12 2 53.125 26.04166 0 1 24 4 6 156.25 BLOCK DIAGRAM OE PIN ASSIGNMENT Pullup 2 F_SEL1:0 Pullup:Pullup nPLL_SEL Pulldown nXTAL_SEL Pulldown XTAL_IN 26.5625MHz OSC F_SEL1:0 0 1 00 01 10 11 XTAL_OUT TEST_CLK Pulldown 1 Phase Detector VCO 0 N ÷3 ÷4 ÷6 ÷12 (default) Q0 Q1 MR 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 F_SEL1 GND Q0 Q1 VDDO Q2 Q3 GND XTAL_IN XTAL_OUT ICS840004I 20-Lead TSSOP Q2 M = ÷24 (fixed) F_SEL0 nc nXTAL_SEL TEST_CLK OE MR nPLL_SEL VDDA nc VDD Q3 6.5mm x 4.4mm x 0.92mm package body G Package Top View Pulldown The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 840004AGI www.icst.com/products/hiperclocks.html 1 REV. A JUNE 28, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS840004I FEMTOCLOCKS™CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER TABLE 1. PIN DESCRIPTIONS Number 2, 9 Name F_SEL0, F_SEL1 nc Unused 3 nXTAL_SEL Input Pulldown 4 TEST_CLK Input Pulldown 5 OE Input Pullup 6 MR Input Pulldown 7 nPLL_SEL Input Pulldown 8 VDDA Power 10 11, 12 13, 19 14, 15 17, 18 16 VDD XTAL_OUT, XTAL_IN GND Q3, Q2, Q1, Q0 VDDO Power 1, 20 Type Input Description Pullup Input Power Output Power Frequency select pin. LVCMOS/LVTTL interface levels. No connect. Selects between the crystal or TEST_CLK inputs as the PLL reference source. When HIGH, selects TEST_CLK. When LOW, selects XTAL inpus. LVCMOS/LVTTL interface levels. Single-ended LVCMOS/LVTTL clock input. Output enable pin. When HIGH, the outputs are active. When LOW, the outputs are in a high impedance state. LVCMOS/LVTTL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the otuputs to go low. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. PLL Bypass. When LOW, the output is driven from the VCO output. When HIGH, the PLL is bypassed and the output frequency = reference clock frequency/N output divider. LVCMOS/LVTTL interface levels. Analog supply pin. Core supply pin. Crystal oscillator interface. XTAL_OUT is the output. XTAL_IN is the input. Power supply ground. Single-ended clock outputs. LVCMOS/LVTTL interface levels. 15Ω typical output impedence. Output supply pin. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance Test Conditions Minimum Typical Maximum Units 4 pF VDD, VDDA, VDDO = 3.465V TBD pF VDD, VDDA = 3.465V, VDDO = 2.625V TBD pF VDD, VDDA, VDDO = 2.625V TBD pF 51 kΩ CPD Power Dissipation Capacitance RPULLUP Input Pullup Resistor RPULLDOWN Input Pulldown Resistor 51 kΩ ROUT Output Impedance 15 Ω 840004AGI www.icst.com/products/hiperclocks.html 2 REV. A JUNE 28, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS840004I FEMTOCLOCKS™CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDD + 0.5V Package Thermal Impedance, θJA 73.2°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDDD = VDDA = 3.3V±5%, VDDO = 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C Symbol VDD Parameter Core Supply Voltage Test Conditions Minimum 3.135 Typical 3.3 Maximum 3.465 Units V VDDA Analog Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 3.135 3.3 3.465 V 2.375 2.5 2.625 V IDD Power Supply Current 90 mA IDDA IDDO Analog Supply Current Output Supply Current 8 5 mA mA TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V±5%, TA = -40°C TO 85°C Symbol VDD Parameter Core Supply Voltage VDDA Test Conditions Minimum 2.375 Typical 2.5 Maximum 2.625 Units V Analog Supply Voltage 2.375 2.5 2.625 V 2.375 2.5 2.625 VDDO Output Supply Voltage IDD Power Supply Current 80 mA IDDA IDDO Analog Supply Current Output Supply Current 8 5 mA mA 840004AGI www.icst.com/products/hiperclocks.html 3 V REV. A JUNE 28, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS840004I FEMTOCLOCKS™CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER TABLE 3D. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5% OR 2.5V±5%, OR VDD = VDDA = 3.3V±5%, VDDO = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL Input Low Current Test Conditions OE, F_SEL0, F_SEL1 nPLL_SEL, MR, nXTAL_SEL, TEST_CLK OE, F_SEL0, F_SEL1 nPLL_SEL, MR, nXTAL_SEL, TEST_CLK VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 Minimum Typical Maximum Units VDD = 3.3V 2 VDD + 0.3 V VDD = 2.5V 1.7 VDD + 0.3 V VDD = 3.3V -0.3 0.8 V VDD = 2.5V VDD = VIN = 3.465V or 2.625V VDD = VIN = 3.465V or 2.625V VDD = 3.465V or 2.625V, VIN = 0V -0.3 0.7 V 5 µA 150 µA -150 µA VDD = 3.465V or 2.625V, VIN = 0V -5 µA VDDO = 3.3V ± 5% 2. 6 V VDDO = 2.5V ± 5% 1.8 V VDDO = 3.3V or 2.5V ± 5% 0. 5 V NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Information, Output Load Test Circuit. TABLE 4. CRYSTAL CHARACTERISTICS Parameter Test Conditions Mode of Oscillation Minimum Typical Maximum Units Fundamental Frequency 26.5625 MHz Ω Equivalent Series Resistance (ESR) 50 Shunt Capacitance 7 pF Drive Level 1 mW NOTE: Characterized using an 18pf parallel resonant cr ystal. 840004AGI www.icst.com/products/hiperclocks.html 4 REV. A JUNE 28, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS840004I FEMTOCLOCKS™CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum 212.5 fOUT tsk(o) tjit(Ø) tR / tF Output Frequency Output Skew; NOTE 1, 2 RMS Phase Jitter (Random); NOTE 3 Output Rise/Fall Time Units MHz 159.375 MHz 156.25 MHz 106.25 MHz 53.125 MHz TBD ps 212.5MHz (2.55MHz - 20MHz) 0.49 ps 159.375MHz (1.875MHz - 20MHz) 0.55 ps 156.25MHz (1.875MHz - 20MHz) TBD ps 106.25MHz (637kHz - 5MHz) 0.79 ps 53.125MHz (637kHz - 5MHz) TBD ps 20% to 80% 400 ps odc Output Duty Cycle 50 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plot. % TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 2.5V±5%, TA = -40°C TO 85°C Symbol fOUT tsk(o) tjit(Ø) t R / tF Parameter Test Conditions Output Frequency Output Skew; NOTE 1, 2 RMS Phase Jitter (Random); NOTE 3 Output Rise/Fall Time Minimum Typical Units 212.5 MHz 159.375 MHz 156.25 MHz 106.25 MHz 53.125 MHz TBD ps 212.5MHz (2.55MHz - 20MHz) 0.46 ps 159.375MHz (1.875MHz - 20MHz) 0.54 ps 156.25MHz (1.875MHz - 20MHz) 0.57 ps 106.25MHz (637kHz - 5MHz) 0.73 ps 53.125MHz (637kHz - 5MHz) 0.63 ps 20% to 80% 450 ps odc Output Duty Cycle 50 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plot. 840004AGI Maximum www.icst.com/products/hiperclocks.html 5 % REV. A JUNE 28, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS840004I FEMTOCLOCKS™CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER TABLE 5C. AC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical 212.5 fOUT tsk(o) tjit(Ø) tR / tF Output Frequency Output Skew; NOTE 1, 2 RMS Phase Jitter (Random); NOTE 3 Output Rise/Fall Time Units MHz 159.375 MHz 156.25 MHz 106.25 MHz 53.125 MHz TBD ps 212.5MHz (2.55MHz - 20MHz) 0.51 ps 159.375MHz (1.875MHz - 20MHz) 0.51 ps 156.25MHz (1.875MHz - 20MHz) 0.54 ps 106.25MHz (637kHz - 5MHz) 0.72 ps 53.125MHz (637kHz - 5MHz) 0.71 ps 20% to 80% 450 ps odc Output Duty Cycle 50 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plot. 840004AGI Maximum www.icst.com/products/hiperclocks.html 6 % REV. A JUNE 28, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS840004I FEMTOCLOCKS™CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER PARAMETER MEASUREMENT INFORMATION 2.05V±5% 1.25V±5% 1.65V±5% SCOPE VDD , VDDA, VDDO Qx LVCMOS SCOPE VDD , VDDA VDDO Qx LVCMOS GND GND -1.25V±5% -1.65V±5% 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT 3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT 1.25V±5% Noise Power Phase Noise Plot SCOPE VDD , VDDA, VDDO Qx LVCMOS Phase Noise Mask GND Offset Frequency f1 RMS Jitter = Area Under the Masked Phase Noise Plot -1.25V±5% 2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT RMS PHASE JITTER V DDO Qx 80% 80% tR tF 2 Clock Outputs V DDO Qy f2 20% 20% 2 tsk(o) OUTPUT SKEW OUTPUT RISE/FALL TIME V DDO 2 Q0:Q3 t PW t odc = PERIOD t PW x 100% t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 840004AGI www.icst.com/products/hiperclocks.html 7 REV. A JUNE 28, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS840004I FEMTOCLOCKS™CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS840004I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10µF and a .01μF bypass capacitor should be connected to each VDDA. 3.3V or 2.5V VDD .01μF 10Ω V DDA .01μF 10μF FIGURE 1. POWER SUPPLY FILTERING CRYSTAL INPUT INTERFACE determined using a 26.5625MHz 18pF parallel resonant crystal and were chosen to minimize the ppm error. The ICS840004I has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were XTAL_IN C1 22p X1 18pF Parallel Cry stal XTAL_OUT C2 22p ICS84332 Figure 2. CRYSTAL INPUt INTERFACE 840004AGI www.icst.com/products/hiperclocks.html 8 REV. A JUNE 28, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS840004I FEMTOCLOCKS™CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER LAYOUT GUIDELINE and C2=22pF are recommended for frequency accuracy. For different board layout, the C1 and C2 may be slightly adjusted for optimizing frequency accuracy. 1KΩ pullup or pulldown resistors can be used for the logic control input pins. Figure 3 shows a schematic example of the ICS840004I. An example of LVCMOS termination is shown in this schematic. Additional LVCMOS termination approaches are shown in the LVCMOS Termination Application Note. In this example, an 18 pF parallel resonant 26.5625MHz crystal is used. The C1=22pF Logic Control Input Examples Set Logic Input to '1' VDD Set Logic Input to '0' VDD RU1 1K VDD=3.3V VDDO=3.3V RU2 Not Install To Logic Input pins R3 36 RD1 Not Install RD2 1K U1 VDDO VDD VDD VDDA R2 10 Zo = 50 Ohm To Logic Input pins C3 10uF VDD C4 0.01u 1 2 3 4 5 6 7 8 9 10 F_SEL0 nc nXTAL_SEL TEST_CLK OE MR nPLL_SEL VDDA nc VDD F_SEL1 GND Q0 Q1 VDDO Q2 Q3 GND XTAL_IN XTAL_OUT LVCMOS 20 19 18 17 16 15 14 13 12 11 VDD R5 100 C6 0.1u Zo = 50 Ohm C5 0.1u ICS840004i R4 100 XTAL_OUT C2 22pF LVCMOS X1 XTAL_IN Optional Termination C1 22pF If not using the crystal input, it can be left floating. For additional protection the XTAL_IN pin can be tied to ground. Unused outputs can be left floating. There should be no trace attached to unused outputs. Device characterized and specification limits set with all outputs terminated. FIGURE 3. ICS840004I SCHEMATIC EXAMPLE RELIABILITY INFORMATION TABLE 6. θJAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP θ JA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 114.5°C/W 73.2°C/W 98.0°C/W 66.6°C/W 88.0°C/W 63.5°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS840004I is: 3085 840004AGI www.icst.com/products/hiperclocks.html 9 REV. A JUNE 28, 2005 PRELIMINARY Integrated Circuit Systems, Inc. PACKAGE OUTLINE - G SUFFIX ICS840004I FEMTOCLOCKS™CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER FOR 20 LEAD TSSOP TABLE 7. PACKAGE DIMENSIONS Millimeters SYMBOL MIN N MAX 20 A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 6.40 E E1 6.60 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 840004AGI www.icst.com/products/hiperclocks.html 10 REV. A JUNE 28, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS840004I FEMTOCLOCKS™CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS840004AGI ICS840004AGI 20 Lead TSSOP tube -40°C to 85°C ICS840004AGIT ICS840004AGI 20 Lead TSSOP 2500 tape & reel -40°C to 85°C The aforementioned trademarks, HiPerClockS™ and FEMTOCLOCKS™ are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 840004AGI www.icst.com/products/hiperclocks.html 11 REV. A JUNE 28, 2005