Maxim MAX5037A Vrm 9.0/vrm 9.1, dual-phase, parallelable, average-current-mode controller Datasheet

19-3033; Rev 1; 4/04
VRM 9.0/VRM 9.1, Dual-Phase,
Parallelable, Average-Current-Mode Controller
The MAX5037A dual-phase, PWM controller provides
high-output-current capability in a compact package
with a minimum number of external components. The
MAX5037A utilizes a dual-phase, average-current-mode
control that enables optimal use of low R DS(ON)
MOSFETs, eliminating the need for external heatsinks
even when delivering high output currents.
Differential sensing enables accurate control of the
output voltage, while adaptive voltage positioning
provides optimum transient response. An internal regulator enables operation with either +5V or +12V input voltage without the need for additional voltage sources. The
high switching frequency, up to 500kHz per phase, and
dual-phase operation allow the use of low output inductor values and input capacitor values. This accommodates the use of PC board-embedded planar magnetics
achieving superior reliability, current sharing, thermal
management, compact size, and low system cost.
The MAX5037A also features a clock input (CLKIN) for
synchronization to an external clock, and a clock output
(CLKOUT) with programmable phase delay (relative to
CLKIN) for paralleling multiple phases. The MAX5037A
also limits the reverse current in case the bus voltage
becomes higher than the regulated output voltage.
The MAX5037A operates over the extended temperature
range (-40°C to +85°C) and is available in 44-pin MQFP
or thin QFN packages. Refer to the MAX5038A/
MAX5041A and MAX5065/MAX5067 data sheets for
either a fixed output voltage controller or an adjustable
output voltage controller in an SSOP or thin QFN package.
Applications
Servers and Workstations
Point-of-Load High-Current/High-Density
Telecom DC-DC Regulators
Features
♦ +4.75V to +5.5V or +8V to +28V Input Voltage
Range
♦ Up to 60A Output Current
♦ Internal Voltage Regulator for a +12V or +24V
Power Bus
♦ Internal 5-Bit DAC VID Control (VRM 9.0/VRM 9.1
Compliant, 0.8% Accuracy)
♦ Programmable Adaptive Output Voltage
Positioning
♦ True Differential Remote Output Sensing
♦ Out-of-Phase Controllers Reduce Input
Capacitance Requirement and Distribute Power
Dissipation
♦ Average-Current-Mode Control
Superior Current Sharing Between Individual
Phases and Paralleled Modules
Accurate Current Limit Eliminates MOSFET and
Inductor Derating
♦ Limits Reverse-Current Sinking in Paralleled
Modules
♦ Integrated High-Output-Current Gate Drivers
♦ Selectable Fixed Frequency 250kHz or 500kHz per
Phase (Up to 1MHz for Two Phases)
♦ External Frequency Synchronization from 125kHz
to 600kHz
♦ Internal PLL with Clock Output for Paralleling
Multiple DC-DC Converters
♦ Power-Good Output
♦ Phase Failure Detector
Networking Systems
♦ Overvoltage and Thermal Protection
Large-Memory Arrays
♦ 44-Pin MQFP or Thin QFN Packages
RAID Systems
Ordering Information
High-End Desktop Computers
TEMP RANGE
PIN-PACKAGE
MAX5037AEMH
PART
-40°C to +85°C
44 MQFP
MAX5037AETH
-40°C to +85°C
44 Thin QFN
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX5037A
General Description
MAX5037A
VRM 9.0/VRM 9.1, Dual-Phase,
Parallelable, Average-Current-Mode Controller
ABSOLUTE MAXIMUM RATINGS
Continuous Power Dissipation (TA = +70°C)
44-Pin MQFP (derate 12.7mW/°C above +70°C).......1013mW
44-Pin Thin QFN (derate 27.0mW/°C
above +70°C) ...........................................................2162.2mW
Package Thermal Resistance, θJC (Thin QFN only) ........+2°C/W
Operating Temperature Range ...........................-40°C to +85°C
Maximum Junction Temperature .....................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
IN to SGND.............................................................-0.3V to +30V
BST_ to SGND…………………………………….… .-0.3V to +35V
DH_ to LX_ .................................-0.3V to [(VBST_ - VLX_) + 0.3V]
DL_ to PGND ..............................................-0.3V to (VDD + 0.3V)
BST_ to LX_ ..............................................................-0.3V to +6V
VCC to SGND............................................................-0.3V to +6V
VDD to PGND............................................................-0.3V to +6V
SGND to PGND .....................................................-0.3V to +0.3V
All Other Pins to SGND...............................-0.3V to (VCC + 0.3V)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = VDD = +5V, circuit of Figure 1, TA = -40°C to +85°C, unless otherwise noted. Typical specifications are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SYSTEM SPECIFICATIONS
8
28
4.75
5.5
Input Voltage Range
VIN
Quiescent Supply Current
IQ
EN = VCC or SGND, VID inputs
unconnected
4
Efficiency
η
ILOAD = 52A (26A per phase)
90
Short IN and VCC together for 5V input
operation
6
V
mA
%
STARTUP/INTERNAL REGULATOR
VCC Undervoltage Lockout
UVLO
VCC rising
4.0
VCC Undervoltage Lockout
Hysteresis
4.15
4.5
200
VCC Output Accuracy
VIN = 8V to 28V, ISOURCE = 0 to 80mA
4.85
5.1
V
mV
5.30
V
VOUT/ADAPTIVE VOLTAGE POSITIONING (AVP)
RREG = RF = 100kΩ, RIN = 1kΩ, no load,
Figure 3
Nominal Output Voltage
Accuracy (VID Setting)
VIN = VCC = 4.75V to 5.5V, or VIN = 8V to
28V, RREG = RF = 100kΩ, RIN = 1kΩ,
no load, Figure 3
Maximum REG Loading
IREG_MAX
REG Accuracy (Voltage
Positioning)
d (∆VOUT)
Maximum CNTR Loading
ICNTR_MAX
Center Voltage Set-Point
Accuracy (Note 2)
d (∆VCNTR)
-0.8
+0.8
%
-1
+1
50
µA
TA = 0°C to +85°C
-3
+3
TA = -40°C to +85°C
-5
+5
50
%
µA
TA = 0°C to +85°C
-3
+3
TA = -40°C to +85°C
-5
+5
%
MOSFET DRIVERS
Output Driver Impedance
Output Driver Peak Source/Sink
Current
2
RON
IDH_, IDL_
Low or high output
1
4
_______________________________________________________________________________________
3
Ω
A
VRM 9.0/VRM 9.1, Dual-Phase,
Parallelable, Average-Current-Mode Controller
(VCC = VDD = +5V, circuit of Figure 1, TA = -40°C to +85°C, unless otherwise noted. Typical specifications are at TA = +25°C.) (Note 1)
PARAMETER
Nonoverlap Time
SYMBOL
tNO
CONDITIONS
MIN
CDH_/DL_ = 5nF
TYP
MAX
60
UNITS
ns
OSCILLATOR AND PLL
Switching Frequency
fSW
PLL Lock Range
fPLL
PLL Locking Time
tPLL
CLKOUT Phase Shift
(at fSW = 125kHz)
φCLKOUT
CLKIN = SGND
238
250
262
CLKIN = VCC
475
500
525
125
600
200
kHz
µs
PHASE = VCC
115
120
125
PHASE = unconnected
85
90
95
PHASE = SGND
55
60
65
ICLKIN
3
5
7
CLKIN High Threshold
VCLKINH
2.4
CLKIN Low Threshold
VCLKINL
CLKIN Input Pulldown Current
kHz
Degrees
µA
V
0.8
V
CLKIN High Pulse Width
tCLKIN
200
ns
PHASE High Threshold
VPHASEH
4
V
PHASE Low Threshold
VPHASEL
PHASE Input Bias Current
IPHASEBIAS
-50
CLKOUT Output Low Level
VCLKOUTL
ISINK = 2mA (Note 3)
CLKOUT Output High Level
VCLKOUTH
ISOURCE = 2mA (Note 3)
4.5
VCL
CSP_ to CSN_
45
Reverse Current-Limit Threshold
VCLR
CSP_ to CSN_
-3.9
Cycle-by-Cycle Current Limit
VCLPK
CSP_ to CSN_ (Note 3)
1
V
+50
µA
100
mV
V
CURRENT LIMIT
Average Current-Limit Threshold
Cycle-by-Cycle Overload
Response Time
tR
90
VCSP_ to VCSN_ = +150mV
48
112
51
mV
-0.2
mV
130
mV
260
ns
CURRENT-SENSE AMPLIFIER
CSP_ to CSN_ Input Resistance
Common-Mode Range
Input Offset Voltage
RCS_
4
kΩ
VCMR(CS)
-0.3
+3.6
V
VOS(CS)
-1
+1
mV
Amplifier Gain
AV(CS)
18
V/V
3dB Bandwidth
f3dB
4
MHz
CURRENT-ERROR AMPLIFIER (TRANSCONDUCTANCE AMPLIFIER)
Transconductance
gmca
Open-Loop Gain
AVOL(CE)
No load
550
µS
50
dB
DIFFERENTIAL VOLTAGE AMPLIFIER (DIFF)
Common-Mode Voltage Range
VCMR(DIFF)
DIFF Output Voltage
VCM
Input Offset Voltage
VOS(DIFF)
Amplifier Gain
AV(DIFF)
3dB Bandwidth
f3dB
Minimum Output Current Drive
IOUT(DIFF)
-0.3
VSENSE+ = VSENSE- = 0
+1.0
V
+2
mV
0.6
-2
0.997
CDIFF = 20pF
1
3
1.0
V
1.003
V/V
MHz
mA
_______________________________________________________________________________________
3
MAX5037A
ELECTRICAL CHARACTERISTICS (continued)
MAX5037A
VRM 9.0/VRM 9.1, Dual-Phase,
Parallelable, Average-Current-Mode Controller
ELECTRICAL CHARACTERISTICS (continued)
(VCC = VDD = +5V, circuit of Figure 1, TA = -40°C to +85°C, unless otherwise noted. Typical specifications are at TA = +25°C.) (Note 1)
PARAMETER
SENSE+ to SENSE- Input
Resistance
SYMBOL
CONDITIONS
RVS_
MIN
TYP
MAX
UNITS
50
100
kΩ
70
dB
VOLTAGE-ERROR AMPLIFIER (EAOUT)
Open-Loop Gain
AVOL(EA)
Unity-Gain Bandwidth
fUGEA
EAN Input Bias Current
IB(EA)
Error-Amplifier Output Clamping
Voltage
3
CNTR and REG = open, VEAN = 2.0V
VCLAMP(EA) With respect to VCM
MHz
-100
+100
nA
810
918
mV
POWER-GOOD, PHASE FAILURE DETECTION, OVERVOLTAGE PROTECTION, AND THERMAL SHUTDOWN
PGOOD Trip Level
PGOOD Output Low Level
VOV
VUV
VPGLO
PGOOD goes low when VOUT is outside of
this window
IPG
PGOOD = VCC
Phase Failure Trip Threshold
VPH
PGOOD goes low when CLP_ is higher than
VPH
OVPTH
OVPOUT Source/Sink Current
IOVPOUT
OVPIN Input Resistance
ROVPIN
Thermal Shutdown
TSHDN
+8
+10
% VO
-12.5
-10
-8.5
(VID)
ISINK = 4mA
PGOOD Output Leakage Current
OVPIN Trip Threshold
+6
Above VID programmed output voltage
0.20
V
1
µA
2.0
+10
+13
15
20
V
+16
% VO
(VID)
VOVPOUT = 2.5V
190
Thermal-Shutdown Hysteresis
280
mA
370
kΩ
150
°C
8
°C
LOGIC INPUTS FOR VID
Logic-Input Pullup Resistors
Logic-Input Low Voltage
RVID
8
12
VIL
Logic-Input High Voltage
VIH
VID Internal Pullup Voltage
VVID
20
kΩ
0.8
V
1.7
All VID_ inputs unconnected
2.8
V
2.9
3.2
V
EN INPUT
EN Input Low Voltage
VENL
EN Input High Voltage
VENH
3
IEN
4.5
EN Pullup Current
1
5
5.5
Note 1: Specifications from -40°C to 0°C are guaranteed by characterization but not production tested.
Note 2: CNTR voltage accuracy is defined as the center of the adaptive voltage-positioning window (see Adaptive Voltage
Positioning section).
Note 3: Guaranteed by design. Not production tested.
Note 4: See Peak-Current Comparator section.
4
V
V
_______________________________________________________________________________________
µA
VRM 9.0/VRM 9.1, Dual-Phase,
Parallelable, Average-Current-Mode Controller
f = 500kHz
60
VIN = +5V
VOUT = +1.8V
30
20
VOUT = +1.8V
fSW = 250kHz
VIN = +24V
VOUT = +1.8V
fSW = 125kHz
10
0
IOUT (A)
IOUT (A)
EFFICIENCY vs. OUTPUT CURRENT
AND OUTPUT VOLTAGE
EFFICIENCY vs. OUTPUT CURRENT
AND OUTPUT VOLTAGE
SUPPLY CURRENT
vs. FREQUENCY AND INPUT VOLTAGE
80
VOUT = +1.5V
70
60
50
40
40
30
30
20
20
VIN = +12V
fSW = 250kHz
10
0
VOUT = +1.8V
ICC (mA)
VOUT = +1.1V
50
90
VOUT = +1.8V
12.0
11.5
11.0
10.5
MAX5037A toc05
MAX5037A toc04
VOUT = +1.5V
100
VOUT = +1.1V
VIN = +24V
10.0
9.5
9.0
8.5
8.0
VIN = +12V
7.5
7.0
6.5
6.0
VIN = +5V
fSW = 500kHz
0
MAX5037A toc06
0 4 8 12 16 20 24 28 32 36 40 44 48 52
IOUT (A)
η (%)
VIN = +5V
EXTERNALCLOCK
NO DRIVER LOAD
0 4 8 12 16 20 24 28 32 36 40 44 48 52
0 4 8 12 16 20 24 28 32 36 40 44 48 52
100 150 200 250 300 350 400 450 500 550 600
IOUT (A)
IOUT (A)
FREQUENCY (kHz)
SUPPLY CURRENT
vs. TEMPERATURE AND FREQUENCY
SUPPLY CURRENT
vs. TEMPERATURE AND FREQUENCY
SUPPLY CURRENT
vs. LOAD CAPACITANCE PER DRIVER
250kHz
600kHz
150
70
100
500kHz
90
80
70
125
ICC (mA)
60
125kHz
50
40
MAX5037A toc09
90
80
175
MAX5037A toc07
100
ICC (mA)
η (%)
40
30
0 4 8 12 16 20 24 28 32 36 40 44 48 52
60
100
60
50
40
75
30
0
50
40
0
70
10
60
0 4 8 12 16 20 24 28 32 36 40 44 48 52
80
ICC (mA)
50
10
90
20
70
VIN = +5V
60
20
100
10
80
MAX5037A toc08
40
90
η (%)
η (%)
f = 250kHz
70
50
VIN = +12V
70
80
η (%)
90
80
EFFICIENCY vs. OUTPUT CURRENT
100
MAX5037A toc02
90
100
MAX5037A toc01
100
EFFICIENCY vs. OUTPUT CURRENT
AND INPUT VOLTAGE
MAX5037A toc03
EFFICIENCY vs. OUTPUT CURRENT AND
INTERNAL OSCILLATOR FREQUENCY
VIN = +12V
CDL_ = 22nF
CDH_ = 8.2nF
50
30
20
VIN = +5V
CDL_ = 22nF
CDH_ = 8.2nF
25
-40
-15
10
35
TEMPERATURE (°C)
60
85
VIN = +12V
fSW = 250kHz
10
0
-40
-15
10
35
TEMPERATURE (°C)
60
85
1
3
5
7
9
11
13
15
CDRIVER (nF)
_______________________________________________________________________________________
5
MAX5037A
Typical Operating Characteristics
(Circuit of Figure 1, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(Circuit of Figure 1, TA = +25°C, unless otherwise noted.)
53
1.9
2.1
MAX5037A toc11
54
VOUT = +1.8V
1.8
2.0
1.8
1.6
1.7
1.5
49
PHASE 2
1.4
48
PHASE 1
1.3
47
1.2
46
1.1
45
OVPTH (V)
1.7
51
50
1.8
1.3
VOUT = +1.1V
1.2
1.1
VIN (V)
VIN (V)
UNDERVOLTAGE THRESHOLD (PGOOD)
vs. INPUT VOLTAGE
OUTPUT VOLTAGE
vs. ILOAD AND RCNTR
OUTPUT VOLTAGE
vs. ILOAD AND RCNTR
1.4
1.5
1.6
1.7
MAX5037A toc13
1.90
VOUT = +1.8V
RCNTR = 50kΩ
1.85
1.60
MAX5037A toc14
1.3
VIN = +12V
VID SETTING = +1.4V
1.55
RCNTR = 50kΩ
1.50
1.45
VOUT (V)
1.25
VOUT (V)
1.80
1.35
RCNTR = 100kΩ
1.75
1.15
1.05
RCNTR = 200kΩ
0.95
RCNTR = 100kΩ
RCNTR = 200kΩ
RCNTR = ∞
RCNTR = ∞
1.25
VIN = +12V
VID SETTING = +1.75V
0.85
1.60
0
4.75 4.80 4.85 4.90 4.95 5.00 5.05 5.10 5.15 5.20 5.25
1.40
1.30
1.65
0.75
1.45
1.35
1.70
VOUT = +1.1V
1.20
5 10 15 20 25 30 35 40 45 50 55
0
5 10 15 20 25 30 35 40 45 50 55
ILOAD (A)
ILOAD (A)
OUTPUT VOLTAGE vs. OUTPUT CURRENT
AND ERROR AMP GAIN (RF / RIN)
DIFFERENTIAL AMPLIFIER BANDWIDTH
DIFF OUTPUT ERROR
vs. SENSE+ TO SENSE- VOLTAGE
PHASE
2.5
Rf / RIN = 12.5
GAIN (V/V)
1.75
1.70
Rf / RIN = 10
0
5 10 15 20 25 30 35 40 45 50 55
ILOAD (A)
0.175
0
0.150
-45
-90
1.5
1.0
-135
GAIN
0.5
1.60
45
2.0
Rf / RIN = 7.5
1.65
0.200
0
0.01
0.1
1
10
ERROR (%)
3.0
90
PHASE (DEGREES)
Rf / RIN = 15
1.80
MAX5037A toc17
3.5
MAX5037A toc16
VIN = +12V
VOUT = +1.8V
MAX5037A toc18
VIN (V)
1.85
MAX5037A toc15
4.75 4.80 4.85 4.90 4.95 5.00 5.05 5.10 5.15 5.20 5.25
VOUT (V)
1.2
1.55
6
1.5
4.75 4.80 4.85 4.90 4.95 5.00 5.05 5.10 5.15 5.20 5.25
1.1
1.75
1.65
1.6
1.4
VOUT = +1.1V
1.0
1.0
VOUT = +1.8V
1.9
52
VOV (V)
(VCSP_ - VCSN_) (mV)
2.0
MAX5037A toc10
55
VUV (V)
OVERVOLTAGE THRESHOLD (OVPOUT)
vs. INPUT VOLTAGE
OVERVOLTAGE THRESHOLD (PGOOD)
vs. INPUT VOLTAGE
MAX5037A toc12
CURRENT-SENSE THRESHOLD
vs. OUTPUT VOLTAGE
VOUT (V)
MAX5037A
VRM 9.0/VRM 9.1, Dual-Phase,
Parallelable, Average-Current-Mode Controller
VIN = +12V
NO DRIVER
0.125
0.100
0.075
-180
0.050
-225
0.025
-270
0
1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0
FREQUENCY (MHz)
_______________________________________________________________________________________
∆VSENSE (V)
VRM 9.0/VRM 9.1, Dual-Phase,
Parallelable, Average-Current-Mode Controller
VCC LOAD REGULATION
vs. INPUT VOLTAGE
VCC LINE REGULATION
ICC = 0
5.20
5.15
5.10
VIN = +8V
4.95
4.90
4.85
DC LOAD
4.80
5.00
5.00
4.95
4.90
4.90
4.85
4.85
4.80
4.80
15 30 45 60 75 90 105 120 135 150
ICC = 80mA
4.75
8
10 12 14 16 18 20 22 24 26 28
8
9
10
11
12
13
ICC (mA)
VIN (V)
VIN (V)
DRIVER RISE TIME
vs. DRIVER LOAD CAPACITANCE
DRIVER FALL TIME
vs. DRIVER LOAD CAPACITANCE
HIGH-SIDE DRIVER (DH_)
SINK AND SOURCE CURRENT
80
70
60
50
40
DL_
DH_
30
20
10
0
11
16
21
26
31
MAX5037A toc23
80
70
60
50
40
DL_
36
DH_
1.6A/div
DH_
30
20
10
0
VIN = +12V
fSW = 250kHz
6
100
90
tR (ns)
100
90
MAX5037A toc24
120
110
MAX5037A toc22
120
110
1
5.05
4.95
4.75
0
tR (ns)
5.10
ICC = 40mA
5.05
VCC (V)
5.00
VCC (V)
VCC (V)
5.05
MAX5037A toc21
VIN = +12V
5.10
5.20
5.15
5.25
MAX5037A toc20
VIN = +24V
5.15
VCC LINE REGULATION
5.25
MAX5037A toc19
5.20
VIN = +12V
CDH_ = 22nF
VIN = +12V
fSW = 250kHz
1
6
11
CDRIVER (nF)
16
21
26
31
100ns/div
36
CDRIVER (nF)
PLL LOCKING TIME
250kHz TO 350kHz AND
350kHz TO 250kHz MAX5037A toc26
LOW-SIDE DRIVER (DL_)
SINK AND SOURCE CURRENT
MAX5037A toc25
PLL LOCKING TIME
250kHz TO 500kHz AND
500kHz TO 250kHz MAX5037A toc27
CLKOUT
5V/div
350kHz
PLLCMP
DL_
1.6A/div 200mV/div
CLKOUT
5V/div
250kHz
500kHz
PLLCMP
200mV/div
0
250kHz
VIN = +12V
CDL_ = 22nF
VIN = +12V
NO LOAD
VIN = +12V
NO LOAD
0
100ns/div
MAX5037A
Typical Operating Characteristics (continued)
(Circuit of Figure 1, TA = +25°C, unless otherwise noted.)
100µs/div
100µs/div
_______________________________________________________________________________________
7
MAX5037A
VRM 9.0/VRM 9.1, Dual-Phase,
Parallelable, Average-Current-Mode Controller
Typical Operating Characteristics (continued)
(Circuit of Figure 1, TA = +25°C, unless otherwise noted.)
PLL LOCKING TIME
250kHz TO 150kHz AND
150kHz TO 250kHz MAX5037A toc28
HIGH-SIDE DRIVER (DH_)
RISE TIME
HIGH-SIDE DRIVER (DH_)
FALL TIME
MAX5037A toc29
MAX5037A toc30
CLKOUT
5V/div
DH_
2V/div
DH_
2V/div
250kHz
PLLCMP
200mV/div
150kHz
0
VIN = +12V
CDH_ = 22nF
VIN = +12V
CDH_ = 22nF
VIN = +12V
NO LOAD
100µs/div
40ns/div
40ns/div
LOW-SIDE DRIVER (DL_)
RISE TIME
LOW-SIDE DRIVER (DL_)
FALL TIME
OUTPUT RIPPLE
MAX5037A toc32
MAX5037A toc31
MAX5037A toc33
DL_
2V/div
DL_
2V/div
VOUT
(AC-COUPLED)
10mV/div
VIN = +12V
VOUT = +1.75V
IOUT = 52A
VIN = +12V
CDL_ = 22nF
VIN = +12V
CDL_ = 22nF
40ns/div
40ns/div
500ns/div
VPGOOD
1V/div
VPGOOD
1V/div
VOUT
1V/div
VOUT
1V/div
VIN
5V/div
VIN = +12V
VOUT = +1.75V
IOUT = 52A
VIN = +12V
VOUT = +1.75V
IOUT = 52A
8
MAX5037A toc36
MAX5037A toc35
MAX5037A toc34
2ms/div
LOAD-TRANSIENT RESPONSE
ENABLE STARTUP RESPONSE
INPUT STARTUP RESPONSE
1ms/div
VEN
2V/div
VOUT
50mV/div
VIN = +12V
VOUT = +1.75V
ISTEP = 8A TO 52A
tRISE = 1µs
40µs/div
_______________________________________________________________________________________
VRM 9.0/VRM 9.1, Dual-Phase,
Parallelable, Average-Current-Mode Controller
REVERSE-CURRENT SINK
AT INPUT TURN-ON
REVERSE-CURRENT SINK vs.
TEMPERATURE
MAX5037A toc38
MAX5037A toc37
2.8
R1 = R2 = 1.5mΩ
2.7
R1 = R2 = 1.5mΩ
VIN = +12V
VOUT = +1.5V
VEXTERNAL = 2.5V
IREVERSE (A)
VEXTERNAL = +3.3V
2.6
REVERSE
CURRENT
5A/div
0A
2.5
VEXTERNAL = +2V
2.4
2.3
VIN = +12V
VOUT = +1.5V
-40
-15
10
35
60
85
200µs/div
TEMPERATURE (°C)
REVERSE-CURRENT SINK
AT INPUT TURN-ON
REVERSE-CURRENT SINK
AT ENABLE TURN-ON
MAX5037A toc39
VIN = +12V
VOUT = +1.5V
VEXTERNAL = 3.3V
R1 = R2 = 1.5mΩ
MAX5037A toc40
VIN = +12V
VOUT = +1.5V
VEXTERNAL = 2.5V
R1 = R2 = 1.5mΩ
REVERSE
CURRENT
10A/div
0A
REVERSE
CURRENT
5A/div
0A
200µs/div
200µs/div
REVERSE-CURRENT SINK
AT ENABLE TURN-ON
MAX5037A toc41
VIN = +12V
VOUT = +1.5V
VEXTERNAL = 3.3V
R1 = R2 = 1.5mΩ
REVERSE
CURRENT
10A/div
0A
200µs/div
_______________________________________________________________________________________
9
MAX5037A
Typical Operating Characteristics (continued)
(Circuit of Figure 1, TA = +25°C, unless otherwise noted.)
VRM 9.0/VRM 9.1, Dual-Phase,
Parallelable, Average-Current-Mode Controller
MAX5037A
Pin Description
PIN
NAME
FUNCTION
1–4, 44
VID3–VID0,
VID4
DAC Code Inputs. VID0 is the LSB and VID4 is the MSB for the internal 5-bit DAC (Table 1). Connect to
SGND for logic low or leave open circuit for logic high. These inputs have 12kΩ internal pullup
resistors to an internal 3V regulator.
5, 20, 35
SGND
Signal Ground. Ground connection for the internal circuitry. QFN package exposed pad connected to
SGND.
6
OVPIN
Overvoltage Protection Circuit Input. Connect DIFF to OVPIN. When OVPIN exceeds +13% above the
VID programmed output voltage, OVPOUT latches DH_ low and DL_ high. Toggle EN low to high or
recycle the power to reset the latch.
7, 43
CLP1, CLP2 Current-Error Amplifier Output. Compensate the current loop by connecting an R-C network to ground.
OVPOUT
Overvoltage Protection Output. Use the OVPOUT active-high, push-pull output to trigger a safety
device such as an SCR.
9
PGOOD
Power-Good Output. The open-drain, active-low PGOOD output goes low when the VID programmed
output voltage falls out of regulation or a phase failure is detected. The power-good window
comparator thresholds are +8% and -10% of the VID programmed output voltage. Forcing EN low also
forces PGOOD low.
10
SENSE+
Differential Output Voltage-Sensing Positive Input. Used to sense a remote load. Connect SENSE+ to
VOUT+ at the load. The device regulates the difference between SENSE+ and SENSE- according to the
programmed VID code and adaptive voltage positioning.
11
SENSE-
Differential Output Voltage-Sensing Negative Input. Used to sense a remote load. Connect SENSE- to
VOUT- or PGND at the load.
12
DIFF
Differential Remote-Sense Amplifier Output. DIFF is the output of a precision unity-gain amplifier.
13
EAN
Voltage-Error Amplifier Inverting Input. Receives the output of the differential remote-sense amplifier.
Referenced to SGND.
14
EAOUT
8
REG Input. A resistor on REG applies the same voltage-positioning window at different VRM voltage
settings. For a no-load output voltage (VCORE) equal to VID, set RREG = RF, where the RF is the
feedback resistor of the voltage-error amplifier. VREG internally regulates to the programmed VID
output voltage.
15
REG
16, 39
CSP1, CSP2
17, 40
CSN1,
CSN2
Current-Sense Differential Amplifier Negative Input. Together with CSP_, senses the inductor current.
18
CNTR
Adaptive Voltage Center Position Input. Connect a resistor between CNTR and SGND to program the
center of the adaptive VOUT position. VCNTR regulates to +1.22V.
19
EN
21, 33, 37
N.C.
22, 34
BST1, BST2
23, 32
DH1, DH2
10
Voltage-Error Amplifier Output. Connect to an external, gain-setting feedback resistor. The error
amplifier gain determines the output voltage load regulation for adaptive voltage positioning.
Current-Sense Differential Amplifier Positive Input. Senses the inductor current. The differential voltage
between CSP_ and CSN_ is amplified internally by the current-sense amplifier gain of 18.
Output Enable. A logic low shuts down the power drivers. EN has an internal 5µA pullup current.
No Connection. Not internally connected.
Boost Flying-Capacitor Connection. Reservoir capacitor connection for the high-side FET driver
supply. Connect a 0.47µF ceramic capacitor between BST_ and LX_.
High-Side Gate-Driver Output. Drives the gate of the high-side MOSFET.
______________________________________________________________________________________
VRM 9.0/VRM 9.1, Dual-Phase,
Parallelable, Average-Current-Mode Controller
PIN
NAME
FUNCTION
24, 31
LX1, LX2
Inductor Connection. Source connection for the high-side MOSFETs. Also serves as the return terminal
for the high-side driver.
25, 30
DL1, DL2
Low-Side Gate-Driver Output. Synchronous MOSFET gate drivers for the two phases.
26
VDD
Supply Voltage for Low-Side and High-Side Drivers. VCC powers VDD. Connect a parallel combination
of 0.1µF and 1µF ceramic capacitors to PGND and a 1Ω resistor to VCC to filter out the high peak
currents of the driver from the internal circuitry.
27
VCC
Internal 5V Regulator Output. VCC is derived internally from the IN voltage. Bypass to SGND with 4.7µF
and 0.1µF ceramic capacitors.
28
IN
29
PGND
36
CLKOUT
38
CLKIN
CMOS Logic Clock Input. Drive the internal oscillator with a frequency range between 125kHz and
600kHz. Connect to VCC or SGND. Connect CLKIN to SGND to set the internal oscillator to 250kHz or
connect to VCC to set the internal oscillator to 500kHz. CLKIN has an internal 5µA pulldown current.
41
PHASE
Phase Shift Setting Input. Drive PHASE high for 120°, leave PHASE unconnected for 90°, and force
PHASE low for 60° of phase shift between the rising edges of CLKOUT and CLKIN/DH1.
42
PLLCMP
External Loop-Compensation Input. Connect compensation network for the phase-locked loop (see
Phase-Locked Loop section).
Supply Voltage Connection. Connect IN to VCC for a 5V system.
Power Ground. Connect PGND, low-side synchronous MOSFET’s source, and VDD bypass capacitor
returns together.
Oscillator Output. CLKOUT is phase shifted from CLKIN by the amount specified by PHASE. Use
CLKOUT to parallel additional MAX5037s.
______________________________________________________________________________________
11
MAX5037A
Pin Description (continued)
VRM 9.0/VRM 9.1, Dual-Phase,
Parallelable, Average-Current-Mode Controller
MAX5037A
Functional Diagram
EN
IN
+5V
LDO
REGULATOR
UVLO
POR
TEMP SENSOR
VCC
TO INTERNAL CIRCUITS
VDD
CSP1
DRV_VCC
CSP1
CSN1
SHDN
BST1
CSN1
CLP1
DH1
CLP1
LX1
PHASE 1
CLK
SGND
DL1
MAX5037A
GMIN
PGND
PHASELOCKED
LOOP
CLKIN
PHASE
RAMP1
CLKOUT
PLLCMP
RAMP
GENERATOR
DIFF
PGOOD
CLP1
SENSE-
+0.6V
DIFF
AMP
SENSE+
CLP2
CNTR
ADAPTIVE
VOLTAGE
POSITIONING
REG
N
POWERGOOD
GENERATOR
DIFF
DAC_OUT
PGND
13% OF
DAC_OUT
EAOUT
EAN
OVPOUT
OVP
COMP
ERROR
AMP
VID0
VID1
VID2
VID3
ROM
VOLTAGEPOSITIONING
DAC
DAC_OUT
DRV_VCC
VID4
PGND
RAMP2
OVPIN
CLP2
CSN2
CSP2
12
SHDN
CLK
GMIN
PHASE 2
DH2
LX2
CLP2
CSN2
CSP2
______________________________________________________________________________________
DL2
BST2
VRM 9.0/VRM 9.1, Dual-Phase,
Parallelable, Average-Current-Mode Controller
The MAX5037A (Figures 1 and 2) average-currentmode PWM controller drives two out-of-phase buck
converter channels. Average-current-mode control
improves current sharing between the channels while
minimizing component derating and size. Parallel multiple MAX5037A regulators to increase the output current
VIN = +5V
C1, C2
VCC
VCC
R13
C31
IN
C32
C42
R4
19
EN
VIN
42
38
PLLCMP
28
CLKIN
IN
11
10
17
C3–C7
5 x 22µF
16
SENSE- SENSE+ CSN1 CSP1
DH1
44
LX1
VID3
DL1
VIN
2
BST1
VID0
VCC
VDD
6
VOUT = +1.1V TO
+1.85V AT 52A
C14,
C15
LOAD
D4
C40
C26–C30,
C37
VIN
12
18
C38
C16–C25
28
C39
DIFF
EAN
DH2
EAOUT
LX2
R10
IN
OVPIN
13
15
D3
27
R3
MAX5037A
R9
22
OVPOUT
R12
14
C12
Q2
C41
8
R8
25
R1
D1
VID1
4
R7
L1
24
VID2
3
C43
Q1
VID4
1
DAC
INPUTS
23
DL2
32
C8–C11
Q3
L2
31
30
REG
Q4
R2
C13
D2
CNTR
CLP1
7
R6
CLP2
43
PGND
29
SGND
PHASE
5, 20, 35 41
PGOOD
9
BST2
34
R11
R5
C36
C34
C35
CSN2 CSP2
40
39
VCC
PGOOD
C33
*SEE TABLE 2 FOR COMPONENT VALUES.
Figure 1. Typical VRM Application Circuit, VIN = +5V
______________________________________________________________________________________
13
MAX5037A
capacity. For maximum ripple rejection at the input, set
the phase shift between phases to 90° for two paralleled
converters, or 60° for three paralleled converters. The
paralleling capability of the MAX5037A improves design
flexibility in applications requiring upgrades (higher load).
The programmable output voltage utilizes VID codes
compliant with Intel’s VRM 9.0/VRM 9.1 specifications.
Detailed Description
MAX5037A
VRM 9.0/VRM 9.1, Dual-Phase,
Parallelable, Average-Current-Mode Controller
Dual-phase converters with an out-of-phase locking
arrangement reduce the input and output capacitor ripple current, effectively multiplying the switching frequency by the number of phases. Each phase of the
MAX5037A consists of an inner average current loop
controlled by a common outer-loop voltage-error amplifier (VEA). The combined action of the two inner current
loops and the output voltage loop corrects the output
voltage errors and forces the phase currents to be
equal.
VIN = +8V TO +28V
C1, C2
2 x 47µF
VCC
VCC
R13
2.2Ω
C31
C32
C42
0.1µF
R4
19
EN
42
PLLCMP
38
CLKIN
28
IN
VIN
C3–C7
5 x 22µF
11
10
17
16
SENSE- SENSE+ CSN1 CSP1
DH1
44
1
VID3
DL1
VIN
2
4
8
VID1
BST1
VID0
VCC
6
18
28
VOUT = +1.1V
TO +1.85V
AT 52A
C14, C15
2 x 100µF
LOAD
D4
C39
1µF
C40
0.1µF
C16–C25
2 x 270µF
DIFF
EAN
DH2
EAOUT
LX2
R10
C38
4.7µF
VIN
12
15
C41
0.1µF
OVPIN
13
R9
D3
27
R3
VDD
14
C12
0.47µF
Q2
22
OVPOUT
MAX5037A
R8
25
R1
1.35mΩ
D1
R12
R7
L1
0.6µH
24
VID2
3
C43
Q1
VID4
LX1
DAC
INPUTS
23
DL2
32
Q3
C8–C11
4 x 22µF
L2
0.6µH
31
30
REG
Q4
R2
1.35mΩ
C13
0.47µF
D2
CNTR
CLP1
7
R6
CLP2
43
PGND
29
SGND
PHASE
5, 20, 35 41
PGOOD
9
CSN2 CSP2
40
39
34
R11
R5
C36
C34
C35
BST2
VCC
PGOOD
C33
NOTE: SEE TABLE 2 FOR COMPONENT VALUES.
Figure 2. Typical VRM Application Circuit, VIN = +8V to +28V
14
______________________________________________________________________________________
C26–C30,
C37
6 x 10µF
VRM 9.0/VRM 9.1, Dual-Phase,
Parallelable, Average-Current-Mode Controller
ICC = IQ + fSW x (QG1 + QG2 + QG3 + QG4) (2)
where, Q G1, Q G2, Q G3, and Q G4 are the total gate
charge of the low-side and high-side external
MOSFETs, IQ is 4mA (typ), and fSW is the switching frequency of each individual phase.
For applications utilizing a +5V input voltage, disable
the VCC regulator by connecting IN and VCC together.
Undervoltage Lockout (UVLO)/Soft-Start
The MAX5037A includes an undervoltage lockout with
hysteresis and a power-on reset circuit for converter
turn-on and monotonic rise of the output voltage. The
UVLO circuit monitors the VCC regulator output while
actively holding down the power-good (PGOOD) output. The UVLO threshold is internally set between
+4.0V and +4.5V with a 200mV hysteresis. Hysteresis
at UVLO eliminates “chattering” during startup.
The compensation network at the current-error amplifier, CLP1 and CLP2, provides an inherent soft-start to
the VRM power supply. It includes a parallel combination of capacitors (C34, C36) and resistors (R5, R6) in
series with other capacitors (C33, C35) (see Figure 1).
The voltage at CLP_ limits the maximum current available to charge output capacitors. The capacitor on
CLP_ in conjunction with the finite output-drive current
of the current-error amplifier yields a finite rise time for
the output current and thus the output voltage.
Internal Oscillator
The internal oscillator generates the 180° out-of-phase
clock signals required by the pulse-width modulation
(PWM) circuits. The oscillator also generates the 2VP-P
voltage ramp signals necessary for the PWM comparators. Connect CLKIN to SGND to set the internal oscillator
frequency to 250kHz or connect CLKIN to VCC to set the
internal oscillator to 500kHz.
CLKIN is a CMOS logic clock for the phase-locked loop
(PLL). When driven externally, the internal oscillator
locks to the signal at CLKIN. A rising edge at CLKIN
starts the ON cycle of the PWM. Ensure that the external clock pulse width is at least 200ns. CLKOUT provides a phase-shifted output with respect to the rising
edge of the signal at CLKIN. PHASE sets the amount of
phase shift at CLKOUT. Connect PHASE to VCC for
120° of phase shift, leave PHASE unconnected for 90°
of phase shift, or connect PHASE to SGND for 60° of
phase shift with respect to CLKIN.
The MAX5037A requires compensation on PLLCMP
even when operating from the internal oscillator. The
device requires an active PLL in order to generate the
proper clock signal required for PWM operation.
Control Loop
The MAX5037A uses an average-current-mode control
scheme to regulate the output voltage (Figure 3). The
main control loop consists of an inner current loop and
an outer voltage loop. The inner loop controls the output currents (IPHASE1 and IPHASE2), while the outer
loop controls the output voltage. The inner current loop
absorbs the inductor pole reducing the order of the
outer voltage loop to that of a single-pole system.
Most of the internal circuitry, including the oscillator,
turns on when the input voltage reaches +4V. The
MAX5037A draws up to 4mA of current before the input
voltage reaches the UVLO threshold.
______________________________________________________________________________________
15
MAX5037A
VIN, VCC, and VDD
The MAX5037A accepts an input voltage range of +4.75V
to +5.5V or +8V to +28V. All internal control circuitry operates from an internally regulated nominal voltage of 5V.
For input voltages of +8V or greater, the internal VCC regulator steps the voltage down to +5V. The VCC output
voltage is a regulated 5V output capable of sourcing up
to 80mA. Bypass VCC to SGND with 4.7µF and 0.1µF lowESR ceramic capacitors in parallel for high-frequency
noise rejection and stable operation (Figure 1).
VCC powers all internal circuitry. VDD is derived externally from VCC and provides power to the high-side and
low-side MOSFET drivers. VDD is internally connected
to the power source of the low-side MOSFET drivers.
Use VDD to charge the boost capacitors that provide
power to the high-side MOSFET drivers. Connect the
VCC regulator output to VDD through an R-C lowpass filter. Use a 1Ω (R3) resistor and a parallel combination of
1µF and 0.1µF ceramic capacitors to filter out the high
peak currents of the MOSFET drivers from the sensitive
internal circuitry.
Calculate power dissipation in the MAX5037A as a
product of the input voltage and the total VCC regulator
output current (ICC). ICC includes quiescent current (IQ)
and gate drive current (IDD):
(1)
PD = VIN x ICC
The current loop consists of a current-sense resistor,
RS (an RC lowpass filter in the case of lossless inductor
current sensing), a current-sense amplifier (CA_), a
current-error amplifier (CEA_), an oscillator providing
the carrier ramp, and a PWM comparator (CPWM_).
The precision CA_ amplifies the sense voltage across
RS by a factor of 18. The inverting input to the CEA_
senses the output of the CA_. The output of the CEA_ is
the difference between the voltage-error amplifier output (EAOUT) and the amplified voltage from the CA_.
The RC compensation network connected to CLP1 and
CLP2 provides external frequency compensation for
the respective CEA_. The start of every clock cycle
enables the high-side drivers and initiates a PWM ON
cycle. Comparator CPWM_ compares the output volt-
age from the CEA_ with a 0 to 2V ramp from the oscillator. The PWM ON cycle terminates when the ramp voltage exceeds the error voltage.
The outer voltage control loop consists of the differential amplifier (DIFF AMP), adaptive voltage-positioning
(AVP) block, digital-to-analog converter (DAC), and
voltage-error amplifier (VEA). The unity-gain differential
amplifier provides true differential remote sensing of the
output voltage. The differential amplifier output and the
AVP connect to the inverting input (EAN) of the VEA.
The noninverting input of VEA is internally connected to
the DAC output. The VEA controls the two inner current
loops (Figure 3). Use a resistive feedback network to
set the gain of the VEA as required by the adaptive
voltage-positioning circuit.
CCF
MAX5037A
CLP1
CSP1
CSN1
RCF
CCFF
CA1
VIN
AVP
RF*
IPHASE1
CEA1
SENSE+
CPWM1
DIFF
AMP
DRIVE 1
RS
RIN*
VEA
SENSE-
VOUT
VIN
CEA2
CPWM2
DAC
DRIVE 2
IPHASE2
RS
COUT
CLP2
CSP2
CA2
CSN2
MAX5037A
VRM 9.0/VRM 9.1, Dual-Phase,
Parallelable, Average-Current-Mode Controller
CCF
RCF
*RF AND RIN ARE EXTERNAL TO MAX5037A
(RF = R8, RIN = R7, FIGURES 1 AND 2).
CCCF
Figure 3. MAX5037A Control Loop
16
______________________________________________________________________________________
LOAD
VRM 9.0/VRM 9.1, Dual-Phase,
Parallelable, Average-Current-Mode Controller
Peak-Current Comparator
The peak-current comparator provides a path for fast
cycle-by-cycle current limit during extreme fault conditions such as an output inductor malfunction (Figure 4).
Note that the average current-limit threshold of 48mV
still limits the output current during short-circuit conditions. So to prevent inductor saturation, select an output inductor with a saturation current specification
greater than the average current limit. Proper inductor
selection ensures that only extreme conditions trip the
peak-current comparator, such as a broken output
inductor. The 112mV voltage threshold for triggering
the peak-current limit is twice the full-scale average
current-limit voltage threshold. The peak-current comparator has a delay of only 260ns.
Current-Error Amplifier
Each phase of the MAX5037A has a dedicated
transconductance current-error amplifier (CEA_) with a
typical gm of 550µS and 320µA output sink and source
current capability. The CEA_ outputs, CLP1 and CLP2,
serve as the inverting input to the PWM comparator.
CLP1 and CLP2 are externally accessible to provide
frequency compensation for the inner current loops
(Figure 3). Compensate CEA_ such that the inductor
current down slope, which becomes the up slope to the
inverting input of the PWM comparator, is less than the
slope of the internally generated voltage ramp (see the
Compensation section).
PWM Comparator and R-S Flip-Flop
The PWM comparator (CPWM) sets the duty cycle for
each cycle by comparing the current-error amplifier
output to a 2VP-P ramp. At the start of each clock cycle,
an R-S flip-flop resets and the high-side driver (DH_)
turns on. The comparator sets the flip-flop as soon as
the ramp voltage exceeds the CLP_ voltage, thus terminating the ON cycle (Figure 4).
Differential Amplifier
The unity-gain differential amplifier (DIFF AMP) facilitates the output voltage remote sensing at the load
(Figure 3). It provides true differential output voltage
sensing while rejecting the common-mode voltage
errors due to high-current ground paths. Sensing the
output voltage directly at the load provides accurate
load voltage sensing in high-current environments. The
VEA provides the difference between the differential
amplifier output (DIFF) and the desired VID programmed output voltage. The differential amplifier has
a unity-gain bandwidth of 3MHz. The difference
between SENSE+ and SENSE- regulates to the programmed VID output voltage.
Connect SENSE+ to an external resistor-divider network
at the output voltage to use the MAX5037A for output
voltages higher than those allowed by the VID codes.
DRV_VCC
PEAK CURRENT
COMPARATOR
112mV
CLP_
CSP_
AV = 18
Gm =
550µS
CSN_
BST_
PWM
COMPARATOR
GMIN
S
Q
DH_
RAMP
LX_
2 x fS (V/s)
CLK
R
Q
DL_
PGND
SHDN
Figure 4. Phase Circuit (Phase 1/Phase 2)
______________________________________________________________________________________
17
MAX5037A
Current-Sense Amplifier
The differential current-sense amplifier (CA_) provides a
DC gain of 18. The maximum input offset voltage of the
current-sense amplifier is 1mV and the common-mode
voltage range is -0.3V to +3.6V. The current-sense amplifier senses the voltage across a current-sense resistor.
MAX5037A
VRM 9.0/VRM 9.1, Dual-Phase,
Parallelable, Average-Current-Mode Controller
Voltage-Error Amplifier
The VEA sets the gain of the voltage control loop. The
VEA determines the error between the differential
amplifier output and the reference voltage generated
from the DAC.
The VEA output clamps to 0.9V relative to VCM (0.6V),
thus limiting the average maximum current from individual phases. The maximum average current-limit threshold for each phase is equal to the maximum clamp
voltage of the VEA divided by the gain (18) of the current-sense amplifier. This results in accurate settings
for the average maximum current for each phase. Set
the VEA gain using RF and RIN for the amount of output
voltage positioning required within the rated current
range as discussed in the Adaptive Voltage Positioning
section (Figure 3).
Adaptive Voltage Positioning
Powering new generation processors requires new
techniques to reduce cost, size, and power dissipation.
Voltage positioning reduces the total number of output
capacitors to meet a given transient response requirement. Setting the no-load output voltage slightly higher
than the output voltage during nominally loaded conditions allows a larger downward voltage excursion when
the output current suddenly increases. Regulating at a
lower output voltage under a heavy load allows a larger
upward voltage excursion when the output current suddenly decreases. A larger allowed voltage step excursion reduces the required number of output capacitors
or allows for the use of higher ESR capacitors.
Set the voltage-positioning window (∆VOUT) using the
resistive feedback of the VEA. See the Adaptive
Voltage-Positioning Design Procedure section and use
the following equation to calculate the voltage-positioning window:
(3)
∆VOUT = IOUT x RIN / (2 x GC x RF )
GC =
0.05
RS
(4)
where RIN and RF are the input and feedback resistors of
the VEA, GC is the current-loop transconductance, and
RS is the current-sense resistor or, if using lossless inductor current sensing, the DC resistance of the inductor.
The voltage at CNTR (VCNTR) regulates to 1.2V (Figure
6). The current set by the resistor RCNTR is mirrored at
the inverting input of the VEA, centering the output voltage-positioning window on the VID programmed output
voltage. Set the center of the output voltage with a
resistor from CNTR to SGND in the following manner:
RCNTR =
VCNTR × RIN
⎛ RIN ⎞
IOUT ⎜
⎟ + (VOUT − VID)
⎝ 2RFGC ⎠
(5)
where VOUT is a required value of output voltage at the
corresponding IOUT. IOUT can be any value from no
load to full load.
Voltage positioning and the ability to operate with the multiple reference voltages may require the output to regulate
away from a center value. Define the center value as the
voltage where the output equals the VID reference voltage at one half the maximum output current (Figure 5).
VCC
1X
VCC
1X
+1.2V
VOLTAGE-POSITIONING WINDOW
VCNTR + ∆VOUT/2
VCNTR
VCNTR - ∆VOUT/2
NO LOAD
1/2 LOAD
FULL LOAD
EAN
CNTR
DAC_OUT
1X
REG
LOAD (A)
Figure 5. Defining the Voltage-Positioning Window
18
Figure 6. Adaptive Voltage-Positioning Circuit
______________________________________________________________________________________
1X
VRM 9.0/VRM 9.1, Dual-Phase,
Parallelable, Average-Current-Mode Controller
RIN × RF
RREG =
⎛
⎞
V
RIN + RF ⎜1 − COREMAX ⎟
VID
⎝
⎠
(6)
DAC Inputs (VID0–VID4)
The DAC programs the output voltage. The DAC typically receives a digital code, alternatively, the VID
inputs are hardwired to SGND or left open circuit.
VID0–VID4 logic can be changed while the MAX5037A
is active, initiating a transition to a new output voltage
level. Change VID0–VID4 together, avoiding greater
than 1µs skew between bits. Otherwise, incorrect DAC
readings may cause a partial transition to the wrong
voltage level followed by the intended transition to the
correct voltage level, lengthening the overall transition
time. For any low-going VID step of 100mV or more, the
OVP can trip because the OVP trip reference changes
instantaneously with the VID code, but the converter
output does not follow immediately. The converter output drops at a rate depending on the output capacitor,
inductor load, and the closed-loop bandwidth of the
converter. Do not exceed a maximum VID step size of
75mV.
VOLTAGE-POSITIONING WINDOW
VCOREMAX ≤ VID
VCOREMAX - ∆VOUT/2
VCOREMAX - ∆VOUT/2
NO LOAD
1/2 LOAD
LOAD (A)
Figure 7. Limiting the Voltage-Positioning Window
FULL LOAD
The available DAC codes and resulting output voltages
(Table 1) comply with Intel’s VRM 9.0 specification.
Internal pullup resistors connect the VID inputs to a
nominal internal 3V supply. Force the VID inputs below
0.8V for logic low or leave unconnected for logic high.
Output voltage accuracy with respect to the programmed VID voltage is ±0.8% over the -40°C to +85°C
temperature range.
Table 1. Output Voltage vs. DAC Codes
VID INPUTS (0 = CONNECTED TO
SGND, 1 = OPEN CIRCUIT)
OUTPUT
VOLTAGE (V)
VID4
VID3
VID2
VID1
VID0
VOUT
1
1
1
1
1
Output off
1
1
1
1
0
1.100
1
1
1
0
1
1.125
1
1
1
0
0
1.150
1
1
0
1
1
1.175
1
1
0
1
0
1.200
1
1
0
0
1
1.225
1
1
0
0
0
1.250
1
0
1
1
1
1.275
1
0
1
1
0
1.300
1
0
1
0
1
1.325
1
0
1
0
0
1.350
1
0
0
1
1
1.375
1
0
0
1
0
1.400
1
0
0
0
1
1.425
1
0
0
0
0
1.450
0
1
1
1
1
1.475
0
1
1
1
0
1.500
0
1
1
0
1
1.525
0
1
1
0
0
1.550
0
1
0
1
1
1.575
0
1
0
1
0
1.600
0
1
0
0
1
1.625
0
1
0
0
0
1.650
0
0
1
1
1
1.675
0
0
1
1
0
1.700
0
0
1
0
1
1.725
0
0
1
0
0
1.750
0
0
0
1
1
1.775
0
0
0
1
0
1.800
0
0
0
0
1
1.825
0
0
0
0
0
1.850
______________________________________________________________________________________
19
MAX5037A
Applying the voltage-positioning window at different
VRM voltage settings requires that RREG = RF. The voltage on REG internally regulates to the programmed
VID output voltage. Choose RREG to limit the current at
REG to 50µA. For example, for a VID setting of 1.85V,
calculate the minimum allowed R REG as R REG =
1.85V/50µA = 37kΩ. To use larger values of RREG while
maintaining the required gain of the VEA, use larger
values for RIN.
In the case of a VID voltage setting equal to VCOREMAX
at IOUT = 0 (no load), RCNTR = ∞ from the above equation (Figure 7). For systems requiring VCOREMAX as an
absolute maximum voltage when IOUT = 0 (no load),
calculate RREG using following the equation:
MAX5037A
VRM 9.0/VRM 9.1, Dual-Phase,
Parallelable, Average-Current-Mode Controller
Phase-Locked Loop: Operation and
Compensation
The phase-locked loop (PLL) synchronizes the internal
oscillator to the external frequency source when driving
CLKIN. Connecting CLKIN to VCC or SGND forces the
PWM frequency to default to the internal oscillator frequency of 500kHz or 250kHz, respectively. The PLL
uses a conventional architecture consisting of a phase
detector and a charge pump capable of providing
20µA of output current. Connect an external series
combination capacitor (C31) and resistor (R4) and a
parallel capacitor (C32) from PLLCMP to SGND to provide frequency compensation for the PLL (Figure 1).
The pole-zero pair compensation provides a zero at fZ
defined by 1 / [R4 x (C31 + C32)] and a pole at fP
defined by 1 / (R4 x C32). Use the following typical values for compensating the PLL: R4 = 7.5kΩ, C31 =
4.7nF, C32 = 470pF. When changing the PLL frequency, expect a finite locking time of approximately 200µs.
The MAX5037A requires compensation on PLLCMP even
when operating from the internal oscillator. The device
requires an active-phase-locked loop in order to generate
the proper internally shifted clock available at CLKOUT.
MOSFET Gate Drivers (DH_, DL_)
The high-side (DH_) and low-side (DL_) drivers drive
the gates of external N-channel MOSFETs (Figure 1).
The drivers’ high-peak sink and source current capability provides ample drive for the fast rise and fall times
of the switching MOSFETs. Faster rise and fall times
result in reduced cross-conduction losses. For modern
CPU applications where the duty cycle is less than
50%, choose high-side MOSFETs (Q1 and Q3) with a
moderate RDS(ON) and very low gate charge. Choose
low-side MOSFETs (Q2 and Q4) with very low RDS(ON)
and moderate gate charge.
The driver block also includes a logic circuit that provides an adaptive nonoverlap time to prevent shootthrough currents during transition. The typical
nonoverlap time is 60ns between the high-side and
low-side MOSFETs.
Protection
The MAX5037A includes output overvoltage protection
(OVP), undervoltage protection (UVP), phase failure,
and overload protection to prevent damage to the powered electronic circuits.
Overvoltage Protection (OVP)
The OVP comparator compares the OVPIN input to the
overvoltage threshold. The overvoltage threshold is typically +13% above the programmed VID output voltage.
A detected overvoltage event latches the comparator
output forcing the power stage into the OVP state. In
the OVP state, the high-side MOSFETs turn off and the
low-side MOSFETs latch on. Use the OVPOUT highcurrent-output driver to turn on an external crowbar
SCR. When the crowbar SCR turns on, a fuse must
blow or the source current for the MAX5037A regulator
must be limited to prevent further damage to the external circuitry. Connect the SCR close to the input source
and after the fuse. Use an SCR large enough to handle
the peak I2t energy due to the input and output capacitors discharging and the current sourced by the power
source output. Connect DIFF to OVPIN for differential
output sensing and overvoltage protection. Add an RC
delay to reduce the sensitivity of overvoltage circuit and
avoid nuisance tripping of the converter (Figure 8).
For any low-going VID step of 75mV or more, the OVP
can trip because the OVP trip reference changes instantaneously with the VID code, but the converter output
does not follow immediately. The converter output drops
at a rate depending on the output capacitor, inductor
load, and the closed-loop bandwidth of the converter.
0.1µF
OVPIN
1kΩ
BST_
VDD powers the low- and high-side MOSFET drivers.
The high-side drivers derive their power through a
bootstrap capacitor and VDD supplies power internally
to the low-side drivers. Connect a 0.47µF low-ESR
ceramic capacitor between BST_ and LX_. Bypass VDD
to PGND with 1µF and 0.1µF low-ESR ceramic capacitors. Reduce the PC board area formed by these
capacitors, the rectifier diodes between VDD and the
boost capacitor, the MAX5037A, and the switching
MOSFETs.
DIFF
RIN
MAX5037A
EAN
RF
EAOUT
Figure 8. OVP Input Delay
20
______________________________________________________________________________________
VRM 9.0/VRM 9.1, Dual-Phase,
Parallelable, Average-Current-Mode Controller
2) Both phases are providing current.
3) EN is HIGH.
A window comparator compares the differential amplifier output (DIFF) against 1.08 times the programmed
VID output voltage for overvoltage and 0.90 times the
programmed VID output voltage for undervoltage monitoring. The phase failure comparator detects a phase
failure by comparing the current-error amplifier output
(CLP_) with a 2.0V reference.
Use a 10kΩ pullup resistor from PGOOD to a voltage
source less than or equal to VCC. An output voltage
outside the comparator window or a phase failure condition forces the open-drain output low. The open-drain
MOSFET sinks 4mA of current while maintaining less
than 0.2V at the PGOOD output.
Phase Failure Detector
Output current contributions from the two phases are
within ±10% of each other. Proper current sharing
reduces the necessity to overcompensate the external
components. However, an undetected failure of one
phase driver causes the other phase driver to run continuously as it tries to provide the entire current requirement to the load. Eventually, the stressed operational
phase driver fails.
During normal operating conditions, the voltage level
on CLP_ is within the peak-to-peak voltage levels of the
PWM ramp. If one of the phases fails, the control loop
raises the CLP_ voltage above its operating range. To
determine a phase failure, the phase failure detection
circuit (Figure 9) monitors the output of the current
amplifiers (CLP1 and CLP2) and compares them to a
2.0V reference. If the voltage levels on CLP1 or CLP2
are above the reference level for more than 1250 clock
cycles, the phase failure circuit forces PGOOD low.
Overload Conditions
Average current-mode control has the ability to limit the
average current sourced by the converter during a fault
condition. When a fault condition occurs, the VEA output clamps to 0.9V with respect to the common-mode
voltage (VCM = 0.6V) and is compared with the output
of the current-sense amplifiers (CA1 and CA2) (see
Figure 3). The current-sense amplifier’s gain of 18 limits
the maximum current in the inductor or sense resistor to
ILIMIT = 50mV/RS.
Parallel Operation
For applications requiring large output current, parallel
up to three MAX5037As (six phases) to triple the available output current. The paralleled converters operating
at the same switching frequency but different phases
keep the capacitor ripple RMS currents to a minimum.
Three parallel MAX5037A converters deliver up to 180A
of output current. To set the phase shift of the on-board
PLL, leave PHASE unconnected for 90° of phase shift
(two paralleled converters), or connect PHASE to SGND
for 60° of phase shift (three converters in parallel).
Designate one converter as master and the remaining
converters as slaves. Connect the master and slave controllers in a daisy-chain configuration as shown in Figure
10. Connect CLKOUT from the master controller to
CLKIN of the first slaved controller, and CLKOUT from
the first slaved controller to CLKIN of the second slaved
controller. Choose the appropriate phase shift for minimum ripple currents at the input and output capacitors.
The master controller senses the output differential voltage through SENSE+ and SENSE- and generates the
DIFF voltage. Disable the voltage sensing of the slaved
controllers by leaving DIFF unconnected (floating).
Figure 11 shows a detailed typical parallel application
circuit using two MAX5037As. This circuit provides four
phases at an input voltage of 12V and an output voltage
range of 1.1V to 1.85V at 104A.
PGOOD
DIFF
DAC_OUT
8% OF DAC
10% OF DAC
CLP1
+2.0V
CLP2
PHASE FAILURE DETECTION
Figure 9. Power-Good Generator
______________________________________________________________________________________
21
MAX5037A
Power-Good Generator (PGOOD)
The PGOOD output is high if all of the following conditions are met (Figure 9):
1) The output is within 90% to 108% of the programmed output voltage.
MAX5037A
VRM 9.0/VRM 9.1, Dual-Phase,
Parallelable, Average-Current-Mode Controller
Applications Information
Each MAX5037A circuit drives two 180° out-of-phase
channels. Parallel two or three MAX5037A circuits to
achieve four- or six-phase operation, respectively.
Figure 1 shows the typical application circuit for twophase operation. The design criteria for a two-phase
converter includes frequency selection, inductor value,
input/output capacitance, switching MOSFETs, sense
resistors, and the compensation network. Follow the
same procedure for the four- and six-phase converter
design, except for the input and output capacitance.
The input and output capacitance requirement varies
depending on the operating duty cycle.
The examples discussed in this data sheet pertain to a
typical VRM application with the following specifications:
VIN = +12V
VOUT = +1.1V to +1.85V
IOUT(MAX) = 52A
VCOREMAX = VID Programmed Output Voltage at No Load
AVP (∆VOUT) = 120mV
fSW = 250kHz
Peak-to-Peak Inductor Current (∆IL) = 10A
Table 2 shows a list of recommended external components (Figure 1) and Table 3 provides component supplier information.
Table 2. Component List
22
DESIGNATION
QTY
C1, C2
2
47µF, 16V X5R input-filter capacitors, TDK C5750X5R1C476M
DESCRIPTION
C3–C11
9
22µF, 16V input-filter capacitors, TDK C4532X5R1C226M
C12, C13
2
0.47µF, 16V capacitors, TDK C1608X5R1A474K
C14, C15
2
100µF, 6.3V output-filter capacitors, Murata GRM44-1X5R107K6.3
C16–C25
10
270µF, 2V output-filter capacitors, Panasonic EEFUE0D271R
C26–C30, C37
6
10µF, 6.3V output-filter capacitors, TDK C2012X5R0J106M
C31
1
4700pF, 16V X7R capacitor, Vishay-Siliconix VJ0603Y471JXJ
C32, C34, C36
3
470pF, 16V capacitors, Murata GRM1885C1H471JAB01
C33, C35, C43
3
0.01µF, 50V X7R capacitors, Murata GRM188R71H103KA01
C38
1
4.7µF, 16V X5R capacitor, Murata GRM40-034X5R475k6.3
C39
1
1.0µF, 10V Y5V capacitor, Murata GRM188F51A105
C40, C41, C42
3
0.1µF, 16V X7R capacitors, Murata GRM188R71C104KA01
D1, D2
2
Schottky diodes, ON-Semiconductor MBRS340T3
D3, D4
2
Schottky diodes, ON-Semiconductor MBR0520LT1
L1, L2
2
0.6µH, 27A inductors, Panasonic ETQP1H0R6BFX
Q1, Q3
2
Upper power MOSFETs, Vishay-Siliconix Si7860DP
Q2, Q4
2
Lower power MOSFETs, Vishay-Siliconix Si7886DP
R1, R2
4
Current-sense resistors, use two 2.70mΩ resistors in parallel, Panasonic ERJM1WSF2M7U
R3, R13
1
2.2Ω ±1% resistor
7.5kΩ ±1% resistor
R4
1
R5, R6
2
1kΩ ±1% resistors
R7
1
4.99kΩ ±1% resistor
R8, R9
2
37.4kΩ ±1% resistors
R11
1
10kΩ ±1% resistor
R12
1
10Ω ±1% resistor
______________________________________________________________________________________
VRM 9.0/VRM 9.1, Dual-Phase,
Parallelable, Average-Current-Mode Controller
MAX5037A
CSN1
CSP1
SENSE+
VIN
SENSEDH1
VCC
LX1
PHASE
DL1
MAX5037A
VCC
CLKIN
VIN
DH2
LX2
VIN
IN
DL2
DIFF
EAN
CSP2
EAOUT
CSN2
PGND
SGND
CLKOUT
CSN1
CSP1
CLKIN
VIN
DH1
VCC
LX1
PHASE
DL1
MAX5037A
IN
VIN
DH2
DIFF
LX2
LOAD
DL2
EAN
CSP2
EAOUT
CSN2
PGND
SGND
CLKOUT
CSN1
CSP1
CLKIN
VIN
DH1
VCC
LX1
PHASE
DL1
MAX5037A
IN
VIN
DH2
DIFF
LX2
DL2
EAN
CSP2
EAOUT
CSN2
PGND
SGND
CLKOUT
TO OTHER MAX5037s
Figure 10. Parallel Configuration of Multiple MAX5037As
______________________________________________________________________________________
23
MAX5037A
VRM 9.0/VRM 9.1, Dual-Phase,
Parallelable, Average-Current-Mode Controller
VIN = +12V
VIN
C1, C2
2 x 47µF
VCC
C31
R13
2.2Ω
C32
C43
R12
8
OVPOUT
44
C42
0.1µF
R4
42
PLLCMP
38
CLKIN
28
IN
VIN
C3–C7
5 x 22µF
11
10
17
16
SENSE- SENSE+ CSN1 CSP1
DH1
VID3
DL1
2
3
4
VCC
19
R7
12
13
R8
14
15
R10
18
25
R1
1.35mΩ
C12
0.47µF
Q2
D1
VID1
BST1
VID0
VCC
22
D3
27
MAX5037A
(MASTER)
C38
4.7µF
C41
0.1µF
R3
EN
28
D4
C39
1µF
C40
0.1µF
OVPIN
VIN
DIFF
EAN
DH2
EAOUT
LX2
R9
L1
0.6µH
24
VID2
VDD
6
Q1
VID4
LX1
1
23
DL2
32
C8–C11
4 x 22µF
Q3
30
C13
0.47µF
Q4
REG
R2
1.35mΩ
L2
0.6µH
31
D2
CNTR
CLP1
7
CLP2
43
R6
PGND
29
SGND
5,
20,
35
CLKOUT
36
PHASE PGOOD
41
9
CSN2 CSP2
40
39
BST2
34
R11
R5
C36
C34
C35
PGOOD
VCC
C33
R24
C14, C15,
C44, C45
2 x 100µF
C70
VID0
R24
2.2Ω
C71
C16–C25,
C57–C60
2 x 270µF
C26–C30, LOAD
C37
6 x 10µF
VID1
DAC
INPUTS
R25
C61
0.1µF
R17
VID2
VID3
19
EN
VID4
4
42
PLLCMP
28
IN
VIN
38
CLKIN
5 x 22µF
C46–C50
11
10
17
16
SENSE- SENSE+ CSN1 CSP1
DH1
VID1
DL1
2
1
44
23
Q5
24
25
6
R20
12
13
R21
14
D5
VID3
BST1
VID4
VCC
OVPOUT
VDD
MAX5037A
(SLAVE)
22
D7
27
R22
15
18
C65
4.7µF
C64
0.1µF
28
D8
C62
1µF
C63
0.1µF
OVPIN
VIN
DIFF
C51–C54
4 x 22µF
EAN
DH2
EAOUT
LX2
R23
R14
1.35mΩ
C55
0.47µF
Q6
VID2
R16
8
L3
0.6µH
VID0
LX1
3
DL2
32
L4
0.6µH
30
R15
1.35mΩ
C56
0.47µF
Q8
D6
CNTR
CLP1
7
CLP2
43
R19
R18
PGND
29
C69
C67
Q7
31
REG
C66
SGND
PHASE PGOOD CSN2 CSP2
5, 20, 35
41
9
40
39
BST2
34
VCC
C68
Figure 11. Four-Phase Parallel Application Circuit (VIN = +12V, VOUT = +1.1V to +1.85V at 104A)
24
VOUT = +1.1V TO
+1.85V AT 104A
______________________________________________________________________________________
VRM 9.0/VRM 9.1, Dual-Phase,
Parallelable, Average-Current-Mode Controller
PHONE
FAX
Murata
SUPPLIER
770-436-1300
770-436-3030
www.murata.com
ON Semiconductor
602-244-6600
602-244-3345
www.on-semi.com
Panasonic
714-373-7939
714-373-7183
www.panasonic.com
TDK
847-803-6100
847-390-4405
www.tcs.tdk.com
1-800-551-6933
619-474-8920
www.vishay.com
Vishay-Siliconix
Number of Phases
Selecting the number of phases for a voltage regulator
depends mainly on the ratio of input-to-output voltage
(operating duty cycle). Optimum output-ripple cancellation depends on the right combination of operating duty
cycle and the number of phases. Use the following
equation as a starting point to choose the number of
phases:
(7)
NPH ≈ K/D
where K = 1, 2, or 3 and the duty cycle D = VOUT/VIN.
Choose K to make NPH an integer number. For example, converting VIN = +12V to VOUT = +1.75V yields better ripple cancellation in the six-phase converter than in
the four-phase converter. Ensure that the output load
justifies the greater number of components for multiphase conversion. Generally, limiting the maximum output current to 25A per phase yields the most costeffective solution. The maximum ripple cancellation
occurs when NPH = K/D.
Single-phase conversion requires greater size and power
dissipation for external components such as the switching MOSFETs and the inductor. Multiphase conversion
eliminates the heatsink by distributing the power dissipation in the external components. The multiple phases
operating at given phase shifts effectively increase the
switching frequency seen by the input/output capacitors,
reducing the input/output capacitance requirement for
the same ripple performance. The lower inductance value
improves the large-signal response of the converter during a transient load at the output. Consider all these
issues when determining the number of phases necessary for the voltage regulator application.
WEBSITE
Adaptive Voltage-Positioning Design
Procedure
The following steps outline the procedure for setting the
adaptive voltage positioning:
1) Choose the voltage-error amplifier input (EAN)
resistor RIN > 5kΩ.
2) Determine a reasonable amount of excursion from
the desired output voltage that the system can tolerate and use as an estimate for the voltage-positioning window, ∆VOUT (see Figures 5 and 7).
3) Calculate RF from equations 22 and 23. Use equation 3 to verify that ∆VOUT remains within tolerable
limits.
4) Calculate the centering resistor, RCNTR, from equation 5. RCNTR sets the center of the adaptive voltage
positioning such that at 1/2 full-load current, the
output voltage is the desired VID programmed output voltage (Figure 5). Do not use values less than
24kΩ for RCNTR.
5) Choose the regulation resistor, RREG, to have the
same value as the feedback resistor, RF (RREG =
RF). RREG maintains the adaptive voltage-positioning window at all VID output voltage settings. Do
not use values less than 37kΩ for RREG.
Inductor Selection
The switching frequency per phase, peak-to-peak ripple current in each phase, and allowable ripple at the
output determine the inductance value.
Selecting higher switching frequencies reduces the
inductance requirement, but at the cost of lower efficiency. The charge/discharge cycle of the gate and drain
capacitances in the switching MOSFETs create switching
losses. The situation worsens at higher input voltages,
since switching losses are proportional to the square of
input voltage. Use 500kHz per phase for VIN = +5V,
250kHz or less per phase for VIN > +12V.
______________________________________________________________________________________
25
MAX5037A
Table 3. Component Suppliers
MAX5037A
VRM 9.0/VRM 9.1, Dual-Phase,
Parallelable, Average-Current-Mode Controller
Although lower switching frequencies per phase increase
the peak-to-peak inductor ripple current (∆IL), the ripple
cancellation in the multiphase topology reduces the RMS
ripple current of the input and output capacitor.
Use the following equation to determine the minimum
inductance value:
LMIN =
(VINMAX
− VOUT ) × VOUT
VIN × fSW × ∆IL
(8)
Choose ∆IL equal to about 40% of the output current
per phase. Since ∆IL affects the output ripple voltage,
the inductance value may need minor adjustment after
choosing the output capacitors for full-rated efficiency.
Choose inductors from the standard high-current, surface-mount inductor series available from various manufacturers. Particular applications may require
custom-made inductors. Use high-frequency core material for custom inductors. High ∆IL causes large peak-topeak flux excursion increasing the core losses at higher
frequencies. The high-frequency operation coupled with
high ∆IL, reduces the required minimum inductance
making possible even the use of planar inductors. The
advantages of using planar magnetics include low-profile design, excellent current sharing between phases
due to the tight control of parasitics, and low cost.
For example, calculate the minimum inductance at
VIN(MAX) = +13.2V, VOUT = +1.75V, ∆IL = 10A, and fSW =
250kHz:
LMIN =
(13.2 − 1.75) × 1.75 = 0.6µH
13.2 × 250k × 10
(9)
The MAX5037A average current-mode control feature
limits the maximum peak-inductor current and prevents
the inductor from saturating. Choose an inductor with a
saturating current greater than the worst-case peak
inductor current. Use the following equation to determine
the worst-case inductor current for each phase:
IL _ PEAK =
0.051
∆I
+ L
RSENSE
2
where RSENSE is the sense resistor in each phase. (10)
Switching MOSFETs
When choosing a MOSFET for voltage regulators, consider the total gate charge, RDS(ON), power dissipation,
and package thermal impedance. The product of the
gate charge and on-resistance of the MOSFET is a figure
of merit, with a lower number signifying better performance. Choose MOSFETs optimized for high-frequency
switching applications.
The average current from the MAX5037A gate-drive
output is proportional to the total capacitance it drives
from DH1, DH2, DL1, and DL2. The power dissipated in
the MAX5037A is proportional to the input voltage and
the average drive current. See the VIN, VCC, and VDD
section to determine the maximum total gate charge
allowed from all the driver outputs combined.
The gate charge and drain capacitance (CV2) loss, the
cross-conduction loss in the upper MOSFET due to
finite rise/fall time, and the I2R loss due to RMS current
in the MOSFET RDS(ON) account for the total losses in
the MOSFET. Estimate the power loss (PDMOS_) in the
high-side and low-side MOSFETs using the following
equations:
(11)
PDMOS−HI = (QG × VDD × fSW ) +
⎛ VIN × IOUT × (tR + tF ) × fSW ⎞
2
⎜
⎟ + 1.4RDS(ON) × I RMS−HI
4
⎝
⎠
where QG, RDS(ON), tR, and tF are the upper switching
MOSFET’s total gate charge, on-resistance at +25°C,
rise time, and fall time, respectively:
D
2
2
DC + I PK + IDC × IPK ×
(I
IRMS−HI =
)
(12)
3
where D = V OUT /V IN , I DC = (I OUT - ∆I L )/2 and I PK =
(IOUT + ∆IL)/2.
PDMOS−LO = (QG × VDD × fSW ) +
(13)
2
⎛ 2×C
⎞
2
OSS × VIN × fSW + 1.4R
⎜
⎟
DS(ON) × I RMS−LO
3
⎝
⎠
IRMS−LO =
(
)
I2DC + I2PK + IDC × IPK ×
(1− D)
(14)
3
where COSS is the MOSFET drain-to-source capacitance.
26
______________________________________________________________________________________
VRM 9.0/VRM 9.1, Dual-Phase,
Parallelable, Average-Current-Mode Controller
TJ = PDMOS x θJ-A + TA
(15)
Input Capacitors
The discontinuous input-current waveform of the buck
converter causes large ripple currents in the input
capacitor. The switching frequency, peak inductor current, and the allowable peak-to-peak voltage ripple
reflected back to the source dictate the capacitance
requirement. Increasing the number of phases increases the effective switching frequency and lowers the
peak-to-average current ratio, yielding a lower input
capacitance requirement.
The input ripple comprises ∆VQ (caused by the capacitor
discharge) and ∆VESR (caused by the ESR of the capacitor). Use low-ESR ceramic capacitors with high ripplecurrent capability at the input. Assume the contributions
from the ESR and capacitor discharge are equal to 30%
and 70%, respectively. Calculate the input capacitance
and ESR required for a specified ripple using the following equations:
ESRIN =
(∆VESR )
⎛ IOUT ∆IL ⎞
+
⎜
⎟
⎝ N
2 ⎠
IOUT
× D(1 − D)
CIN = N
∆VQ × fSW
(16)
(17)
where IOUT is the total output current of the multiphase
converter and N is the number of phases.
For example, at V OUT = 1.75V, the ESR and input
capacitance are calculated for the input peak-to-peak
ripple of 100mV or less yielding an ESR and capacitance value of 1mΩ and 200µF.
Output Capacitors
The worst-case peak-to-peak and capacitor RMS ripple
current, the allowable peak-to-peak output ripple voltage, and the maximum deviation of the output voltage
during step loads determine the capacitance and the
ESR requirements for the output capacitors.
In multiphase converter design, the ripple currents from
the individual phases cancel each other and lower the
ripple current. The degree of ripple cancellation
depends on the operating duty cycle and the number of
phases. Choose the right equation from Table 4 to calculate the peak-to-peak output ripple for a given duty
cycle of two-, four-, and six-phase converters. The maximum ripple cancellation occurs when NPH = K / D.
The allowable deviation of the output voltage during the
fast-transient load dictates the output capacitance and
ESR. The output capacitors supply the load step until
the controller responds with a greater duty cycle. The
response time (tRESPONSE) depends on the closed-loop
bandwidth of the converter. The resistive drop across
the capacitor ESR and capacitor discharge causes a
voltage drop during a step load. Use a combination of
SP polymer and ceramic capacitors for better transient
load and ripple/noise performance.
Table 4. Peak-to-Peak Output Ripple
Current Calculations
NO. OF
DUTY
PHASES (N) CYCLE (D) (%)
EQUATION FOR ∆IP-P
V (1 − 2D)
∆I = O
L × fSW
2
< 50
2
> 50
4
0 to 25
V (1− 4D)
∆I = O
L × fSW
4
25 to 50
V (1 − 2D)(4D − 1)
∆I = O
2 × D × L × fSW
4
> 50
V (2D − 1)(3 − 4D)
∆I = O
D × L × fSW
6
< 17
V (1− 6D)
∆I = O
L × fSW
∆I =
(VIN − VO )(2D − 1)
L × fSW
______________________________________________________________________________________
27
MAX5037A
For example, from the typical VRM specifications in the
Applications Information section with VOUT = +1.75V,
the high-side and low-side MOSFET RMS currents are
9.9A and 24.1A, respectively. Ensure that the thermal
impedance of the MOSFET package keeps the junction
temperature at least +25°C below the absolute maximum rating. Use the following equation to calculate
maximum junction temperature:
MAX5037A
VRM 9.0/VRM 9.1, Dual-Phase,
Parallelable, Average-Current-Mode Controller
Keep the maximum output voltage deviation less than
or equal to the adaptive voltage-positioning window
(∆VOUT). Assume 50% contribution each from the output capacitance discharge and the ESR drop. Use the
following equations to calculate the required ESR and
capacitance value:
ESROUT =
∆VESR
ISTEP
(18)
I
×t
COUT = STEP RESPONSE
∆VQ
(19)
where I STEP is the load step and t RESPONSE is the
response time of the controller. Controller response
time depends on the control-loop bandwidth.
Compensation
The main control loop consists of an inner current loop
and an outer voltage loop. The MAX5037A uses an
average current-mode control scheme to regulate the
output voltage (Figure 3). IPHASE1 and IPHASE2 are the
inner average current loops. The VEA output provides
the controlling voltage for these current sources. The
inner current loop absorbs the inductor pole reducing
the order of the outer voltage loop to that of a singlepole system.
A resistive feedback network around the VEA provides
the best possible response, since there are no capacitors to charge and discharge during large-signal excursions. The required amount of adaptive voltage
positioning (∆VOUT) determines the VEA gain. Use the
following equation to calculate the value for RF when
using adaptive voltage positioning:
RF =
Current Limit
The average current-mode control technique of the
MAX5037A accurately limits the maximum output current per phase. The MAX5037A senses the voltage
across the sense resistor and limits the peak inductor
current (IL-PK) accordingly. The ON cycle terminates
when the current-sense voltage reaches 45mV (min).
Use the following equation to calculate maximum current-sense resistor value:
RSENSE =
PDR =
0.045
IOUT
N
2.5 × 10−3
RSENSE
(20)
(22)
0.05
RS
(23)
GC =
where GC is the current-source transconductance and
N is the number of phases.
When designing the current-control loop ensure that the
inductor downslope (when it becomes an upslope at the
CEA output) does not exceed the ramp slope. This is a
necessary condition to avoid subharmonic oscillations
similar to those in peak current-mode control with insufficient slope compensation. Use the following equation to
calculate the resistor RCF:
(21)
where PDR is the power dissipation in sense resistors.
Select 5% lower value of RSENSE to compensate for any
parasitics associated with the PC board. Also, select a
noninductive resistor with the appropriate wattage rating.
IOUT × RIN
N × GC × ∆VOUT
RCF ≤
2 × fSW × L × 102
VOUT × RSENSE
For example, the maximum RCF is 12kΩ for RSENSE =
1.35mΩ.
Reverse Current Limit
The MAX5037A limits the reverse current in the case that
VBUS is higher than the preset output voltage setting.
Calculate the maximum reverse current based on VCLR,
the reverse current-limit threshold, and the currentsense resistor:
IREVERSE =
28
(24)
2 x VCLR
RSENSE
______________________________________________________________________________________
VRM 9.0/VRM 9.1, Dual-Phase,
Parallelable, Average-Current-Mode Controller
1
CCF =
2 × π × fZ × RCF
(25)
BST2
SGND
CLKOUT
N.C.
CLKIN
CSP2
CSN2
PHASE
PLLCMP
CLP2
VID4
Pin Configuration
44 43 42 41 40 39 38 37 36 35 34
VID3 1
33 N.C
VID2 2
32 DH2
VID1 3
31 LX2
VID0 4
30 DL2
SGND 5
29 PGND
OVPIN 6
1
CCFF =
2 × π × fP × RCF
28 IN
MAX5037A
CLP1 7
27 VCC
OVPOUT 8
26 VDD
PGOOD 9
25 DL1
PC Board Layout
SENSE+ 10
24 LX1
Use the following guidelines to lay out the switching
voltage regulator.
1) Place the V IN , V CC, and V DD bypass capacitors
close to the MAX5037A.
2) Minimize the area and length of the high-current
loops from the input capacitor, upper switching
MOSFET, inductor, and output capacitor back to
the input capacitor negative terminal.
3) Keep short the current loop formed by the lower
switching MOSFET, inductor, and output capacitor.
4) Place the Schottky diodes close to the lower
MOSFETs and on the same side of the PC board.
5) Keep the SGND and PGND isolated and connect
them at one single point close to the negative terminal of the input filter capacitor.
6) Run the current-sense lines CS+ and CS- very
close to each other to minimize the loop area.
Similarly, run the remote voltage sense lines
SENSE+ and SENSE- close to each other. Do not
cross these critical signal lines through power circuitry. Sense the current right at the pads of the
current-sense resistors.
SENSE- 11
7) Avoid long traces between the VDD bypass capacitors, driver output of the MAX5037A, MOSFET
gates, and PGND. Minimize the loop formed by the
VDD bypass capacitors, bootstrap diode, bootstrap
capacitor, MAX5037A, and upper MOSFET gate.
23 DH1
BST1
N.C.
SGND
EN
CNTR
CSN1
CSP1
REG
EAEOUT
EAN
12 13 14 15 16 17 18 19 20 21 22
DIFF
(26)
MQFP/THIN QFN*
*CONNECT THE QFN EXPOSED PAD TO SGND GROUND PLANE.
8) Place the bank of output capacitors close to the load.
9) Distribute the power components evenly across the
board for proper heat dissipation.
10) Provide enough copper area at and around the
switching MOSFETs, inductor, and sense resistors
to aid in thermal dissipation.
11) Use 4oz copper to keep the trace inductance and
resistance to a minimum. Thin copper PC boards
can compromise efficiency since high currents are
involved in the application. Also, thicker copper
conducts heat more effectively, thereby reducing
thermal impedance.
Chip Information
TRANSISTOR COUNT: 5431
PROCESS: BiCMOS
______________________________________________________________________________________
29
MAX5037A
CCF provides a low-frequency pole while RCF provides a
midband zero. Place a zero at fZ to obtain a phase bump
at the crossover frequency. Place a high-frequency pole
(fP) at least a decade away from the crossover frequency
to reduce the influence of the switching noise and
achieve maximum phase margin. Use the following
equations to calculate CCF and CCFF:
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
MQFP44.EPS
MAX5037A
VRM 9.0/VRM 9.1, Dual-Phase,
Parallelable, Average-Current-Mode Controller
PACKAGE OUTLINE
44L MQFP, 1.60 LEAD FORM
21-0826
30
______________________________________________________________________________________
D
1
1
VRM 9.0/VRM 9.1, Dual-Phase,
Parallelable, Average-Current-Mode Controller
DETAIL A
32, 44, 48L QFN.EPS
E
(NE-1) X e
E/2
k
e
D/2
CL
(ND-1) X e
D
D2
D2/2
b
L
E2/2
e
E2
CL
L
L1
CL
k
DETAIL B
CL
L
L
e
A1
A2
e
A
PACKAGE OUTLINE
32, 44, 48, 56L THIN QFN, 7x7x0.8mm
21-0144
E
1
2
PACKAGE OUTLINE
32, 44, 48, 56L THIN QFN, 7x7x0.8mm
21-0144
E
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 31
© 2004 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
MAX5037A
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)