TI ADS8331IBRGER Low-power, 16-bit, 500ksps, 4-/8-channel unipolar input analog-to-digital converters with serial interface Datasheet

ADS8331
ADS8332
www.ti.com
SBAS363 – DECEMBER 2009
Low-Power, 16-Bit, 500kSPS, 4-/8-Channel Unipolar Input
ANALOG-TO-DIGITAL CONVERTERS with Serial Interface
Check for Samples: ADS8331, ADS8332
FEATURES
DESCRIPTION
• Low-Power, Flexible Supply Range:
– 2.7V to 5.5V Analog Supply
– 8.7mW (250kSPS in Auto-Nap Mode,
VA = 2.7V, VBD = 1.65V)
– 14.2mW (500kSPS, VA = 2.7V, VBD = 1.65V)
• Up to 500kSPS Sampling Rate
• Excellent DC Performance:
– ±1.2 LSB Typ, ±2 LSB Max INL at 2.7V
– ±0.6 LSB Typ, –1.0/1.5 LSB Max DNL at 2.7V
– 16-Bit NMC Over Temperature
• Excellent AC Performance at 5V, fIN = 1kHz:
– 91.5dB SNR, 101dB SFDR, –100dB THD
• Flexible Analog Input Arrangement:
– On-Chip 4-/8-Channel Mux with Breakout
– Auto/Manual Channel Select and Trigger
• Other Hardware Features:
– On-Chip Conversion Clock (CCLK)
– Software/Hardware Reset
– Programmable Status/Polarity EOC/INT
– Daisy-Chain Mode
– Global CONVST (Independent of CS)
– Deep, Nap, and Auto-Nap Powerdown
Modes
– SPI™/DSP Compatible Serial Interface
– Separate I/O Supply: 1.65V to VA
– SCLK up to 40MHz (VA = VBD = 5V)
• 24-Pin 4x4 QFN and 24-Pin TSSOP(1) Packages
The ADS8331 is a low-power, 16-bit, 500k
samples-per-second (SPS) analog-to-digital converter
(ADC) with a unipolar, 4-to-1 multiplexer (mux) input.
The device includes a 16-bit capacitor-based
successive approximation register (SAR) ADC with
inherent sample and hold.
1
234
The ADS8332 is based on the same core and
includes a unipolar 8-to-1 input mux. Both devices
offer a high-speed, wide-voltage serial interface and
are capable of daisy-chain operation when multiple
converters are used.
These converters are available in 24-pin, 4x4 QFN
and 24-pin TSSOP (1) packages and are fully specified
for operation over the industrial –40°C to +85°C
temperature range.
Low-Power, High-Speed, SAR Converter Family
RESOLUTION/TYPE
Communications
Transducer Interfaces
Medical Instruments
Magnetometers
Industrial Process Control
Data Acquisition Systems
Automatic Test Equipment
500kSPS
1MHz
1
ADS8327
ADS8329
2
ADS8328
ADS8330
4
ADS8331
—
8
ADS8332
—
1
—
ADS7279
2
—
ADS7280
4
ADS8301
—
8
ADS8302
—
1
—
ADS7229
2
—
ADS7230
16-Bit Pseudo-Diff
14-Bit Pseudo-Diff
12-Bit Pseudo-Diff
BLANKSPACE
Functional Block Diagram
APPLICATIONS
•
•
•
•
•
•
•
CHANNELS
MUXOUT
IN[0:3]
or
IN[0:7]
ADCIN
SAR
M
U
X
+
_
COM
Output
Latch
and
3-State
Driver
SDO
CDAC
FS/CS
Comparator
REF+
REF-
Conversion
and
Control
Logic
SCLK
SDI
CONVST
EOC/INT/CDI
RESET
(1)
TSSOP (PW) package available Q1, 2010.
1
2
3
4
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TMS320 is a trademark of Texas Instruments.
SPI is a trademark of Motorola, Inc..
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
ADS8331
ADS8332
SBAS363 – DECEMBER 2009
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION (1)
PRODUCT
ADS8331I
MAXIMUM
INTEGRAL
LINEARITY
(LSB)
MAXIMUM
DIFFERENTIAL
LINEARITY
(LSB)
±3
PACKAGE-LEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
TSSOP-24 (2)
PW
–40°C to +85°C
TSSOP-24
±2
(2)
TSSOP-24 (2)
±3
TSSOP-24 (2)
±2
(2)
RGE
ADS8331IRGET
Small tape and reel, 250
ADS8331IRGER
Tape and reel, 3000
PW
–40°C to +85°C
ADS8331IBPWT
Tube 90
ADS8331IBPWR
Tape and reel, 2000
ADS8331IBRGET
Small tape and reel, 250
ADS8331IBRGER
Tape and reel, 3000
–40°C to +85°C
RGE
PW
–40°C to +85°C
ADS8332IPWT
Tube, 90
ADS8332IPWR
Tape and reel, 2000
ADS8332IRGET
Small tape and reel, 250
ADS8332IRGER
Tape and reel, 3000
–40°C to +85°C
RGE
PW
–40°C to +85°C
ADS8332IBPWT
Tube, 90
ADS8332IBPWR
Tape and reel, 2000
ADS8332IBRGET
Small tape and reel, 250
ADS8332IBRGER
Tape and reel, 3000
–40°C to +85°C
–1/+1.5
4X4 QFN-24
(1)
Tube, 90
Tape and reel, 2000
–1/+2
4X4 QFN-24
ADS8332IB
ADS8331IPWT
ADS8331IPWR
–1/+1.5
4X4 QFN-24
ADS8332I
TRANSPORT
MEDIA, QUANTITY
–1/+2
4X4 QFN-24
ADS8331IB
ORDERING
INFORMATION
RGE
–40°C to +85°C
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
TSSOP (PW) package available Q1, 2010.
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range, unless otherwise noted. (1)
ADS8331, ADS8332
UNIT
–0.3 to VA + 0.3
V
–0.3 to 0.3
V
VA to AGND
–0.3 to 7
V
VBD to BDGND
–0.3 to 7
V
–0.3 to 0.3
V
Digital input voltage to BDGND
–0.3 to VBD + 0.3
V
Digital output voltage to BDGND
–0.3 to VBD + 0.3
V
Operating free-air temperature range, (TA)
–40 to +85
°C
Storage temperature range, (TSTG)
–65 to +150
°C
+150
°C
Voltage
Voltage range
INX, MUXOUT, ADCIN, REF+ to AGND
COM, REF– to AGND
AGND to BDGND
Junction temperature (TJ Max)
4x4 QFN-24
Package
Power dissipation
TSSOP-24
Package
Power dissipation
(1)
2
(TJMax – TA)/θJA
W
47
°C/W
θJA thermal impedance
(TJMax – TA)/θJA
W
47
°C/W
θJA thermal impedance
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): ADS8331 ADS8332
ADS8331
ADS8332
www.ti.com
SBAS363 – DECEMBER 2009
ELECTRICAL CHARACTERISTICS: VA = 2.7V
At TA = –40°C to +85°C, VA = 2.7V, VBD = 1.65V to 2.7V, VREF = 2.5V, and fSAMPLE = 500kSPS, unless otherwise noted.
ADS8331I, ADS8332I
PARAMETER
TEST CONDITIONS
MIN
TYP
ADS8331IB, ADS8332IB
MAX
MIN
VREF
TYP
MAX
UNIT
0
VREF
V
VA + 0.2 AGND – 0.2
VA + 0.2
V
ANALOG INPUT
Full-scale input voltage
(1)
Absolute input voltage
INX – COM, ADCIN – COM
0
INX, ADCIN
AGND – 0.2
COM
AGND – 0.2
Input capacitance
ADCIN
Input leakage current
Unselected ADC input
AGND + 0.2 AGND – 0.2
40
–1
45
1
40
–1
AGND + 0.2
V
45
pF
1
nA
SYSTEM PERFORMANCE
Resolution
16
16
Bits
No missing codes
16
INL
Integral linearity
–3
±2
3
–2
±1.2
2
LSB (2)
DNL
Differential linearity
–1
±0.6
2
–1
±0.6
1.5
LSB (2)
–0.5
±0.15
0.5
–0.5
±0.15
0.5
EO
Offset error
(3)
Offset error drift
±1
Offset error matching
EG
–0.25
Gain error drift
–0.06
–0.003
mV
PPM/°C
±0.2
0.25
–0.25
0.003
–0.003
±0.4
Gain error matching
Bits
±1
±0.2
Gain error
PSRR
16
–0.06
mV
0.25
±0.4
%FSR
PPM/°C
0.003
%FSR
Transition noise
28
28
μV RMS
Power-supply rejection ratio
74
74
dB
18
CCLK
SAMPLING DYNAMICS
tCONV
tSAMPLE1
tSAMPLE2
Conversion time
18
Manual-Trigger mode
Acquisition time
Auto-Trigger mode
3
3
3
Throughput rate
CCLK
3
500
CCLK
500
kSPS
Aperture delay
15
15
ns
Aperture jitter
10
10
ps
Step response
100
100
ns
Overvoltage recovery
100
100
ns
VIN = 2.5VPP at 1kHz
–101
–101
dB
VIN = 2.5VPP at 10kHz
–95
–95
dB
VIN = 2.5VPP at 1kHz
88
89
dB
VIN = 2.5VPP at 10kHz
86.5
87.5
dB
VIN = 2.5VPP at 1kHz
87.5
88.5
dB
VIN = 2.5VPP at 10kHz
86
87
dB
VIN = 2.5VPP at 1kHz
103
103
dB
VIN = 2.5VPP at 10kHz
98
98
dB
VIN = 2.5VPP at 1kHz
125
125
dB
VIN = 2.5VPP at 100kHz
108
108
dB
INX – COM with MUXOUT
tied to ADCIN
17
17
MHz
ADCIN – COM
30
30
MHz
DYNAMIC CHARACTERISTICS
THD
Total harmonic distortion
SNR
(4)
Signal-to-noise ratio
SINAD
SFDR
Signal-to-noise + distortion
Spurious-free dynamic range
Crosstalk
–3dB small-signal bandwidth
(1)
(2)
(3)
(4)
Ideal input span; does not include gain or offset error.
LSB means least significant bit.
Measured relative to an ideal full-scale input (INX – COM) of 2.5V when VA = 2.7V.
Calculated on the first nine harmonics of the input frequency.
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): ADS8331 ADS8332
3
ADS8331
ADS8332
SBAS363 – DECEMBER 2009
www.ti.com
ELECTRICAL CHARACTERISTICS: VA = 2.7V (continued)
At TA = –40°C to +85°C, VA = 2.7V, VBD = 1.65V to 2.7V, VREF = 2.5V, and fSAMPLE = 500kSPS, unless otherwise noted.
ADS8331I, ADS8332I
PARAMETER
TEST CONDITIONS
ADS8331IB, ADS8332IB
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
10.5
11
12.2
10.5
11
12.2
MHz
25
MHz
MHz
CLOCK
Internal conversion clock
frequency
Used as I/O clock only
SCLK external serial clock
Used as both I/O clock and
conversion clock
25
1
21
1
21
1.2
2.525
1.2
2.525
0.1
–0.1
EXTERNAL VOLTAGE REFERENCE INPUT
VREF
Input
reference
range (5)
Resistance
(REF+) – (REF–)
(REF–) – AGND
(6)
–0.1
Reference input
0.1
20
20
CMOS
CMOS
V
V
kΩ
DIGITAL INPUT/OUTPUT
Logic family
VIH
High-level input voltage
VA ≥ VBD ≥ 1.65V
0.65 ×
(VBD)
VBD + 0.3
0.65 ×
(VBD)
VBD + 0.3
V
VIL
Low-level input voltage
VA ≥ VBD ≥ 1.65V
–0.3
0.25 ×
(VBD)
–0.3
0.25 ×
(VBD)
V
II
Input current
VIN = VBD or DGND
–50
50
–50
50
nA
CI
Input capacitance
5
VOH
High-level output voltage
VA ≥ VBD ≥ 1.65V,
IO = 100μA
VOL
Low-level output voltage
VA ≥ VBD ≥ 1.65V,
IO = –100μA
CO
SDO pin capacitance
Hi-Z state
CL
Load capacitance
5
VBD – 0.6
VBD
VBD – 0.6
VBD
V
0
0.4
0
0.4
V
5
5
30
Data format
pF
Straight binary
pF
30
pF
V
Straight binary
POWER-SUPPLY REQUIREMENTS
VA
Analog supply voltage (5)
2.7
3.6
2.7
3.6
VBD
Digital I/O supply voltage
1.65
VA + 0.2
1.65
VA + 0.2
IA
IBD
Analog supply current
Digital I/O supply current
Power dissipation
5.2
fSAMPLE = 250kSPS in
Auto-Nap mode
3.2
Nap mode, SCLK = VBD or
DGND
325
400
325
400
μA
Deep PD mode, SCLK = VBD
or DGND
50
250
50
250
nA
fSAMPLE = 500kSPS
0.1
0.4
0.1
0.4
mA
fSAMPLE = 250kSPS in
Auto-Nap mode
0.05
VA = 2.7V, VBD = 1.65V,
fSAMPLE = 500kSPS
14.2
VA = 2.7V, VBD = 1.65V,
fSAMPLE = 250kSPS in
Auto-Nap mode
8.72
6.5
5.2
6.5
V
fSAMPLE = 500kSPS
3.2
mA
0.05
18.2
14.2
mA
mA
18.2
8.72
mW
mW
TEMPERATURE RANGE
TA
(5)
(6)
4
Operating free-air temperature
–40
+85
–40
+85
°C
The ADS8331/32 operates with VA between 2.7V and 5.5V, and VREF between 1.2V and VA. However, the device may not meet the
specifications listed in the Electrical Characteristics when VA is between 3.6V and 4.5V.
Can vary ±30%.
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): ADS8331 ADS8332
ADS8331
ADS8332
www.ti.com
SBAS363 – DECEMBER 2009
ELECTRICAL CHARACTERISTICS: VA = 5V
At TA = –40°C to +85°C, VA = 5V, VBD = 1.65V to 5V, VREF = 4.096V, and fSAMPLE = 500kSPS, unless otherwise noted.
ADS8331I, ADS8332I
PARAMETER
TEST CONDITIONS
MIN
TYP
ADS8331IB, ADS8332IB
MAX
MIN
VREF
TYP
MAX
UNIT
0
VREF
V
VA + 0.2 AGND – 0.2
VA + 0.2
V
ANALOG INPUT
Full-scale input voltage
(1)
Absolute input voltage
INX – COM, ADCIN – COM
0
INX, ADCIN
AGND – 0.2
COM
AGND – 0.2
Input capacitance
ADCIN
Input leakage current
Unselected ADC input
AGND + 0.2 AGND – 0.2
40
–1
45
1
40
–1
AGND + 0.2
V
45
pF
1
nA
SYSTEM PERFORMANCE
Resolution
16
16
Bits
No missing codes
16
INL
Integral linearity
–3
±2
3
–2
±1
2
LSB (2)
DNL
Differential linearity
–1
±1
2
–1
±0.5
1.5
LSB (2)
–1
±0.23
1
–1
±0.23
1
EO
Offset error
(3)
Offset error drift
±1
Offset error matching
EG
–0.125
Gain error
–0.25
Gain error drift
–0.06
–0.003
Bits
±1
0.125
–0.125
0.25
–0.25
0.003
–0.003
±0.02
Gain error matching
PSRR
16
–0.06
mV
PPM/°C
0.125
mV
0.25
%FSR
±0.02
PPM/°C
0.003
%FSR
Transition noise
30
30
μV RMS
Power-supply rejection ratio
78
78
dB
18
CCLK
SAMPLING DYNAMICS
tCONV
tSAMPLE1
tSAMPLE2
Conversion time
18
Manual-Trigger mode
Acquisition time
Auto-Trigger mode
3
3
3
Throughput rate
CCLK
3
500
CCLK
500
kSPS
Aperture delay
10
10
ns
Aperture jitter
10
10
ps
Step response
100
100
ns
Overvoltage recovery
100
100
ns
VIN = 4.096VPP at 1kHz
–100
–100
dB
VIN = 4.096VPP at 10kHz
–94
–95
dB
VIN = 4.096VPP at 1kHz
90.5
91.5
dB
VIN = 4.096VPP at 10kHz
88
88
dB
VIN = 4.096VPP at 1kHz
90
91
dB
VIN = 4.096VPP at 10kHz
87
87
dB
VIN = 4.096VPP at 1kHz
101
101
dB
VIN = 4.096VPP at 10kHz
96
96
dB
VIN = 4.096VPP at 1kHz
119
119
dB
VIN = 4.096VPP at 100kHz
107
107
dB
INX – COM with MUXOUT
tied to ADCIN
22
22
MHz
ADCIN – COM
40
40
MHz
DYNAMIC CHARACTERISTICS
THD
Total harmonic distortion
SNR
(4)
Signal-to-noise ratio
SINAD
SFDR
Signal-to-noise + distortion
Spurious-free dynamic range
Crosstalk
–3dB small-signal bandwidth
(1)
(2)
(3)
(4)
Ideal input span; does not include gain or offset error.
LSB means least significant bit.
Measured relative to an ideal full-scale input (INX – COM) of 4.096V when VA = 5V.
Calculated on the first nine harmonics of the input frequency.
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): ADS8331 ADS8332
5
ADS8331
ADS8332
SBAS363 – DECEMBER 2009
www.ti.com
ELECTRICAL CHARACTERISTICS: VA = 5V (continued)
At TA = –40°C to +85°C, VA = 5V, VBD = 1.65V to 5V, VREF = 4.096V, and fSAMPLE = 500kSPS, unless otherwise noted.
ADS8331I, ADS8332I
PARAMETER
TEST CONDITIONS
ADS8331IB, ADS8332IB
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
10.9
11.5
12.6
10.9
11.5
12.6
MHz
40
MHz
21
MHz
4.2
V
CLOCK
Internal conversion clock
frequency
Used as I/O clock only
SCLK external serial clock
Used as both I/O clock and
conversion clock
40
1
21
1
4.2
1.2
0.1
–0.1
EXTERNAL VOLTAGE REFERENCE INPUT
VREF
Input
reference
range (5)
Resistance
(REF+) – (REF–)
1.2
(REF–) – AGND
(6)
4.096
–0.1
Reference input
4.096
0.1
20
20
CMOS
CMOS
V
kΩ
DIGITAL INPUT/OUTPUT
Logic family
VIH
High-level input voltage
VA ≥ VBD ≥ 1.65V
0.65 ×
(VBD)
VBD + 0.3
0.65 ×
(VBD)
VBD + 0.3
V
VIL
Low-level input voltage
VA ≥ VBD ≥ 1.65V
–0.3
0.25 ×
(VBD)
–0.3
0.25 ×
(VBD)
V
II
Input current
VIN = VBD or DGND
–50
50
–50
50
nA
CI
Input capacitance
5
VOH
High-level output voltage
VA ≥ VBD ≥ 1.65V,
IO = 100μA
VOL
Low-level output voltage
VA ≥ VBD ≥ 1.65V,
IO = –100μA
CO
SDO pin capacitance
Hi-Z state
CL
Load capacitance
5
VBD – 0.6
VBD
VBD – 0.6
VBD
V
0
0.4
0
0.4
V
5
5
30
Data format
pF
Straight binary
pF
30
pF
5.5
V
Straight binary
POWER-SUPPLY REQUIREMENTS
VA
Analog supply voltage (5)
4.5
VBD
Digital I/O supply voltage
1.65
IA
IBD
Analog supply current
Digital I/O supply current
Power dissipation
5
5.5
4.5
VA + 0.2
1.65
7.75
5
VA + 0.2
6.6
7.75
V
fSAMPLE = 500kSPS
6.6
fSAMPLE = 250kSPS in
Auto-Nap mode
4.2
Nap mode, SCLK = VBD or
DGND
390
500
390
500
μA
Deep PD mode, SCLK = VBD
or DGND
80
250
80
250
nA
fSAMPLE = 500kSPS
1.2
2.0
1.2
2.0
mA
fSAMPLE = 250kSPS in
Auto-Nap mode
0.7
VA = 5.0V, VBD = 5.0V,
fSAMPLE = 500kSPS
39
VA = 5.0V, VBD = 5.0V,
fSAMPLE = 250kSPS in
Auto-Nap mode
24.5
4.2
mA
0.7
48.75
39
mA
mA
48.75
24.5
mW
mW
TEMPERATURE RANGE
TA
(5)
(6)
6
Operating free-air temperature
–40
+85
–40
+85
°C
The ADS8331/32 operates with VA between 2.7V and 5.5V, and VREF between 1.2V and VA. However, the device may not meet the
specifications listed in the Electrical Characteristics when VA is between 3.6V and 4.5V.
Can vary ±30%.
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): ADS8331 ADS8332
ADS8331
ADS8332
www.ti.com
SBAS363 – DECEMBER 2009
TIMING CHARACTERISTICS: VA = 2.7V
At TA = –40°C to +85°C, VA = 2.7V, and VBD = 1.65V, unless otherwise noted.
(1) (2)
PARAMETER
MIN
External, fCCLK = 1/2 fSCLK
fCCLK Frequency, conversion clock, CCLK
Internal
TYP
0.5
10.5
11
MAX
UNIT
10.5
MHz
12.2
MHz
tSU1
Setup time, rising edge of CS to EOC
1
CCLK
tH1
Hold time, rising edge of CS to EOC
25
ns
tWL1
Pulse duration, CONVST low
40
ns
tWH1
Pulse duration, CS high
40
ns
tSU2
Setup time, rising edge of CS to EOS
25
ns
tH2
Hold time, rising edge of CS to EOS
25
ns
tSU3
Setup time, falling edge of CS to first falling edge of SCLK
14
ns
tWL2
Pulse duration, SCLK low
17
tSCLK – 17
ns
tWH2
Pulse duration, SCLK high
12
tSCLK – 12
ns
I/O clock only
40
I/O and conversion clocks
tSCLK Cycle time, SCLK
I/O clock, daisy-chain mode
I/O and conversion clocks,
daisy-chain mode
47.6
ns
1000
40
47.6
ns
ns
1000
tD1
Delay time, falling edge of SCLK to SDO invalid
10pF load
tD2
Delay time, falling edge of SCLK to SDO valid
10pF load
35
ns
tD3
Delay time, falling edge of CS to SDO valid, SDO MSB output
10pF load
35
ns
tSU4
Setup time, SDI to falling edge of SCLK
8
tH3
Hold time, SDI to falling edge of SCLK
8
tD4
Delay time, rising edge of CS to SDO 3-state
tSU5
Setup time, last falling edge of SCLK before rising edge of CS
tD5
Delay time, falling edge of CS to deactivation of INT
tD6
Delay time, CDI to SDO in daisy-chain mode
(1)
(2)
8
ns
ns
ns
ns
10
10
10pF load
ns
ns
40
ns
35
ns
All input signals are specified with tr = tf = 1.5ns (10% to 90% of VBD) and timed from a voltage level of (VIL + VIH)/2.
See the Timing Diagrams section.
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TIMING CHARACTERISTICS: VA = 5V
At TA = –40°C to +85°C, and VA = VBD = 5V, unless otherwise noted.
(1) (2)
PARAMETER
MIN
External, fCCLK = 1/2 fSCLK
fCCLK Frequency, conversion clock, CCLK
Internal
TYP
0.5
10.9
11.5
MAX
UNIT
10.5
MHz
12.6
MHz
tSU1
Setup time, rising edge of CS to EOC
1
CCLK
tH1
Hold time, rising edge of CS to EOC
20
ns
tWL1
Pulse duration, CONVST low
40
ns
tWH1
Pulse duration, CS high
40
ns
tSU2
Setup time, rising edge of CS to EOS
20
ns
tH2
Hold time, rising edge of CS to EOS
20
ns
tSU3
Setup time, falling edge of CS to first falling edge of SCLK
8
ns
tWL2
Pulse duration, SCLK low
12
tSCLK – 12
ns
tWH2
Pulse duration, SCLK high
11
tSCLK – 11
ns
I/O clock only
25
I/O and conversion clocks
tSCLK Cycle time, SCLK
I/O clock, daisy-chain mode
I/O and conversion clocks,
daisy-chain mode
47.6
ns
1000
25
47.6
ns
ns
1000
tD1
Delay time, falling edge of SCLK to SDO invalid
10pF load
tD2
Delay time, falling edge of SCLK to SDO valid
10pF load
20
ns
tD3
Delay time, falling edge of CS to SDO valid, SDO MSB output
10pF load
20
ns
tSU4
Setup time, SDI to falling edge of SCLK
8
tH3
Hold time, SDI to falling edge of SCLK
8
tD4
Delay time, rising edge of CS to SDO 3-state
tSU5
Setup time, last falling edge of SCLK before rising edge of CS
tD5
Delay time, falling edge of CS to deactivation of INT
tD6
Delay time, CDI to SDO in daisy-chain mode
(1)
(2)
8
5
ns
ns
ns
ns
10
10
10pF load
ns
ns
20
ns
20
ns
All input signals are specified with tr = tf = 1.5ns (10% to 90% of VBD) and timed from a voltage level of (VIL + VIH)/2.
See the Timing Diagrams section.
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TIMING DIAGRAMS
tWL1
CONVST
EOC
(active low)
tSU2
tH1
tSU5
CS
tSCLK
SCLK
tD1
SDO
High-Z
MSB
MSB - 1 MSB - 2 MSB - 3
tD3
SDI
'1'
LSB + 1
tD2
LSB
TAG2
X
X
tD4
TAG1
TAG0
'0'
High-Z
'0'
tSU4
'1'
'0'
X
'1'
X
X
X
X
tH3
Figure 1. Read While Sampling (Shown with Manual-Trigger Mode)
CONVST
21 Conversion Clock Cycles
EOC
(active low)
tH2
tSU1
CS
tWL2
tSU3
SCLK
tWH2
High-Z
SDO
MSB
LSB
MSB - 1 MSB - 2 MSB - 3
TAG2
TAG1
High-Z
TAG0
tD4
SDI
'1'
'1'
'0'
X
'1'
X
X
X
X
Figure 2. Read While Converting (Shown with Auto-Trigger Mode at 500 kSPS)
CS
tSU3
tSU5
SCLK
tH3
MSB
SDI
tD3
SDO
MSB - 1
tD1
MSB
MSB - 2
LSB + 1
LSB
tD2
MSB - 1
MSB - 2
LSB + 1
LSB
Don’t Care
tD4
‘0’
Figure 3. SPI I/O
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TIMING DIAGRAMS (continued)
CS
tH1
EOC
(active low)
tD5
INT
(active low)
Figure 4. Relationship among CS, EOC, and INT
PIN ASSIGNMENTS
MUXOUT
IN4/NC(1)
1
18
IN5/NC(1)
2
17
IN6/NC(1)
3
IN7/NC(1)
4
RESET
5
EOC/INT/CDI
6
IN1
1
24
IN0
IN2
2
23
COM
IN3
3
22
MUXOUT
IN4/NC(3)
4
21
ADCIN
IN5/NC(3)
5
20
AGND
ADCIN
IN6/NC(3)
6
19
REF-
AGND
IN7/NC(3)
7
18
REF+
RESET
8
17
VA
EOC/INT/CDI
9
16
VBD
SCLK
10
15
CONVST
FS/CS
11
14
DGND
SDI
12
13
SDO
19
COM
PW PACKAGE
TSSOP-24
(TOP VIEW)
20
IN0
21
IN1
22
IN2
23
24
IN3
RGE PACKAGE
4x4 QFN-24
(TOP VIEW)
ADS8331
ADS8332
Thermal Pad(2)
(Bottom Side)
16
REF-
15
REF+
14
VA
13
VBD
10
7
8
9
10
11
12
SCLK
FS/CS
SDI
SDO
DGND
CONVST
(3)
(1)
NC = No internal connection (ADS8331
only).
(2)
Connect thermal pad to analog ground.
ADS8331
ADS8332
NC = No internal connection (ADS8331
only).
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ADS8331 PIN DESCRIPTIONS
PIN NO.
NAME
TSSOP
QFN
I/O
ADCIN
21
18
I
ADC input
AGND
20
17
–
Analog ground
DGND
14
11
–
Digital interface ground
COM
23
20
I
Common ADC input (usually connected to AGND)
CONVST
15
12
I
Conversion start. Freezes sample and hold, starts conversion.
EOC/INT/CDI
9
6
O/O/I
DESCRIPTION
Status output. If programmed as end-of-conversion (EOC), this pin is low (default) when a
conversion is in progress. If programmed as an interrupt (INT), this pin is low (default) after
the end of conversion and returns high after FS/CS goes low. The polarity of EOC or INT is
programmable.
This pin can also be used as a chain data input (CDI) when operated in daisy-chain mode.
FS/CS
11
8
I
Frame sync signal for DSP (such as TMS320™ DSP) or chip select input for SPI.
IN[0:3]
1-3, 24
21-24
I
Mux inputs
NC
4-7
1-4
–
No connection
MUXOUT
22
19
O
Mux output
REF+
18
15
I
External reference input
REF–
19
16
–
External reference ground (connect to AGND through an individual via on the printed circuit
board)
RESET
8
5
I
External reset (active low)
SCLK
10
7
I
SPI clock for serial interface
SDI
12
9
I
SPI serial data in
SDO
13
10
O
SPI serial data out
VA
17
14
–
Analog supply, +2.7V to +5.5V
VBD
16
13
–
Digital interface supply
ADS8332 PIN DESCRIPTIONS
PIN NO.
TSSOP
QFN
I/O
ADCIN
NAME
21
18
I
ADC input
AGND
20
17
–
Analog ground
DGND
14
11
–
Digital interface ground
COM
23
20
I
Common ADC input (usually connected to AGND)
CONVST
15
12
I
Conversion start. Freezes sample and hold, starts conversion.
EOC/INT/CDI
9
6
O/O/I
DESCRIPTION
Status output. If programmed as end-of-conversion (EOC), this pin is low (default) when a
conversion is in progress. If programmed as an interrupt (INT), this pin is low (default) after
the end of conversion and returns high after FS/CS goes low. The polarity of EOC or INT is
programmable.
This pin can also be used as a chain data input (CDI) when operated in daisy-chain mode.
FS/CS
11
8
I
IN[0:7]
1-7, 24
1-4,
21-24
Frame sync signal for DSP (such as TMS320™ DSP) or chip select input for SPI.
I
MUXOUT
22
19
O
Mux output
REF+
18
15
I
External reference input
REF–
19
16
–
External reference ground (connect to AGND through an individual via on the printed circuit
board)
RESET
8
5
I
External reset (active low)
SCLK
10
7
I
SPI clock for serial interface
SDI
12
9
I
SPI serial data in
SDO
13
10
O
SPI serial data out
VA
17
14
–
Analog supply, +2.7 V to +5.5 V
VBD
16
13
–
Digital interface supply
Mux inputs
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TYPICAL CHARACTERISTICS: DC Performance
At TA = +25°C, VREF (REF+ – REF–) = 4.096V when VA = VBD = 5V or VREF (REF+ – REF–) = 2.5V when VA = VBD = 2.7V,
fSCLK = 21MHz, and fSAMPLE = 500kSPS, unless otherwise noted.
INTEGRAL LINEARITY ERROR
vs CODE
3
INTEGRAL LINEARITY ERROR
vs CODE
3
VA = VBD = 2.7V
VREF = 2.500V
2
2
1
ILE (LSB)
ILE (LSB)
1
0
0
-1
-1
-2
-2
-3
0000h
4000h
8000h
Output Code
C000h
-3
0000h
FFFFh
C000h
Figure 6.
DIFFERENTIAL LINEARITY ERROR
vs CODE
DIFFERENTIAL LINEARITY ERROR
vs CODE
3
VA = VBD = 2.7V
VREF = 2.500V
2
FFFFh
VA = VBD = 5.0V
VREF = 4.096V
2
1
DLE (LSB)
1
DLE (LSB)
8000h
Output Code
4000h
Figure 5.
3
0
0
-1
-1
-2
-2
-3
0000h
4000h
8000h
Output Code
C000h
FFFFh
-3
0000h
8000h
Output Code
4000h
C000h
Figure 7.
Figure 8.
ANALOG SUPPLY CURRENT
vs ANALOG SUPPLY VOLTAGE
ANALOG SUPPLY CURRENT IN NAP MODE
vs ANALOG SUPPLY VOLTAGE
FFFFh
500
8.0
7.5
VREF = 4.096V
VREF = 4.096V
450
Nap Current (mA)
7.0
IA (mA)
VA = VBD = 5.0V
VREF = 4.096V
6.5
VREF = 2.500V
6.0
5.5
VREF = 2.500V
400
350
5.0
4.5
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
4.5
4.6
4.7
4.8
4.9
5.0
5.1
5.2
5.3
5.4
5.5
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
4.5
4.6
4.7
4.8
4.9
5.0
5.1
5.2
5.3
5.4
5.5
300
4.0
VA (V)
VA (V)
Figure 9.
12
Figure 10.
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TYPICAL CHARACTERISTICS: DC Performance (continued)
At TA = +25°C, VREF (REF+ – REF–) = 4.096V when VA = VBD = 5V or VREF (REF+ – REF–) = 2.5V when VA = VBD = 2.7V,
fSCLK = 21MHz, and fSAMPLE = 500kSPS, unless otherwise noted.
ANALOG SUPPLY CURRENT
vs SAMPLING RATE IN AUTO-NAP MODE
DEEP POWER-DOWN CURRENT
vs TEMPERATURE
120
8
VA = VBD = 5.0V
VREF = 4.096V
6
IA (mA)
Deep Power-Down Current (nA)
7
5
4
3
VA = VBD = 2.7V
VREF = 2.500V
2
1
100
80
60
40
50
100
150 200 250 300
Sampling Rate (kHz)
350
400
0
-50
450
25
50
Temperature (°C)
Figure 12.
INTERNAL CLOCK FREQUENCY
vs ANALOG SUPPLY VOLTAGE
CHANGE IN GAIN
vs TEMPERATURE
75
100
75
100
4
D Gain (LSB relative to +25°C)
11.7
Frequency (MHz)
0
-25
Figure 11.
12.2
VREF = 4.096V
VREF = 2.500V
11.2
10.7
10.2
VA = VBD = 2.7V
VREF = 2.500V
2
1
0
VA = VBD = 5.0V
VREF = 4.096V
-1
-2
-3
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
4.5
4.6
4.7
4.8
4.9
5.0
5.1
5.2
5.3
5.4
5.5
0
-25
25
50
Temperature (°C)
Figure 13.
Figure 14.
CHANGE IN OFFSET
vs TEMPERATURE
CHANGE IN ANALOG SUPPLY CURRENT
vs TEMPERATURE
6
1.0
5
DIA (mA relative to +25°C)
0.8
4
VA = VBD = 2.7V
VREF = 2.500V
3
2
1
0
-1
-2
VA = VBD = 5.0V
VREF = 4.096V
-3
-4
-5
-6
-50
3
-4
-50
VA (V)
D Offset (LSB relative to +25°C)
VA = VBD = 2.7V
VREF = 2.500V
20
0
0
VA = VBD = 5.0V
VREF = 4.096V
0.6
0.4
0.2
0
VA = VBD = 2.7V
VREF = 2.500V
-0.2
-0.4
-0.6
VA = VBD = 5.0V
VREF = 4.096V
-0.8
-25
0
25
50
Temperature (°C)
75
100
-1.0
-50
-25
Figure 15.
0
25
50
Temperature (°C)
75
100
Figure 16.
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TYPICAL CHARACTERISTICS: DC Performance (continued)
At TA = +25°C, VREF (REF+ – REF–) = 4.096V when VA = VBD = 5V or VREF (REF+ – REF–) = 2.5V when VA = VBD = 2.7V,
fSCLK = 21MHz, and fSAMPLE = 500kSPS, unless otherwise noted.
CHANGE IN DIGITAL SUPPLY CURRENT
vs TEMPERATURE
CHANGE IN INTERNAL CLOCK FREQUENCY
vs TEMPERATURE
150
D Frequency (kHz relative to +25°C)
1.0
DIBD (mA relative to +25°C)
0.8
0.6
VA = VBD = 2.7V
VREF = 2.500V
0.4
0.2
0
-0.2
VA = VBD = 5.0V
VREF = 4.096V
-0.4
-0.6
-0.8
-1.0
-50
-25
0
25
50
Temperature (°C)
75
125
100
VA = VBD = 2.7V
VREF = 2.500V
75
50
25
0
-25
-50
VA = VBD = 5.0V
VREF = 4.096V
-75
-100
-125
-150
-50
100
0
-25
Figure 17.
25
50
Temperature (°C)
75
100
Figure 18.
CHANGE IN ANALOG SUPPLY CURRENT IN NAP MODE
vs TEMPERATURE
D Nap Current Relative to +25°C (mA)
25
VA = VBD = 2.7V
VREF = 2.500V
20
15
10
5
VA = VBD = 5.0V
VREF = 4.096V
0
-5
-10
-15
-20
-25
-50
-25
0
25
50
Temperature (°C)
75
100
Figure 19.
14
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SBAS363 – DECEMBER 2009
TYPICAL CHARACTERISTICS: AC Performance
At TA = +25°C, VREF (REF+ – REF–) = 4.096V when VA = VBD = 5V or VREF (REF+ – REF–) = 2.5V when VA = VBD = 2.7V,
fSCLK = 21MHz, fSAMPLE = 500kSPS, and fIN = 10kHz, unless otherwise noted.
OUTPUT CODE HISTOGRAM
FOR A DC INPUT (8192 Conversions)
OUTPUT CODE HISTOGRAM
FOR A DC INPUT (8192 Conversions)
VA = VBD = 2.7V
VREF = 2.500V
6336
4791
1665
1643
1088
768
53
7FFD
7FFE
7FFF
8000
40
0
8001
7FFD
7FFF
Code
Figure 20.
Figure 21.
FREQUENCY SPECTRUM
(8192 Point FFT, fIN = 1.0376kHz, –0.2dB)
FREQUENCY SPECTRUM
(8192 Point FFT, fIN = 1.0376kHz, –0.2dB)
7FFE
8000
8001
0
VA = VBD = 2.7V
VREF = 2.500V
-20
VA = VBD = 5.0V
VREF = 4.096V
-20
-40
Amplitude (dB)
-40
Amplitude (dB)
0
Code
0
-60
-80
-100
-60
-80
-100
-120
-120
-140
-140
-160
-160
0
50
100
150
200
250
0
50
Frequency (kHz)
100
150
200
250
Frequency (kHz)
Figure 22.
Figure 23.
FREQUENCY SPECTRUM
(8192 Point FFT, fIN = 10.0708kHz, –0.2dB)
FREQUENCY SPECTRUM
(8192 Point FFT, fIN = 10.0708kHz, –0.2dB)
0
0
VA = VBD = 2.7V
VREF = 2.500V
-20
VA = VBD = 5.0V
VREF = 4.096V
-20
-40
Amplitude (dB)
-40
Amplitude (dB)
VA = VBD = 5.0V
VREF = 4.096V
-60
-80
-100
-60
-80
-100
-120
-120
-140
-140
-160
-160
0
50
100
150
200
250
0
Frequency (kHz)
50
100
150
200
250
Frequency (kHz)
Figure 24.
Figure 25.
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TYPICAL CHARACTERISTICS: AC Performance (continued)
At TA = +25°C, VREF (REF+ – REF–) = 4.096V when VA = VBD = 5V or VREF (REF+ – REF–) = 2.5V when VA = VBD = 2.7V,
fSCLK = 21MHz, fSAMPLE = 500kSPS, and fIN = 10kHz, unless otherwise noted.
SIGNAL-TO-NOISE + DISTORTION
vs TEMPERATURE
SIGNAL-TO-NOISE RATIO
vs INPUT FREQUENCY
95
93
fIN = 1.03760kHz, -0.2dB
90
91
SNR (dB)
SINAD (dB)
VA = VBD = 5.0V
VREF = 4.096V
VA = VBD = 5.0V
VREF = 4.096V
92
90
VA = VBD = 2.7V
VREF = 2.500V
85
89
VA = VBD = 2.7V
VREF = 2.500V
88
80
87
-50
-25
0
25
50
75
10
1
100
Figure 27.
TOTAL HARMONIC DISTORTION
vs INPUT FREQUENCY
SPURIOUS-FREE DYNAMIC RANGE
vs INPUT FREQUENCY
105
-70
100
-75
95
-80
SFDR (dB)
THD (dB)
Figure 26.
-65
VA = VBD = 5.0V
VREF = 4.096V
-85
100
250
fIN (kHz)
Temperature (°C)
-90
VA = VBD = 2.7V
VREF = 2.500V
90
VA = VBD = 5.0V
VREF = 4.096V
85
80
75
-95
VA = VBD = 2.7V
VREF = 2.500V
-100
70
65
-105
1
10
100
250
10
1
100
250
fIN (kHz)
fIN (kHz)
Figure 28.
Figure 29.
SIGNAL-TO-NOISE + DISTORTION
vs INPUT FREQUENCY
95
VA = VBD = 5.0V
VREF = 4.096V
SINAD (dB)
90
85
VA = VBD = 2.7V
VREF = 2.500V
80
75
70
65
1
10
100
250
fIN (kHz)
Figure 30.
16
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TYPICAL CHARACTERISTICS: AC Performance (continued)
At TA = +25°C, VREF (REF+ – REF–) = 4.096V when VA = VBD = 5V or VREF (REF+ – REF–) = 2.5V when VA = VBD = 2.7V,
fSCLK = 21MHz, fSAMPLE = 500kSPS, and fIN = 10kHz, unless otherwise noted.
EFFECTIVE NUMBER OF BITS
vs INPUT FREQUENCY
POWER-SUPPLY REJECTION RATIO
vs POWER-SUPPLY RIPPLE FREQUENCY
16.0
VA = VBD = 5.0V
VREF = 4.096V
15.5
15.0
PSRR (dB)
ENOB (Bits)
14.5
14.0
13.5
VA = VBD = 2.7V
VREF = 2.500V
13.0
12.5
12.0
11.5
11.0
1
10
100
95
90
85
80
75
70
65
60
55
50
45
40
35
250
VRIPPLE = 0.5VPP
VA = VBD = 2.7V
VREF = 2.500V
VA = VBD = 5.0V
VREF = 4.096V
0.1
1
fIN (kHz)
Figure 31.
10
Ripple Frequency (kHz)
100
500
Figure 32.
CROSSTALK
vs INPUT FREQUENCY
-95
Crosstalk (dB)
-100
-105
-110
VA = VBD = 5.0V
VREF = 4.096V
-115
-120
VA = VBD = 2.7V
VREF = 2.500V
-125
-130
1
10
100
250
fIN (kHz)
Figure 33.
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THEORY OF OPERATION
DESCRIPTION
The ADS8331/32 is a high-speed, low-power, successive approximation register (SAR) analog-to-digital
converter (ADC) that uses an external reference. The architecture is based on charge redistribution, which
inherently includes a sample/hold function.
The ADS8331/32 has an internal clock that is used to run the conversion. However, the ADS8331/32 can be
programmed to run the conversion based on the external serial clock (SCLK).
The analog input to the ADS8331/32 is provided to two input pins: one of the INX input channels and the shared
COM pin. When a conversion is initiated, the differential input on these pins is sampled on the internal capacitor
array. While a conversion is in progress, both INX and COM inputs are disconnected from any internal function.
The ADS8331 has four analog inputs while the ADS8332 has eight inputs. All inputs share the same common
pin, COM. Both the ADS8331 and ADS8332 can be programmed to select a channel manually or can be
programmed into the auto channel select mode to sweep through the input channels automatically.
SIGNAL CONDITIONING
The ADS8331/32 has the flexibility to add signal conditioning between the MUXOUT and ADCIN pins, such as a
programmable gain amplifier (PGA) or filter. This feature reduces the system component count and cost because
each input channel does not require separate signal conditioning circuits, especially if the source impedance
connected to each channel is similar in value.
ANALOG INPUT
When the converter enters the hold mode, the voltage difference between the INX and COM inputs is captured
on the internal capacitor array. The voltage on the COM pin is limited between (AGND – 0.2V) and (AGND +
0.2V). This limitation allows the ADS8331/32 to reject small signals that are common to both the INX and COM
inputs. The INX inputs have a range of –0.2V to (VA + 0.2V). The input span of (INX – COM) is limited to 0V to
VREF.
The peak input current through the analog inputs depends upon a number of factors: reference voltage, sample
rate, input voltage, and source impedance. The current flowing into the ADS8331/32 charges the internal
capacitor array during the sample period. After this capacitance has been fully charged, there is no further input
current. The source of the analog input voltage must be able to charge the maximum input capacitance (45pF) to
a 16-bit settling level within the minimum acquisition time (238ns). When the converter goes into hold mode, the
input impedance is greater than 1GΩ.
Care must be taken regarding the absolute analog input voltage. To maintain linearity of the converter, the INX
inputs, the COM input, and the input span of (INX – COM) should be within the limits specified. If these inputs are
outside of these ranges, the linearity of the converter may not meet specifications. To minimize noise,
low-bandwidth input signals with low-pass filters should be used. Care should be taken to ensure that the output
impedance of the sources driving the INX and COM inputs are matched, as shown in Figure 34. If this matching
is not observed, the two inputs could have different settling times, which may result in an offset error, gain error,
and linearity error that change with temperature and input voltage.
MUXOUT
ADCIN
Device in Hold Mode
50W
40W
40pF
55W
40pF
IN0
50W
4pF
VA
INX
4pF
AGND
COM
AGND
Figure 34. Input Equivalent Circuit
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Driver Amplifier Choice
In order to take advantage of the high sample rate offered by the ADS8331/32, the analog inputs to the converter
should be driven with low-noise operational amplifiers (op amps), such as the OPA365, OPA211, OPA827, or
THS4031. An RC filter is recommended at each of the input channels to low-pass filter noise generated by the
input driving sources. These channels can accept unipolar signals with voltages between INX and COM in the
range of 0V to VREF. If RC filters are not used between the op amps and the input channels, the minimum –3dB
bandwidth required by the driving op amps for the sampled signals to settle to within 1/2 LSB of the final voltage
can be calculated using Equation 1:
(n + 1) ´ ln(2)
f-3dB ³
2p ´ tSAMPLE_MIN
(1)
Where:
n = resolution of the converter (n = 16 for the ADS8331/32).
tSAMPLE_MIN = minimum acquisition time.
The minimum value of tSAMPLE in the Electrical Characteristics tables is 238ns (3 CCLKs with the internal
oscillator at 12.6MHz). Substituting these values for n and tSAMPLE_MIN into Equation 1 shows f–3dB must be at
least 7.9MHz. This bandwidth can be relaxed if the acquisition time is increased or an RC filter is added between
the driving op amp and the corresponding input channel (refer to Texas Instruments' Application Report
SBAA173 and associated references for additional information, available for download at www.ti.com). The
OPA365 used in the source-follower (unity-gain) configuration is shown in Figure 35 with recommended values
for the RC filter.
Input Signal
(0V to 4V)
MUXOUT
ADCIN
VA
20W
OPA365
5V
ADS8331
ADS8332
INX
1000pF
COM
Figure 35. Unipolar Input Drive Configuration
Bipolar to Unipolar Driver
In systems where the input signal is bipolar, op amps such as the OPA365 and OPA211 can be used in the
inverting configuration with a dc bias applied to the noninverting input in order to keep the input signal to the
ADS8331/32 within its rated operating voltage range. This configuration is also recommended when the
ADS8331/32 is used in signal-processing applications where good SNR and THD performance is required. The
dc bias can be derived from low-noise reference voltage ICs such as the REF5025 or REF5040. The input
configuration shown in Figure 36 is capable of delivering better than 91dB SNR and –99dB THD at an input
frequency of 1kHz. If bandpass filters are used to filter the input to the driving op amp, the signal swing at the
input of the bandpass filter should be small enough to minimize the distortion introduced by the filter. In these
cases, the gain of the circuit shown in Figure 36 can be increased to maintain a large enough input signal to the
ADS8331/32 to keep the system SNR as high as possible.
MUXOUT
ADCIN
5V
2.048VDC
VA
20W
600W
OPA211
INX
1000pF
Input Signal
(-2V to +2V)
600W
ADS8331
ADS8332
COM
Figure 36. Bipolar Input Drive Configuration
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REFERENCE
The ADS8331/32 can operate with an external reference with a range from 1.2V to 4.2V. A clean, low-noise
reference voltage on this pin is required to ensure good converter performance. A low-noise band-gap reference
such as the REF5025 or REF5040 can be used to drive this pin. A 10μF ceramic bypass capacitor is required
between the REF+ and REF– pins of the converter. This capacitor should be placed as close as possible to the
pins of the device. Note that the REF– pin should not be connected to the AGND pin of the converter; instead,
the REF– pin must be connected to the analog ground plane with a separate via.
CONVERTER OPERATION
The ADS8331/32 has an internal oscillator that can be used as the conversion clock (CCLK) source. The
minimum frequency of this oscillator is 10.5MHz. The internal oscillator is only active during the conversion
period unless the converter is using Auto-Trigger and/or Auto-Nap modes. The minimum acquisition/sampling
time for the ADS8331/32 is 3 CCLKs (250ns with a 12MHz conversion clock), while the minimum conversion time
is 18 CCLKs (1500ns with a 12MHz conversion clock).
As shown in Figure 37, the ADS8331/32 can also be programmed to run conversions using the external serial
clock (SCLK). This feature allows system designers to achieve system synchronization. Each rising edge of
SCLK toggles the state of the conversion clock (CCLK), which reduces the frequency of SCLK by a factor of two
before it is used as CCLK. For example, a 21MHz SCLK provides a 10.5MHz CCLK. If the start of a conversion
must occur on a specific rising edge of SCLK when the external serial clock is used for the conversion clock (and
Manual-Trigger mode is enabled), a minimum setup time of 20ns between the falling edge of CONVST and the
rising edge of SCLK must be met. This timing ensures the conversion is completed in 18 CCLKs (36 SCLKs).
The duty cycle of SCLK is not critical, as long as the minimum high and low times (11ns for VA = 5.0V) are
satisfied. Because the ADS8331/32 is designed for high-speed applications, a high-frequency serial clock must
be supplied to maintain the high throughput of the interface. This requirement can be accomplished if the period
of SCLK is at most 1μs when SCLK is used as the conversion clock (CCLK). The 1μs maximum period for SCLK
is also set by the leakage of charge from the capacitors in the capacitive digital-to-analog converter (CDAC)
block in the ADS8331/32. If SCLK is used as the conversion clock, the SCLK source must have minimal rise/fall
times and low jitter to provide the best converter performance.
CFR_D10
Conversion Clock
(CCLK)
=1
Oscillator
SPI Serial
Clock (SCLK)
=0
Divide by 2
Figure 37. Conversion Clock Source
Manual Channel Select Mode
Manual Channel Select mode is enabled through the Configuration register (CFR) by setting the CFR_D11 bit to
'0' (see Table 5). The acquisition process starts with selecting an input channel. This selection is done by writing
the desired channel number to the Command register (CMR); see Table 4 for further details. The associated
timing diagram is shown in Figure 38.
CS
SCLK
< 30ns
Mux switch
CHOLD
CHNEW
Figure 38. Manual Channel Select Timing
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Auto Channel Select Mode
Channel selection can also be done automatically if Auto Channel Select mode (default) is enabled (CFR_D11 =
'1'). If the device is programmed for Auto Channel Select mode, then signals from all channels are acquired in a
fixed order. In Auto Channel Select mode, the first conversion after entering this mode is always from the
channel of the last conversion completed before this mode is enabled. The channels are then sequentially
scanned up to and including the last channel (that is, channel 3 for the ADS8331 and channel 7 for the
ADS8332) and then back to the channel that started the sequence. For example, if the last channel used in the
conversion before enabling Auto Channel Select mode was channel 2, the sequence for the ADS8332 would be:
2, 3, 4, 5, 6, 7, 2, etc., as shown in Figure 39. If the last channel in Manual Channel Select mode happened to be
channel 7, the sequence would be: 7, 7, 7, etc. Figure 40 shows when the next channel in the sequence
activates during Auto Channel Select mode. This timing allows the next channel to settle before it is acquired.
This automatic sequencing stops the cycle after CFR_D11 is set to '0'.
Manual Channel Select Channel 2
Enable Auto Channel Select
Conversion Start is Automatic or Manual
Manual- or Auto-Trigger Mode
Ch 2
Ch 7
Ch 3
Ch 6
Ch 4
Ch 5
Figure 39. Auto Channel Select for the ADS8332
CCLK
EOC
(active low)
Channel #
1 CCLK Minimum
N-1
N
Figure 40. Channel-Number Update in Auto Channel Select Mode Timing
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Start of a Conversion
The end of acquisition is the same as the start of a conversion. This process is initiated by bringing the CONVST
pin low for a minimum of 40ns. After the minimum requirement has been met, the CONVST pin can be brought
high. CONVST acts independently of FS/CS so it is possible to use one common CONVST for applications that
require simultaneous sample/hold with multiple converters. The ADS8331/32 switches from sample to hold mode
on the falling edge of the CONVST signal. The ADS8331/32 requires 18 conversion clock (CCLK) cycles to
complete a conversion. The conversion time is equivalent to 1500ns with a 12MHz internal clock. The minimum
time between two consecutive CONVST signals is 21 CCLKs.
A conversion can also be initiated without using CONVST if the ADS8331/32 is programmed for Auto-Trigger
mode (CFR_D9 = '0'). When the converter is configured in this mode, and with CFR_D8 = '0', the next
conversion is automatically started three conversion clocks (CCLK) after the end of a conversion. These three
conversion clocks (CCLK) are used for the acquisition time. In this case, the time to complete one acquisition
and conversion cycle is 21 CCLKs. Table 1 summarizes the different conversion modes.
Table 1. Different Types of Conversion
MODE
Automatic
SELECT CHANNEL
Auto-Trigger Mode
No need to write channel number to CMR. Use internal sequencer for
ADS8331/32.
Start a conversion based on conversion
clock CCLK
Manual
(1)
START CONVERSION
Auto Channel Select (1)
Manual Channel Select
Manual-Trigger Mode
Write channel number to CMR
Start a conversion with CONVST
Auto channel select should be used with Auto-Trigger mode and TAG bit output enabled.
Status Output Pin (EOC/INT)
The status output pin is programmable. It can be used as an EOC output (CFR_D[7:6] = '11') where the low time
is equal to the conversion time. When the status pin is programmed as EOC and the polarity is set as active low,
the pin works in the following manner: the EOC output goes low immediately following CONVST going low with
Manual-Trigger mode enabled. EOC stays low throughout the conversion process and returns high when the
conversion has ended. If Auto-Trigger mode is enabled, the EOC output remains high for three conversion clocks
(CCLK) after the previous rising edge of EOC .
This status pin can also be used as an interrupt output, INT (CFR_D[7:6] = '10'), which is set low at the end of a
conversion, and is brought high (cleared) by the next read cycle. The polarity of this pin, whether used as EOC
or INT, is programmable through the CFR_D7 bit.
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Power-Down Modes and Acquisition Time
There are three power-down modes that reduce power dissipation: Nap, Deep, and Auto-Nap. The first two, Nap
and Deep Power-Down modes, are enabled/disabled by bits CFR_D3 and CFR_D2, respectively, in the
Configuration register (see Table 5 for details).
Deep Power-Down mode provides maximum power savings. When this mode is enabled, the analog core in the
converter is shut down, and the analog supply current falls from 6.6mA (VA = 5.0V) to 1μA in 2μs. The wakeup
time from Deep Power-Down mode is 1μs. The device can wake up from Deep Power-Down mode by either
disabling this mode, issuing the wakeup command, loading the default value into the CFR, or performing a reset
(either with the software reset command, CFR_D0 bit, or the external reset). See Table 4 and Table 5 along with
the Reset Function section for further information.
In Nap Power-Down mode, the bias currents for the analog core of the device are significantly reduced. Because
the bias currents are not completely shut off, the ADS8331/32 can wake up from this power-down mode much
faster than from Deep Power-Down mode. After Nap Power-Down mode is enabled, the analog supply current
falls from 6.6mA (VA = 5.0V) to 0.39mA in 200ns. The wakeup time from this mode is three conversion clock
cycles (CCLK). The device can wake up from Nap Power-Down mode in the same manner as waking up from
Deep Power-Down mode.
The third power-down mode, Auto-Nap, is enabled/disabled by bit CFR_D4 in the Configuration register (see
Table 5 for details). Once this mode is enabled, the device is controlled by the digital core logic on the chip. The
device is automatically placed into Nap Power-Down mode after the next end of conversion (EOC). The analog
supply current falls from 6.6mA (VA = 5.0V) to 0.39mA in 200ns. A conversion start wakes up the device in three
conversion clock cycles. Issuing the wake-up command, loading the default value into the CFR, disabling
Auto-Nap Power-Down mode, issuing a manual channel select command, or resetting the device can wake the
ADS8331/32 from Auto-Nap Power-Down mode. A comparison of the three power-down modes is listed in
Table 2.
Table 2. Comparison of Power-Down Modes
POWER
CONSUMPTION
(VA = 5.0V)
POWER-DOWN
BY:
POWER-DOWN TIME
WAKEUP BY:
WAKEUP TIME
Normal operation
6.6mA
—
—
—
—
—
Deep power-down
1μA
Setting CFR_D2
2μs
Wakeup command 1011b
1μs
Set CFR_D2
Nap power-down
0.39mA
Setting CFR_D3
200ns
Wakeup command 1011b
3 CCLKs
Set CFR_D3
Auto-Nap
power-down
0.39mA
EOC (end of
conversion)
200ns
CONVST, any channel select command, default
command 1111b, or wakeup command 1011b.
3 CCLKs
Set CFR_D4
TYPE OF
POWER-DOWN
ENABLE
The default acquisition time is three conversion clock (CCLK) cycles. Figure 41 shows the timing diagram for
CONVST, EOC, and auto-nap power-down signals in Manual-Trigger mode. As shown in the diagram, the device
wakes up after a conversion is triggered by the CONVST pin going low. However, a conversion is not yet started
at this time. The conversion start signal to the analog core of the chip is internally generated no less than six
conversion clock (CCLK) cycles later, to allow at least three CCLKs for wake up and three CCLKs for acquisition.
The ADS8331/32 enters Nap Power-Down mode one conversion cycle after the end of conversion (EOC).
CCLK
CONVST
CONVST_OUT
(internal)
3 + 3 = 6 Cycles
1 Cycle
NAP_ACTIVE
(internal)
EOC
(active low)
Figure 41. Timing for CONVST, EOC, and Auto-Nap Power-Down Signals in Manual-Trigger Mode (Three
Conversion Clock Cycles for Acquisition)
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The ADS8331/32 can support sampling rates of up to 500kSPS in Auto-Trigger mode. This rate is selectable by
programming the CFR_D8 bit in the Configuration register. In 500kSPS mode, consecutive conversion start
pulses to the analog core are generated 21 conversion clock cycles apart. In 250kSPS mode, consecutive
conversion-start pulses are 42 conversion clock cycles apart. The Nap and Deep Power-Down modes are
available with either sampling rate; however, Auto-Nap mode is available only with a sampling rate of 250kSPS
when Auto-Trigger mode is enabled. The analog core cannot be powered down when the Auto-Nap mode
sampling rate is 500kSPS because at that rate, there is no period of time when the analog core is not actively
being used.
Figure 42 shows the timing diagram for conversion start and auto-nap power-down signals for a 250kSPS
sampling rate in Auto-Trigger mode. For a 16-bit ADC output word, consecutive new conversion start pulses are
generated 2 × (18 + 3) cycles apart. NAP_ACTIVE (the signal to power down the analog core in Nap and
Auto-Nap modes) goes low six (3 + 3) conversion clock cycles before the conversion start falling edge, thus
powering up the analog core. It takes three conversion clock cycles after NAP_ACTIVE goes low to power up the
analog core. The analog core is powered down a cycle after the end of a conversion. For a 16-bit ADC with a
500kSPS sampling rate and three conversion clock cycle sampling, consecutive conversion start pulses are
generated 21 conversion clock cycles apart.
1
2
3
19
20
21
37
38
42
43
CCLK
CONVST_OUT
(internal)
EOC
(active low)
NAP_ACTIVE
(internal)
Figure 42. Timing for Conversion Start and Auto-Nap Power-Down Signals in Auto-Trigger Mode
(250kSPS Sampling and Three Conversion Clock Cycles for Acquisition)
Timing diagrams for reading from the ADS8331/32 with various trigger and power-down modes are shown in
Figure 43 through Figure 45. The total (acquisition + conversion) times for the different trigger and power-down
modes are listed in Table 3.
Table 3. Total Acquisition + Conversion Times
MODE
= 21 CCLK
Manual-Trigger
≥ 21 CCLK
Manual-Trigger with Deep Power-Down
≥ 4 SCLK + 1μs + 3 CCLK + 18 CCLK + 16 SCLK + 2μs
Manual-Trigger with Nap Power-Down
≥ 4 SCLK + 3 CCLK + 3 CCLK + 18 CCLK + 16 SCLK + 200ns
Manual-Trigger with Auto-Nap Power-Down
24
ACQUISITION + CONVERSION TIME
Auto-Trigger at 500kSPS
≥ 4 SCLK + 3 CCLK + 3 CCLK + 18 CCLK + 1 CCLK + 200ns (using wakeup to resume)
≥ 3 CCLK + 3 CCLK + 18 CCLK + 1 CCLK + 200ns (using CONVST to resume)
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EOS
EOC
EOS
EOC
(active low)
Sample (N + 1)
Conversion N
tH2
Read While Converting
CS
EOC
(N+1)
N
CONVST
Conversion (N + 1)
tSU1
Read Result (N - 1)
Read While Sampling
tSU2
tH1
CS
Read Result N
Figure 43. Read While Converting vs Read While Sampling (Manual-Trigger Mode)
BLANKSPACE
Wakeup
Sample N
Conversion N
³ 3 CCLK
= 18 CCLK
Read Result
(N - 1)
Note
(2)
Power-Down Wakeup
Sample (N + 1)
Conversion (N + 1)
³ 3 CCLK
= 18 CCLK
Note
(2)
Read Result
(N - 1)
Note
(1)
Power-Down
tH2
Note
(3)
Note
(2)
Note
(3)
Note
(2)
Read Result
N
tSU2
Read While Sampling
CS
Note
(1)
tH2
Read While Converting
CS
EOS
EOC
EOS
Converter State
EOC
(N+1)
N
CONVST
Note
(3)
tSU2
Read Result
N
(1)
Converter is in acquisition mode between end of conversion and activation of Nap or Deep Power-Down mode.
(2)
Command on SDI pin to wake up converter (minimum of four SCLKs).
(3)
Command on SDI pin to place converter into Nap or Deep Power-Down mode (minimum of 16 SCLKs).
Note
(3)
Figure 44. Read While Converting vs Read While Sampling with Nap or Deep Power-Down
(Manual-Trigger Mode)
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MANUAL TRIGGER CASE 1 (Wakeup Using CONVST):
tWL1
(N+1)
N
CONVST
Converter State
Wakeup
Sample N
Conversion N
³ 3 CCLK
= 18 CCLK
³ 6 CCLK
Note
(1)
tH2
Read While Converting
Power-Down Wakeup
Sample (N + 1)
Conversion (N + 1)
³ 3 CCLK
= 18 CCLK
³ 6 CCLK
tSU1
tSU1
tSU2
Read Result
N
Read Result
(N - 1)
CS
Power-Down
Read Result
N
tSU2
Read While Sampling
Note
(1)
tH2
Read Result
(N - 1)
CS
EOC
EOS
EOS
EOC
EOC
(active low)
MANUAL TRIGGER CASE 2 (Wakeup Using Wakeup Command):
tWL1
(N+1)
N
CONVST
Converter State
Wakeup
Sample N
Conversion N
³ 3 CCLK
= 18 CCLK
tH2
Read While Converting
CS
Power-Down Wakeup
Conversion (N + 1)
³ 3 CCLK
= 18 CCLK
Read Result
(N - 1)
Note
(1)
tH2
Note
(2)
Power-Down
tSU1
Read Result
N
tSU2
Note
(2)
EOC
Sample (N + 1)
tSU1
Read Result
(N - 1)
Note
(2)
Read While Sampling
CS
Note
(1)
EOS
EOS
EOC
EOC
(active low)
tSU2
Note
(2)
(1)
Time between end of conversion and Nap Power-Down mode is 1 CCLK.
(2)
Command on SDI to wake up converter (minimum of four SCLKs).
Read Result
N
Figure 45. Read While Converting vs Read While Sampling with Auto-Nap Power-Down
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DIGITAL INTERFACE
The serial interface is designed to accommodate the latest high-speed processors with an SCLK frequency of up
to 40MHz (VA = VBD = 5.0V). Each cycle starts with the falling edge of FS/CS. The internal data register
content, which is made available to the output register at the end of conversion, is presented on the SDO output
pin on the falling edge of FS/CS. The first bit is the most significant bit (MSB). The output data bits are valid on
the falling edge of SCLK with the tD2 delay (see the Timing Characteristics)so that the host processor can read
the data on the falling edge. Serial data input is also read on the falling edge of SCLK.
The complete serial I/O cycle starts after the falling edge of FS/CS and ends 16 falling edges of SCLK later (see
NOTE). The serial interface works with CPOL = '1', CPHA = '0'. This setting means the falling edge of FS/CS
may fall while SCLK is high. The same timing relaxation applies to the rising edge of FS/CS where SCLK may be
high or low as long as the last SCLK falling edge happens before the rising edge of FS/CS.
NOTE
There are cases where a cycle can be anywhere from 4 SCLKs up to 24 SCLKs,
depending on the read mode combination. See Table 4 for details.
Internal Register
The internal register consists of two parts: four bits for the Command register (CMR) and 12 bits for the
Configuration register (CFR).
Table 4. Command Set Defined by Command Register (CMR) (1)
(1)
(2)
D[15:12]
HEX
D[11:0]
WAKE UP
FROM
AUTO-NAP
0000b
0h
Select analog input channel 0
Don't care
Y
4
W
0001b
1h
Select analog input channel 1
Don't care
Y
4
W
0010b
2h
Select analog input channel 2
Don't care
Y
4
W
0011b
3h
Select analog input channel 3
Don't care
Y
4
W
0100b
4h
Select analog input channel 4 (2)
Don't care
Y
4
W
0101b
5h
Select analog input channel 5
(2)
Don't care
Y
4
W
0110b
6h
Select analog input channel 6 (2)
Don't care
Y
4
W
0111b
7h
Select analog input channel 7 (2)
Don't care
Y
4
W
1000b
8h
Reserved
Reserved
—
—
—
1001b
9h
Reserved
Reserved
—
—
—
1010b
Ah
Reserved
Reserved
—
—
—
1011b
Bh
Wake up
Don't care
Y
4
W
1100b
Ch
Read CFR
Don't care
—
16
R
1101b
Dh
Read data
Don't care
—
16
R
1110b
Eh
Write CFR
CFR Value
—
16
W
1111b
Fh
Default mode
(load CFR with default value)
Don't care
Y
4
W
COMMAND
MINIMUM
SCLKs
REQUIRED
R/W
The first four bits from SDO after the falling edge of FS/CS are the four MSBs from the previous conversion result. The next 12 bits from
SDO are the contents of the CFR.
These commands apply only to the ADS8332; they are reserved (not availble) for the ADS8331.
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WRITING TO THE CONVERTER
There are two different types of writes to the register: a 4-bit write to the CMR and a full 16-bit write to the CMR
plus CFR. The command set is listed in Table 4 and the configuration register map is listed in Table 5. A simple
command requires only four SCLKs; the write takes effect on the fourth falling edge of SCLK. A 16-bit write or
read takes at least 16 SCLKs (see Table 7 for exceptions that require more than 16 SCLKs).
Configuring the Converter and Default Mode
The converter can be configured with command 1110b (write to the CFR) or command 1111b (default mode). A
write to the CFR requires a 4-bit command followed by 12 bits of data. A 4-bit command takes effect on the
fourth falling edge of SCLK. A write to the CFR takes effect on the 16th falling edge of SCLK.
The CFR default value for each bit is '1'. The default values are applied to the CFR after issuing command 1111b
or when the device is reset with a power-on reset (POR), software reset, or external reset using the RESET pin
(see the Reset Function section).
READING THE CONFIGURATION REGISTER
The host processor can read back the value programmed in the CFR by issuing command 1100b. The timing is
similar to reading a conversion result except CONVST is not used. There is also no activity on the EOC/INT pin.
The CFR value readback contains the first four bits (MSBs) of the previous conversion data plus the 12-bit CFR
contents.
Table 5. Configuration Register (CFR) Map
CFR SDI BIT
(Default = FFFh)
DEFINITION
BIT = '0'
Channel select mode
D11
28
BIT = '1'
Manual channel select enabled. Use channel Auto channel select enabled. Channels are
select commands to access a desired
sampled and converted sequentially until the
channel.
cycle after this bit is set to 0.
D10
Conversion clock (CCLK) source select
D9
Trigger (conversion start) select: start
Auto-Trigger: conversions automatically start
conversion at the end of sampling (EOS). If
three conversion clocks after EOC at
D9 = '0' and D8 = '0', the D4 setting is
500kSPS
ignored.
Conversion clock (CCLK) = SCLK/2
D8
Sample rate for Auto-Trigger mode
500kSPS (21 CCLKs)
250kSPS (42 CCLKs)
D7
Pin 10 polarity select when used as an
output (EOC/INT)
EOC/INT active high
EOC/INT active low
D6
Pin 10 function select when used as an
output (EOC/INT)
Pin used as INT
Pin used as EOC
D5
Pin 10 I/O select for daisy-chain mode
operation
Pin 10 is used as CDI input
(daisy-chain mode enabled)
Pin 10 is used as EOC/INT output
D4
Auto-Nap Power-Down enable/disable.
This bit setting is ignored if D9 = '0' and D8
='0'.
Auto-Nap Power-Down mode enabled (not
activated)
Auto-Nap Power-Down mode disabled
D3
Nap Power-Down. This bit is set to 1
automatically by wake-up command.
Nap Power-Down enabled
Nap Power-Down disabled
(resume normal operation)
D2
Deep Power-Down. This bit is set to 1
automatically by wake-up command.
Deep Power-Down enabled
Deep Power-Down disabled
(resume normal operation)
D1
TAG bit output enable
TAG bit output disabled
TAG bit output enabled. TAG bits appear
after conversion data
D0
Software reset
System reset, returns to '1' automatically
Normal operation
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Conversion clock (CCLK) = internal OSC
Manual-Trigger: conversions manually start
on falling edge of CONVST
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READING THE CONVERSION RESULT
The conversion result is available to the input of the output data register (ODR) at EOC and presented to the
output of the output register at the next falling edge of FS/CS. The host processor can then shift the data out via
the SDO pin at any time except during the quiet zone. This duration is 20ns before and 20ns after the end of
sampling (EOS) period. End of sampling (EOS) is defined as the falling edge of CONVST when Manual-Trigger
mode is used or the end of the third conversion clock (CCLK) after EOC if Auto-Trigger mode is used.
The falling edge of FS/CS should not be placed at the precise moment at the end of a conversion (by default
when EOC goes high). Otherwise, the data could be corrupt. If FS/CS is placed before the end of a conversion,
the previous conversion result is read. If FS/CS is placed after the end of a conversion, the current conversion
result is read.
The conversion result is 16-bit data in straight binary format as shown in Table 6. Generally 16 SCLKs are
necessary, but there are exceptions when more than 16 SCLKs are required (see Table 7). Data output from the
serial output (SDO) is left-adjusted MSB first. The trailing bits are filled with three TAG bits first (if enabled) plus
all '0's. SDO remains low until FS/CS is brought high again.
SDO is active when FS/CS is low. The rising edge of FS/CS 3-states the SDO output.
NOTE
Whenever SDO is not in 3-state (that is, when FS/CS is low and SCLK is running), a
portion of the conversion result is output at the SDO pin. The number of bits depends
on how many SCLKs are supplied. For example, a manual channel select command
cycle requires 4 SCLKs. Therefore, four MSBs of the conversion result are output at
SDO. The exception is when SDO outputs all '1's during the cycle immediately after
any reset (POR, software reset, or external reset).
If SCLK is used as the conversion clock (CCLK) and a continuous SCLK is used, it is not possible to clock out all
16 bits from SDO during the sampling time (6 SCLKs) because of the quiet zone requirement. In this case, it is
better to read the conversion result during the conversion time (36 SCLKs or 48 SCLKs in Auto-Nap mode).
Table 6. Ideal Input Voltages and Output Codes
DESCRIPTION
Full-scale range
Least significant bit (LSB)
Full-scale
Midscale
Midscale – 1 LSB
Zero
ANALOG VALUE
VREF
DIGITAL OUTPUT
STRAIGHT BINARY
VREF/65536
BINARY CODE
HEX CODE
VREF – 1 LSB
1111 1111 1111 1111
FFFF
VREF/2
1000 0000 0000 0000
8000
VREF/2– 1 LSB
0111 1111 1111 1111
7FFF
0V
0000 0000 0000 0000
0000
TAG Mode
The ADS8331/32 includes a TAG feature that can be used to indicate which channel sourced the converted
result. If TAG mode is enabled, three address bits are added after the LSB of the conversion data is read out
from SDO to indicate which channel corresponds to the result. These address bits are '000' for channel 0, '001'
for channel 1, '010' for channel 2, '011' for channel 3, '100' for channel 4, '101' for channel 5, '110' for channel 6,
and '111' for channel 7. The converter requires at least 19 SCLKs when TAG mode is enabled in order to
transfer the 16-bit conversion result and the three TAG bits.
Daisy-Chain Mode
The ADS8331/32 can operate as a single converter or in a system with multiple converters. System designers
can take advantage of the simple, high-speed, SPI-compatible serial interface by cascading converters in a
single chain when multiple converters are used. The CFR_D5 bit in the Configuration register is used to
reconfigure the EOC/INT status pin as the chain data input (CDI) pin, a secondary serial data input, for the
conversion result from an upstream converter. This configuration is called daisy-chain mode operation. A typical
connection of three converters in daisy-chain mode is shown in Figure 46.
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MICROCONTROLLER
INT
CS1
CS2
CS3
SDI SCLK CONVST
CS
SDI SCLK
CS
ADS8331/32
#1
SDO
EOC/INT
CONVST
Program Device #1: CFR_D5 = ‘1’
SDI SCLK
CS
ADS8331/32
#2
CDI
SDO SCLK
SDO
SDI
CONVST
ADS8331/32
#3
CDI
SDO
Program Devices #2 and #3: CFR_D5 = ‘0’
Figure 46. Multiple Converters Connected Using Daisy-Chain Mode
When multiple converters are used in daisy-chain mode, the first converter is configured in regular mode while
the rest of the converters downstream are configured in daisy-chain mode. When a converter is configured in
daisy-chain mode, the CDI input data go straight to the output register. Therefore, the serial input data passes
through the converter with either a 16 SCLK (if the TAG feature is disabled) or 24 SCLK delay, as long as CS is
active. See Figure 47 for detailed timing. In this timing diagram, the conversion in each converter is performed
simultaneously.
Manual Trigger, Read While Sampling
(Use internal CCLK, EOC active low, and TAG mode disabled)
Conversion N
EOS
EOC
EOC #1
(active low)
EOS
CONVST #1
CONVST #2
CONVST #3
tSAMPLE1 = 3 CCLK min
tCONV = 18 CCLK
tSU2
CS #1
SCLK #1
SCLK #2
SCLK #3
SDO #1
CDI #2
1. . . . . . . . . . . . . .16
High-Z
1. . . . . . . . . . . . . .16
1. . . . . . . . . . . . . .16
High-Z
Conversion N
from Device #1
tSU2
CS #2
CS #3
SDO #2
CDI #3
SDO #3
SDI #1
SDI #2
SDI #3
High-Z
High-Z
Don't Care
High-Z
Conversion N
from Device #2
Conversion N
from Device #1
Conversion N
from Device #3
Conversion N
from Device #2
Conversion N
from Device #1
Read Data
Read Data
Configure
High-Z
Don't Care
Figure 47. Simplified Dasiy-Chain Mode Timing with Shared CONVST and Continuous CS
30
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The multiple CS signals must be handled with care when the converters are operating in daisy-chain mode. The
different chip select signals must be low for the entire data transfer (in this example, 48 bits for three
conversions). The first 16-bit word after the falling chip select is always the data from the chip that received the
chip select signal.
Case 1: If chip select is not toggled (CS stays low), the next 16 bits of data are from the upstream converter, and
so on. This configuration is shown in Figure 47.
Case 2: If the chip select is toggled during a daisy-chain mode data transfer cycle, as illustrated in Figure 48, the
same data from the converter are read out again and again in all three discrete 16-bit cycles. This state is not a
desired result.
Manual Trigger, Read While Sampling
(Use internal CCLK, EOC active low, and TAG mode disabled)
Conversion N
EOS
EOC
EOC #1
(active low)
EOS
CONVST #1
CONVST #2
CONVST #3
tCONV = 18 CCLK
tWH1
tSAMPLE1 = 3 CCLK min
tWH1
tSU2
CS #1
SCLK #1
SCLK #2
SCLK #3
SDO #1
CDI #2
1. . . . . . . . . . . . . .16
High-Z
Conversion N
from Device #1
1. . . . . . . . . . . . . .16
High-Z
tWH1
Conversion N
from Device #1
1. . . . . . . . . . . . . .16
High-Z
tWH1
Conversion N
from Device #1
High-Z
tSU2
CS #2
CS #3
SDO #2
CDI #3
SDO #3
SDI #1
SDI #2
SDI #3
High-Z
High-Z
Don't Care
Conversion N
from Device #2
Conversion N
from Device #3
Configure
High-Z
High-Z
Don't Care
Conversion N
from Device #2
Conversion N
from Device #3
Read Data
High-Z
High-Z
Don't Care
Conversion N
from Device #2
Conversion N
from Device #3
Read Data
High-Z
High-Z
Don't Care
Figure 48. Simplified Daisy-Chain Mode Timing with Shared CONVST and Noncontinuous CS
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Figure 49 shows a slightly different scenario where CONVST is not shared with the second converter. Converters
#1 and #3 have the same CONVST signal. In this case, converter #2 simply passes previous conversion data
downstream.
Manual Trigger, Read While Sampling
(Use internal CCLK, EOC active low, and TAG mode disabled)
CONVST #1
CONVST #3
Conversion N
EOS
EOS
EOC #1
(active low)
EOC
CONVST #2
tSAMPLE1 = 3 CCLK min
tCONV = 18 CCLK
tSU2
CS #1
SCLK #1
SCLK #2
SCLK #3
SDO #1
CDI #2
1. . . . . . . . . . . . . .16
High-Z
1. . . . . . . . . . . . . .16
1. . . . . . . . . . . . . .16
High-Z
Conversion N
from Device #1
tSU2
CS #2
CS #3
SDO #2
CDI #3
SDO #3
SDI #1
SDI #2
SDI #3
(1)
High-Z
High-Z
High-Z
Conversion (N - 1)
from Device #2(1)
Conversion N
from Device #1
Conversion N
from Device #3
Conversion (N - 1)
from Device #2(1)
Conversion N
from Device #1
Read Data
Read Data
Don't Care
Configure
High-Z
Don't Care
Data from device #2 is from previous converison.
Figure 49. Simplified Daisy-Chain Mode Timing with Separate CONVST and Continuous CS
The number of SCLKs required for a serial read cycle depends on the combination of different read modes, TAG
mode, daisy-chain mode, and the manner in which a channel is selected (for example, Auto Channel Select
mode). The required number of SCLKs for different readout modes are listed in Table 7.
Table 7. Required SCLKs For Different Readout Mode Combinations
DAISY-CHAIN MODE
CFR_D5
TAG MODE
CFR_D1
NUMBER OF SCLK CYCLES
PER SPI READ
1
0
16
1
1
≥ 19
0
0
16
None
0
1
24
TAG bits plus 5 zeros
32
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TRAILING BITS
None
TAG bits plus up to 5 zeros
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SCLK skew between converters and data path delay through the converters configured in daisy-chain mode can
affect the maximum frequency of SCLK. The delay can also be affected by supply voltage and loading. It may be
necessary to slow down the SCLK when the devices are configured in daisy-chain mode. Typical delays are
shown in Figure 50.
ADS8331/32 #3
SDO
CDI
Logic
Delay
Plus PAD
2.7ns
D
Logic
Delay
<=8.3ns
Logic
Delay
Plus PAD
8.3ns
Q
CLK
Serial data
output
ADS8331/32 #2
SDO
CDI
Logic
D
Delay
<= . ns
Logic
Delay
Plus PAD
2.7ns
Logic
Delay
Plus PAD
8.3ns
Q
CLK
ADS8331/32 #1
CDI
Serial data
input
SDO
Logic
Delay
Plus PAD
2.7ns
D
Logic
Delay
<=8.3ns
CLK
Q
Logic
Delay
Plus PAD
8.3ns
SCLK input
Figure 50. Typical Delays Through Converters Configured in Daisy-Chain Mode
RESET FUNCTION
The ADS8331/32 can be reset with three different methods: internal POR, software reset, and external reset
using the RESET pin.
The internal POR circuit is activated when power is initially applied to the converter. This internal circuit
eliminates the need for commands to be sent to the converter after power-on in order to set the default mode of
operation (see the Power-On Sequence Timing section for further details).
Software reset can be used to place the converter in the default mode by setting the CFR_D0 bit to '0' in the
Configuration register (see Table 5). This bit is automatically returned to '1' (default) after the converter is reset.
This reset method is useful in systems that cannot dedicate a separate control signal to the RESET pin. In these
situations, the RESET pin must be connected to VBD in order for the ADS8331/32 to operate properly.
If communication in the system becomes corrupted and a software reset cannot be issued, the RESET pin can
be used to reset the device manually. In order to reset the device and return the device to default mode, this pin
must held low for a minimum of 25ns.
After the ADS8331/32 detects a reset condition, the minimum time before the device can be reconfigured by
FS/CS going low and data clocking in on SDI is 2μs.
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APPLICATION INFORMATION
TYPICAL CONFIGURATION EXAMPLE
Figure 51 illustrates a typical circuit configuration using the ADS8331/32.
Analog +5V
4.7mF
AGND
External
Reference
Input
22mF
Analog Input
AGND
VA
REF+ REF- AGND
MUXOUT ADCIN INX COM
Interface
Supply
+1.8V
FS/CS
SDO
SDI
SCLK
4.7mF
DGND
Host
Processor
ADS8331/32
CONVST
VBD
EOC/INT
Figure 51. Typical Circuit Configuration
POWER-ON SEQUENCE TIMING
During power-on of the ADS8331/32, the digital interface supply voltage (VBD) should not exceed the analog
supply voltage (VA). This condition is specified in the Power-Supply Requirements section of the Electrical
Characteristics tables. If the analog and digital interface supplies for the converter are not generated by a single
voltage source, it is recommended to power-on the analog supply and wait for it to reach its final value before the
digital interface supply is activated. Furthermore, the voltages applied to the analog input pins (INX, ADCIN) and
digital input pins (RESET, FS/CS, SCLK, SDI, and CONVST) should not exceed the voltages on VA and VBD,
respectively, during the power-on sequence. This requirement prevents these input pins from powering the
ADS8331/32 through the ESD protection diodes/circuitry and causing a latch-up condition (see the Electrical
Characteristic tables and Figure 34 for further details).
Communication with the ADS8331/32, such as initiating a conversion with CONVST or writing to the
Configuration register, should not occur for a minimum of 2μs after the analog and digital interface supplies have
finished the power-on sequence and reached the respective final values in the system. This time is required for
the internal POR to activate and place the digital core of the device into the default mode of operation. This
minimum delay time must also be adhered to whenever a reset condition occurs (see the Reset Function section
for additional information).
34
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LAYOUT
For optimum performance, care should be taken with the physical layout of the ADS8331/32 circuitry. This
consideration is particularly true if the reference voltage is low and/or the conversion rate is high. With a
conversion clock of 12MHz, the ADS8331/32 makes a bit decision every 83ns. That is, for each subsequent bit
decision, the capacitor array must be switched and charged, and the input to the comparator settled to a 16-bit
level, all within one conversion clock cycle.
The basic SAR architecture is sensitive to spikes on the power supply, reference, and ground connections that
occur just prior to latching the comparator output. Thus, during any single conversion for an n-bit SAR converter,
there are n windows in which large external transient voltages can easily affect the conversion result. Such
spikes might originate from switching power supplies, digital logic, and high-power devices, to name a few
potential sources. This particular source of error can be very difficult to track down if the glitch is almost
synchronous to the converter CCLK signal because the phase difference between the two changes with time and
temperature, causing sporadic misoperation.
With this possibility in mind, power to the ADS8331/32 should be clean and well-bypassed. A 0.1μF ceramic
bypass capacitor should be placed as close as possible to the ADS8331/32 package. In addition, a 1μF to 10μF
capacitor and a 5Ω or 10Ω series resistor may be used to low-pass filter a noisy supply.
The reference should be similarly bypassed with a 22μF capacitor. Again, a series resistor and large capacitor
can be used to low-pass filter the reference voltage. If the reference voltage originates from an op amp, make
sure that the op amp can drive the bypass capacitor without oscillation (the series resistor can help in this case).
Although the ADS8331/32 draws very little current from the reference on average, there can still be
instantaneous current demands placed on the external input and reference circuitry.
The OPA365 or OPA211 from Texas Instrumets provide optimum performance for buffering the signal inputs; the
OPA350 can be used to effectively buffer the reference input.
Also, keep in mind that the ADS8331/32 offers no inherent rejection of noise or voltage variation in regards to the
reference input. This consideration is of particular concern when the reference input is tied to the power supply.
Any noise and ripple from the supply will appear directly in the digital results. While high-frequency noise can be
filtered, voltage variation resulting from the line frequency (50Hz or 60Hz) can be difficult to remove.
The AGND pin on the ADS8331/32 should be placed on a clean ground point. In many cases, this location is the
analog ground. Avoid connecting the AGND pin too close to the grounding point for a microprocessor,
microcontroller, or digital signal processor. If needed, run a ground trace directly from the converter to the
power-supply connection point. The ideal layout includes an analog ground plane for the converter and
associated analog circuitry.
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PACKAGE OPTION ADDENDUM
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27-Feb-2010
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
ADS8331IBRGER
ACTIVE
VQFN
RGE
24
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ADS8331IBRGET
ACTIVE
VQFN
RGE
24
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ADS8331IRGER
ACTIVE
VQFN
RGE
24
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ADS8331IRGET
ACTIVE
VQFN
RGE
24
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ADS8332IBRGER
ACTIVE
VQFN
RGE
24
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ADS8332IBRGET
ACTIVE
VQFN
RGE
24
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ADS8332IRGER
ACTIVE
VQFN
RGE
24
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ADS8332IRGET
ACTIVE
VQFN
RGE
24
250
CU NIPDAU
Level-2-260C-1 YEAR
Green (RoHS &
no Sb/Br)
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
IMPORTANT NOTICE
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Products
Applications
Amplifiers
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DLP® Products
www.dlp.com
Communications and
Telecom
www.ti.com/communications
DSP
dsp.ti.com
Computers and
Peripherals
www.ti.com/computers
Clocks and Timers
www.ti.com/clocks
Consumer Electronics
www.ti.com/consumer-apps
Interface
interface.ti.com
Energy
www.ti.com/energy
Logic
logic.ti.com
Industrial
www.ti.com/industrial
Power Mgmt
power.ti.com
Medical
www.ti.com/medical
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
RFID
www.ti-rfid.com
Space, Avionics &
Defense
www.ti.com/space-avionics-defense
RF/IF and ZigBee® Solutions www.ti.com/lprf
Video and Imaging
www.ti.com/video
Wireless
www.ti.com/wireless-apps
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