PD - 95588A
IRL1404PbF
HEXFET® Power MOSFET
l
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Advanced Process Technology
Ultra Low On-Resistance
Dynamic dv/dt Rating
175°C Operating Temperature
Fast Switching
Fully Avalanche Rated
Lead-Free
D
VDSS = 40V
RDS(on) = 4.0mΩ
G
ID = 160A
S
Description
Seventh Generation HEXFET® power MOSFETs from International
Rectifier utilize advanced processing techniques to achieve extremely
low on-resistance per silicon area. This benefit, combined with the fast
switching speed and ruggedized device design that HEXFET power
MOSFETs are well known for, provides the designer with an extremely
efficient and reliable device for use in a wide variety of applications.
The TO-220 package is universally preferred for all commercial-industrial
applications at power dissipation levels to approximately 50 watts. The
low thermal resistance and low package cost of the TO-220 contribute to
its wide acceptance throughout the industry.
TO-220AB
Absolute Maximum Ratings
Parameter
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TC = 25°C
VGS
EAS
IAR
EAR
dv/dt
TJ
TSTG
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
Mounting torque, 6-32 or M3 srew
Max.
Units
160
110
640
200
1.3
± 20
620
95
20
5.0
-55 to + 175
A
W
W/°C
V
mJ
A
mJ
V/ns
°C
300 (1.6mm from case)
10 lbf•in (1.1N•m)
Thermal Resistance
RθJC
RθCS
RθJA
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Parameter
Typ.
Max.
Units
Junction-to-Case
Case-to-Sink, Flat, Greased Surface
Junction-to-Ambient (PCB Mounted)
–––
0.50
–––
0.75
–––
62
°C/W
1
09/27/10
IRL1404PbF
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
∆V(BR)DSS/∆TJ
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Min.
40
–––
–––
–––
1.0
93
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Typ.
–––
0.038
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
18
270
38
37
RDS(on)
Static Drain-to-Source On-Resistance
VGS(th)
gfs
Gate Threshold Voltage
Forward Transconductance
IDSS
Drain-to-Source Leakage Current
LD
Internal Drain Inductance
–––
4.5
LS
Internal Source Inductance
–––
7.5
Ciss
Coss
Crss
Coss
Coss
Coss eff.
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Output Capacitance
Output Capacitance
Effective Output Capacitance
–––
–––
–––
–––
–––
–––
6590
1710
350
6650
1510
1480
V(BR)DSS
IGSS
Max. Units
Conditions
–––
V
VGS = 0V, ID = 250µA
––– V/°C Reference to 25°C, ID = 1mA
4.0
VGS = 10V, ID = 95A
mΩ
5.9
VGS = 4.3V, ID = 40A
3.0
V
VDS = VGS, ID = 250µA
–––
S
VDS = 25V, ID = 95A
20
VDS = 40V, VGS = 0V
µA
250
VDS = 32V, VGS = 0V, TJ = 150°C
200
VGS = 20V
nA
-200
VGS = -20V
140
ID = 95A
48
nC
VDS = 32V
60
VGS = 5.0V, See Fig. 6
–––
VDD = 20V
ns
–––
ID = 95A
–––
RG = 2.5Ω
VGS = 4.5V
–––
RD = 0.25Ω
D
Between lead,
–––
nH
6mm (0.25in.)
G
from package
–––
and center of die contact
S
–––
VGS = 0V
–––
pF
VDS = 25V
–––
ƒ = 1.0MHz, See Fig. 5
–––
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
–––
VGS = 0V, VDS = 32V, ƒ = 1.0MHz
–––
VGS = 0V, VDS = 0V to 32V
Source-Drain Ratings and Characteristics
IS
ISM
VSD
trr
Qrr
ton
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11).
Starting TJ = 25°C, L = 0.35mH
RG = 25Ω, IAS = 95A. (See Figure 12).
ISD ≤ 95A, di/dt ≤ 160A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 175°C.
Pulse width ≤ 300µs; duty cycle ≤ 2%.
2
Min. Typ. Max. Units
Conditions
D
MOSFET symbol
––– ––– 160
showing the
A
G
integral reverse
––– ––– 640
S
p-n junction diode.
––– ––– 1.3
V
TJ = 25°C, IS = 95A, VGS = 0V
––– 63
94
ns
TJ = 25°C, IF = 95A
––– 170 250
nC di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS.
Calculated continuous current based on maximum allowable
junction temperature; for recommended current-handing of the
package refer to Design Tip # 93-4.
Calculated continuous current based on maximum allowable
junction temperature. Package limitation current is 75A.
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IRL1404PbF
1000
1000
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.3V
I D , Drain-to-Source Current (A)
I D , Drain-to-Source Current (A)
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.3V
TOP
TOP
4.3V
4.3V
100
100
20µs PULSE WIDTH
TJ = 25 °C
10
0.1
1
10
10
0.1
100
Fig 1. Typical Output Characteristics
2.5
RDS(on) , Drain-to-Source On Resistance
(Normalized)
I D , Drain-to-Source Current (A)
TJ = 25 ° C
TJ = 175 ° C
V DS = 15V
20µs PULSE WIDTH
6.0
7.0
VGS , Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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10
100
Fig 2. Typical Output Characteristics
1000
5.0
1
VDS , Drain-to-Source Voltage (V)
VDS , Drain-to-Source Voltage (V)
100
4.0
20µs PULSE WIDTH
TJ = 175 °C
8.0
ID = 160A
2.0
1.5
1.0
0.5
0.0
-60 -40 -20 0
VGS = 10V
20 40 60 80 100 120 140 160 180
TJ , Junction Temperature ( °C)
Fig 4. Normalized On-Resistance
Vs. Temperature
3
IRL1404PbF
VGS = 0V,
f = 1MHz
Ciss = Cgs + Cgd , Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
C, Capacitance (pF)
8000
Ciss
6000
4000
Coss
2000
20
VGS , Gate-to-Source Voltage (V)
10000
1
10
VDS = 32V
VDS = 20V
16
12
8
4
Crss
0
ID = 95A
0
100
FOR TEST CIRCUIT
SEE FIGURE 13
0
VDS , Drain-to-Source Voltage (V)
300
400
500
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
1000
10000
OPERATION IN THIS AREA LIMITED
BY RDS(on)
100
ID , Drain Current (A)
ISD , Reverse Drain Current (A)
200
QG , Total Gate Charge (nC)
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
1000
TJ = 175 ° C
10
10us
100us
100
TJ = 25 ° C
1
0.0
V GS = 0 V
0.5
1.0
1.5
2.0
2.5
VSD ,Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
100
3.0
1ms
10
TC = 25 ° C
TJ = 175 ° C
Single Pulse
1
10ms
10
100
VDS , Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRL1404PbF
RD
160
VDS
LIMITED BY PACKAGE
VGS
ID , Drain Current (A)
D.U.T.
RG
120
+
-VDD
10V
80
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
40
VDS
90%
0
25
50
75
100
125
150
175
TC , Case Temperature ( °C)
10%
VGS
Fig 9. Maximum Drain Current Vs.
Case Temperature
td(on)
tr
t d(off)
tf
1
Thermal Response (Z thJC )
D = 0.50
0.20
0.1
0.10
0.05
0.02
0.01
0.01
P DM
SINGLE PULSE
(THERMAL RESPONSE)
t1
t2
0.001
0.00001
Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJC + TC
0.0001
0.001
0.01
0.1
1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRL1404PbF
D.U.T
RG
IAS
20V
tp
+
V
- DD
0.01Ω
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
tp
I AS
Fig 12b. Unclamped Inductive Waveforms
ID
49A
101A
BOTTOM 121A
TOP
1200
DRIVER
L
VDS
EAS , Single Pulse Avalanche Energy (mJ)
1500
15V
A
900
600
300
0
25
50
75
125
150
175
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
Current Regulator
Same Type as D.U.T.
QG
10 V
100
Starting TJ , Junction Temperature ( ° C)
50KΩ
QGS
QGD
12V
.2µF
.3µF
D.U.T.
VG
+
V
- DS
VGS
3mA
Charge
IG
ID
Current Sampling Resistors
Fig 13a. Basic Gate Charge Waveform
6
Fig 13b. Gate Charge Test Circuit
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IRL1404PbF
Peak Diode Recovery dv/dt Test Circuit
+
D.U.T*
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
-
-
+
RG
• dv/dt controlled by RG
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
VGS
*
+
-
VDD
Reverse Polarity of D.U.T for P-Channel
Driver Gate Drive
P.W.
Period
D=
P.W.
Period
[VGS=10V ] ***
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
[VDD]
Forward Drop
Inductor Curent
Ripple ≤ 5%
[ISD ]
*** VGS = 5.0V for Logic Level and 3V Drive Devices
Fig 14. For N-channel HEXFET® power MOSFETs
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7
IRL1404PbF
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
TO-220AB Part Marking Information
EXAMPLE: T HIS IS AN IRF1010
LOT CODE 1789
AS S EMBLED ON WW 19, 2000
IN THE AS S EMBLY LINE "C"
Note: "P" in as sembly line position
indicates "Lead - Free"
INT ERNAT IONAL
RECT IFIER
LOGO
AS S EMBLY
LOT CODE
PART NUMBER
DAT E CODE
YEAR 0 = 2000
WEEK 19
LINE C
Notes:
1. For an Automotive Qualified version of this part please seehttp://www.irf.com/product-info/auto/
2. For the most current drawing please refer to IR website at http://www.irf.com/package/
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.09/2010
8
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