E2U0042-28-81 ¡ Semiconductor MSM7705-01/02/03 ¡ Semiconductor This version: Aug. 1998 MSM7705-01/02/03 Previous version: Nov. 1996 4ch Single Rail CODEC GENERAL DESCRIPTION The MSM7705-01/02/03 are four-channel CODEC CMOS ICs for voice signals ranging from 300 to 3400 Hz. These devices contain filters for A/D and D/A conversion. Designed especially for a single-power supply and low-power applications, these devices contain four-channel A/D and D/A converters in a single chip and achieve a reduced footprint and a reduced number of external components. The MSM7705-01/02/03 are best suited for digital telephone terminals, digital PABXs, and pushbutton phones. FEATURES • Single power supply: +5 V • Power consumption Operating mode: 70 mW Typ. 140 mW Max. Power-saving mode: 14 mW Typ. 32 mW Max. Power-down mode: 0.05 mW Typ. 0.3 mW Max. • Conforms to ITU-T Companding law MSM7705-01: m/A-law pin-selectable MSM7705-02: m-law MSM7705-03: A-law • Built-in PLL eliminates a master clock • The PCM interface can be switched between 4 channel serial/parallel • Transmission clock: 64/128/256/512/1024/2048 kHz 96/192/384/768/1536/1544 kHz (During 4 channel serial mode, the 64, 96, 128, and 192 kHz clocks are disabled) • Transmit gain adjustable for each channel • Built-in reference voltage supply • Analog output can directly drive a 600 W line transformer • Package: 44-pin plastic QFP (QFP44-P-910-0.80-2K) (Product name : MSM7705-01GS-2K) (Product name : MSM7705-02GS-2K) (Product name : MSM7705-03GS-2K) 1/20 ¡ Semiconductor MSM7705-01/02/03 BLOCK DIAGRAM AIN1 RC LPF – + 8th BPF AD CONV. TCONT GSX1 AIN2 – RC LPF + 8th BPF GSX2 AIN3 AUTO ZERO – + DOUT1 DOUT2 DOUT3 DOUT4 RC LPF 8th BPF RC LPF 8th BPF PLL XSYNC BCLK AD CONV. (ALAW) GSX3 CHPS AIN4 – + GSX4 AOUT1 AOUT2 AOUT3 AOUT4 SGC AUTO ZERO RTIM 5th LPF – + S&H RSYNC DA CONV. – + – + 5th LPF S&H 5th LPF S&H RCONT DIN1 DIN2 DIN3 DIN4 DA CONV. 5th LPF – + S&H PWD Logic SG GEN VR GEN PDN VDD AG DG 2/20 ¡ Semiconductor MSM7705-01/02/03 DIN2 10 RSYNC 12 DIN1 11 35 GSX3 36 GSX4 37 AIN4 38 SGC 39 AG 40 AG 41 AOUT1 42 AOUT2 43 AOUT3 34 AIN3 33 AIN2 32 GSX2 31 GSX1 30 AIN1 29 NC 28 NC 27 NC 26 NC 25 (ALAW)* 24 PDN 23 CHPS DOUT1 22 DIN3 9 DOUT2 21 DIN4 8 DOUT3 20 NC 7 DOUT4 19 NC 6 NC 18 5 DG 16 DD ( DG 17 VDD 4 (V NC 15 NC 3 BCLK 14 NC 2 XSYNC 13 NC 1 ( 44 AOUT4 PIN CONFIGURATION (TOP VIEW) NC : No connect pin 44-Pin Plastic QFP VDD, DG, and AG have two pins each. Each of these pairs are internally connected with each other. * The ALAW pin is only supported by MSM7705-01GS-2K. 3/20 ¡ Semiconductor MSM7705-01/02/03 PIN AND FUNCTIONAL DESCRIPTIONS AIN1, AIN2, AIN3, AIN4, GSX1, GSX2, GSX3, GSX4 AIN1, AIN2, AIN3, and AIN4 are the transmit analog inputs for channels 1, 2, 3 and 4 respectively. GSX1, GSX2, GSX3, and GSX4 are the transmit level adjustments for channels 1, 2, 3 and 4 respectively. AIN1, AIN2, AIN3, and AIN4 are connected to the inverting inputs for the op-amps. GSX1, GSX2, GSX3, and GSX4 are connected to the outputs for the op-amps. They are used to adjust levels as shown below, and are connected to the outputs of the op-amps. During power saving mode and power down mode, the GSX1, GSX2, GSX3, and GSX4 outputs are at 0 V. When these pins are not used, connect AIN1 to GSX1, AIN2 to GSX2, AIN3 to GSX3, and AIN4 to GSX4. R2n CHn Analog Input C1n R1n GSXn AINn – + CHn Gain Gain = R2n/R1n £ 10 R1n: Variable R2n > 20 kW C1n > 1/(2 ¥ 3.14 ¥ 30 ¥ R1n) (F) AOUT1, AOUT2, AOUT3, AOUT4 AOUT1, AOUT2, AOUT3, and AOUT4 are the receive filter outputs for channels 1, 2, 3, and 4 respectively. When the digital signal of +3 dBm0 is input to DIN1, DIN2, DIN3, and DIN4, the output signal has an amplitude of 3.4 VPP above and below the signal ground voltage (SG : 1/2 VDD). The output can drive a load of 600 W or more. During power saving or power down mode, these outputs are at the voltage level of SG with a high impedance. 4/20 ¡ Semiconductor MSM7705-01/02/03 DIN1, DIN2, DIN3 PCM signal inputs for channels 1, 2, and 3 when the parallel mode is selected. D/A conversion is performed by the serial PCM signals to these pins, the RSYNC signals synchronous with the serial PCM signals, and the BCLK signal. Then the analog signals are output from AOUT1, AOUT2, and AOUT3 pins, respectively. The data rate of the PCM signal is equal to the frequency of the BCLK signal. The PCM signal is shifted at the falling edge of the BCLK signal and latched into the internal register when shifted by eight bits. The start of the PCM data (MSD) is identified at the rising edge of RSYNC. When the serial mode is selected, this pin is not used and should be connected to GND (0 V). DIN4 PCM signal input for channel 4 when the parallel mode is selected. D/A conversion is performed by the serial PCM signal to this pin, the RSYNC signal synchronous with the serial PCM signal, and the BCLK signal. Then the analog signal is output from AOUT4 pin. The data rate of the PCM signal is equal to the frequency of the BCLK signal. The PCM signal is shifted at the falling edge of the BCLK signal and latched into the internal register when shifted by eight bits. The start of the PCM data (MSD) is identified at the rising edge of RSYNC. When the serial mode is selected, this pin is used for the 4ch multiplexed PCM signal input. BCLK Shift clock signal input for DIN1, DIN2, DIN3, DIN4, DOUT1, DOUT2, DOUT3, and DOUT4. The frequency is equal to the data rate. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power saving state. RSYNC Receive synchronizing signal input. Eight bits of PCM data required are selected from a series of PCM signal to the DIN1, DIN2, DIN3, and DIN4 pins by the receive synchronizing signal. All timing signals in the receive section are synchronized by this synchronizing signal. This signal must be synchronized in phase with the BCLK (generated from the same clock source as BCLK). The frequency should be 8 kHz ±50 ppm to guarantee the AC characteristics which are mainly the frequency characteristics of the receive section. However, this device operates in the range of 6 kHz to 10 kHz unless the frequency characteristics of the system used are strictly specified, but the electrical characteristics specified in the data sheet are not guaranteed. 5/20 ¡ Semiconductor MSM7705-01/02/03 XSYNC Transmit synchronizing signal input. PCM output signal from the DOUT1, DOUT2, DOUT3, and DOUT4 pins is output in synchronization with this transmit synchronizing signal. This synchronizing signal triggers the PLL and synchronizes all timing signals of the transmit section. This synchronizing signal must be synchronized in phase with BCLK. The frequency should be 8 kHz ±50 ppm to guarantee the AC characteristics which are mainly the frequency characteristics of the transmit section. However, this device can be operated in the range of 6 kHz to 10 kHz unless the frequency characteristics of the system used are strictly specified, but the electrical characteristics are not guaranteed. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to power saving state. DOUT1 PCM signal output of channel 1 when the parallel mode is selected. The PCM output signal is output from MSD in a sequential order, synchronizing with the rising edge of the BCLK signal. MSD may be output at the rising edge of the XSYNC signal, based on the timing between BCLK and XSYNC. This pin is in a high impedance state except during 8-bit PCM output. It is also in a high impedance state during power-saving state or power-down state. When the serial mode is selected, this pin is configured to be the output of serial multiplexed 4ch PCM signal. A pull-up resistor must be connected to this pin because it is an open drain output. This device is compatible with the ITU-T recommendation on coding law and output coding format. The MSM7705-03 (A-law) outputs the character signal, inverting the even bits. Input/Output Level PCMIN/PCMOUT MSM7705-02 (m-law) MSD MSM7705-03 (A-law) MSD +Full scale 1 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 +0 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 –0 0 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 –Full scale 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 6/20 ¡ Semiconductor MSM7705-01/02/03 DOUT2, DOUT3, DOUT4 PCM signal outputs for channels 2, 3, and 4 when parallel mode is selected. The PCM output signal is output from MSD in a sequential order, synchronizing with the rising edge of the BCLK signal. MSD may be output at the rising edge of the XSYNC signal, based on the timing between BCLK and XSYNC. This pin is in a high impedance state except during 8-bit PCM output. It is also in a high impedance state during power-saving state or power-down state. When the serial mode is selected, this pin is unconnected. A pull-up resistor must be connected to each of these pins because it is an open drain output. This device is compatible with the ITU-T recommendation on coding law and output coding format. The MSM7705-03 (A-law) outputs the character signal inverting the even bits. CHPS Control signal input for the mode selection of PCM input and output. When this signal is at a logic "1" level, the PCM input and output are in parallel mode. The PCM data of CH1, CH2, CH3, and CH4 is input to DIN1, DIN2, DIN3, and DIN4 outputs from DOUT1, DOUT2, DOUT3, and DOUT4 with the same timing. When this signal is at logic "0" level, the PCM input and output are in serial mode. The PCM data of CH1 to CH4 is input from DIN4 and output from DOUT1 as time division multiplexed data. PDN Power down control signal. When PDN is at a logic "0" level, both transmit and receive circuits are in power down state. VDD Power supply for +5 V. A power supply for an analog circuit in the system to which the device is applied should be used. A bypass capacitor of 0.1 mF to 1 mF with excellent high-frequency characteristics and a capacitor of 10 mF to 20 mF should be connected between this pin and the AG pin if needed. AG Analog signal ground. DG Ground for digital signal circuits. This ground is separate from the analog signal ground. The DG pin must be connected to the AG pin on the printed circuit board to make a common analog ground. 7/20 ¡ Semiconductor MSM7705-01/02/03 SGC Used to generate the signal ground voltage level by connecting a bypass capacitor. Connect a 0.1 mF capacitor with excellent high frequency characteristics between the AG pin and the SGC pin. ALAW Control signal input of the companding law selection. Only the MSM7705-01GS-2K has this pin. The CODEC will operate in the m-law when this pin is at a logic "0" level and will operate in the A-law when this pin is at a logic "1" level. The CODEC operates in the m-law if the pin is left open, since this pin is internally pulled down. 8/20 ¡ Semiconductor MSM7705-01/02/03 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Condition Rating Unit Power Supply Voltage VDD Analog Input Voltage VAIN — 0 to 7.0 V — –0.3 to VDD + 0.3 V Digital Input Voltage Storage Temperature VDIN — –0.3 to VDD + 0.3 V TSTG — –55 to +150 °C RECOMMENDED OPERATING CONDITIONS Parameter Symbol Power Supply Voltage VDD Operating Temperature Ta Typ. Max. 4.75 5.0 5.25 V –30 +25 +85 °C Min. Condition Voltage must be fixed — Unit Analog Input Voltage VAIN Gain = 1 — — 3.4 VPP High Level Input Voltage VIH XSYNC, RSYNC, BCLK, DIN1, 2.2 — VDD V Low Level Input Voltage VIL 0 — 0.8 V DIN2, DIN3, DIN4, PDN, Clock Frequency FC Sync Pulse Frequency FS Clock Duty Ratio Digital Input Rise Time Digital Input Fall Time Transmit Sync Pulse Setting Time Receive Sync Pulse Setting Time CHPS, ALAW BCLK = (When in 4ch serial 64, 128, 256, 512, 1024, mode, 64, 96, 128, 192 kHz 2048, 96, 192, 384, 768, are not used) 1536, 1544 XSYNC, RSYNC 6.0 8.0 10.0 DC BCLK 40 50 60 % tIr XSYNC, RSYNC, BCLK, DIN1, — — 50 ns tIf DIN2, DIN3, DIN4, PDN, CHPS — — 50 ns BCLKÆXSYNC, See Fig. 1 100 — — ns tSX XSYNCÆBCLK, See Fig. 1 100 — — ns tRS BCLKÆRSYNC, See Fig. 1 100 — — ns 100 — — ns 1 BCLK — 100 ms DIN1, DIN2, DIN3, DIN4 100 — — ns DIN1, DIN2, DIN3, DIN4 100 — — ns Pull-up resistor 0.5 — — kW — — tSR RSYNCÆBCLK, See Fig. 1 XSYNC, RSYNC DIN Setup Time tDS DIN Hold Time tDH RDL DOUT1, DOUT2, CDL DOUT3, DOUT4 Digital Output Load kHz tXS tWS Sync Pulse Width kHz Analog Input Allowable DC Offset Voff Allowable Jitter Width — — 100 pF Transmit gain stage, Gain = 1 VDD/2 –100 — VDD/2 +100 mV Transmit gain stage, Gain = 10 VDD/2 –10 — VDD/2 +10 mV — — 500 ns XSYNC, RSYNC 9/20 ¡ Semiconductor MSM7705-01/02/03 ELECTRICAL CHARACTERISTICS DC and Digital Interface Characteristics (VDD = +5 V ±5%, Ta = –30°C to +85°C) Parameter Symbol IDD1 Condition Operating mode, No signal Min. Typ. Max. Unit — 14.0 28.0 mA — 2.6 6.0 mA Power-save mode, PDN = 1, Power Supply Current IDD2 XSYNC or BCLK OFF IDD3 Power-down mode, PDN = 0 BCLK OFF — 0.01 0.05 mA High Level Input Voltage VIH — 2.2 — VDD V Low Level Input Voltage VIL — 0.0 — 0.8 V High Level Input Leakage Current IIH — — — 2.0 mA Low Level Input Leakage Current IIL Digital Output Low Voltage VOL — Pull-up resistor > 500 W — — 0.5 mA 0.0 0.2 0.4 V Digital Output Leakage Current IO — — — 10 mA Input Capacitance CIN — — 5 — pF Transmit Analog Interface Characteristics (VDD = +5 V ± 5%, Ta = –30°C to +85°C) Parameter Min. Typ. Max. Unit Input Resistance Symbol RINX AIN1, AIN2, AIN3, AIN4 Condition 10 — — MW Output Load Resistance RLGX GSX1, GSX2, GSX3, GSX4 20 — — kW Output Load Capacitance CLGX with respect to SG Output Amplitude VOGX Offset Voltage VOSGX Gain = 1 — — 30 pF –1.7 — +1.7 V –20 — +20 mV Receive Analog Interface Characteristics (VDD = +5 V ±5%, Ta = –30°C to +85°C) Parameter Symbol Output Load Resistance RLAO Output Load Capacitance CLAO Output Amplitude VOAO Offset Voltage VOSAO Condition Each output; AOUT1 with respect to SG AOUT2 — AOUT3 RL = 0.6 kW; AOUT4 with respect to SG — Min. Typ. Max. Unit 0.6 — — kW — — 50 pF –1.7 — +1.7 V –100 — +100 mV 10/20 ¡ Semiconductor MSM7705-01/02/03 AC Characteristics (VDD = +5 V ±5%, Ta = –30°C to +85°C) Parameter Transmit Frequency Response Receive Frequency Response Loss T1 Freq. (Hz) 60 Loss T2 300 Loss T3 1020 Loss T4 2020 Loss T5 Loss T6 Symbol Min. Typ. Max. 20 26 — –0.15 +0.07 +0.20 Reference 0 –0.15 –0.04 +0.20 3000 –0.15 +0.03 +0.20 3400 0 0.40 0.80 Loss R1 300 –0.15 –0.03 +0.20 Loss R2 1020 Loss R3 2020 Loss R4 Loss R5 –0.15 +0.04 +0.20 3000 –0.15 +0.11 +0.20 3400 0.0 0.47 0.80 0 3 35 43 — SD T2 0 35 41 — 1020 35 38 — –40 29 31.5 — SD T5 –45 24 27 — SD R1 3 36 43 — 36 41 — 36 40 — 30 33.5 — SD R3 –30 *1 SD T4 SD R2 0 1020 –30 *1 SD R4 –40 SD R5 –45 25 30 — GT T1 3 –0.3 +0.02 +0.3 –10 GT T2 Transmit Gain Tracking Receive Gain Tracking GT T3 –0.3 +0.04 +0.3 GT T4 –50 –0.5 +0.15 +0.5 GT T5 –55 –1.2 +0.40 +1.2 GT R1 3 –0.3 0.0 +0.3 GT R2 –10 1020 dB dB dB dB Reference –40 GT R3 1020 Unit Reference SD T1 Transmit Signal to Distortion Ratio SD T3 Receive Signal to Distortion Ratio Level Condition (dBm0) dB Reference –40 –0.3 +0.04 +0.3 GT R4 –50 –0.5 +0.16 +0.5 GT R5 –55 –1.2 +0.37 +1.2 dB *1 Psophometric filter is used 11/20 ¡ Semiconductor MSM7705-01/02/03 AC Characteristics (Continued) (VDD = +5 V ±5%, Ta = –30°C to +85°C) Parameter Idle Channel Noise Symbol Freq. (Hz) Nidle T — Nidle R — Level Condition (dBm0) AIN = SG — *1 *2 — *1 *3 VDD = 5.0 V AV T Absolute Level (Initial Difference) (Deviation of Temperature and Power) Typ. Max. — –73.5 –70 — –71.5 –68 — –78 –75 0.821 0.850 0.880 0.821 0.850 0.880 AV Tt 1020 0 VDD = 5 V ±5% Ta = –30 AV Rt to +85°C Unit –0.2 — +0.2 dB –0.2 — +0.2 dB — — 0.60 ms dBm0p Vrms Ta = 25°C AV R Absolute Level Min. A to A Absolute Delay tD 1020 0 BCLK = 64 kHz Transmit Group Delay Receive Group Delay tGD T1 500 — 0.19 0.75 tGD T2 600 — 0.11 0.35 tGD T3 1000 — 0.02 0.125 tGD T4 2600 — 0.05 0.125 tGD T5 2800 — 0.07 0.75 tGD R1 500 — 0.00 0.75 tGD R2 600 tGD R3 1000 tGD R4 2600 tGD R5 2800 0 0 CR T Crosstalk Attenuation CR R CR CH *1 *2 *3 *4 1020 0 *4 *4 — 0.00 0.35 — 0.00 0.125 — 0.09 0.125 — 0.12 0.75 TRANS Æ RECV 75 80 — RECV Æ TRANS 70 76 — CH to CH 75 80 — ms ms dB Psophometric filter is used Upper columns are specified for the m-law, lower for the A-law Input "0" code to PCMIN Minimum value of the group delay distortion 12/20 ¡ Semiconductor MSM7705-01/02/03 AC Characteristics (Continued) (VDD = +5 V ±5%, Ta = –30°C to +85°C) Parameter Discrimination Out-of-band Spurious Intermodulation Distortion Power Supply Noise Rejection Ratio Freq. Level Condition (Hz) (dBm0) 4.6 kHz to 0 to 0 DIS 72 kHz 4000 Hz Symbol S IMD 300 to 3400 fa = 470 fd = 320 PSR T 0 to PSR R 50 kHz 0 4.6 kHz to 100 kHz tXD1 tXD2 Typ. Max. Unit 30 32 — dB — –37.5 –35 dBm0 –4 2fa – fd — –52 –35 dBm0 50 mVPP *5 — 30 — dB 20 — 200 20 — 200 20 — 200 20 — 200 tSD Digital Output Delay Time Min. CL = 100 pF + 1 LSTTL tXD3 ns *5 Measurement performed under idle channel noise 13/20 , , ¡ Semiconductor MSM7705-01/02/03 TIMING DIAGRAM Transmit Timing BCLK 1 2 tXS XSYNC DOUT1 DOUT2 DOUT3 DOUT4 3 4 5 6 7 8 9 10 11 9 10 11 tSX tWS tXD1 tSD MSD D2 tXD2 D3 D4 D5 D6 tXD3 D8 D7 Transmit Side Receive Timing BCLK 1 tRS RSYNC DIN1 DIN2 DIN3 DIN4 2 3 4 5 6 7 8 tSR tWS tDS MSD D2 tDH D3 D4 D5 D6 D7 D8 Receive Side Figure 1 Timing Diagram in the Parallel Mode (CHPS = 1) BCLK XSYNC MSD DOUT1 MSD D2 D3 D4 D5 D6 D7 D8 MSD D2 D3 D4 D5 D6 D7 D8 CH1 PCM Data MSD D2 D3 D4 D5 D6 D7 D8 CH2 PCM Data D2 D3 D4 D5 D6 D7 D8 CH3 PCM Data CH4 PCM Data Transmit Side BCLK RSYNC MSD DIN4 MSD D2 D3 D4 D5 D6 D7 D8 CH1 PCM Data MSD D2 D3 D4 D5 D6 D7 D8 CH2 PCM Data MSD D2 D3 D4 D5 D6 D7 D8 CH3 PCM Data D2 D3 D4 D5 D6 D7 D8 CH4 PCM Data Receive Side Figure 2 Timing Diagram in the Serial Mode (CHPS = 0) 14/20 ¡ Semiconductor MSM7705-01/02/03 APPLICATION CIRCUIT Example of Basic Connection (PCM Serial Mode Operation) +5 V CH1 Analog Input 1 mF 20 kW CH1 Analog Output 1 mF CH2 Analog Input 1 mF 20 kW CH2 Analog Output 1 mF CH3 Analog Input 1 mF 20 kW CH3 Analog Output 1 mF CH4 Analog Input 1 mF 20 kW CH4 Analog Output 20 kW AIN1 GSX1 AOUT1 AIN2 GSX2 20 kW AOUT2 20 kW 1 mF 4ch Multiplex PCM (Open) Signal Output (Open) (Open) DIN4 DIN3 DIN2 DIN1 4ch Multiplex PCM Signal Input AOUT3 AIN4 GSX4 ALAW 20 kW 1 kW DOUT1 DOUT2 DOUT3 DOUT4 BCLK XSYNC RSYNC PDN AIN3 GSX3 0V Bit Clock Input Sync Pulse Input Power Down Control Input 1 : Operation 0 : Power Down Companding Law Control Input 1 : A-law 0 : m-law AOUT4 0.1 mF 0V 10 mF + +5 V MSM7705-01 SGC AG AG DG DG CHPS 0V VDD VDD 1 mF 0 to 20 W 15/20 ¡ Semiconductor MSM7705-01/02/03 APPLICATION INFORMATION DOUT Pull-up Resistor A value of the pull-up resistor for the DOUT pin should be determined depending on frequencies of BCLK and load capacitance. If a smaller value is used, there may be some degradation in noise performance, resulting in an increase in supply current. Equation to give pull-up resistor 1 ———— – 50 ns 4 ¥ fBCLK Rpull = ———————— (W) CL where fBCLK = Frequency of BCLK CL = Load capacitance of the PCMOUT pin (approximately 20 pF for a CMOS or TTL load) 50 ns = Internal delay of the MSM7705 Condition for Calculation If data is turned back from DOUT to DIN under the condition the SYNC signal and BCLK signal rise simultaneously, the data can normally be transferred. X, RSYNC BCLK T T = Rpull ¥ CL DOUT 16/20 ¡ Semiconductor MSM7705-01/02/03 Calculation Example for Typical Values BCLK (kHz) Rpull (kW) CL = 10 pF CL = 20 pF CL = 50 pF CL = 100 pF 64 385.6 192.8 77.1 38.6 128 190.3 95.2 38.1 19.0 256 92.7 46.3 18.5 9.3 512 43.8 21.9 8.8 4.4 1024 19.4 9.7 3.9 1.9 1544 11.2 5.6 2.2 1.1 2048 7.2 3.6 1.4 0.7 Choice of Actual Resistor Value If the calculated value is more than or equal to 100 kW, 100 kW should be employed. +10% of the calculated value is within a tolerance, thus, for example, the value of 10 kW can be used for the calculated value of 9.3 kW in the above examples. Channel Crosstalk The MSM7705 contains the 4-channel CODEC. The circuit and trace design and pin layout are made to minimize crosstalk between channels inside the LSI device provided the following should be taken into consideration. Transmit side The GSX1 – AIN2, AIN3, and AIN4 traces should not be kept closer. The GSX2 – AIN1, AIN3, and AIN4 traces should not be kept closer. The GSX3 – AIN1, AIN2, and AIN4 traces should not be kept closer. The GSX4 – AIN1, AIN2, and AIN3 traces should not be kept closer. AIN1, AIN2, AIN3, and AIN4, which are op-amp inverting input pins, have higher resistance, therefore proximity of these lines to signal lines of other channels may cause crosstalk. Receive side The channel outputs AOUT1, AOUT2, AOUT3, and AOUT4 of the receive side are amplifier outputs with lower resistance, thus crosstalk due to PCB traces is smaller. Nevertheless, the PCB traces should not be run closer together and in parallel wherever possible. 17/20 ¡ Semiconductor MSM7705-01/02/03 How to Avoid Transmit Side Amplifier Oscillation Due to PCB Layout AINn RF – + GSXn MSM7705 The trace length (illustrated by the bold line in the above drawing) should be kept as short as possible in order to avoid oscillation. The length of less than 2 cm or 3 cm is permissible, though it depends on PCB layout. It is recommended to connect a capacitor of 20 pF to 50 pF across the feedback resistor RF, if the oscillation occurs. 18/20 ¡ Semiconductor MSM7705-01/02/03 NOTES ON USED • To ensure proper electrical characteristics, use bypass capacitors with excellent high frequency characteristics for the power supply and keep them as close as possible to the device pins. • Connect the AG pin and the DG pin as close as possible. Connect to the system ground with low impedance. • Mount the device directly on the board when mounted on PCBs. Do not use IC sockets. If the use of IC socket is unavoidable, use the short lead type socket. • When mounted on a frame, use electro-magnetic shielding, if any electro-magnetic wave sources such as power supply transformers surround the device. • Keep the voltage on the VDD pin not lower than –0.3 V even instantaneously to avoid latchup that may otherwise occur when power is turned on. • Use a low noise (particularly, low level type of high frequency spike noise or pulse noise) power supply to avoid erroneous operation and the degradation of the characteristics of these devices. 19/20 ¡ Semiconductor MSM7705-01/02/03 PACKAGE DIMENSIONS (Unit : mm) QFP44-P-910-0.80-2K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Epoxy resin 42 alloy Solder plating 5 mm or more Package weight (g) 0.41 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 20/20