Touch A/D Flash MCU BS84B08C Revision: V1.00 Date: ���������������� October 27, 2017 BS84B08C Touch A/D Flash MCU Table of Contents Features............................................................................................................. 6 CPU Features.......................................................................................................................... 6 Peripheral Features.................................................................................................................. 6 General Description.......................................................................................... 7 Block Diagram................................................................................................... 7 Pin Assignment................................................................................................. 8 Pin Description................................................................................................. 9 Absolute Maximum Ratings........................................................................... 10 D.C. Characteristics........................................................................................ 10 Operating Voltage Characteristics.......................................................................................... 10 Standby Current Characteristics.............................................................................................11 Operating Current Characteristics...........................................................................................11 A.C. Characteristics........................................................................................ 12 High Speed Internal Oscillator – HIRC – Frequency Accuracy.............................................. 12 Low Speed Internal Oscillator Characteristics – LIRC........................................................... 12 Operating Frequency Characteristic Curves.......................................................................... 13 System Start Up Time Characteristics................................................................................... 13 A/D Converter Electrical Characteristics...................................................... 14 Input/Output Characteristics......................................................................... 14 Memory Characteristics................................................................................. 15 LVR Electrical Characteristics....................................................................... 15 Power-on Reset Characteristics.................................................................... 16 System Architecture....................................................................................... 16 Clocking and Pipelining.......................................................................................................... 16 Program Counter.................................................................................................................... 17 Stack...................................................................................................................................... 18 Arithmetic and Logic Unit – ALU............................................................................................ 18 Flash Program Memory.................................................................................. 19 Structure................................................................................................................................. 19 Special Vectors...................................................................................................................... 19 Look-up Table......................................................................................................................... 19 Table Program Example......................................................................................................... 20 In Circuit Programming – ICP................................................................................................ 21 On-Chip Debug Support – OCDS.......................................................................................... 22 Data Memory................................................................................................... 23 Structure................................................................................................................................. 23 General Purpose Data Memory............................................................................................. 23 Special Purpose Data Memory.............................................................................................. 24 Rev. 1.00 2 October 27, 2017 BS84B08C Touch A/D Flash MCU Special Function Register Description......................................................... 25 Indirect Addressing Register – IAR0, IAR1............................................................................ 25 Memory Pointers – MP0, MP1............................................................................................... 25 Bank Pointer – BP.................................................................................................................. 26 Accumulator – ACC................................................................................................................ 26 Program Counter Low Register – PCL................................................................................... 26 Look-up Table Registers – TBLP, TBHP, TBLH...................................................................... 26 Status Register – STATUS..................................................................................................... 27 EEPROM Data Memory................................................................................... 29 EEPROM Data Memory Structure......................................................................................... 29 EEPROM Registers............................................................................................................... 29 Reading Data from the EEPROM.......................................................................................... 30 Writing Data to the EEPROM................................................................................................. 31 Write Protection...................................................................................................................... 31 EEPROM Interrupt................................................................................................................. 31 Programming Considerations................................................................................................. 31 Oscillators....................................................................................................... 33 Oscillator Overview................................................................................................................ 33 System Clock Configurations................................................................................................. 33 Internal RC Oscillator – HIRC................................................................................................ 34 Internal 32kHz Oscillator – LIRC............................................................................................ 34 Operating Modes and System Clocks.......................................................... 34 System Clocks....................................................................................................................... 34 System Operation Modes....................................................................................................... 35 Control Registers................................................................................................................... 36 Operating Mode Switching..................................................................................................... 38 Standby Current Considerations............................................................................................ 41 Wake-up................................................................................................................................. 41 Programming Considerations................................................................................................. 41 Watchdog Timer.............................................................................................. 42 Watchdog Timer Clock Source............................................................................................... 42 Watchdog Timer Control Register.......................................................................................... 42 Watchdog Timer Operation.................................................................................................... 43 Reset and Initialisation................................................................................... 44 Reset Functions..................................................................................................................... 44 Reset Initial Conditions ......................................................................................................... 46 Input/Output Ports.......................................................................................... 49 Pull-high Resistors................................................................................................................. 49 Port A Wake-up...................................................................................................................... 50 I/O Port Control Registers...................................................................................................... 50 I/O Port Source Current Control............................................................................................. 51 Pin-remapping Function......................................................................................................... 52 I/O Pin Structures................................................................................................................... 52 Programming Considerations ................................................................................................ 53 Rev. 1.00 3 October 27, 2017 BS84B08C Touch A/D Flash MCU Timer Modules – TM....................................................................................... 53 Introduction............................................................................................................................ 53 TM Operation......................................................................................................................... 53 TM Clock Source.................................................................................................................... 54 TM Interrupts.......................................................................................................................... 54 TM External Pins.................................................................................................................... 54 TM Input/Output Pin Control Register.................................................................................... 54 Programming Considerations................................................................................................. 56 Periodic Type TM – PTM................................................................................. 57 Periodic TM Operation .......................................................................................................... 57 Periodic Type TM Register Description ................................................................................. 58 Periodic Type TM Operating Modes ...................................................................................... 62 Analog to Digital Converter .......................................................................... 71 A/D Converter Overview........................................................................................................ 71 A/D Converter Register Description....................................................................................... 71 A/D Converter Reference Voltage.......................................................................................... 75 A/D Converter Input Pins....................................................................................................... 75 A/D Converter Operation........................................................................................................ 75 Conversion Rate and Timing Diagram................................................................................... 76 Summary of A/D Conversion Steps ....................................................................................... 77 Programming Considerations................................................................................................. 78 A/D Conversion Function....................................................................................................... 78 A/D Conversion Programming Examples............................................................................... 79 Touch Key Function....................................................................................... 81 Touch Key Structure............................................................................................................... 81 Touch Key Register Definition................................................................................................ 82 Touch Key Operation.............................................................................................................. 86 Touch Key Interrupt................................................................................................................ 87 Programming Considerations................................................................................................. 87 Serial Interface Module – SIM........................................................................ 88 SPI Interface.......................................................................................................................... 88 I2C Interface........................................................................................................................... 95 Interrupts....................................................................................................... 105 Interrupt Registers................................................................................................................ 105 Interrupt Operation............................................................................................................... 107 External Interrupt.................................................................................................................. 108 Touch Key Interrupt.............................................................................................................. 109 Time Base Interrupt.............................................................................................................. 109 A/D Converter Interrupt.........................................................................................................110 Multi-function Interrupt..........................................................................................................110 Serial Interface Module Interrupt...........................................................................................111 EEPROM Interrupt................................................................................................................111 TM Interrupt...........................................................................................................................111 Rev. 1.00 4 October 27, 2017 BS84B08C Touch A/D Flash MCU Interrupt Wake-up Function...................................................................................................112 Programming Considerations................................................................................................112 Application Circuits.......................................................................................113 Instruction Set................................................................................................114 Introduction...........................................................................................................................114 Instruction Timing..................................................................................................................114 Moving and Transferring Data...............................................................................................114 Arithmetic Operations............................................................................................................114 Logical and Rotate Operation...............................................................................................115 Branches and Control Transfer.............................................................................................115 Bit Operations.......................................................................................................................115 Table Read Operations.........................................................................................................115 Other Operations...................................................................................................................115 Instruction Set Summary..............................................................................116 Table Conventions.................................................................................................................116 Instruction Definition.....................................................................................118 Package Information.................................................................................... 127 16-pin NSOP (150mil) Outline Dimensions.......................................................................... 128 16-pin SSOP (150mil) Outline Dimensions.......................................................................... 129 20-pin SOP (300mil) Outline Dimensions............................................................................ 130 20-pin NSOP (150mil) Outline Dimensions.......................................................................... 131 20-pin SSOP (150mil) Outline Dimensions.......................................................................... 132 24-pin SOP (236mil) Outline Dimensions............................................................................ 133 24-pin SSOP (150mil) Outline Dimensions.......................................................................... 134 Rev. 1.00 5 October 27, 2017 BS84B08C Touch A/D Flash MCU Features CPU Features • Operating voltage ♦♦ fSYS=8MHz: 2.2V~5.5V ♦♦ fSYS=12MHz: 2.7V~5.5V ♦♦ fSYS=16MHz: 3.3V~5.5V • Up to 0.25μs instruction cycle with 16MHz system clock at VDD=5V • Power down and wake-up functions to reduce power consumption • Oscillator types: ♦♦ Internal High Speed RC – HIRC ♦♦ Internal Low Speed 32kHz RC – LIRC • Multi-mode operation: FAST, SLOW, IDLE and SLEEP • Fully integrated internal oscillators require no external components • All instructions executed in one or two instruction cycles • Table read instructions • 63 powerful instructions • 6-level subroutine nesting • Bit manipulation instruction Peripheral Features • Flash Program Memory: 3K×16 • Data Memory: 288×8 • True EEPROM Memory: 64×8 • Watchdog Timer function • 22 bidirectional I/O lines Programmable • I/O port source current for LED applications • Single external interrupt line shared with I/O pin • Single 10-bit PTM for time measurement, capture input, compare match output or PWM output or single pulse output function • Single Time-Base function for generation of fixed time interrupt signals • Multi-channel 12-bit resolution A/D converter • Serial Interface Module includes SPI and I2C interfaces • Low voltage reset function • 8 Touch Key functions • Package types: 16-pin NSOP/SSOP, 20-pin SOP/NSOP/SSOP, 24-pin SOP/SSOP Rev. 1.00 6 October 27, 2017 BS84B08C Touch A/D Flash MCU General Description The device is a Flash Memory type 8-bit high performance RISC architecture microcontroller with fully integrated Touch Key functions. With the Touch Key function provided internally and including a fully functional microcontroller as well as the convenience of Flash Memory multiprogramming features, this device has all the features to offer designers a reliable and easy means of implementing Touch Keys within their product applications. Analog features include a multi-channel 12-bit A/D converter. Protective features such as an internal Watchdog Timer and Low Voltage Reset functions coupled with excellent noise immunity and ESD protection ensure that reliable operation is maintained in hostile electrical environments. The Touch Key function is completely integrated eliminating the need for external components. In addition to the flash program memory, other memory includes an area of RAM Data Memory as well as an area of true EEPROM memory for storage of non-volatile data such as serial numbers, calibration data etc. The device includes fully integrated low and high speed oscillators which require no external components for their implementation. The ability to operate and switch dynamically between a range of operating modes using different clock sources gives users the ability to optimise microcontroller operation and minimise power consumption. Easy communication with the outside world is provided using the internal I2C and SPI interfaces, while the inclusion of flexible I/O programming features, Timer Module and many other features further enhance device functionality and flexibility. This Touch Key device will find excellent use in a huge range of modern Touch Key product applications such as instrumentation, household appliances, electronically controlled tools to name but a few. Block Diagram Interrupt Controller INT Pin-Shared With Port A ROM 3K × 16 RAM 288 × 8 SIM EEPR�M 64 × 8 Stack 6-level Timer Watchdog Timer LVR HT8 MCU Core HIRC 8/12/16MHz AN0~AN� VDD VDD VSS VSS : Bus Ent�y Rev. 1.00 Pin-Sha�ed With Po�t D : Pin-Sha�ed Node VBG Touch Key Module 0 Key �SC Analog Filte� 16-�it C/F Counte� MUX PB0~PB7 Touch Key Module 1 MUX VDD Pin-Sha�ed With Po�t D Port B Driver Digital Peripherals Clock System VREF PA0~PA4,PA7 Bus LIRC 32kHz Port A Driver I/O SYSCLK Time Base Pin-Remapping Fun�tion 1�-�it ADC Multif�equen�y Time slot �ounte� Analog To Digital Conve�te� Analog Pe�iphe�als MUX Reset Circuit KEY1~KEY8 Key �SC Key �SC Key �SC Pin-Shared With Port B Tou�h Key Fun�tion : SIM in�luding SPI & I�C 7 October 27, 2017 BS84B08C Touch A/D Flash MCU Pin Assignment PB0/KEY1 1 16 PB1/KEY� PB�/KEY3 � 15 3 14 PB3/KEY4 PB4/KEY5 PB5/KEY6 4 13 5 1� PA0/SDI/SDA/ICPDA/�CDSDA PA1/PTP/SD� PA�/SCK/SCL/ICPCK/�CDSCK PA3/PTCK/SCS PA4/PTPI/[SDI/SDA]/INT 6 11 PA�/PTPB/[SCK/SCL] VSS � 10 PD1/AN1 VDD 8 9 PD0/AN0/VREF BS84B08C/BS84BV08C 16 NSOP-A/SSOP-A PB0/KEY1 1 20 PA0/SDI/SDA/ICPDA/OCDSDA PB1/KEY2 PB2/KEY3 2 19 3 18 PA1/PTP/SDO PA2/SCK/SCL/ICPCK/OCDSCK PB3/KEY4 4 17 PB4/KEY5 5 16 PA3/PTCK/SCS PA4/PTPI/[SDI/SDA]/INT PB5/KEY6 6 15 PA7/PTPB/[SCK/SCL] PB6/KEY7 PB7/KEY8 VSS 7 14 PD7/AN7 8 13 PD6/AN6 9 12 PD1/AN1 10 11 PD0/AN0/VREF VDD BS84B08C/BS84BV08C 20 SOP-A/NSOP-A/SSOP-A PB0/KEY1 1 �4 PA0/SDI/SDA/ICPDA/�CDSDA PB1/KEY� PB�/KEY3 � �3 PA1/PTP/SD� 3 �� PB3/KEY4 4 �1 PA�/SCK/SCL/ICPCK/�CDSCK PA3/PTCK/SCS PB4/KEY5 5 �0 PB5/KEY6 6 19 PB6/KEY� PB�/KEY8 � 18 8 1� PD�/AN� PD6/AN6 VSS PA4/PTPI/[SDI/SDA]/INT PA�/PTPB/[SCK/SCL] 9 16 PD5/AN5 VDD PD0/AN0/VREF 10 15 11 14 PD1/AN1 1� 13 PD4/AN4 PD3/AN3 PD�/AN� BS84B08C/BS84BV08C 24 SOP-A/SSOP-A Notes: 1. Bracketed pin names indicate non-default pinout remapping locations. The detailed information can be referenced to the relevant chapter. 2. If the pin-shared pin functions have multiple outputs simultaneously, its pin names at the right side of the "/" sign can be used for higher priority. 3. The OCDSDA and OCDSCK pins are supplied for the OCDS dedicated pins and as such only available for the BS84BV08C device which is the OCDS EV chip for the BS84B08C device. 4. For less pin-count package types there will be unbonded pins which should be properly configured to avoid unwanted current consumption resulting from floating input conditions. Refer to the "Standby Current Considerations" and "Input/Output Ports" sections. Rev. 1.00 8 October 27, 2017 BS84B08C Touch A/D Flash MCU Pin Description With the exception of the power pins and some relevant transformer control pins, all pins on the device can be referenced by their Port name, e.g. PA0, PA1 etc., which refer to the digital I/O function of the pins. However these Port pins are also shared with other function such as the Touch Key function and Timer Module pins etc. The function of each pin is listed in the following tables, however the details behind how each pin is configured is contained in other sections of the datasheet. As the Pin Description table shows the situation for the package with the most pins, not all pins in the table will be available on smaller package sizes. Pin Name PA0/SDI/SDA/ ICPDA/OCDSDA PA1/PTP/SDO PA2/SCK/SCL/ ICPCK/ OCDSCK PA3/PTCK/SCS PA4/PTPI/ [SDI/SDA]/INT PA7/PTPB/ [SCK/SCL] Rev. 1.00 Function OPT PA0 PAWU PAPU I/T O/T Description ST CMOS SDI SIMC0 PXRM ST — SDA SIMC0 PXRM ST NMOS I2C data line ICPDA — ST CMOS In-circuit programming address/data pin OCDSDA — ST CMOS OCDS data/address pin, for EV chip only PA1 PAWU PAPU ST CMOS General purpose I/O. Register enabled pull-up and wake-up PTP PTMC0 PTMC1 PXRM — CMOS PTM output SDO SIMC0 — CMOS SPI serial data output PA2 PAWU PAPU ST CMOS General purpose I/O. Register enabled pull-up and wake-up SCK SIMC0 PXRM ST CMOS SPI serial clock SCL SIMC0 PXRM ST NMOS I2C clock line General purpose I/O. Register enabled pull-up and wake-up SPI serial data input ICPCK — ST — In-circuit programming clock pin OCDSCK — ST — OCDS clock pin, for EV chip only PA3 PAWU PAPU ST CMOS PTCK PTMC0 ST — SCS SIMC0 ST CMOS SPI slave select pin PA4 PAWU PAPU ST CMOS General purpose I/O. Register enabled pull-up and wake-up PTPI PTMC0 PTMC1 ST — PTM capture input SDI SIMC0 PXRM ST — SPI serial data input SDA SIMC0 PXRM ST NMOS INT INTC0 INTEG ST — PA7 PAWU PAPU ST CMOS General purpose I/O. Register enabled pull-up and wake-up PTPB PXRM – CMOS PTM inverted output SCK SIMC0 PXRM ST CMOS SPI serial clock SCL SIMC0 PXRM ST NMOS I2C clock line 9 General purpose I/O. Register enabled pull-up and wake-up PTM clock input I2C data line External interrupt input October 27, 2017 BS84B08C Touch A/D Flash MCU Pin Name PB0/KEY1~ PB3/KEY4 PB4/KEY5~ PB7/KEY8 PD0/AN0/VREF Function OPT I/T O/T PB0~PB3 PBPU ST CMOS Description KEY1~KEY4 TKM0C1 NSI — PB4~PB7 PBPU ST CMOS KEY5~KEY8 TKM1C1 NSI — PD0 PDPU ST CMOS AN0 ACERL AN — A/D Converter external input channel General purpose I/O. Register enabled pull-up Touch Key inputs General purpose I/O. Register enabled pull-up Touch Key inputs General purpose I/O. Register enabled pull-up VREF ADCR1 AN — A/D Converter external reference voltage input PD1~PD7 PDPU ST CMOS General purpose I/O. Register enabled pull-up AN1~AN7 ACERL AN — A/D Converter external input channel VDD VDD — PWR — Positive power supply VSS VSS — PWR — Negative power supply, ground PD1/AN1~ PD7/AN7 Legend: I/T: Input type; OPT: Optional by register option; ST: Schmitt Trigger input; NMOS: NMOS output; NSI: Non Standard input. O/T: Output type; PWR: Power; CMOS: CMOS output; AN: Analog signal; Absolute Maximum Ratings Supply Voltage..................................................................................................VSS-0.3V to VSS+6.0V Input Voltage....................................................................................................VSS-0.3V to VDD+0.3V Storage Temperature.....................................................................................................-50˚C to 125˚C Operating Temperature...................................................................................................-40˚C to 85˚C IOL Total...................................................................................................................................... 80mA IOH Total.....................................................................................................................................-80mA Total Power Dissipation.......................................................................................................... 500mW Note: These are stress ratings only. Stresses exceeding the range specified under "Absolute Maximum Ratings" may cause substantial damage to the device. Functional operation of the devices at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. D.C. Characteristics For data in the following tables, note that factors such as oscillator type, operating voltage, operating frequency, pin load conditions, temperature and program instruction type, etc., can all exert an influence on the measured values. Operating Voltage Characteristics Ta = -40˚C~85˚C Symbol VDD Parameter Operating Voltage – HIRC Operating Voltage – LIRC Rev. 1.00 Test Conditions Min. Typ. Max. fSYS=8MHz 2.2 — 5.5 fSYS=12MHz 2.7 — 5.5 fSYS=16MHz 3.3 — 5.5 fSYS=32kHz 2.2 — 5.5 10 Unit V October 27, 2017 BS84B08C Touch A/D Flash MCU Standby Current Characteristics Ta = 25˚C Symbol Test Conditions Standby Mode VDD Conditions 2.2V 1.2 2.4 2.9 — 1.5 3 3.6 — 3 5 6 — 2.4 4 4.8 — 3 5 6 5V — 5 10 12 2.2V — 288 400 480 WDT on 5V 2.2V IDLE0 Mode – LIRC 3V 3V IDLE1 Mode – HIRC Max. Unit @85˚C — 3V SLEEP Mode ISTB Min. Typ. Max. fSUB on μA — 360 500 600 5V — 600 800 960 2.7V — 432 600 720 — 540 750 900 — 800 1200 1440 — 1.1 1.6 1.9 — 1.4 2.0 2.4 3V fSUB on, fSYS=8MHz fSUB on, fSYS=12MHz 5V 3.3V 5V fSUB on, fSYS=16MHz μA μA mA Notes: When using the characteristic table data, the following notes should be taken into consideration: 1. Any digital inputs are setup in a non-floating condition. 2. All measurements are taken under conditions of no load and with all peripherals in an off state. 3. There are no DC current paths. 4. All Standby Current values are taken after a HALT instruction execution thus stopping all instruction execution. Operating Current Characteristics Ta = 25˚C Symbol Operating Mode Test Conditions Typ. Max. — 8 16 — 10 20 — 30 50 — 0.6 1.0 — 0.8 1.2 — 1.6 2.4 — 1.0 1.4 — 1.2 1.8 5V — 2.4 3.6 3.3V — 3.0 4.5 — 4.0 6.0 VDD Conditions 2.2V SLOW Mode – LIRC 3V fSYS=32kHz 5V 2.2V 3V IDD fSYS=8MHz 5V FAST Mode – HIRC 2.7V 3V 5V fSYS=12MHz fSYS=16MHz Min. Unit μA mA Notes: When using the characteristic table data, the following notes should be taken into consideration: 1. Any digital inputs are setup in a non-floating condition. 2. All measurements are taken under conditions of no load and with all peripherals in an off state. 3. There are no DC current paths. 4. All Operating Current values are measured using a continuous NOP instruction program loop. Rev. 1.00 11 October 27, 2017 BS84B08C Touch A/D Flash MCU A.C. Characteristics For data in the following tables, note that factors such as oscillator type, operating voltage, operating frequency and temperature etc., can all exert an influence on the measured values. High Speed Internal Oscillator – HIRC – Frequency Accuracy During the program writing operation the writer will trim the HIRC oscillator at a user selected HIRC frequency and user selected voltage of 3V or 5V. 8/12/16MHz Symbol Parameter 8MHz Writer Trimmed HIRC Frequency 12MHz Writer Trimmed HIRC Frequency fHIRC 16MHz Writer Trimmed HIRC Frequency Test Conditions Min. Typ. Max. 25°C -1% 8 +1% -40°C ~ 85°C -2% 8 +2% -2.5% 8 +2.5% VDD Temp. 3V/5V 2.2V~5.5V 3V/5V 2.7V~5.5V 5V 3.3V~5.5V 25°C -40°C ~ 85°C -3% 8 +3% 25°C -1% 12 +1% -40°C ~ 85°C -2% 12 +2% -2.5% 12 +2.5% -40°C ~ 85°C -3% 12 +3% 25°C -1% 16 +1% -40°C ~ 85°C -2% 16 +2% -2.5% 16 +2.5% -3% 16 +3% 25°C 25°C -40°C ~ 85°C Unit MHz MHz MHz Notes: 1. The 3V/5V values for VDD are provided as these are the two selectable fixed voltages at which the HIRC frequency is trimmed by the writer. 2. The row below the 3V/5V trim voltage row is provided to show the values for the full VDD range operating voltage. It is recommended that the trim voltage is fixed at 3V for application voltage ranges from 2.2V to 3.6V and fixed at 5V for application voltage ranges from 3.3V to 5.5V. 3. The minimum and maximum tolerance values provided in the table are only for the frequency at which the writer trims the HIRC oscillator. After trimming at this chosen specific frequency any change in HIRC oscillator frequency using the oscillator register control bits by the application program will give a frequency tolerance to within ±20%. Low Speed Internal Oscillator Characteristics – LIRC Ta = 25˚C, unless otherwise specified Symbol Parameter fLIRC LIRC Frequency tSTART LIRC Start Up Time Rev. 1.00 Test Conditions Min. Typ. Max. 25˚C -10% 32 +10% -40˚C~85˚C -50% 32 +60% — — 500 VDD 2.2V~5.5V Temp. — — 12 Unit kHz μs October 27, 2017 BS84B08C Touch A/D Flash MCU Operating Frequency Characteristic Curves System Operating Frequency 16MHz 1�MHz ~ ~ ~ ~ 8MHz �.�V �.�V 5.5V 3.3V Operating Voltage System Start Up Time Characteristics Ta = 25˚C Symbol tSST tRSTD tSRESET Parameter Test Conditions Min. Typ. Max. Unit VDD Conditions System Start-up Time Wake-up from condition where fSYS is off — fSYS=fH~fH/64, fH=fHIRC — 16 — tHIRC — fSYS=fSUB=fLIRC — 2 — tLIRC System Start-up Time Wake-up from condition where fSYS is on — fSYS=fH~fH/64, fH=fHIRC — 2 — tH — fSYS=fSUB=fLIRC — 2 — tSUB System Speed Switch Time FAST to SLOW Mode or SLOW to FAST Mode — fHIRC switches from off → on — 16 — tHIRC System Reset Delay Time Reset source from Power-on reset or LVR hardware reset — RRPOR=5V/ms 42 48 54 ms System Reset Delay Time LVRC/WDTC software reset — — System Reset Delay Time Reset source from WDT overflow — — 14 16 18 ms Minimum Software Reset Width to Reset — — 45 90 120 μs Notes: 1. For the System Start-up time values, whether fSYS is on or off depends upon the mode type and the chosen fSYS system oscillator. Details are provided in the System Operating Modes section. 2. The time units, shown by the symbols tHIRC, tSYS etc. are the inverse of the corresponding frequency values as provided in the frequency tables. For example tHIRC=1/fHIRC, tSYS=1/fSYS etc. 3. If the LIRC is used as the system clock and if it is off when in the SLEEP Mode, then an additional LIRC start up time, tSTART, as provided in the LIRC frequency table, must be added to the tSST time in the table above. 4. The System Speed Switch Time is effectively the time taken for the newly activated oscillator to start up. Rev. 1.00 13 October 27, 2017 BS84B08C Touch A/D Flash MCU A/D Converter Electrical Characteristics Ta = -40˚C~85˚C, unless otherwise specify Symbol Test Conditions Parameter VDD Conditions Min. Typ. Max. Unit VDD A/D Converter Operating Voltage — — 2.2 — 5.5 V VADI A/D Converter Input Voltage — — 0 — VREF V VREF A/D Converter Reference Voltage — — 2 — VDD V -3 — +3 LSB -4 — +4 LSB — 1 2 mA — 1 2 mA — 1.5 3.0 mA μs 2.2V DNL 5V Differential Non-linearity 3V VREF=VDD, tADCK=10μs 5V 2.2V INL 5V Integral Non-linearity 3V VREF=VDD, tADCK=0.5μs VREF=VDD, tADCK=10μs 5V IADC VREF=VDD, tADCK=0.5μs 2.2V Additional Current Consumption for A/D Converter Enable 3V No load, tADCK=0.5μs 5V tADCK A/D Converter Clock Period — — 0.5 — 10 tON2ST A/D Converter On-to-Start Time — — 4 — — μs tADS A/D Converter Sampling Time — — — 4 — tADCK tADC A/D Converter Conversion Time (Including A/D Sample and Hold Time) — — — 16 — tADCK Input/Output Characteristics Ta = 25˚C Symbol Parameter Test Conditions VDD VIL Input Low Voltage for I/O Ports or Input Pins 5V VIH Input High Voltage for I/O Ports or Input Pins 5V IOL Sink Current for I/O Pins 3V 5V 3V 5V 3V 5V 3V 5V RPH Pull-high Resistance for I/O Ports (Note) 3V ILEAK Input Leakage Current 5V Rev. 1.00 Min. Typ. Max. 0 — 1.5 0 — 0.2VDD 3.5 — 5.0 0.8VDD — VDD 16 32 — 32 65 — VOH=0.9VDD SLEDCn[m+1, m]=00B (n=0,1, m=0, 2, 4, 6) -0.7 -1.5 — -1.5 -2.9 — VOH = 0.9VDD, SLEDCn[m+1, m]=01B (n=0,1, m=0, 2, 4, 6) -1.3 -2.5 — -2.5 -5.1 — VOH = 0.9VDD, SLEDCn[m+1, m]=10B (n=0,1, m=0, 2, 4, 6) -1.8 -3.6 — -3.6 -7.3 — VOH = 0.9VDD, SLEDCn[m+1, m]=11B (n=0,1, m=0, 2, 4, 6) -4 -8 — -8 -16 — 20 60 100 10 30 50 — — ±1 — — 5V Port Source Current for I/O Pins — — 3V IOH Conditions VOL=0.1VDD — 5V VIN=VDD or VIN=VSS 14 Unit V V mA mA kΩ μA October 27, 2017 BS84B08C Touch A/D Flash MCU Symbol Parameter Test Conditions VDD Conditions Min. Typ. Max. Unit tTCK TM TCK Input Pin Minimum Pulse Width — — 0.3 — — μs tTPI TM TPI Input Pin Minimum Pulse Width — — 0.3 — — μs Note: The RPH internal pull high resistance value is calculated by connecting to ground and enabling the input pin with a pull-high resistor and then measuring the input sink current at the specified supply voltage level. Dividing the voltage by this measured current provides the RPH value. Memory Characteristics Ta = -40˚C~85˚C Symbol Test Conditions Min. Typ. Max. Unit — VDDmin — VDDmax V — — — 2 3 ms Write Cycle Time – Data EEPROM Memory — — — 4 6 ms IDDPGM Programming/Erase Current on VDD — — — — 5.0 mA EP Cell Endurance — — 100K — — E/W tRETD ROM Data Retention Time — Ta=25˚C — 40 — Year — Device in SLEEP Mode 1.0 — — V VRW Parameter VDD Conditions — Erase/Write Cycle Time – Flash Program Memory VDD for Read / Write Flash Program Memory/Data EEPROM Memory tDEW RAM Data Memory VDR RAM Data Retention Voltage LVR Electrical Characteristics Ta = 25˚C Symbol VLVR Parameter Low Voltage Reset Voltage ILVR Additional Current for LVR Enable tLVR Minimum Low Voltage Width to Reset Rev. 1.00 Test Conditions VDD Conditions Min. Typ. Max. Unit — LVR enable, voltage select 2.1V 2.1 — LVR enable, voltage select 2.55V 2.55 — LVR enable, voltage select 3.15V — LVR enable, voltage select 3.8V 3V 5V LVR disable → LVR enable — — 15 -5% 3.15 +5% V 3.8 — 15 25 — 20 30 120 240 480 μA μs October 27, 2017 BS84B08C Touch A/D Flash MCU Power-on Reset Characteristics Ta=25˚C Symbol Test Conditions Parameter VDD Conditions Min. Typ. Max. Unit VPOR VDD Start Voltage to Ensure Power-on Reset — — — — 100 mV RRPOR VDD Rising Rate to Ensure Power-on Reset — — 0.035 — — V/ms tPOR Minimum Time for VDD Stays at VPOR to Ensure Power-on Reset — — 1 — — ms VDD tP�R RRP�R VP�R Time System Architecture A key factor in the high-performance features of the Holtek range of microcontrollers is attributed to their internal system architecture. The range of the device take advantage of the usual features found within RISC microcontrollers providing increased speed of operation and enhanced performance. The pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. An 8-bit wide ALU is used in practically all instruction set operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the Accumulator and the ALU. Certain internal registers are implemented in the Data Memory and can be directly or indirectly addressed. The simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional I/O and A/D control system with maximum reliability and flexibility. This makes the device suitable for low-cost, high-volume production for controller applications. Clocking and Pipelining The main system clock, derived from either a HIRC or LIRC oscillator is subdivided into four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms one instruction cycle. Although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. The exception to this are instructions where the contents of the Program Counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. For instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. An extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. The requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. Rev. 1.00 16 October 27, 2017 BS84B08C Touch A/D Flash MCU fSYS (System Clo�k) Phase Clo�k T1 Phase Clo�k T� Phase Clo�k T3 Phase Clo�k T4 P�og�am Counte� Pipelining PC PC+1 PC+� Fet�h Inst. (PC) Exe�ute Inst. (PC-1) Fet�h Inst. (PC+1) Exe�ute Inst. (PC) Fet�h Inst. (PC+�) Exe�ute Inst. (PC+1) System Clocking and Pipelining 1 � 3 4 5 6 DELAY: M�V A� [1�H] CALL DELAY CPL [1�H] : : N�P Fet�h Inst. 1 Exe�ute Inst. 1 Fet�h Inst. � Exe�ute Inst. � Fet�h Inst. 3 Flush Pipeline Fet�h Inst. 6 Exe�ute Inst. 6 Fet�h Inst. � Instruction Fetching Program Counter During program execution, the Program Counter is used to keep track of the address of the next instruction to be executed. It is automatically incremented by one each time an instruction is executed except for instructions, such as "JMP" or "CALL" that demand a jump to a nonconsecutive Program Memory address. Only the lower 8 bits, known as the Program Counter Low Register, are directly addressable by the application program. When executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the Program Counter. For conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. Program Counter High Byte Low Byte (PCL) PC11~PC8 PCL7~PCL0 Program Counter The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is available for program control and is a readable and writeable register. By transferring data directly into this register, a short program jump can be executed directly; however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory that is 256 locations. When such program jumps are executed it should also be noted that a dummy cycle will be inserted. Manipulating the PCL register may cause program branching, so an extra cycle is needed to pre-fetch. Rev. 1.00 17 October 27, 2017 BS84B08C Touch A/D Flash MCU Stack This is a special part of the memory which is used to save the contents of the Program Counter only. The stack has six levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the Stack Pointer, and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value from the stack. After a device reset, the Stack Pointer will point to the top of the stack. If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack overflow. Precautions should be taken to avoid such cases which might cause unpredictable program branching. If the stack is overflow, the first Program Counter save in the stack will be lost. P�og�am Counte� Top of Sta�k Sta�k Pointe� Bottom of Sta�k Sta�k Level 1 Sta�k Level � Sta�k Level 3 : : : P�og�am Memo�y Sta�k Level 6 Arithmetic and Logic Unit – ALU The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. Connected to the main microcontroller data bus, the ALU receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. As these ALU calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to reflect these changes. The ALU supports the following functions: • Arithmetic operations: ADD, ADDM, ADC, ADCM, SUB, SUBM, SBC, SBCM, DAA • Logic operations: AND, OR, XOR, ANDM, ORM, XORM, CPL, CPLA • Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA, RLC • Increment and Decrement INCA, INC, DECA, DEC • Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA, SDZA, CALL, RET, RETI Rev. 1.00 18 October 27, 2017 BS84B08C Touch A/D Flash MCU Flash Program Memory The Program Memory is the location where the user code or program is stored. For the device the Program Memory is Flash type, which means it can be programmed and re-programmed a large number of times, allowing the user the convenience of code modification on the same device. By using the appropriate programming tools, the Flash devices offer users the flexibility to conveniently debug and develop their applications while also offering a means of field programming and updating. Structure The Program Memory has a capacity of 3K×16 bits. The Program Memory is addressed by the Program Counter and also contains data, table information and interrupt entries. Table data, which can be setup in any location within the Program Memory, is addressed by a separate table pointer register. 000H Initialisation Ve�to� 004H Inte��upt Ve�to� 01CH BFFH 16 �its Program Memory Structure Special Vectors Within the Program Memory, certain locations are reserved for the reset and interrupts. The location 000H is reserved for use by the device reset for program initialisation. After a device reset is initiated, the program will jump to this location and begin execution. Look-up Table Any location within the Program Memory can be defined as a look-up table where programmers can store fixed data. To use the look-up table, the table pointer must first be setup by placing the address of the look up data to be retrieved in the table pointer register, TBLP and TBHP. These registers define the total address of the look-up table. After setting up the table pointer, the table data can be retrieved from the Program Memory using the "TABRD [m]" or "TABRDL [m]" instructions, respectively. When the instruction is executed, the lower order table byte from the Program Memory will be transferred to the user defined Data Memory register [m] as specified in the instruction. The higher order table data byte from the Program Memory will be transferred to the TBLH special register. Any unused bits in this transferred higher order byte will be read as "0". The accompanying diagram illustrates the addressing data flow of the look-up table. Rev. 1.00 19 October 27, 2017 BS84B08C Touch A/D Flash MCU P�og�am Memo�y Add�ess Last page o� TBHP Registe� TBLP Registe� TBLH Registe� Data High Byte Data 16 �its Use� Sele�ted Registe� Data Low Byte Table Program Example The following example shows how the table pointer and table data is defined and retrieved from the microcontroller. This example uses raw table data located in the Program Memory which is stored there using the ORG statement. The value at this ORG statement is "0B00H" which refers to the start address of the last page within the 3K Program Memory of the device. The table pointer is setup here to have an initial value of "06H". This will ensure that the first data read from the data table will be at the Program Memory address "0B06H" or 6 locations after the start of the last page. Note that the value for the table pointer is referenced to first address specified by TBLP and TBHP if the "TABRD [m]" instruction is being used. The high byte of the table data which in this case is equal to zero will be transferred to the TBLH register automatically when the "TABRD [m]" instruction is executed. Because the TBLH register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and Interrupt Service Routine use table read instructions. If using the table read instructions, the Interrupt Service Routines may change the value of the TBLH and subsequently cause errors if used again by the main routine. As a rule it is recommended that simultaneous use of the table read instructions should be avoided. However, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. Note that all table related instructions require two instruction cycles to complete their operation. Table Read Program Example tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a,06h ; initialise low table pointer – note that this address is referenced mov tblp,a ; to the last page or the page that tbhp pointed mov a,0Bh ; initialise high table pointer mov tbhp,a : : tabrd tempreg1 ; transfers value in table referenced by table pointer data at program ; memory address "0B06H" transferred to tempreg1 and TBLH dec tblp ; reduce value of table pointer by one tabrd tempreg2 ; transfers value in table referenced by table pointer ; data at program memory address "0B05H" transferred to ; tempreg2 and TBLH in this example the data "1AH" is ; transferred to tempreg1 and data "0FH" to register tempreg2 : : org 0B00h ; sets initial address of program memory dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh : : Rev. 1.00 20 October 27, 2017 BS84B08C Touch A/D Flash MCU In Circuit Programming – ICP The provision of Flash type Program Memory provides the user with a means of convenient and easy upgrades and modifications to their programs on the same device. As an additional convenience, Holtek has provided a means of programming the microcontroller in-circuit using a 4-pin interface. This provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller, and then programming or upgrading the program at a later stage. This enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re-insertion of the device. The Holtek Flash MCU to Writer Programming Pin correspondence table is as follows: Holtek Write Pins MCU Programming Pins ICPDA PA0 Serial data/address input/output Function ICPCK PA2 Serial Clock input VDD VDD Power Supply VSS VSS Ground The Program Memory and EEPROM data memory can both be programmed serially in-circuit using this 4-wire interface. Data is downloaded and uploaded serially on a single pin with an additional line for the clock. Two additional lines are required for the power supply. The technical details regarding the in-circuit programming of the device are beyond the scope of this document and will be supplied in supplementary literature. During the programming process the ICPDA and ICPCK pins for data and clock programming purposes. The user must there take care to ensure that no other outputs are connected to these two pins. W�ite� Conne�to� Signals MCU P�og�amming Pins W�ite�_VDD VDD ICPDA PA0 ICPCK PA� W�ite�_VSS VSS * * To othe� Ci��uit Note: * may be resistor or capacitor. The resistance of * must be greater than 1kΩ or the capacitance of * must be less than 1nF. Rev. 1.00 21 October 27, 2017 BS84B08C Touch A/D Flash MCU On-Chip Debug Support – OCDS There is an EV chip named BS84BV08C which is used to emulate the BS84B08C device. The EV chip device also provides an "On-Chip Debug" function to debug the real MCU device during the development process. The EV chip and the real MCU device are almost functionally compatible except for "On-Chip Debug" function. Users can use the EV chip device to emulate the real chip device behavior by connecting the OCDSDA and OCDSCK pins to the Holtek HT-IDE development tools. The OCDSDA pin is the OCDS Data/Address input/output pin while the OCDSCK pin is the OCDS clock input pin. When users use the EV chip for debugging, other functions which are shared with the OCDSDA and OCDSCK pins in the real MCU device will have no effect in the EV chip. However, the two OCDS pins which are pin-shared with the ICP programming pins are still used as the Flash Memory programming pins for ICP. For more detailed OCDS information, refer to the corresponding document named "Holtek e-Link for 8-bit MCU OCDS User’s Guide". Rev. 1.00 Holtek e-Link Pins EV Chip Pins OCDSDA OCDSDA On-Chip Debug Support Data/Address input/output Pin Description OCDSCK OCDSCK On-Chip Debug Support Clock input VDD VDD Power Supply VSS VSS Ground 22 October 27, 2017 BS84B08C Touch A/D Flash MCU Data Memory The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where temporary information is stored. Structure Divided into two areas, the first of these is an area of RAM, known as the Special Function Data Memory. Here are located registers which are necessary for correct operation of the device. Many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. The second area of Data Memory is known as the General Purpose Data Memory, which is reserved for general purpose use. All locations within this area are read and write accessible under program control. The overall Data Memory is subdivided into two banks. The Special Purpose Data Memory registers are accessible in all banks, with the exception of the EEC register at address 40H, which is only accessible in Bank 1. Switching between the different Data Memory banks is achieved by setting the Bank Pointer to the correct value. The start address of the Data Memory for the device is the address 00H. Special Purpose Data Memory General Purpose Data Memory Located Banks Bank: Address Capacity Bank: Address 0,1 0: 00H~5FH 1: 00H~7FH 288×8 0: 60H~FFH 1: 80H~FFH Data Memory Summary 00H Spe�ial Pu�pose Data Memo�y (Bank 0: 00H~5FH Bank 1: 00H~�FH) EEC at 40H in Bank 1 only 5FH 60H �FH 80H Gene�al Pu�pose Data Memo�y (Bank 0: 60H~FFH Bank 1: 80H~FFH) Bank 0 Bank 1 FFH Data Memory Structure General Purpose Data Memory All microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later. It is this area of RAM memory that is known as General Purpose Data Memory. This area of Data Memory is fully accessible by the user programing for both reading and writing operations. By using the bit operation instructions individual bits can be set or reset under program control giving the user a large range of flexibility for bit manipulation in the Data Memory. Rev. 1.00 23 October 27, 2017 BS84B08C Touch A/D Flash MCU Special Purpose Data Memory This area of Data Memory is where registers, necessary for the correct operation of the microcontroller, are stored. Most of the registers are both readable and writeable but some are protected and are readable only, the details of which are located under the relevant Special Function Register section. Note that for locations that are unused, any read instruction to these addresses will return the value "00H". Bank 1 IAR0 MP0 IAR1 MP1 BP ACC PCL TBLP TBLH TBHP STATUS SM�D CTRL INTEG INTC0 INTC1 Bank 0 Bank 0 00H 01H 0�H 03H 04H 05H 06H 0�H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 1�H 13H 14H 15H 16H 1�H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH �0H �1H ��H �3H �4H �5H �6H ��H �8H �9H �AH �BH �CH �DH �EH �FH MFI LVRC PA PAC PAPU PAWU PXRM WDTC TBC PSCR EEA EED PB PBC PBPU SIMT�C SIMC0 SIMC1 SIMD SIMC�/SIMA ADRL ADRH 30H 31H 3�H 33H 34H 35H 36H 3�H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 4�H 43H 44H 45H 46H 4�H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH 50H 51H 5�H 53H 54H 55H 56H 5�H 58H 59H 5AH 5BH 5CH 5DH 5EH 5FH Bank 1 ADCR0 ADCR1 ACERL SLEDC0 SLEDC1 PD PDC PDPU PTMC0 PTMC1 PTMDL PTMDH PTMAL PTMAH EEC PTMRPL PTMRPH TKTMR TKC0 TK16DL TK16DH TKC1 TKM016DL TKM016DH TKM0R�L TKM0R�H TKM0C0 TKM0C1 TKM116DL TKM116DH TKM1R�L TKM1R�H TKM1C0 TKM1C1 : Unused� �ead as 00H. Note: The address range of the Special Purpose Data Memory for the device Bank 1 is from 00H to 7FH, the address range of 60H~7FH are unused, read as 00H. Special Purpose Data Memory Structure Rev. 1.00 24 October 27, 2017 BS84B08C Touch A/D Flash MCU Special Function Register Description Most of the Special Function Register details will be described in the relevant functional sections, however several registers require a separate description in this section. Indirect Addressing Register – IAR0, IAR1 The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal RAM register space, do not actually physically exist as normal registers. The method of indirect addressing for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the IAR0 and IAR1 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corresponding Memory Pointers, MP0 or MP1. Acting as a pair, IAR0 and MP0 can together access data from Bank 0 while the IAR1 and MP1 register pair can access data from any bank. As the Indirect Addressing Registers are not physically implemented, reading the Indirect Addressing Registers indirectly will return a result of "00H" and writing to the registers indirectly will result in no operation. Memory Pointers – MP0, MP1 Two Memory Pointers, known as MP0 and MP1 are provided. These Memory Pointers are physically implemented in the Data Memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. When any operation to the relevant Indirect Addressing Registers is carried out, the actual address that the microcontroller is directed to, is the address specified by the related Memory Pointer. MP0, together with Indirect Addressing Register, IAR0, are used to access data from Bank 0, while MP1 and IAR1 are used to access data from all banks according to BP register. Direct Addressing can only be used with Bank 0, all other Banks must be addressed indirectly using MP1 and IAR1. The following example shows how to clear a section of four Data Memory locations already defined as locations adres1 to adres4. Indirect Addressing Program Example data .section ´data´ adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 ´code´ org 00h start: mov a,04h ; setup size of block mov block,a mov a,offset adres1 ; Accumulator loaded with first RAM address mov mp0,a ; setup memory pointer with first RAM address loop: clr IAR0 ; clear the data at address defined by mp0 inc mp0; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue: The important point to note here is that in the example shown above, no reference is made to specific Data Memory addresses. Rev. 1.00 25 October 27, 2017 BS84B08C Touch A/D Flash MCU Bank Pointer – BP For this device, the Data Memory is divided into two banks, Bank 0 and Bank 1. Selecting the required Data Memory area is achieved using the Bank Pointer. Bit 0 of the Bank Pointer is used to select Data Memory Bank 0 or Bank 1. The Data Memory is initialised to Bank 0 after a reset, except for a WDT time-out reset in the Power Down Mode, in which case, the Data Memory bank remains unaffected. It should be noted that the Special Function Data Memory is not affected by the bank selection, which means that the Special Function Registers can be accessed from within any bank. Directly addressing the Data Memory will always result in Bank 0 being accessed irrespective of the value of the Bank Pointer. Accessing data from Bank 1 must be implemented using Indirect Addressing. • BP Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — — DMBP0 R/W — — — — — — — R/W POR — — — — — — — 0 Bit 7~1 Unimplemented, read as "0" Bit 0 DMBP0: Select Data Memory Banks 0: Bank 0 1: Bank 1 Accumulator – ACC The Accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the ALU. The Accumulator is the place where all intermediate results from the ALU are stored. Without the Accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory resulting in higher programming and timing overheads. Data transfer operations usually involve the temporary storage function of the Accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the Accumulator as no direct transfer between two registers is permitted. Program Counter Low Register – PCL To provide additional program control functions, the low byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area of the Data Memory. By manipulating this register, direct jumps to other program locations are easily implemented. Loading a value directly into this PCL register will cause a jump to the specified Program Memory location, however, as the register is only 8-bit wide, only jumps within the current Program Memory page are permitted. When such operations are used, note that a dummy cycle will be inserted. Look-up Table Registers – TBLP, TBHP, TBLH These three special function registers are used to control operation of the look-up table which is stored in the Program Memory. TBLP and TBHP are the table pointers and indicate the location where the table data is located. Their value must be setup before any table read commands are executed. Their value can be changed, for example using the "INC" or "DEC" instructions, allowing for easy table data pointing and reading. TBLH is the location where the high order byte of the table data is stored after a table read data instruction has been executed. Note that the lower order table data byte is transferred to a user defined location. Rev. 1.00 26 October 27, 2017 BS84B08C Touch A/D Flash MCU Status Register – STATUS This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/logical operation and system management flags are used to record the status and operation of the microcontroller. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition, operations related to the status register may give different results due to the different instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or by executing the "CLR WDT" or "HALT" instruction. The PDF flag is affected only by executing the "HALT" or "CLR WDT" instruction or during a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations. • C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. • AC is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. • Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared. • OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. • PDF is cleared by a system power-up or executing the "CLR WDT" instruction. PDF is set by executing the "HALT" instruction. • TO is cleared by a system power-up or executing the "CLR WDT" or "HALT" instruction. TO is set by a WDT time-out. In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. Rev. 1.00 27 October 27, 2017 BS84B08C Touch A/D Flash MCU • STATUS Register Bit 7 6 5 4 3 2 1 0 Name — — TO PDF OV Z AC C R/W — — R R R/W R/W R/W R/W POR — — 0 0 x x x x "x": Unknown Rev. 1.00 Bit 7~6 Unimplemented, read as "0" Bit 5 TO: Watchdog Time-Out flag 0: After power up or executing the "CLR WDT" or "HALT" instruction 1: A watchdog time-out occurred Bit 4 PDF: Power down flag 0: After power up or executing the "CLR WDT" instruction 1: By executing the "HALT" instruction Bit 3 OV: Overflow flag 0: No overflow 1: An operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa Bit 2 Z: Zero flag 0: The result of an arithmetic or logical operation is not zero 1: The result of an arithmetic or logical operation is zero Bit 1 AC: Auxiliary flag 0: No auxiliary carry 1: An operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction Bit 0 C: Carry flag 0: No carry-out 1: An operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation The "C" flag is also affected by a rotate through carry instruction. 28 October 27, 2017 BS84B08C Touch A/D Flash MCU EEPROM Data Memory This device contains an area of internal EEPROM Data Memory. EEPROM is by its nature a nonvolatile form of re-programmable memory, with data retention even when its power supply is removed. By incorporating this kind of data memory, a whole new host of application possibilities are made available to the designer. The availability of EEPROM storage allows information such as product identification numbers, calibration values, specific user data, system setup data or other product information to be stored directly within the product microcontroller. The process of reading and writing data to the EEPROM memory has been reduced to a very trivial affair. EEPROM Data Memory Structure The EEPROM Data Memory capacity is 64×8 bits for the device. Unlike the Program Memory and RAM Data Memory, the EEPROM Data Memory is not directly mapped into memory space and is therefore not directly addressable in the same way as the other types of memory. Read and Write operations to the EEPROM are carried out in single byte operations using an address and a data register in Bank 0~Bank1 and a single control register in Bank 1. EEPROM Registers Three registers control the overall operation of the internal EEPROM Data Memory. These are the address register, EEA, the data register, EED and a single control register, EEC. As both the EEA and EED registers can be located in Bank 0, they can be directly accessed in the same way as any other Special Function Register when they are located in Bank 0. The EEC register, however, being located in Bank 1, can be read from or written to indirectly using the MP1 Memory Pointer and Indirect Addressing Register, IAR1. Because the EEC control register is located at address 40H in Bank 1, the MP1 Memory Pointer must first be set to the value 40H and the Bank Pointer register, BP, set to the value, 01H, before any operations on the EEC register are executed. Bit Register Name 7 6 5 4 3 2 1 0 EEA — — EEA5 EEA4 EEA3 EEA2 EEA1 EEA0 EED D7 D6 D5 D4 D3 D2 D1 D0 EEC — — — — WREN WR RDEN RD EEPROM Register List • EEA Register Bit 7 6 5 4 3 2 1 0 Name — — EEA5 EEA4 EEA3 EEA2 EEA1 EEA0 R/W — — R/W R/W R/W R/W R/W R/W POR — — 0 0 0 0 0 0 Bit 7~6 Unimplemented, read as "0" Bit 5~0 EEA5~EEA0: Data EEPROM address Data EEPROM address bit 5~bit 0 • EED Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 Rev. 1.00 D7~D0: Data EEPROM data Data EEPROM data bit 7~bit 0 29 October 27, 2017 BS84B08C Touch A/D Flash MCU • EEC Register Bit 7 6 5 4 3 2 1 0 Name — — — — WREN WR RDEN RD R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as "0" Bit 3 WREN: Data EEPROM Write Enable 0: Disable 1: Enable This is the Data EEPROM Write Enable Bit which must be set high before Data EEPROM write operations are carried out. Clearing this bit to zero will inhibit Data EEPROM write operations. Bit 2 WR: EEPROM Write Control 0: Write cycle has finished 1: Activate a write cycle This is the Data EEPROM Write Control Bit and when set high by the application program will activate a write cycle. This bit will be automatically reset to zero by the hardware after the write cycle has finished. Setting this bit high will have no effect if the WREN has not first been set high. Bit 1 RDEN: Data EEPROM Read Enable 0: Disable 1: Enable This is the Data EEPROM Read Enable Bit which must be set high before Data EEPROM read operations are carried out. Clearing this bit to zero will inhibit Data EEPROM read operations. Bit 0 RD: EEPROM Read Control 0: Read cycle has finished 1: Activate a read cycle This is the Data EEPROM Read Control Bit and when set high by the application program will activate a read cycle. This bit will be automatically reset to zero by the hardware after the read cycle has finished. Setting this bit high will have no effect if the RDEN has not first been set high. Note: The WREN, WR, RDEN and RD can not be set high at the same time in one instruction. The WR and RD cannot be set high at the same time. Reading Data from the EEPROM To read data from the EEPROM, the read enable bit, RDEN, in the EEC register must first be set high to enable the read function. The EEPROM address of the data to be read must then be placed in the EEA register. If the RD bit in the EEC register is now set high, a read cycle will be initiated. Setting the RD bit high will not initiate a read operation if the RDEN bit has not been set. When the read cycle terminates, the RD bit will be automatically cleared to zero, after which the data can be read from the EED register. The data will remain in the EED register until another read or write operation is executed. The application program can poll the RD bit to determine when the data is valid for reading. Rev. 1.00 30 October 27, 2017 BS84B08C Touch A/D Flash MCU Writing Data to the EEPROM To write data to the EEPROM, the EEPROM address of the data to be written must first be placed in the EEA register and the data placed in the EED register. Then the write enable bit, WREN, in the EEC register must first be set high to enable the write function. After this, the WR bit in the EEC register must be immediately set high to initiate a write cycle. These two instructions must be executed consecutively. The global interrupt bit EMI should also first be cleared before implementing any write operations, and then set again after the write cycle has started. Note that setting the WR bit high will not initiate a write cycle if the WREN bit has not been set. As the EEPROM write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the EEPROM. Detecting when the write cycle has finished can be implemented either by polling the WR bit in the EEC register or by using the EEPROM interrupt. When the write cycle terminates, the WR bit will be automatically cleared to zero by the microcontroller, informing the user that the data has been written to the EEPROM. The application program can therefore poll the WR bit to determine when the write cycle has ended. Write Protection Protection against inadvertent write operation is provided in several ways. After the device is powered-on the Write Enable bit in the control register will be cleared preventing any write operations. Also at power-on the Bank Pointer, BP, will be reset to zero, which means that Data Memory Bank 0 will be selected. As the EEPROM control register is located in Bank 1, this adds a further measure of protection against spurious write operations. During normal program operation, ensuring that the Write Enable bit in the control register is cleared will safeguard against incorrect write operations. EEPROM Interrupt The EEPROM write interrupt is generated when an EEPROM write cycle has ended. The EEPROM interrupt must first be enabled by setting the DEE bit in the relevant interrupt register. When an EEPROM write cycle ends, the DEF request flag will be set. If the global, EEPROM interrupt is enabled and the stack is not full, a jump to the associated Interrupt vector will take place. When the interrupt is serviced, the EEPROM interrupt flag will automatically reset. More details can be obtained in the Interrupt section. Programming Considerations Care must be taken that data is not inadvertently written to the EEPROM. Protection can be enhanced by ensuring that the Write Enable bit is normally cleared to zero when not writing. Also the Bank Pointer could be normally cleared to zero as this would inhibit access to Bank 1 where the EEPROM control register exist. Although certainly not necessary, consideration might be given in the application program to the checking of the validity of new write data by a simple read back process. When writing data the WR bit must be set high immediately after the WREN bit has been set high, to ensure the write cycle executes correctly. The global interrupt bit EMI should also be cleared before a write cycle is executed and then re-enabled after the write cycle starts. Note that the device should not enter the IDLE or SLEEP mode until the EEPROM read or write operation is totally complete. Otherwise, the EEPROM read or write operation will fail. Rev. 1.00 31 October 27, 2017 BS84B08C Touch A/D Flash MCU Programming Examples Reading data from the EEPROM – polling method MOV A, EEPROM_ADRES ; user defined address MOV EEA, A MOV A, 040H ; setup memory pointer MP1 MOV MP1, A ; MP1 points to EEC register MOV A, 01H ; setup Bank Pointer MOV BP, A SET IAR1.1 ; set RDEN bit, enable read operations SET IAR1.0 ; start Read Cycle – set RD bit BACK: SZ IAR1.0 ; check for read cycle end JMP BACK CLR IAR1 ; disable EEPROM read/write CLR BP MOV A, EED ; move read data to register MOV READ_DATA, A Writing Data to the EEPROM – polling method MOV A, EEPROM_ADRES ; user defined address MOV EEA, A MOV A, EEPROM_DATA ; user defined data MOV EED, A MOV A, 040H ; setup memory pointer MP1 MOV MP1, A ; MP1 points to EEC register MOV A, 01H ; setup Bank Pointer MOV BP, A CLR EMI SET IAR1.3 ; set WREN bit, enable write operations SET IAR1.2 ; start Write Cycle – set WR bit – executed immediately ; after set WREN bit SET EMI BACK: SZ IAR1.2 ; check for write cycle end JMP BACK CLR IAR1 ; disable EEPROM read/write CLR BP Rev. 1.00 32 October 27, 2017 BS84B08C Touch A/D Flash MCU Oscillators Various oscillator options offer the user a wide range of functions according to their various application requirements. The flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. Oscillator selections and operation are selected through registers. Oscillator Overview In addition to being the source of the main system clock the oscillators also provide clock sources for the Watchdog Timer and Time Base Interrupts. Two fully integrated internal oscillators, requiring no external components, are provided to form a wide range of both fast and slow system oscillators. The higher frequency oscillators provide higher performance but carry with it the disadvantage of higher power requirements, while the opposite is of course true for the lower frequency oscillators. With the capability of dynamically switching between fast and slow system clock, the device has the flexibility to optimize the performance/power ratio, a feature especially important in power sensitive portable applications. Type Name Frequency Internal High Speed RC HIRC 8/12/16MHz Internal Low Speed RC LIRC 32kHz Oscillator Types System Clock Configurations There are two methods of generating the system clock, one high speed oscillator and one low speed oscillator. The high speed oscillator is the internal 8/12/16MHz RC oscillator. The low speed oscillator is the internal 32kHz RC oscillator. Selecting whether the low or high speed oscillator is used as the system oscillator is implemented using the HLCLK bit and CKS2~CKS0 bits in the SMOD register and as the system clock can be dynamically selected. The actual source clock used for the high speed and low speed oscillators is chosen via registers. The frequency of the slow speed or high speed system clock is also determined using the HLCLK bit and CKS2~CKS0 bits in the SMOD register. Note that two oscillator selections must be made namely one high speed and one low speed system oscillators. It is not possible to choose a nooscillator selection for either the high or low speed oscillator. High Speed �s�illato� HIRC fH 6-stage P�es�ale� fH/� fH/4 fH/8 fSYS fH/16 Low Speed �s�illato� fH/3� fH/64 LIRC fSUB HLCLK� CKS�~CKS0 �its System Clock Configurations Rev. 1.00 33 October 27, 2017 BS84B08C Touch A/D Flash MCU Internal RC Oscillator – HIRC The internal RC oscillator is a fully integrated system oscillator requiring no external components. The internal RC oscillator has a power on default frequency of 8MHz but can be selected to be either 8MHz, 12MHz or 16MHz using the HIRCS1 and HIRCS0 bits in the CTRL register. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. Internal 32kHz Oscillator – LIRC The internal 32kHz System Oscillator is the low frequency oscillator. It is a fully integrated RC oscillator with a typical frequency of 32kHz at 5V, requiring no external components for its implementation. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. After power on this LIRC oscillator will be permanently enabled; there is no provision to disable the oscillator using. Operating Modes and System Clocks Present day applications require that their microcontrollers have high performance but often still demand that they consume as little power as possible, conflicting requirements that are especially true in battery powered portable applications. The fast clocks required for high performance will by their nature increase current consumption and of course vice-versa, lower speed clocks reduce current consumption. As Holtek has provided this device with both high and low speed clock sources and the means to switch between them dynamically, the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. System Clocks The device has many different clock sources for both the CPU and peripheral function operation. By providing the user with a wide range of clock options using register programming, a clock system can be configured to obtain maximum application performance. The main system clock, can come from either a high frequency, fH, or low frequency, fSUB, source, and is selected using the HLCLK bit and CKS2~CKS0 bits in the SMOD register. The high speed system clock can be sourced from the HIRC oscillator. The low speed system clock source can be sourced from the LIRC oscillator. The other choice, which is a divided version of the high speed system oscillator has a range of fH/2~fH/64. Rev. 1.00 34 October 27, 2017 BS84B08C Touch A/D Flash MCU High Speed �s�illato� HIRC fH 6-stage P�es�ale� fH/� fH/4 fH/8 fSYS fH/16 fH/3� Low Speed �s�illato� LIRC fH/64 fSUB HLCLK� CKS�~CKS0 �its fSUB fPSC fSYS fSYS/4 fH Time Base TB[�:0] CLKSEL[1:0] fS WDT Device Clock Configurations Note: When the system clock source fSYS is switched to fSUB from fH, the high speed oscillator can be stopped to conserve the power. Thus there is no fH~fH/64 for peripheral circuit to use. System Operation Modes There are five different modes of operation for the microcontroller, each one with its own special characteristics and which can be chosen according to the specific performance and power requirements of the application. There are two modes allowing normal operation of the microcontroller, the FAST Mode and SLOW Mode. The remaining three modes, the SLEEP, IDLE0 and IDLE1 Mode are used when the microcontroller CPU is switched off to conserve power. Operation Mode Description CPU fSYS fSUB fS FAST On fH~fH/64 On On SLOW On fSUB On On IDLE0 Off Off On On IDLE1 Off On On On SLEEP Off Off On On FAST Mode As the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by one of the high speed oscillators. This mode operates allowing the microcontroller to operate normally with a clock source will come from the high speed oscillators, HIRC. The high speed oscillator will however first be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the CKS2~CKS0 and HLCLK bits in the SMOD register. Although a high speed oscillator is used, running the microcontroller at a divided clock ratio reduces the operating current. Rev. 1.00 35 October 27, 2017 BS84B08C Touch A/D Flash MCU SLOW Mode This is also a mode where the microcontroller operates normally although now with a slower speed clock source. The clock source used will be from fSUB. Running the microcontroller in this mode allows it to run with much lower operating currents. In the SLOW Mode, the fH is off. SLEEP Mode The SLEEP Mode is entered when an HALT instruction is executed and when the IDLEN bit in the SMOD register be low. In the SLEEP mode the CPU will be stopped, the fSUB clock will continue to operate since the WDT function is always enabled. IDLE0 Mode The IDLE0 Mode is entered when a HALT instruction is executed and when the IDLEN bit in the SMOD register is high and the FSYSON bit in the CTRL register is low. In the IDLE0 Mode the system oscillator will be stopped and will therefore be inhibited from driving the CPU but some peripheral functions will remain operational such as the Watchdog Timer and TM. IDLE1 Mode The IDLE1 Mode is entered when an HALT instruction is executed and when the IDLEN bit in the SMOD register is high and the FSYSON bit in the CTRL register is high. In the IDLE1 Mode the system oscillator will be inhibited from driving the CPU but may continue to provide a clock source to keep some peripheral functions operational such as the Watchdog Timer and TM. In the IDLE1 Mode, the system oscillator will continue to run, and this system oscillator may be high speed or low speed system oscillator. Control Registers The registers, SMOD and CTRL are used to control the system clock and the corresponding oscillator configurations. Bit Register Name 7 6 5 4 3 2 1 0 SMOD CKS2 CKS1 CKS0 — LTO HTO IDLEN HLCLK CTRL FSYSON — HIRCS1 HIRCS0 — LVRF LRF WRF System Operating Mode Control Register List • SMOD Register Rev. 1.00 Bit 7 6 5 4 3 2 1 0 Name CKS2 CKS1 CKS0 — LTO HTO IDLEN HLCLK R/W R/W R/W R/W — R R R/W R/W POR 0 0 0 — 0 0 1 1 Bit 7~5 CKS2~CKS0: System clock selection when HLCLK is "0" 000: fSUB(fLIRC) 001: fSUB(fLIRC) 010: fH/64 011: fH/32 100: fH/16 101: fH/8 110: fH/4 111: fH/2 These three bits are used to select which clock is used as the system clock source. In addition to the system clock source, which can be LIRC, a divided version of the high speed system oscillator can also be chosen as the system clock source. Bit 4 Unimplemented, read as "0" 36 October 27, 2017 BS84B08C Touch A/D Flash MCU Bit 3 LTO: Low system oscillator ready flag 0: Not ready 1: Ready This is the low speed system oscillator ready flag which indicates when the low speed system oscillator is stable after power on reset or a wake-up has occurred. The flag will change to a high level after 1~2 clock cycles. Bit 2 HTO: High system oscillator ready flag 0: Not ready 1: Ready This is the high speed system oscillator ready flag which indicates when the high speed system oscillator is stable. This flag is cleared to "0" by hardware when the device is powered on and then changes to a high level after the high speed system oscillator is stable.Therefore this flag will always be read as "1" by the application program after device power-on. The flag will be low when in the SLEEP or IDLE0 Mode but after a wake-up has occurred, the flag will change to a high level after 15~16 clock cycles. Bit 1 IDLEN: IDLE mode control 0: Disable 1: Enable This is the IDLE mode control bit and determines what happens when the HALT instruction is executed. If this bit is high, when a HALT instruction is executed, the device will enter the IDLE mode. In the IDLE1 mode the CPU will stop running but the system clock will continue to keep the peripheral functions operational, if the FSYSON bit is high. If the FSYSON bit is low, the CPU and the system clock will all stop in IDLE0 mode. If the bit is low, the device will enter the SLEEP mode when a HALT instruction is executed. Bit 0 HLCLK: System clock selection 0: fH/2~fH/64 or fSUB 1: fH This bit is used to select if the fH clock or the fH/2~fH/64 or fSUB clock is used as the system clock. When the bit is high the fH clock will be selected and if low the fH/2~fH/64 or fSUB clock will be selected. When system clock switches from the fH clock to the fSUB clock and the fH clock will be automatically switched off to conserve power. • CTRL Register Bit 7 6 5 4 3 2 1 0 Name FSYSON — HIRCS1 HIRCS0 — LVRF LRF WRF R/W R/W — R/W R/W — R/W R/W R/W POR 0 — 0 0 — x 0 0 "x": Unknown Bit 7 Rev. 1.00 FSYSON: fSYS control in IDLE Mode 0: Disable 1: Enable This bit is used to control whether the system clock is switched on or not in the IDLE Mode. If this bit is set to "0", the system clock will be switched off in the IDLE Mode. However, the system clock will be switched on in the IDLE Mode when the FSYSON bit is set to "1". Bit 6 Unimplemented, read as "0" Bit 5~4 HIRCS1~HIRCS0: HIRC frequency clock selection 00: 8MHz 01: 16MHz 10: 12MHz 11: 8MHz Bit 3 Unimplemented, read as "0" 37 October 27, 2017 BS84B08C Touch A/D Flash MCU Bit 2 LVRF: LVR function reset flag Describe elsewhere. Bit 1 LRF: LVR control register software reset flag Describe elsewhere. Bit 0 WRF: WDT control register software reset flag Describe elsewhere. Operating Mode Switching The device can switch between operating modes dynamically allowing the user to select the best performance/power ratio for the present task in hand. In this way microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. In simple terms, Operating Mode Switching between the FAST Mode and SLOW Mode is executed using the HLCLK bit and CKS2~CKS0 bits in the SMOD register while Operating Mode Switching from the FAST/SLOW Modes to the SLEEP/IDLE Modes is executed via the HALT instruction. When a HALT instruction is executed, whether the device enters the IDLE Mode or the SLEEP Mode is determined by the condition of the IDLEN bit in the SMOD register and the FSYSON bit in the CTRL register. When the HLCLK bit switches to a low level, which implies that clock source is switched from the high speed clock, fH, to the clock source, fH/2~fH/64 or fSUB. If the clock is from the fSUB, the high speed clock source will stop running to conserve power. When this happens, it must be noted that the fH/16 and fH/64 internal clock sources will also stop running, which may affect the operation of other internal functions such as the TM. The accompamying chart shows what happens when the device moves between the various operating modes. FAST fSYS=fH~fH/64 fH on CPU �un fSYS on fSUB on WDT on SLOW fSYS=fSUB CPU �un fSYS on fSUB on fH off fS on WDT on SLEEP HALT inst�u�tion exe�uted fSYS off CPU stop IDLEN=0 fSUB on fS on WDT on IDLE1 HALT inst�u�tion exe�uted CPU stop IDLEN=1 FSYS�N=1 IDLE0 HALT inst�u�tion exe�uted CPU stop IDLEN=1 FSYS�N=0 fSYS on fSUB on fS on WDT on Rev. 1.00 fSYS off fSUB on fS on WDT on 38 October 27, 2017 BS84B08C Touch A/D Flash MCU FAST Mode to SLOW Mode Switching When running in the FAST Mode, which uses the high speed system oscillator, and therefore consumes more power, the system clock can switch to run in the SLOW Mode by set the HLCLK bit to "0" and set the CKS2~CKS0 bits to "000" or "001" in the SMOD register. This will then use the low speed system oscillator which will consume less power. Users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. The SLOW Mode is sourced from the LIRC oscillator and therefore requires this oscillator to be stable before full mode switching occurs. This is monitored using the LTO bit in the SMOD register. FAST Mode CKS�~CKS0 = 00xB & HLCLK = 0 SLOW Mode IDLEN=0 HALT inst�u�tion is exe�uted SLEEP Mode IDLEN=1� FSYS�N=0 HALT inst�u�tion is exe�uted IDLE0 Mode IDLEN=1� FSYS�N=1 HALT inst�u�tion is exe�uted IDLE1 Mode SLOW Mode to FAST Mode Switching In SLOW mode the system uses the LIRC system oscillator. To switch back to the FAST Mode, where the high speed system oscillator is used, the HLCLK bit should be set to "1" or HLCLK bit is "0", but CKS2~CKS0 field is set to "010", "011", "100", "101", "110" or "111". As a certain amount of time will be required for the high frequency clock to stabilise, the status of the HTO bit is checked. SLOW Mode CKS2~CKS0 ≠ 000B or 001B as HLCLK = 0 or HLCLK = 1 FAST Mode IDLEN=0 HALT instruction is executed SLEEP Mode IDLEN=1, FSYSON=0 HALT instruction is executed IDLE0 Mode IDLEN=1, FSYSON=1 HALT instruction is executed IDLE1 Mode Rev. 1.00 39 October 27, 2017 BS84B08C Touch A/D Flash MCU Entering the SLEEP Mode There is only one way for the device to enter the SLEEP Mode and that is to execute the "HALT" instruction in the application program with the IDLEN bit in the SMOD register equal to "0". When this instruction is executed under the conditions described above, the following will occur: • The system clock and Time Base clock will be stopped and the application program will stop at the "HALT" instruction, but the fSUB clock will be on. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and resume counting since the WDT function is always enabled. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag PDF will be set, and WDT timeout flag TO will be cleared. Entering the IDLE0 Mode There is only one way for the device to enter the IDLE0 Mode and that is to execute the "HALT" instruction in the application program with the IDLEN bit in the SMOD register equal to "1" and the FSYSON bit in the CTRL register equal to "0". When this instruction is executed under the conditions described above, the following will occur: • The system clock will be stopped and the application program will stop at the "HALT" instruction, but the Time Base and fSUB clocks will be on. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and resume counting since the WDT function is always enabled. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag PDF will be set, and WDT timeout flag TO will be cleared. Entering the IDLE1 Mode There is only one way for the device to enter the IDLE1 Mode and that is to execute the "HALT" instruction in the application program with the IDLEN bit in the SMOD register equal to "1" and the FSYSON bit in the CTRL register equal to "1". When this instruction is executed under the conditions described above, the following will occur: • The system clock and the low frequency fSUB clocks will be on but the application program will stop at the "HALT" instruction. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and resume counting since the WDT function is always enabled. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag PDF will be set, and WDT timeout flag TO will be cleared. Rev. 1.00 40 October 27, 2017 BS84B08C Touch A/D Flash MCU Standby Current Considerations As the main reason for entering the SLEEP or IDLE Mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps except in the IDLE1 Mode, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. Special attention must be made to the I/O pins on the device. All high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. This also applies to the device which has different package types, as there may be unbonbed pins. These must either be setup as outputs or if setup as inputs must have pull-high resistors connected. Care must also be taken with the loads, which are connected to I/O pins, which are setup as outputs. These should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other CMOS inputs. In the IDLE1 Mode the system oscillator is on, if the system oscillator is from the high speed oscillator, the additional standby current will also be perhaps in the order of several hundred micro-amps. Wake-up To minimise power consumption the device can enter the SLEEP or any IDLE Mode, where the CPU will be switched off. However, when the device is woken up again, it will take a considerable time for the original system oscillator to restart, stablise and allow normal operation to resume. After the system enters the SLEEP or IDLE Mode, it can be woken up from one of various sources listed as follows: • An external falling edge on Port A • A system interrupt • A WDT overflow If the device is woken up by a WDT overflow, a Watchdog Timer reset will be initiated. The PDF flag is cleared by a system power-up or executing the clear Watchdog Timer instructions and is set when executing the "HALT" instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the Program Counter and Stack Pointer, the other flags remain in their original status. Each pin on Port A can be setup using the PAWU register to permit a negative transition on the pin to wake up the system. When a Port A pin wake-up occurs, the program will resume execution at the instruction following the "HALT" instruction. If the system is woken up by an interrupt, then two possible situations may occur. The first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the "HALT" instruction. In this situation, the interrupt which woke up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free. The other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. If an interrupt request flag is set high before entering the SLEEP or IDLE Mode, the wake-up function of the related interrupt will be disabled. Programming Considerations The high speed and low speed oscillators both use the same SST counter. For example, if the system is woken up from the SLEEP Mode the HIRC oscillator need to start-up from an off state. If the device is woken up from the SLEEP Mode to the FAST Mode, the high speed system oscillator needs an SST period. The device will execute first instruction after HTO is high. Rev. 1.00 41 October 27, 2017 BS84B08C Touch A/D Flash MCU Watchdog Timer The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. Watchdog Timer Clock Source The Watchdog Timer clock source is provided by the internal clock, fS, which is sourced from the LIRC oscillator. The LIRC internal oscillator has an approximate period of 32kHz at a supply voltage of 5V. However, it should be noted that this specified internal clock period can vary with VDD, temperature and process variations. The Watchdog Timer source clock is then subdivided by a ratio of 28 to 218 to give longer timeouts, the actual value being chosen using the WS2~WS0 bits in the WDTC register. Watchdog Timer Control Register A single register, WDTC, controls the required timeout period as well as the enable and reset MCU operation. The WDTC register is initiated to 01010011B at any reset except WDT time-out hardware warm reset. • WDTC Register Bit 7 6 5 4 3 2 1 0 Name WE4 WE3 WE2 WE1 WE0 WS2 WS1 WS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 1 0 1 0 0 1 1 Bit 7~3 Bit 2~0 WE4~WE0: WDT function software control 01010/10101: Enable Others: Reset MCU When these bits are changed to any other values due to environmental noise the microcontroller will be reset; this reset operation will be activated after a delay time, tSRESET and the WRF bit in the CTRL register will be set high. WS2~WS0: WDT time-out period selection 000: 28/fS 001: 210/fS 010: 212/fS 011: 214/fS 100: 215/fS 101: 216/fS 110: 217/fS 111: 218/fS These three bits determine the division ratio of the watchdog timer source clock, which in turn determines the time-out period. • CTRL Register Bit 7 6 5 4 3 2 1 0 Name FSYSON — HIRCS1 HIRCS0 — LVRF LRF WRF R/W R/W — R/W R/W — R/W R/W R/W POR 0 — 0 0 — x 0 0 "x": Unknown Bit 7 Bit 6 Bit 5~4 Bit 3 Rev. 1.00 FSYSON: fSYS control in IDLE Mode Describe elsewhere. Unimplemented, read as "0" HIRCS1~HIRCS0: HIRC frequency clock selection Describe elsewhere. Unimplemented, read as "0" 42 October 27, 2017 BS84B08C Touch A/D Flash MCU Bit 2 Bit 1 Bit 0 LVRF: LVR function reset flag Describe elsewhere. LRF: LVR control register software reset flag Describe elsewhere. WRF: WDT control register software reset flag 0: Not occur 1: Occurred This bit is set high by the WDT control register software reset and cleared to zero by the application program. Note that this bit can only be cleared to zero by the application program. Watchdog Timer Operation The Watchdog Timer operates by providing a device reset when its timer overflows. This means that in the application program and during normal operation the user has to strategically clear the Watchdog Timer before it overflows to prevent the Watchdog Timer from executing a reset. This is done using the clear watchdog instructions. If the program malfunctions for whatever reason, jumps to an unknown location, or enters an endless loop, these clear instructions will not be executed in the correct manner, in which case the Watchdog Timer will overflow and reset the device. There are five bits, WE4~WE0, in the WDTC register to offer the enable control and reset control of the Watchdog Timer. The WDT function will be enabled when the WE4~WE0 bits are set to a value of 10101B or 01010B. If the WE4~WE0 bits are set to any other values, other than 01010B and 10101B, it will reset the device after a delay time, tSRESET. After power on these bits will have a value of 01010B. WE4~WE0 Bits WDT Function 10101B/01010B Enable Any other values Reset MCU Watchdog Timer Enable/Reset Control Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set the status bit TO. However, if the system is in the SLEEP or IDLE Mode, when a Watchdog Timer time-out occurs, the TO bit in the status register will be set and only the Program Counter and Stack Pointer will be reset. Three methods can be adopted to clear the contents of the Watchdog Timer. The first is a WDT reset, which means a certain value except 01010B and 10101B written into the WE4~WE0 bit filed, the second is using the Watchdog Timer software clear instruction and the third is via a HALT instruction. There is only one method of using software instruction to clear the Watchdog Timer. That is to use the single "CLR WDT" instruction to clear the WDT. The maximum time out period is when the 218 division ratio is selected. As an example, with a 32kHz LIRC oscillator as its source clock, this will give a maximum watchdog period of around 8 second for the 218 division ratio, and a minimum timeout of 8ms for the 28 division ration. WDTC Registe� WE4~WE0 �its Reset MCU CLR “HALT”Inst�u�tion “CLR WDT”Inst�u�tion fS 11-stage Divide� 8-to-1 MUX �-stage Divide� WDT Time-out (�8/fS ~ �18/fS) WS�~WS0 Watchdog Timer Rev. 1.00 43 October 27, 2017 BS84B08C Touch A/D Flash MCU Reset and Initialisation A reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. The most important reset condition is after power is first applied to the microcontroller. In this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well-defined state and ready to execute the first program instruction. After this power-on reset, certain important internal registers will be set to defined states before the program commences. One of these registers is the Program Counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest Program Memory address. In addition to the power-on reset, another reset exists in the form of a Low Voltage Reset, LVR, where a full reset is implemented in situations where the power supply voltage falls below a certain threshold. Another type of reset is when the Watchdog Timer overflows and resets the microcontroller. All types of reset operations result in different register conditions being setup. Reset Functions There are several ways in which a microcontroller reset can occur, through events occurring internally. Power-on Reset The most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. As well as ensuring that the Program Memory begins execution from the first memory address, a power-on reset also ensures that certain other registers are preset to known conditions. All the I/O port and port control registers will power up in a high condition ensuring that all I/O ports will be first set to inputs. VDD Powe�-on Reset tRSTD SST Time-out Power-On Reset Timing Chart Low Voltage Reset – LVR The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. The LVR function is always enabled with a specific LVR voltage VLVR. If the supply voltage of the device drops to within a range of 0.9V~VLVR such as might occur when changing the battery, the LVR will automatically reset the device internally and the LVRF bit in the CTRL register will also be set high. For a valid LVR signal, a low supply voltage, i.e., a voltage in the range between 0.9V~VLVR must exist for a time greater than that specified by tLVR in the LVR Electrical Characteristics. If the low supply voltage state does not exceed this value, the LVR will ignore the low supply voltage and will not perform a reset function. The actual VLVR value can be selected by the LVS7~LVS0 bits in the LVRC register. If the LVS7~LVS0 bits are changed to some certain values by the environmental noise or software setting, the LVR will reset the device after a delay time, tSRESET. When this happens, the LRF bit in the CTRL register will be set high. After power on the register will have the value of 01010101B. Note that the LVR function will be automatically disabled when the device enters the SLEEP or IDLE mode. LVR tRSTD + tSST Inte�nal Reset Low Voltage Reset Timing Chart Rev. 1.00 44 October 27, 2017 BS84B08C Touch A/D Flash MCU • LVRC Register Bit 7 6 5 4 3 2 1 0 Name LVS7 LVS6 LVS5 LVS4 LVS3 LVS2 LVS1 LVS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 1 0 1 0 1 0 1 Bit 7~0 LVS7~LVS0: LVR Voltage Select control 01010101: 2.1V 00110011: 2.55V 10011001: 3.15V 10101010: 3.8V Any other value: Generates MCU reset – register is reset to POR value When an actual low voltage condition occurs, as specified by one of the four defined LVR voltage values above, an MCU reset will be generated. The reset operation will be activated after the low voltage condition keeps more than a tLVR time. In this situation the register contents will remain the same after such a reset occurs. Any register value, other than the four defined LVR values above, will also result in the generation of an MCU reset. The reset operation will be activated after a delay time, tSRESET. However in this situation the register contents will be reset to the POR value. • CTRL Register Bit 7 6 5 4 3 2 1 0 Name FSYSON — HIRCS1 HIRCS0 — LVRF LRF WRF R/W R/W — R/W R/W — R/W R/W R/W POR 0 — 0 0 — x 0 0 "x": Unknown Rev. 1.00 Bit 7 FSYSON: fSYS control in IDLE Mode Describe elsewhere. Bit 6 Unimplemented, read as "0" Bit 5~4 HIRCS1~HIRCS0: HIRC frequency clock selection Describe elsewhere. Bit 3 Unimplemented, read as "0" Bit 2 LVRF: LVR function reset flag 0: Not occur 1: Occurred This bit is set high when a specific Low Voltage Reset situation condition occurs. This bit can only be cleared to zero by the application program. Bit 1 LRF: LVR control register software reset flag 0: Not occur 1: Occurred This bit is set to 1 if the LVRC register contains any non-defined LVR voltage register values. This in effect acts like a software-reset function. This bit can only be cleared to 0 by the application program. Bit 0 WRF: WDT control register software reset flag Describe elsewhere. 45 October 27, 2017 BS84B08C Touch A/D Flash MCU Watchdog Time-out Reset during Normal Operation The Watchdog time-out Reset during normal operation in the FAST or SLOW mode is the same as LVR reset except that the Watchdog time-out flag TO will be set high. WDT Time-out tRSTD + tSST Inte�nal Reset WDT Time-out Reset during Normal Operation Timing Chart Watchdog Time-out Reset during SLEEP or IDLE Mode The Watchdog time-out Reset during SLEEP or IDLE Mode is a little different from other kinds of reset. Most of the conditions remain unchanged except that the Program Counter and the Stack Pointer will be cleared to zero and the TO flag will be set high. Refer to the System Start Up Time Characteristics for tSST details. WDT Time-out tSST Inte�nal Reset WDT Time-out Reset during Sleep or IDLE Mode Timing Chart Reset Initial Conditions The different types of reset described affect the reset flags in different ways. These flags, known as PDF and TO are located in the status register and are controlled by various microcontroller operations, such as the SLEEP or IDLE Mode function or Watchdog Timer. The reset flags are shown in the table: TO PDF 0 0 Power-on reset Reset Conditions u u LVR reset during FAST or SLOW Mode operation 1 u WDT time-out reset during FAST or SLOW Mode operation 1 1 WDT time-out reset during IDLE or SLEEP Mode operation "u": stands for unchanged The following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. Item Condition after Reset Program Counter Reset to zero Interrupts All interrupts will be disabled WDT, Time Base Clear after reset, WDT begins counting Timer Module Timer Module will be turned off Input/Output Ports I/O ports will be setup as inputs and AN0~AN7 as A/D input pins Stack Pointer Stack Pointer will point to the top of the stack The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. The following table describes how each type of reset affects each of the microcontroller internal registers. Note that where more than one package type exists the table will refelect the situation for the larger package type. Rev. 1.00 46 October 27, 2017 BS84B08C Touch A/D Flash MCU Reset (Power On) LVR Reset (Normal Operation) WDT Time-out (Normal Operation) WDT Time-out (SLEEP or IDLE) IAR0 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu MP0 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu IAR1 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu MP1 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu BP ---- ---0 ---- ---0 ---- ---0 ---- ---u ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu PCL 0000 0000 0000 0000 0000 0000 0000 0000 TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu TBLH xxxx xxxx uuuu uuu uuuu uuu uuuu uuuu TBHP ---- xxxx ---- uuuu ---- uuuu ---- uuuu STATUS --00 xxxx --uu uuuu --1u uuuu - - 11 u u u u SMOD 0 0 0 - 0 0 11 0 0 0 - 0 0 11 0 0 0 - 0 0 11 uuu- uuuu CTRL 0-00 -x00 0-00 -100 0-00 -x00 u-uu --uu LVRC 0101 0101 0101 0101 0101 0101 uuuu uuuu INTEG ---- --00 ---- --00 ---- --00 ---- --uu INTC0 -000 0000 -000 0000 -000 0000 -uuu uuuu INTC1 -000 -000 -000 -000 -000 -000 -uuu -uuu MFI --00 --00 --00 --00 --00 --00 --uu --uu PA 1 - - 1 1111 1 - - 1 1111 1 - - 1 1111 u--u uuuu PAC 1 - - 1 1111 1 - - 1 1111 1 - - 1 1111 u--u uuuu PAPU 0--0 0000 0--0 0000 0--0 0000 u--u uuuu PAWU 0--0 0000 0--0 0000 0--0 0000 u--u uuuu PXRM 00-- ---00 00-- ---00 00-- ---00 uu-- ---uu WDTC 0 1 0 1 0 0 11 0 1 0 1 0 0 11 0 1 0 1 0 0 11 uuuu uuuu TBC ---- 0000 ---- 0000 ---- 0000 ---- uuuu PSCR ---- ---- ---- –00 ---- --uu EEA --00 0000 --00 0000 --00 0000 --uu uuuu EED 0000 0000 0000 0000 0000 0000 uuuu uuuu PB 1111 1111 1111 1111 1111 1111 uuuu uuuu PBC 1111 1111 1111 1111 1111 1111 uuuu uuuu PBPU 0000 0000 0000 0000 0000 0000 uuuu uuuu SIMTOC 0000 0000 0000 0000 0000 0000 uuuu uuuu SIMC0 111 - 0 0 0 0 111 - 0 0 0 0 111 - 0 0 0 0 uuu- uuuu SIMC1 1000 0001 1000 0001 1000 0001 uuuu uuuu SIMD xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu SIMA/SIMC2 0000 0000 0000 0000 0000 0000 uuuu uuuu Register ADRL –00 xxxx ---- –00 xxxx ---- xxxx ---- uuuu ---(ADRFS=0) uuuu uuuu (ADRFS=1) uuuu uuuu (ADRFS=0) ADRH xxxx xxxx xxxx xxxx xxxx xxxx ADCR0 0 11 0 - 0 0 0 0 11 0 - 0 0 0 0 11 0 - 0 0 0 uuuu -uuu ADCR1 00-0 -000 00-0 -000 00-0 -000 uu-u -uuu ACERL 1111 1111 1111 1111 1111 1111 uuuu uuuu SLEDC0 0000 0000 0000 0000 0000 0000 uuuu uuuu Rev. 1.00 47 ---- uuuu (ADRFS=1) October 27, 2017 BS84B08C Touch A/D Flash MCU Register Reset (Power On) LVR Reset (Normal Operation) WDT Time-out (Normal Operation) WDT Time-out (SLEEP or IDLE) SLEDC1 ---- 0000 ---- 0000 ---- 0000 ---- uuuu PD 1111 1111 1111 1111 1111 1111 uuuu uuuu PDC 1111 1111 1111 1111 1111 1111 uuuu uuuu PDPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PTMC0 0000 0--- 0000 0--- 0000 0--- uuuu u--- PTMC1 0000 0000 0000 0000 0000 0000 uuuu uuuu PTMDL 0000 0000 0000 0000 0000 0000 uuuu uuuu PTMDH ---- --00 ---- --00 ---- --00 ---- --uu PTMAL 0000 0000 0000 0000 0000 0000 uuuu uuuu PTMAH ---- --00 ---- --00 ---- --00 ---- --uu PTMRPL 0000 0000 0000 0000 0000 0000 uuuu uuuu PTMRPH ---- --00 ---- --00 ---- --00 ---- --uu TKTMR 0000 0000 0000 0000 0000 0000 uuuu uuuu TKC0 -000 0000 -000 0000 -000 0000 -uuu uuuu TK16DL 0000 0000 0000 0000 0000 0000 uuuu uuuu TK16DH 0000 0000 0000 0000 0000 0000 uuuu uuuu TKC1 ---- --11 ---- --11 ---- --11 ---- --uu TKM016DL 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM016DH 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM0ROL 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM0ROH ---- --00 ---- --00 ---- --00 ---- --uu TKM0C0 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM0C1 0-00 0000 0-00 0000 0-00 0000 u-uu uuuu TKM116DL 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM116DH 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM1ROL 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM1ROH ---- --00 ---- --00 ---- --00 ---- --uu TKM1C0 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM1C1 0-00 0000 0-00 0000 0-00 0000 u-uu uuuu EEC ---- 0000 ---- 0000 ---- 0000 ---- uuuu Note: "u" stands for unchanged "x" stands for unknown "-" stands for unimplemented Rev. 1.00 48 October 27, 2017 BS84B08C Touch A/D Flash MCU Input/Output Ports Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an I/O structure to meet the needs of a wide range of application possibilities. The device provides bidirectional input/output lines labeled with port names PA, PB and PD. These I/O ports are mapped to the RAM Data Memory with specific addresses as shown in the Special Purpose Data Memory table. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, which means the inputs must be ready at the T2 rising edge of instruction "MOV A, [m]", where m denotes the port address. For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Bit Register Name 7 6 5 4 3 2 1 0 PA PA7 — — PA4 PA3 PA2 PA1 PA0 PAC PAC7 — — PAC4 PAC3 PAC2 PAC1 PAC0 PAPU PAPU7 — — PAPU4 PAPU3 PAPU2 PAPU1 PAPU0 PAWU PAWU7 — — PAWU4 PAWU3 PAWU2 PAWU1 PAWU0 PB PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PBC PBC7 PBC6 PBC5 PBC4 PBC3 PBC2 PBC1 PBC0 PBPU PBPU7 PBPU6 PBPU5 PBPU4 PBPU3 PBPU2 PBPU1 PBPU0 PD PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PDC PDC7 PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 PDPU PDPU7 PDPU6 PDPU5 PDPU4 PDPU3 PDPU2 PDPU1 PDPU0 "—": Unimplemented, read as "0" I/O Logic Function Register List Pull-high Resistors Many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. To eliminate the need for these external resistors, all I/O pins, when configured as an input have the capability of being connected to an internal pull-high resistor. These pull-high resistors are selected using registers PAPU, PBPU and PDPU, and are implemented using weak PMOS transistors. • PxPU Register Bit 7 6 5 4 3 2 1 0 Name PxPU7 PxPU6 PxPU5 PxPU4 PxPU3 PxPU2 PxPU1 PxPU0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 PxPUn: I/O Port x pin pull-high function control 0: Disable 1: Enable The PxPUn bit is used to control the pin pull-high function. Here the "x" can be A, B or D. However, the actual available bits for each I/O Port may be different. Rev. 1.00 49 October 27, 2017 BS84B08C Touch A/D Flash MCU Port A Wake-up The HALT instruction forces the microcontroller into the SLEEP or IDLE Mode which preserves power, a feature that is important for battery and other low-power applications. Various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the Port A pins from high to low. This function is especially suitable for applications that can be woken up via external switches. Each pin on Port A can be selected individually to have this wake-up feature using the PAWU register. • PAWU Register Bit 7 6 5 4 3 2 1 0 Name PAWU7 — — PAWU4 PAWU3 PAWU2 PAWU1 PAWU0 R/W R/W — — R/W R/W R/W R/W R/W POR 0 — — 0 0 0 0 0 Bit 7 PAWU7: PA7 wake-up function control 0: Disable 1: Enable Bit 6~5 Unimplemented, read as "0" Bit 4~0 PAWU4~PAWU0: PA4~PA0 wake-up function control 0: Disable 1: Enable I/O Port Control Registers Each Port has its own control register, known as PAC, PBC and PDC, which control the input/ output configuration. With this control register, each CMOS output or input can be reconfigured dynamically under software control. Each pin of the I/O ports is directly mapped to a bit in its associated port control register. For the I/O pin to function as an input, the corresponding bit of the control register must be written as a "1". This will then allow the logic state of the input pin to be directly read by instructions. When the corresponding bit of the control register is written as a "0", the I/O pin will be setup as a CMOS output. If the pin is currently setup as an output, instructions can still be used to read the output register. However, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. • PxC Register Bit 7 6 5 4 3 2 1 0 Name PxC7 PxC6 PxC5 PxC4 PxC3 PxC2 PxC1 PxC0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 1 1 1 1 1 1 PxCn: I/O Port x pin type selection 0: Output 1: Input The PxCn bit is used to control the pin type selection. Here the "x" can be A, B or D. However, the actual available bits for each I/O Port may be different. Rev. 1.00 50 October 27, 2017 BS84B08C Touch A/D Flash MCU I/O Port Source Current Control The device supports different source current driving capability for each I/O port. With the corresponding selection register, SLEDC0 and SLEDC1, each I/O port can support four levels of the source current driving capability. Users should refer to the Input/Output Characteristics section to select the desired source current for different applications. Register Name Bit 7 6 5 4 3 2 1 0 SLEDC0 SLEDC07 SLEDC06 SLEDC05 SLEDC04 SLEDC03 SLEDC02 SLEDC01 SLEDC00 SLEDC1 — — — — SLEDC13 SLEDC12 SLEDC11 SLEDC10 I/O Port Source Current Control Register List • SLEDC0 Register Bit Name 7 6 5 4 3 2 1 0 SLEDC07 SLEDC06 SLEDC05 SLEDC04 SLEDC03 SLEDC02 SLEDC01 SLEDC00 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 1 0 Bit 7~6 Bit 5~4 Bit 3~2 Bit 1~0 SLEDC07~SLEDC06: PB7~PB4 source current selection 00: source current = Level 0 (min.) 01: source current = Level 1 10: source current = Level 2 11: source current = Level 3 (max.) SLEDC05~SLEDC04: PB3~PB0 source current selection 00: source current = Level 0 (min.) 01: source current = Level 1 10: source current = Level 2 11: source current = Level 3 (max.) SLEDC03~SLEDC02: PA7 or PA4 source current selection 00: source current = Level 0 (min.) 01: source current = Level 1 10: source current = Level 2 11: source current = Level 3 (max.) SLEDC01~SLEDC00: PA3~PA0 source current selection 00: source current = Level 0 (min.) 01: source current = Level 1 10: source current = Level 2 11: source current = Level 3 (max.) • SLEDC1 Register Rev. 1.00 Bit 7 6 5 4 Name — — — — 3 2 R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 SLEDC13 SLEDC12 SLEDC11 SLEDC10 Bit 7~4 Unimplemented, read as "0" Bit 3~2 SLEDC13~SLEDC12: PD7~PD4 source current selection 00: source current = Level 0 (min.) 01: source current = Level 1 10: source current = Level 2 11: source current = Level 3 (max.) Bit 1~0 SLEDC11~SLEDC10: PD3~PD0 source current selection 00: source current = Level 0 (min.) 01: source current = Level 1 10: source current = Level 2 11: source current = Level 3 (max.) 51 October 27, 2017 BS84B08C Touch A/D Flash MCU Pin-remapping Function The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. Limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these difficulties can be overcome. The way in which the pin function of each pin is selected is different for each function and a priority order is established where more than one pin function is selected simultaneously. Additionally there is a register, PXRM, to establish certain pin functions. If the pin-shared pin function have multiple outputs simultaneously, its pin names at the right side of the "/" sign can be used for higher priority. • PXRM Register Bit 7 6 5 4 3 2 1 0 Name TMPC1 TMPC0 — — — — PXRM1 PXRM0 R/W R/W R/W — — — — R/W R/W POR 0 0 — — — — 0 0 Bit 7 Bit 6 Bit 5~2 Bit 1 Bit 0 TMPC1: PTPB pin control Described elsewhere. TMPC0: PTP pin control Described elsewhere. Unimplemented, read as "0" PXRM1: SIM module SCK/SCL pin-remapping selection 0: PA2 1: PA7 PXRM0: SIM module SDI/SDA pin-remapping selection 0: PA0 1: PA4 I/O Pin Structures The accompanying diagram illustrates the internal structures of the I/O logic function. As the exact logical construction of the I/O pin will differ from this drawing, it is supplied as a guide only to assist with the functional understanding of the logic function I/O pins. The wide range of pin-shared structures does not permit all types to be shown. VDD Cont�ol Bit Data Bus W�ite Cont�ol Registe� Chip Reset Read Cont�ol Registe� D Weak Pull-up CK Q S I/� pin Data Bit D W�ite Data Registe� Q Pull-high Registe� Sele�t Q CK Q S Read Data Registe� System Wake-up M U X wake-up Sele�t PA only Logic Function Input/Output Structure Rev. 1.00 52 October 27, 2017 BS84B08C Touch A/D Flash MCU Programming Considerations Within the user program, one of the first things to consider is port initialisation. After a reset, all of the I/O data and port control registers will be set high. This means that all I/O pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high selections have been chosen. If the port control registers, PAC, PBC and PDC, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers, PA, PB and PD, are first programmed. Selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the "SET [m].i" and "CLR [m].i" instructions. Note that when using these bit control instructions, a read-modify-write operation takes place. The microcontroller must first read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. Port A has the additional capability of providing wake-up functions. When the device is in the SLEEP or IDLE Mode, various methods are available to wake the device up. One of these is a high to low transition of any of the Port A pins. Single or multiple pins on Port A can be setup to have this function. Timer Modules – TM One of the most fundamental functions in any microcontroller device is the ability to control and measure time. To implement time related functions the device includes single Timer Module, abbreviated to the name TM. The TM is multi-purpose timing unit and serve to provide operations such as Timer/Counter, Input Capture, Compare Match Output and Single Pulse Output as well as being the functional unit for the generation of PWM signals. The TM has two individual interrupts. The addition of input and output pins for TM ensures that users are provided with timing units with a wide and flexible range of features. Introduction The device contains only one Periodic Type TM unit, with its individual reference name, PTM. The main features of PTM are summarised in the accompanying table. TM Function PTM Timer/Counter √ Input Capture √ Compare Match Output √ PWM Channels 1 Single Pulse Output 1 PWM Alignment Edge PWM Adjustment Period & Duty Duty or Period TM Function Summary TM Operation The Periodic type TM offers a diverse range of functions, from simple timing operations to PWM signal generation. The key to understanding how the TM operates is to see it in terms of a free running counter whose value is then compared with the value of pre-programmed internal comparators. When the free running counter has the same value as the pre-programmed comparator, known as a compare match situation, a TM interrupt signal will be generated which can clear the counter and perhaps also change the condition of the TM output pin. The internal TM counter is driven by a user selectable clock source, which can be an internal clock or an external pin. Rev. 1.00 53 October 27, 2017 BS84B08C Touch A/D Flash MCU TM Clock Source The clock source which drives the main counter in each TM can originate from various sources. The selection of the required clock source is implemented using the PTCK2~PTCK0 bits in the PTM control registers. The clock source can be a ratio of the system clock fSYS or the internal high clock fH, the fSUB clock source or the external PTCK pin. The PTCK pin clock source is used to allow an external signal to drive the TM as an external clock source or for event counting. TM Interrupts The Periodic type TM has two internal interrupts, the internal comparator A or comparator P, which generate a TM interrupt when a compare match condition occurs. When a TM interrupt is generated, it can be used to clear the counter and also to change the state of the TM output pin. TM External Pins The Periodic type TM has two TM input pin, with the label PTCK and PTPI. The PTM input pin, PTCK, is essentially a clock source for the PTM and is selected using the PTCK2~PTCK0 bits in the PTMC0 register. This external TM input pin allows an external clock source to drive the internal TM. The TM input pin can be chosen to have either a rising or falling active edge. The PTCK pin is also used as the external trigger input pin in single pulse output mode. The other PTM input pin, PTPI, is the capture input whose active edge can be a rising edge, a falling edge or both rising and falling edges and the active edge transition type is selected using the PTIO1~PTIO0 bits in the PTMC1 register. The Periodic type TM has two output pins with the label PTP and PTPB. The PTPB pin outputs the inverted signal of the PTP. When the TM is in the Compare Match Output Mode, these pins can be controlled by the TM to switch to a high or low level or to toggle when a compare match situation occurs. The external PTP and PTPB output pins are also the pins where the TM generates the PWM output waveform. As the TM input and output pins are pin-shared with other function, the TM input and output function must first be setup using the associated register. A single bit in the register determines if its associated pin is to be used as an external TM pin or if it is to have another function. PTM Input Output PTCK, PTPI PTP, PTPB TM External Pins TM Input/Output Pin Control Register Selecting to have a TM input/output or whether to retain its other shared function is implemented using one register, with a single bit in the register corresponding to a TM input/output pin. Configuring the selection bits correctly will setup the corresponding pin as a TM input/output. Setting the bit high will setup the corresponding pin as a TM input/output, if reset to zero the pin will retain its original other function. Rev. 1.00 54 October 27, 2017 BS84B08C Touch A/D Flash MCU PA1 �utput Fun�tion 0 PA1/PTP 1 0 1 TMPC0 PA1 PA� �utput Fun�tion �utput 0 1 PTM PA�/PTPB 1 0 TMPC1 PA� Captu�e Input PA4/PTPI 0 1 TCK Input PTCAPTS PA3/PTCK PTM Function Pin Control Block Diagram • PXRM Register Bit 7 6 5 4 3 2 1 0 Name TMPC1 TMPC0 — — — — PXRM1 PXRM0 R/W R/W R/W — — — — R/W R/W POR 0 0 — — — — 0 0 Bit 7 Bit 6 Bit 5~2 Bit 1 Bit 0 Rev. 1.00 TMPC1: PTPB pin control 0: Disable 1: Enable TMPC0: PTP pin control 0: Disable 1: Enable Unimplemented, read as "0" PXRM1: SIM module SCK/SCL pin-remapping selection Described elsewhere. PXRM0: SIM module SDI/SDA pin-remapping selection Described elsewhere. 55 October 27, 2017 BS84B08C Touch A/D Flash MCU Programming Considerations The TM Counter Registers and the Capture/Compare CCRA and CCRP registers, being 10-bit, all have a low and high byte structure. The high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buffer, reading or writing to these register pairs must be carried out in a specific way. The important point to note is that data transfer to and from the 8-bit buffer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed. As the CCRA and CCRP registers are implemented in the way shown in the following diagram and accessing this register pair is carried out in a specific way described above, it is recommended to use the "MOV" instruction to access the CCRA and CCRP low byte register, named PTMAL and PTMRPL, in the following access procedures. Accessing the CCRA or CCRP low byte register without following these access procedures will result in unpredictable values. PTM Counte� Registe� (Read only) PTMDL PTMDH 8-�it Buffe� PTMAL PTMAH PTM CCRA Registe� (Read/W�ite) PTMRPL PTMRPH PTM CCRP Registe� (Read/W�ite) Data Bus The following steps show the read and write procedures: • Writing Data to CCRA or CCRP ♦♦ Step 1. Write data to Low Byte PTMAL or PTMRPL ––Note that here data is only written to the 8-bit buffer. ♦♦ Step 2. Write data to High Byte PTMAH or PTMRPH ––Here data is written directly to the high byte registers and simultaneously data is latched from the 8-bit buffer to the Low Byte registers. • Reading Data from the Counter Registers and CCPR or CCRA ♦♦ Step 1. Read data from the High Byte PTMDH, PTMAH or PTMRPH ––Here data is read directly from the High Byte registers and simultaneously data is latched from the Low Byte register into the 8-bit buffer. ♦♦ Step 2. Read data from the Low Byte PTMDL, PTMAL or PTMRPL ––This step reads data from the 8-bit buffer. Rev. 1.00 56 October 27, 2017 BS84B08C Touch A/D Flash MCU Periodic Type TM – PTM The Periodic Type TM contains five operating modes, which are Compare Match Output, Timer/ Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Periodic TM can be controlled with two external input pins and can drive two external output pins. CCRP 10-�it Compa�ato� P fSYS/4 fSYS fH/16 000 fH/64 fSUB 011 fSUB 101 001 PTMPF Inte��upt PT�C �0~�9 010 10-�it Count-up Counte� 100 110 PTCK Compa�ato� P Mat�h PT�N PTPAU Counte� Clea� PTCCLR �0~�9 111 PTCK�~PTCK0 10-�it Compa�ato� A CCRA �utput Cont�ol 0 1 PTM1� PTM0 PTI�1� PTI�0 Compa�ato� A Mat�h Pola�ity Cont�ol PTP�L Pin �utput Cont�ol PTP PTPB TMPC1 TMPC0 PTMAF Inte��upt PTI�1� PTI�0 PTCAPTS Edge Dete�to� 0 1 PTPI Note: PTPB is the inverted output of the PTP. Periodic Type TM Block Diagram Periodic TM Operation The Periodic Type TM core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. There are also two internal comparators with the names, Comparator A and Comparator P. These comparators will compare the value in the counter with CCRP and CCRA registers. The CCRP and CCRA comparators are 10-bit wide. The only way of changing the value of the 10-bit counter using the application program, is to clear the counter by changing the PTON bit from low to high. The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. When these conditions occur, a PTM interrupt signal will also usually be generated. The Periodic Type TM can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control more than one output pin. All operating setup conditions are selected using relevant internal registers. Rev. 1.00 57 October 27, 2017 BS84B08C Touch A/D Flash MCU Periodic Type TM Register Description Overall operation of the Periodic Type TM is controlled using a series of registers. A read only register pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store the internal 10-bit CCRA value and CCRP value. The remaining two registers are control registers which setup the different operating and control modes. Bit Register Name 7 6 5 4 3 2 1 0 PTMC0 PTPAU PTCK2 PTCK1 PTCK0 PTON — — — PTMC1 PTM1 PTM0 PTIO1 PTIO0 PTOC PTPOL PTCAPTS PTCCLR PTMDL D7 D6 D5 D4 D3 D2 D1 D0 PTMDH — — — — — — D9 D8 PTMAL D7 D6 D5 D4 D3 D2 D1 D0 PTMAH — — — — — — D9 D8 PTMRPL D7 D6 D5 D4 D3 D2 D1 D0 PTMRPH — — — — — — D9 D8 10-bit Periodic TM Register List • PTMC0 Register Rev. 1.00 Bit 7 6 5 4 3 2 1 0 Name PTPAU PTCK2 PTCK1 PTCK0 PTON — — — R/W R/W R/W R/W R/W R/W — — — POR 0 0 0 0 0 — — — Bit 7 PTPAU: PTM Counter Pause Control 0: Run 1: Pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the PTM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. Bit 6~4 PTCK2~PTCK0: Select PTM Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fSUB 101: fSUB 110: PTCK rising edge clock 111: PTCK falling edge clock These three bits are used to select the clock source for the PTM. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and fSUB are other internal clocks, the details of which can be found in the oscillator section. 58 October 27, 2017 BS84B08C Touch A/D Flash MCU Bit 3 PTON: PTM Counter On/Off Control 0: Off 1: On This bit controls the overall on/off function of the PTM. Setting the bit high enables the counter to run, clearing the bit disables the PTM. Clearing this bit to zero will stop the counter from counting and turn off the PTM which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. If the PTM is in the Compare Match Output Mode, PWM output Mode or Single Pulse Output Mode then the PTM output pin will be reset to its initial condition, as specified by the PTOC bit, when the PTON bit changes from low to high. Bit 2~0 Unimplemented, read as "0" • PTMC1 Register Rev. 1.00 Bit 7 6 5 4 3 2 Name PTM1 PTM0 PTIO1 PTIO0 PTOC PTPOL 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 PTCAPTS PTCCLR Bit 7~6 PTM1~PTM0: Select PTM Operating Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Output Mode or Single Pulse Output Mode 11: Timer/Counter Mode These bits setup the required operating mode for the PTM. To ensure reliable operation the PTM should be switched off before any changes are made to the PTM1 and PTM0 bits. In the Timer/Counter Mode, the PTM output pin control must be disabled. Bit 5~4 PTIO1~PTIO0: Select PTM external pin function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Output Mode/Single Pulse Output Mode 00: PWM Output inactive state 01: PWM Output active state 10: PWM output 11: Single pulse output Capture Input Mode 00: Input capture at rising edge of PTPI or PTCK 01: Input capture at falling edge of PTPI or PTCK 10: Input capture at falling/rising edge of PTPI or PTCK 11: Input capture disabled Timer/Counter Mode Unused These two bits are used to determine how the PTM output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the PTM is running. In the Compare Match Output Mode, the PTIO1 and PTIO0 bits determine how the PTM output pin changes state when a compare match occurs from the Comparator A. The PTM output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the PTM output pin should be setup using the PTOC bit in the PTMC1 register. Note that the output level requested by the PTIO1 and PTIO0 bits must be different from the initial value 59 October 27, 2017 BS84B08C Touch A/D Flash MCU setup using the PTOC bit otherwise no change will occur on the PTM output pin when a compare match occurs. After the PTM output pin changes state, it can be reset to its initial level by changing the level of the PTON bit from low to high. In the PWM Output Mode, the PTIO1 and PTIO0 bits determine how the PTM output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to only change the values of the PTIO1 and PTIO0 bits only after the TM has been switched off. Unpredictable PWM outputs will occur if the PTIO1 and PTIO0 bits are changed when the PTM is running. Bit 3 PTOC: PTM PTP Output control bit Compare Match Output Mode 0: Initial low 1: Initial high PWM Output Mode/Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the PTM output pin. Its operation depends upon whether PTM is being used in the Compare Match Output Mode or in the PWM Output Mode/Single Pulse Output Mode. It has no effect if the PTM is in the Timer/ Counter Mode. In the Compare Match Output Mode it determines the logic level of the PTM output pin before a compare match occurs. In the PWM Output Mode it determines if the PWM signal is active high or active low. In the Single Pulse Output Mode it determines the logic level of the PTM output pin when the PTON bit changes from low to high. Bit 2 PTPOL: PTM PTP Output Polarity Control 0: Non-invert 1: Invert This bit controls the polarity of the PTP output pin. When the bit is set high the PTM output pin will be inverted and not inverted when the bit is zero. It has no effect if the PTM is in the Timer/Counter Mode. Bit 1 PTCAPTS: PTM Capture Trigger Source Selection 0: From PTPI pin 1: From PTCK pin Bit 0 PTCCLR: Select PTM Counter clear condition 0: PTM Comparator P match 1: PTM Comparator A match This bit is used to select the method which clears the counter. Remember that the Periodic TM contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter. With the PTCCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The PTCCLR bit is not used in the PWM Output Mode, Single Pulse Output Mode or Capture Input Mode. • PTMDL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0 Rev. 1.00 D7~D0: PTM Counter Low Byte Register bit 7~bit 0 PTM 10-bit Counter bit 7~bit 0 60 October 27, 2017 BS84B08C Touch A/D Flash MCU • PTMDH Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R R POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0 D9~D8: PTM Counter High Byte Register bit 1~bit 0 PTM 10-bit Counter bit 9~bit 8 • PTMAL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 D7~D0: PTM CCRA Low Byte Register bit 7~bit 0 PTM 10-bit CCRA bit 7~bit 0 • PTMAH Register Bit 7 6 5 4 3 2 1 0 Name — — — — — D8 R/W — — — — — R/W R/W POR — — — — — — — — D9 0 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0 D9~D8: PTM CCRA High Byte Register bit 1~bit 0 PTM 10-bit CCRA bit 9~bit 8 • PTMRPL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 D7~D0: PTM CCRP Low Byte Register bit 7~bit 0 PTM 10-bit CCRP bit 7~bit 0 • PTMRPH Register Rev. 1.00 Bit 7 6 5 4 3 2 1 0 Name — — — — — D9 D8 R/W — — — — — R/W R/W POR — — — — — — — — 0 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0 D9~D8: PTM CCRP High Byte Register bit 1~bit 0 PTM 10-bit CCRP bit 9~bit 8 61 October 27, 2017 BS84B08C Touch A/D Flash MCU Periodic Type TM Operating Modes The Periodic Type TM can operate in one of five operating modes, Compare Match Output Mode, PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The operating mode is selected using the PTM1 and PTM0 bits in the PTMC1 register. Compare Match Output Mode To select this mode, bits PTM1 and PTM0 in the PTMC1 register, should be set to 00 respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the PTCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both PTMAF and PTMPF interrupt request flags for Comparator A and Comparator P respectively, will both be generated. If the PTCCLR bit in the PTMC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the PTMAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when PTCCLR is high no PTMPF interrupt request flag will be generated. In the Compare Match Output Mode, the CCRA can not be cleared to zero. If the CCRA bits are all zero, the counter will overflow when its reaches its maximum 10-bit, 3FF Hex, value, however here the PTMAF interrupt request flag will not be generated. As the name of the mode suggests, after a comparison is made, the PTM output pin, will change state. The PTM output pin condition however only changes state when a PTMAF interrupt request flag is generated after a compare match occurs from Comparator A. The PTMPF interrupt request flag, generated from a compare match occurs from Comparator P, will have no effect on the PTM output pin. The way in which the PTM output pin changes state are determined by the condition of the PTIO1 and PTIO0 bits in the PTMC1 register. The PTM output pin can be selected using the PTIO1 and PTIO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the PTM output pin, which is setup after the PTON bit changes from low to high, is setup using the PTOC bit. Note that if the PTIO1 and PTIO0 bits are zero then no pin change will take place. Rev. 1.00 62 October 27, 2017 BS84B08C Touch A/D Flash MCU Counte� ove�flow Counte� Value 0x3FF PTCCLR = 0; PTM [1:0] = 00 CCRP > 0 Counte� �lea�ed �y CCRP value CCRP=0 CCRP > 0 Counte� Resta�t Resume CCRP Pause CCRA Stop Time PT�N PTPAU PTP�L CCRP Int. Flag PTMPF CCRA Int. Flag PTMAF PTM �/P Pin �utput pin set to initial Level Low if PT�C=0 �utput not affe�ted �y PTMAF flag. Remains High until �eset �y PT�N �it �utput Toggle with PTMAF flag He�e PTI� [1:0] = 11 Toggle �utput sele�t Note PTI� [1:0] = 10 A�tive High �utput sele�t �utput Inve�ts when PTP�L is high �utput Pin Reset to Initial value �utput �ont�olled �y othe� pin-sha�ed fun�tion Compare Match Output Mode – PTCCLR = 0 Notes: 1. With PTCCLR=0 a Comparator P match will clear the counter 2. The PTM output pin is controlled only by the PTMAF flag 3. The output pin is reset to its initial state by a PTON bit rising edge Rev. 1.00 63 October 27, 2017 BS84B08C Touch A/D Flash MCU Counte� Value PTCCLR = 1; PTM [1:0] = 00 CCRA = 0 Counte� ove�flow CCRA > 0 Counte� �lea�ed �y CCRA value 0x3FF CCRA=0 Resume CCRA Pause Stop Counte� Resta�t CCRP Time PT�N PTPAU PTP�L No PTMAF flag gene�ated on CCRA ove�flow CCRA Int. Flag PTMAF CCRP Int. Flag PTMPF PTMPF not gene�ated �utput does not �hange PTM �/P Pin �utput pin set to initial Level Low if PT�C=0 �utput Toggle with PTMAF flag He�e PTI� [1:0] = 11 Toggle �utput sele�t �utput not affe�ted �y PTMAF flag. Remains High until �eset �y PT�N �it Note PTI� [1:0] = 10 A�tive High �utput sele�t �utput Inve�ts when PTP�L is high �utput Pin Reset to Initial value �utput �ont�olled �y othe� pin-sha�ed fun�tion Compare Match Output Mode – PTCCLR = 1 Notes: 1. With PTCCLR=1 a Comparator A match will clear the counter 2. The PTM output pin is controlled only by the PTMAF flag 3. The output pin is reset to its initial state by a PTON bit rising edge 4. A PTMPF flag is not generated when PTCCLR=1 Rev. 1.00 64 October 27, 2017 BS84B08C Touch A/D Flash MCU Timer/Counter Mode To select this mode, bits PTM1 and PTM0 in the PTMC1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the PTM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the TM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, bits PTM1 and PTM0 in the PTMC1 register should be set to 10 respectively and also the PTnIO1 and PTnIO0 bits should be set to 10 respectively. The PWM function within the PTM is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the PTM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM Output Mode, the PTCCLR bit has no effect on the PWM operation. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency, while the other one is used to control the duty cycle. The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers. An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match occurs from either Comparator A or Comparator P. The PTOC bit in the PTMC1 register is used to select the required polarity of the PWM waveform while the two PTIO1 and PTIO0 bits are used to enable the PWM output or to force the PTM output pin to a fixed high or low level. The PTPOL bit is used to reverse the polarity of the PWM output waveform. • 10-bit PTM, PWM Output Mode, Edge-aligned Mode CCRP 1~1023 0 Period 1~1023 1024 Duty CCRA If fSYS=16MHz, PTM clock source select fSYS/4, CCRP=512 and CCRA=128, The PTM PWM output frequency=(fSYS/4)/512=fSYS/2048=7.8125kHz, duty=128/512=25%. If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty is 100%. Rev. 1.00 65 October 27, 2017 BS84B08C Touch A/D Flash MCU Counte� Value PTM [1:0] = 10 Counte� �lea�ed �y CCRP Counte� Reset when PT�N �etu�ns high CCRP Pause Resume Counte� Stop if PT�N �it low CCRA Time PT�N PTPAU PTP�L CCRA Int. Flag PTMAF CCRP Int. Flag PTMPF PTM �/P Pin (PT�C=1) PTM �/P Pin (PT�C=0) PWM Duty Cy�le set �y CCRA PWM �esumes ope�ation �utput �ont�olled �y othe� pin-sha�ed fun�tion PWM Pe�iod set �y CCRP �utput Inve�ts When PTP�L = 1 PWM Output Mode Notes: 1. Counter cleared by CCRP 2. A counter clear sets the PWM Period 3. The internal PWM function continues running even when PTIO [1:0] = 00 or 01 4. The PTCCLR bit has no influence on PWM operation Rev. 1.00 66 October 27, 2017 BS84B08C Touch A/D Flash MCU Single Pulse Output Mode To select this mode, bits PTM1 and PTM0 in the PTMC1 register should be set to 10 respectively and also the PTIO1 and PTIO0 bits should be set to 11 respectively. The Single Pulse Output Mode, as the name suggests, will generate a single shot pulse on the PTM output pin. The trigger for the pulse output leading edge is a low to high transition of the PTON bit, which can be implemented using the application program. However in the Single Pulse Output Mode, the PTON bit can also be made to automatically change from low to high using the external PTCK pin, which will in turn initiate the Single Pulse output. When the PTON bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. The PTON bit should remain high when the pulse is in its active state. The generated pulse trailing edge will be generated when the PTON bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from Comparator A. However a compare match from Comparator A will also automatically clear the PTON bit and thus generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control the pulse width. A compare match from Comparator A will also generate a PTM interrupt. The counter can only be reset back to zero when the PTON bit changes from low to high when the counter restarts. In the Single Pulse Output Mode CCRP is not used. The PTCCLR bit is not used in this Mode. S/W Command SET“PT�N” o� PTCK Pin T�ansition CCRA Leading Edge CCRA T�ailing Edge PT�N �it 0 1 PT�N �it 1 0 S/W Command CLR“PT�N” o� CCRA Compa�e Mat�h PTP �utput Pin Pulse Width = CCRA Value Single Pulse Generation Rev. 1.00 67 October 27, 2017 BS84B08C Touch A/D Flash MCU Counte� Value PTM [1:0] = 10 ; PTIO [1:0] = 11 Counte� stopped �y CCRA Counte� Reset when PT�N �etu�ns high CCRA Pause Counte� Stops �y softwa�e Resume CCRP Time PT�N Softwa�e T�igge� Clea�ed �y CCRA mat�h Auto. set �y PTCK pin Softwa�e T�igge� Softwa�e T�igge� Softwa�e Clea� Softwa�e T�igge� PTCK pin PTCK pin T�igge� PTPAU PTP�L CCRP Int. Flag PTMPF No CCRP Inte��upts gene�ated CCRA Int. Flag PTMAF PTM �/P Pin (PT�C=1) PTM �/P Pin (PT�C=0) �utput Inve�ts when PTP�L = 1 Pulse Width set �y CCRA Single Pulse Output Mode Notes: 1. Counter stopped by CCRA 2. CCRP is not used 3. The pulse is triggered by the PTCK pin or by setting the PTON bit high 4. A PTCK pin active edge will automatically set the PTON bit high 5. In the Single Pulse Output Mode, PTIO [1:0] must be set to "11" and cannot be changed Rev. 1.00 68 October 27, 2017 BS84B08C Touch A/D Flash MCU Capture Input Mode To select this mode bits PTM1 and PTM0 in the PTMC1 register should be set to 01 respectively. This mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. The external signal is supplied on the PTPI or PTCK pin which is selected using the PTCAPTS bit in the PTMC1 register. The input pin active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the PTIO1 and PTIO0 bits in the PTMC1 register. The counter is started when the PTON bit changes from low to high which is initiated using the application program. When the required edge transition appears on the PTPI or PTCK pin the present value in the counter will be latched into the CCRA registers and a PTM interrupt generated. Irrespective of what events occur on the PTPI or PTCK pin, the counter will continue to free run until the PTON bit changes from high to low. When a CCRP compare match occurs the counter will reset back to zero; in this way the CCRP value can be used to control the maximum counter value. When a CCRP compare match occurs from Comparator P, a PTM interrupt will also be generated. Counting the number of overflow interrupt signals from the CCRP can be a useful method in measuring long pulse widths. The PTIO1 and PTIO0 bits can select the active trigger edge on the PTPI or PTCK pin to be a rising edge, falling edge or both edge types. If the PTIO1 and PTIO0 bits are both set high, then no capture operation will take place irrespective of what happens on the PTPI or PTCK pin, however it must be noted that the counter will continue to run. As the PTPI or PTCK pin is pin shared with other functions, care must be taken if the PTM is in the Capture Input Mode. This is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. The PTCCLR, PTOC and PTPOL bits are not used in this Mode. Rev. 1.00 69 October 27, 2017 BS84B08C Touch A/D Flash MCU Counte� Value PTM[1:0] = 01 Counte� �lea�ed �y CCRP Counte� Stop Counte� Reset CCRP Resume YY Pause XX Time PT�N PTPAU A�tive edge A�tive edge A�tive edge PTM Captu�e Pin PTPI o� PTCK CCRA Int. Flag PTMAF CCRP Int. Flag PTMPF CCRA Value PTI� [1:0] Value XX 00 - Rising edge YY 01 - Falling edge XX 10 - Both edges YY 11 - Disa�le Captu�e Capture Input Mode Notes: 1. PTM [1:0] = 01 and active edge set by the PTIO [1:0] bits 2. A PTM Capture input pin active edge transfers the counter value to CCRA 3. PTCCLR bit not used 4. No output function – PTOC and PTPOL bits are not used 5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal to zero Rev. 1.00 70 October 27, 2017 BS84B08C Touch A/D Flash MCU Analog to Digital Converter The need to interface to real world analog signals is a common requirement for many electronic systems. However, to properly process these signals by a microcontroller, they must first be converted into digital signals by A/D converters. By integrating the A/D conversion electronic circuitry into the microcontroller, the need for external components is reduced significantly with the corresponding follow-on benefits of lower costs and reduced component space requirements. A/D Converter Overview The device contains a multi-channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into a 12-bit digital value. More detailed information about the A/D input signal is described in the "A/D Converter Control Registers Description" and "A/D Converter Input Pins" sections respectively. Input Channels A/D Channel Select Bits Input Pins 8 ACS4, ACS2~ACS0 AN0~AN7 The accompanying block diagram shows the overall internal structure of the A/D converter, together with its associated registers. VDD fSYS SACK�~SACK0 ACE�~ACE0 PD0/VREF ÷ �N (N=0~6) AD�FF A/D Clo�k AN0 AN1 VREFS A/D Refe�en�e Voltage SAD�L A/D Conve�te� A/D Data Registe�s SAD�H AN� ADRFS 1.19V SACS4，SACS�~SACS0 START E�CB VSS AD�FF V119EN A/D Converter Structure A/D Converter Register Description Overall operation of the A/D converter is controlled using several registers. A read only register pair exists to store the A/D converter data 12-bit value. The remaining two registers are control registers which setup the operating and control function of the A/D converter. Register Name Bit 7 6 5 4 3 2 1 0 ADRH (ADRFS=0) D11 D10 D9 D8 D7 D6 D5 D4 ADRL (ADRFS=0) D3 D2 D1 D0 — — — — ADRH (ADRFS=1) — — — — D11 D10 D9 D8 ADRL (ADRFS=1) D7 D6 D5 D4 D3 D2 D1 D0 ADCR0 START EOCB ADOFF ADRFS — ACS2 ACS1 ACS0 ADCR1 ACS4 V119EN — VREFS — ADCK2 ADCK1 ADCK0 ACERL ACE7 ACE6 ACE5 ACE4 ACE3 ACE2 ACE1 ACE0 A/D Converter Register List Rev. 1.00 71 October 27, 2017 BS84B08C Touch A/D Flash MCU A/D Converter Data Registers – ADRL, ADRH As the device contains an internal 12-bit A/D converter, they require two data registers to store the converted value. These are a high byte register, known as ADRH, and a low byte register, known as ADRL. After the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitized conversion value. As only 12 bits of the 16-bit register space is utilized, the format in which the data is stored is controlled by the ADRFS bit in the ADCR0 register as shown in the accompanying table. D0~D11 are the A/D conversion result data bits. Any unused bits will be read as zero. ADRH ADRFS ADRL 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 1 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A/D Data Registers A/D Converter Control Registers – ADCR0, ADCR1, ACERL To control the function and operation of the A/D converter, three control registers known as ADCR0, ADCR1, ACERL are provided. These 8-bit registers define functions such as the selection of which analog channel is connected to the internal A/D converter, the digitized data format, the A/D clock source as well as controlling the start function and monitoring the A/D converter end of conversion status. The ACS2~ACS0 bits in the ADCR0 register and ACS4 bit is the ADCR1 register define the A/D converter input channel number. As the device contains only one actual analog to digital converter hardware circuit, each of the individual 8 analog inputs must be routed to the converter. It is the function of the ACS4 and ACS2~ACS0 bits to determine which analog channel input signals or internal 1.19V is actually connected to the internal A/D converter. The ACERL control register contains the ACE7~ACE0 bits which determine which pins on Port D are used as analog inputs for the A/D converter input and which pins are not to be used as the A/D converter input. Setting the corresponding bit high will select the A/D input function, clearing the bit to zero will select either the I/O or other pin-shared function. When the pin is selected to be an A/D input, its original function whether it is an I/O or other pin-shared function will be removed. In addition, any internal pull-high resistors connected to these pins will be automatically removed if the pin is selected to be an A/D input. • ADCR0 Register Rev. 1.00 Bit 7 6 5 4 3 2 1 0 Name START EOCB ADOFF ADRFS — ACS2 ACS1 ACS0 R/W R/W R R/W R/W — R/W R/W R/W POR 0 1 1 0 — 0 0 0 Bit 7 START: Start the A/D conversion 0→1→0: Start This bit is used to initiate an A/D conversion process. The bit is normally low but if set high and then cleared low again, the A/D converter will initiate a conversion process. When the bit is set high the A/D converter will be reset. Bit 6 EOCB: End of A/D conversion flag 0: A/D conversion ended 1: A/D conversion is in progress This read only flag is used to indicate when an A/D conversion process has completed. When the conversion process running the bit will be high. 72 October 27, 2017 BS84B08C Touch A/D Flash MCU Bit 5 ADOFF: A/D converter module power on/off control bit 0: A/D converter module power on 1: A/D converter module power off This bit controls the power to the A/D internal function. This bit should be cleared to zero to enable the A/D converter. If the bit is set high then the A/D converter will be switched off reducing the device power consumption. As the A/D converter will consume a limited amount of power, even when not executing a conversion, this may be an important consideration in power sensitive battery powered applications. Note that it is recommended to set ADOFF=1 before entering IDLE/SLEEP Mode for saving power. Bit 4 ADRFS: A/D converter data format selection 0: A/D converter data format → ADRH = D[11:4]; ADRL = D[3:0] 1: A/D converter data format → ADRH = D[11:8]; ADRL = D[7:0] This bit controls the format of the 12-bit converted A/D value in the two A/D data registers. Details are provided in the A/D data register section. Bit 3 Unimplemented, read as "0" Bit 2~0 ACS2~ACS0: A/D converter analog channel input select when ACS4 is "0" 000: AN0 001: AN1 010: AN2 011: AN3 100: AN4 101: AN5 110: AN6 111: AN7 These are the A/D converter analog channel input select control bits. As there is only one internal hardware A/D converter each of the eight A/D inputs must be routed to the internal converter using these bits. If bit ACS4 in the ADCR1 register is set high then the internal 1.19V will be routed to the A/D Converter. • ADCR1 Register Rev. 1.00 Bit 7 6 5 4 3 2 1 0 Name ACS4 V119EN — VREFS — ADCK2 ADCK1 ADCK0 R/W R/W R/W — R/W — R/W R/W R/W POR 0 0 — 0 — 0 0 0 Bit 7 ACS4: Select Internal 1.19V as A/D converter input signal control 0: Disable 1: Enable This bit enables 1.19V to be connected to the A/D converter. The V119EN bit must first have been set to enable the bandgap circuit 1.19V voltage to be used by the A/D converter. When the ACS4 bit is set high, the bandgap 1.19V voltage will be routed to the A/D converter and the other A/D input channels disconnected. Bit 6 V119EN: Internal 1.19V Control 0: Disable 1: Enable This bit controls the internal bandgap circuit on/off function to the A/D converter. When the bit is set high the bandgap 1.19V voltage can be used by the A/D converter. If 1.19V is not used by the A/D converter and the LVR function is disabled then the bandgap reference circuit will be automatically switched off to conserve power. When 1.19V is switched on for use by the A/D converter, a time tBG should be allowed for the bandgap circuit to stabilise before implementing an A/D conversion. Bit 5 Unimplemented, read as "0" 73 October 27, 2017 BS84B08C Touch A/D Flash MCU Bit 4 VREFS: A/D converter reference voltage select 0: Internal A/D converter power, VDD 1: From external VREF pin This bit is used to select the A/D converter reference voltage. If the bit is high then the A/D converter reference voltage is supplied on the external VREF pin. If the pin is low then the internal reference is used which is taken from the power supply pin VDD. Bit 3 Unimplemented, read as "0" Bit 2~0 ADCK2~ADCK0: A/D conversion clock source select 000: fSYS 001: fSYS/2 010: fSYS/4 011: fSYS/8 100: fSYS/16 101: fSYS/32 110: fSYS/64 111: Undefined These three bits are used to select the clock source for the A/D converter. • ACERL Register Rev. 1.00 Bit 7 6 5 4 3 2 1 0 Name ACE7 ACE6 ACE5 ACE4 ACE3 ACE2 ACE1 ACE0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 1 1 1 1 1 1 Bit 7 ACE7: AN7 input pin enable control 0: Disable – not A/D input 1: Enable – A/D input, AN7 Bit 6 ACE6: AN6 input pin enable control 0: Disable – not A/D input 1: Enable – A/D input, AN6 Bit 5 ACE5: AN5 input pin enable control 0: Disable – not A/D input 1: Enable – A/D input, AN5 Bit 4 ACE4: AN4 input pin enable control 0: Disable – not A/D input 1: Enable – A/D input, AN4 Bit 3 ACE3: AN3 input pin enable control 0: Disable – not A/D input 1: Enable – A/D input, AN3 Bit 2 ACE2: AN2 input pin enable control 0: Disable – not A/D input 1: Enable – A/D input, AN2 Bit 1 ACE1: AN1 input pin enable control 0: Disable – not A/D input 1: Enable – A/D input, AN1 Bit 0 ACE0: AN0 input pin enable control 0: Disable – not A/D input 1: Enable – A/D input, AN0 74 October 27, 2017 BS84B08C Touch A/D Flash MCU A/D Converter Reference Voltage The reference voltage supply to the A/D Converter can be supplied from either the positive power supply pin, VDD, or from an external reference sources supplied on pin VREF. The desired selection is made using the VREFS bit. As the VREF pin is pin-shared with other functions, when the VREFS bit is set high, the VREF pin function will be selected and the other pin functions will be disabled automatically. A/D Converter Input Pins All of the A/D analog input pins are pin-shared with the I/O pins on Port D as well as other functions. The ACE7~ACE0 bits in the ACERL registers, determine whether the input pins are setup as A/D converter analog inputs or whether they have other functions. If the ACE7~ACE0 bits for its corresponding pin is set high then the pin will be setup to be an A/D converter input and the original pin functions disabled. In this way, pins can be changed under program control to change their function between A/D inputs and other functions. All pull-high resistors, which are setup through register programming, will be automatically disconnected if the pins are setup as A/D inputs. Note that it is not necessary to first setup the A/D pin as an input in the PDC port control register to enable the A/D input as when the ACE7~ACE0 bits enable an A/D input, the status of the port control register will be overridden. The A/D converter has its own reference voltage pin, VREF, however the reference voltage can also be supplied from the power supply pin, a choice which is made through the VREFS bit in the ADCR1 register. The analog input values must not be allowed to exceed the value of VREF. AN0 AN� 1.19V SACS4� SACS�~SACS0 Input Voltage 1�-�it A/D �onve�te� Buffe� V119EN VREFS VDD VREF VREF Bandgap Refe�en�e Voltage A/D Converter Input Structure A/D Converter Operation The START bit in the ADCR0 register is used to start the A/D conversion. When the microcontroller sets this bit from low to high and then low again, an analog to digital conversion cycle will be initiated. The EOCB bit in the ADCR0 register is used to indicate whether the analog to digital conversion process is in progress or not. This bit will be automatically set to "0" by the microcontroller after a conversion cycle has ended. In addition, the corresponding A/D interrupt request flag will be set in the interrupt control register, and if the interrupts are enabled, an appropriate internal interrupt signal will be generated. This A/D internal interrupt signal will direct the program flow to the associated A/D internal interrupt address for processing. If the A/D internal interrupt is disabled, the microcontroller can be used to poll the EOCB bit in the ADCR0 register to check whether it has been cleared as an alternative method of detecting the end of an A/D conversion cycle. Rev. 1.00 75 October 27, 2017 BS84B08C Touch A/D Flash MCU The clock source for the A/D converter, which originates from the system clock fSYS, can be chosen to be either fSYS or a subdivided version of fSYS. The division ratio value is determined by the ADCK2~ADCK0 bits in the ADCR1 register. Although the A/D converter clock source is determined by the system clock fSYS, and by bits ADCK2~ADCK0, there are some limitations on the maximum A/D clock source speed that can be selected. As the minimum value of permissible A/D clock period, tADCK, is from 0.5μs~10μs, care must be taken for system clock frequencies. For example, if the system clock operates at a frequency of 4MHz, the ADCK2~ADCK0 bits should not be set to 000B or 110B. Doing so will give A/D clock periods that are less than the minimum A/D clock period or greater than the maximum A/D clock period which may result in inaccurate A/D conversion values. Refer to the following table for examples, where values marked with an asterisk * show where, depending upon the device, special care must be taken, as the values may be less or larger than the specified A/D Clock Period range. A/D Clock Period (tADCK) fSYS ADCK[2:0] ADCK[2:0] ADCK[2:0] ADCK[2:0] ADCK[2:0] ADCK[2:0] ADCK[2:0] ADCK[2:0] = 000 = 001 = 010 = 011 = 100 = 101 = 110 = 111 (fSYS) (fSYS/2) (fSYS/4) (fSYS/8) (fSYS/16) (fSYS/32) (fSYS/64) 1MHz 1μs 2μs 4μs 8μs 16μs * 32μs * 64μs * Undefined 2MHz 500ns 1μs 2μs 4μs 8μs 16μs * 32μs * Undefined 4MHz 250ns * 500ns 1μs 2μs 4μs 8μs 16μs * Undefined 8MHz 125ns * 250ns * 500ns 1μs 2μs 4μs 8μs Undefined 12MHz 83ns* 167ns* 333ns* 667ns 1.33μs 2.67μs 5.33μs Undefined 16MHz 62.5ns* 125ns* 250ns* 500ns 1μs 2μs 4μs Undefined A/D Clock Period Examples Controlling the power on/off function of the A/D converter circuitry is implemented using the ADOFF bit in the ADCR0 register. This bit must be zero to power on the A/D converter. When the ADOFF bit is cleared to zero to power on the A/D converter internal circuitry a certain delay, as indicated in the timing diagram, must be allowed before an A/D conversion is initiated. Even if no pins are selected for use as A/D inputs by clearing the ACE7~ACE0 bits in the ACERL registers, if the ADOFF bit is zero then some power will still be consumed. In power conscious applications it is therefore recommended that the ADOFF is set high to reduce power consumption when the A/D converter function is not being used. Conversion Rate and Timing Diagram A complete A/D conversion contains two parts, data sampling and data conversion. The data sampling which is defined as tADS takes 4 A/D clock cycles and the data conversion takes 12 A/D clock cycles. Therefore a total of 16 A/D clock cycles for an external input A/D conversion which is defined as tADC are necessary. Maximum single A/D conversion rate = A/D clock period÷16 The accompanying diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing. After an A/D conversion process has been initiated by the application program, the microcontroller internal hardware will begin to carry out the conversion, during which time the program can continue with other functions. The time taken for the A/D conversion is 16 tADCK clock cycles where tADCK is equal to the A/D clock period. Rev. 1.00 76 October 27, 2017 BS84B08C Touch A/D Flash MCU AD�FF A/D Conve�te� Module �n t�N�ST off on off A/D sampling time tADS A/D sampling time tADS Sta�t of A/D �onve�sion Sta�t of A/D �onve�sion End of A/D �onve�sion End of A/D �onve�sion on START E�CB ACS4� ACS[�:0] 011B A/D �hannel swit�h 010B 000B tADC A/D �onve�sion time tADC A/D �onve�sion time Sta�t of A/D �onve�sion 001B tADC A/D �onve�sion time A/D Conversion Timing Summary of A/D Conversion Steps The following summarises the individual steps that should be executed in order to implement an A/D conversion process. • Step 1 Select the required A/D conversion clock by correctly programming bits ADCK2~ADCK0 in the ADCR1 register. • Step 2 Enable the A/D converter by clearing the ADOFF bit in the ADCR0 register to zero. • Step 3 Select which channel is to be connected to the internal A/D converter by correctly programming the ACS4, ACS2~ACS0 bits which are also contained in the ADCR1 and ADCR0 register. • Step 4 Select which pins are to be used as A/D converter inputs and configure them by correctly programming the ACE7~ACE0 bits are in the ACERL register. • Step 5 If the interrupts are to be used, the interrupt control registers must be correctly configured to ensure the A/D converter interrupt function is active. The master interrupt control bit, EMI, and the A/D converter interrupt bit, ADE, must both be set high to do this. • Step 6 The analog to digital conversion process can now be initialised by setting the START bit in the ADCR0 register from low to high and then low again. Note that this bit should have been originally cleared to zero. • Step 7 To check when the analog to digital conversion process is complete, the EOCB bit in the ADCR0 register can be polled. The conversion process is complete when this bit goes low. When this occurs the A/D converter data registers ADRL and ADRH can be read to obtain the conversion value. As an alternative method, if the interrupts are enabled and the stack is not full, the program can wait for an A/D interrupt to occur. Note: When checking for the end of the conversion process, if the method of polling the EOCB bit in the ADCR0 register is used, the interrupt enable step above can be omitted. Rev. 1.00 77 October 27, 2017 BS84B08C Touch A/D Flash MCU Programming Considerations During microcontroller operations where the A/D converter is not being used, the A/D internal circuitry can be switched off to reduce power consumption, by setting bit ADOFF high in the ADCR0 register. When this happens, the internal A/D converter circuits will not consume power irrespective of what analog voltage is applied to their input lines. If the A/D converter input lines are used as normal I/Os, then care must be taken as if the input voltage is not at a valid logic level, then this may lead to some increase in power consumption. A/D Conversion Function As the device contains a 12-bit A/D converter, its full-scale converted digitised value is equal to FFFH. Since the full-scale analog input value is equal to the actual A/D converter reference voltage, VREF, this gives a single bit analog input value of VREF divided by 4096. 1 LSB = VREF ÷ 4096 The A/D Converter input voltage value can be calculated using the following equation: A/D input voltage = A/D output digital value × (VREF ÷ 4096) The diagram shows the ideal transfer function between the analog input value and the digitised output value for the A/D converter. Except for the digitised zero value, the subsequent digitised values will change at a point 0.5 LSB below where they would change without the offset, and the last full scale digitised value will change at a point 1.5 LSB below the VREF level. Note that here the VREF voltage is the actual A/D converter reference voltage determined by the VREFS bit in the ADCR1 register. 1.5 LSB FFFH FFEH FFDH A/D Conversion Result 03H 0.5 LSB 0�H 01H 0 1 � 3 4093 4094 4095 4096 VREF 4096 Analog Input Voltage Ideal A/D Transfer Function Rev. 1.00 78 October 27, 2017 BS84B08C Touch A/D Flash MCU A/D Conversion Programming Examples The following two programming examples illustrate how to setup and implement an A/D conversion. In the first example, the method of polling the EOCB bit in the ADCR0 register is used to detect when the conversion cycle is complete, whereas in the second example, the A/D interrupt is used to determine when the conversion is complete. Example: using an EOCB polling method to detect the end of conversion clr ADE ; disable A/D interrupt mov a,03H mov ADCR1,a ; select fSYS/8 as A/D clock and switch off 1.19V clr ADOFF mov a,0Fh ; setup ACERL to configure pins AN0~AN7 mov ACERL,a mov a,01h mov ADCR0,a ; enable and connect AN0 channel to A/D converter : start_conversion: clr START ; high pulse on start bit to initiate conversion set START ; reset A/D clr START ; start A/D polling_EOC: sz EOCB ; poll the ADCR0 register EOCB bit to detect end of A/D conversion jmp polling_EOC ; continue polling mov a,ADRL ; read low byte conversion result value mov ADRL_buffer,a ; save result to user defined register mov a,ADRH ; read high byte conversion result value mov ADRH_buffer,a ; save result to user defined register : : jmp start_conversion ; start next A/D conversion Rev. 1.00 79 October 27, 2017 BS84B08C Touch A/D Flash MCU Example: using the interrupt method to detect the end of conversion clr ADE ; disable A/D interrupt mov a,03H mov ADCR1,a ; select fSYS/8 as A/D clock and switch off 1.19V clr ADOFF mov a,0Fh ; setup ACERL to configure pins AN0~AN7 mov ACERL,a mov a,01h mov ADCR0,a ; enable and connect AN0 channel to A/D converter Start_conversion: clr START ; high pulse on START bit to initiate conversion set START ; reset A/D clr START ; start A/D clr ADF ; clear A/D interrupt request flag set ADE ; enable A/D interrupt set EMI ; enable global interrupt : : ; ADC interrupt service routine ADC_ISR: mov acc_stack,a ; save ACC to user defined memory mov a,STATUS mov status_stack,a ; save STATUS to user defined memory : : mov a,ADRL ; read low byte conversion result value mov adrl_buffer,a ; save result to user defined register mov a,ADRH ; read high byte conversion result value mov adrh_buffer,a ; save result to user defined register : : EXIT_INT_ISR: mov a,status_stack mov STATUS,a ; restore STATUS from user defined memory mov a,acc_stack ; restore ACC from user defined memory reti Rev. 1.00 80 October 27, 2017 BS84B08C Touch A/D Flash MCU Touch Key Function The device provides multiple Touch Key functions. The Touch Key function is fully integrated and requires no external components, allowing Touch Key functions to be implemented by the simple manipulation of internal registers. Touch Key Structure The Touch Keys are pin shared with the PB logic I/O pins, with the desired function chosen via register bits. Keys are organised into two groups, with each group known as a module and having a module number, M0 to M1. Each module is a fully independent set of four Touch Keys and each Touch Key has its own oscillator. Each module contains its own control logic circuits and register set. Examination of the register names will reveal the module number it is referring to. Keys Touch Key Module Touch Key Shared I/O Pin M0 KEY 1~KEY 4 PB0~PB3 M1 KEY 5~KEY 8 PB4~PB7 8 Touch Key Structure Tou�h Key Module n Key KEY 1 �SC Key KEY � �SC Mux. 33MHz Analog Filte� Multif�equen�y 16-�it C/F Counte� TKCF�V Key KEY 3 �SC MnDFEN MnFILEN Key KEY 4 �SC MnK4EN~MnK1EN MnK�EN MnMXS1~MnMXS0 MnTSS MnFILEN MnR�EN fCFTMCK Refe�en�e �s�illato� 33MHz Analog Filte� fSYS/4 M U X TKTMR 8-�it time slot time� �ounte� 5-�it �ounte� TKRC�V TKMnR�H/TKMnR�L TKTMR 8-�it time slot time� �ounte� p�eload �egiste� �ve�flow fSYS fSYS/� fSYS/4 fSYS/8 M U X 16-�it Counte� TK16�V TK16DL/TK16DH TK16S1~TK16S0 Notes: 1. The structure contained in the dash line is identical for each touch key module which contains four touch keys. 2. Need to set MnTSS=0 & MnROEN=1 or MnTSS=1, the touch key function 16-bit counter (TK16DH/ TK16DL) will count properly. Touch Key Module Block Diagram (n=0~1) Rev. 1.00 81 October 27, 2017 BS84B08C Touch A/D Flash MCU Touch Key Register Definition Each Touch Key module, which contains four Touch Key functions, has its own suite registers. The following table shows the register set for each Touch Key module. The Mn within the register name refers to the Touch Key module numbers, this device has a range of M0 to M1. Register Name TKTMR Description Touch key time slot 8-bit counter preload register TKC0 Touch key function control register 0 TKC1 Touch key function control register 1 TK16DL Touch key function 16-bit counter low byte TK16DH Touch key function 16-bit counter high byte TKMn16DL Touch key module n 16-bit C/F counter low byte TKMn16DH Touch key module n 16-bit C/F counter high byte TKMnROL Touch key module n reference oscillator capacitor select low byte TKMnROH Touch key module n reference oscillator capacitor select high byte TKMnC0 Touch key module n control register 0 TKMnC1 Touch key module n control register 1 Touch Key Function Register Definition (n=0~1) Bit Register Name 7 6 5 4 3 2 1 0 TKTMR D7 D6 D5 D4 D3 D2 D1 D0 TKC0 — TKRCOV TKST TSCS TK16S1 TK16S0 TKC1 — — — TKCFOV TK16OV — — — TKFS1 TKFS0 TK16DL D7 D6 D5 D4 D3 D2 D1 D0 TK16DH D15 D14 D13 D12 D11 D10 D9 D8 TKMn16DL D7 D6 D5 D4 D3 D2 D1 D0 TKMn16DH D15 D14 D13 D12 D11 D10 D9 D8 TKMnROL D7 D6 D5 D4 D3 D2 D1 D0 — — — — — — D9 D8 TKMnROH TKMnC0 TKMnC1 MnMXS1 MnMXS0 MnDFEN MnFILEN MnSOFC MnSOF2 MnSOF1 MnSOF0 MnTSS — MnROEN MnKOEN MnK4EN MnK3EN MnK2EN MnK1EN Touch Key Function Register List (n=0~1) • TKTMR Register Bit 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 Rev. 1.00 7 D7~D0: Touch Key time slot 8-bit counter preload register The touch key time slot counter preload register is used to determine the touch key time slot overflow time. The time slot unit period is obtained by a 5-bit counter and equal to 32 time slot clock cycles. Therefore, the time slot counter overflow time is equal to the following equation shown. Time slot counter overflow time = (256 - TKTMR[7:0]) × 32tTSC, where tTSC is the time slot counter clock period. 82 October 27, 2017 BS84B08C Touch A/D Flash MCU • TKC0 Register Bit 7 6 5 4 3 2 1 0 Name — TKRCOV TKST TKCFOV TK16OV TSCS TK16S1 TK16S0 R/W — R/W R/W R/W R/W R/W R/W R/W POR — 0 0 0 0 0 0 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1~0 Unimplemented, read as "0" TKRCOV: Time slot counter overflow flag 0: No overflow 1: Overflow If module 0 or all module time slot counter, selected by the TSCS bit, is overflow, the Touch Key Interrupt request flag, TKMF, will be set and all module keys and reference oscillators will automatically stop. The touch key module n 16-bit C/F counter, touch key function 16-bit counter, 5-bit time slot counter and 8-bit time slot timer counter will be automatically switched off. Note that this bit can not be set by application program but must be cleared to 0 by application program. TKST: Start Touch Key detection control bit 0: Stopped or no operation 0→1: Started The touch key module n 16-bit C/F counter, touch key function 16-bit counter and 5-bit time slot unit period counter will be automatically cleared when this bit is cleared to zero. However, the 8-bit programmable time slot counter will not be cleared, which overflow time is setup by user. When this bit changes from low to high, the touch key module n 16-bit C/F counter, touch key function 16-bit counter, 5-bit time slot unit period counter and 8-bit time slot timer counter will be automatically on and enable key and reference oscillators to drive the corresponding counters. TKCFOV: Touch Key module n 16-bit C/F counter overflow flag 0: Not overflow 1: Overflow This bit is set by touch key module n 16-bit C/F counter overflow and must be cleared to 0 by application program. TK16OV: Touch Key function 16-bit counter overflow flag 0: Not overflow 1: Overflow This bit is set by touch key function 16-bit counter overflow and must be cleared to 0 by application program. TSCS: Touch Key time slot counter selection 0: Each Module uses its own time slot counter 1: All Touch Key Module use Module 0 time slot counter TK16S1~TK16S0: The Touch Key function 16-bit counter clock source selection 00: fSYS 01: fSYS/2 10: fSYS/4 11: fSYS/8 • TKC1 Register Rev. 1.00 Bit 7 6 5 4 3 2 1 0 Name — — — — — — TKFS1 TKFS0 R/W — — — — — — R/W R/W POR — — — — — — 1 1 Bit 7~2 Unimplemented, read as "0" Bit 1~0 TKFS1~TKFS0: Touch key oscillator and Reference oscillator frequency selection 00: 1MHz 01: 3MHz 10: 7MHz 11: 11MHz 83 October 27, 2017 BS84B08C Touch A/D Flash MCU • TK16DH/TK16DL – Touch Key Function 16-bit Counter Register Pair Register Bit Name TK16DH 7 6 5 4 TK16DL 3 2 1 D15 D14 D13 D12 D11 D10 D9 0 7 6 5 4 3 2 1 0 D8 D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R R R R R R R R R POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 The TK16DH/TK16DL register pair is used to store the touch key function 16-bit counter value. This 16-bit counter can be used to calibrate the reference or key oscillator frequency. When the touch key time slot counter overflows, this 16-bit counter will be stopped and the counter content will be unchanged. This register pair will be cleared to zero when the TKST bit is set low. • TKMn16DH/TKMn16DL – Touch Key Module n 16-bit C/F Counter Register Pair Register Bit Name TKMn16DH 7 6 5 4 3 TKMn16DL 2 1 D15 D14 D13 D12 D11 D10 D9 0 7 6 5 4 3 2 1 0 D8 D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R R R R R R R R R POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 The TKMn16DH/TKMn16DLregister pair is used to store the touch key module n 16-bit C/ F counter value. This 16-bit C/F counter will be stopped and the counter content will be kept unchanged when the touch key time slot counter overflows. This register pair will be cleared to zero when the TKST bit is set low. • TKMnROH/TKMnROL – Touch Key Module n Reference Oscillator Capacitor Select Register Pair Register TKMnROH TKMnROL Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 R/W — — — — — — POR — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 0 0 The TKMnROH/TKMnROL register pair is used to store the touch key module n reference oscillator capacitor value. This register pair will be loaded with the corresponding next time slot capacitor value from the dedicated touch key data memory at the end of the current time slot. The reference oscillator internal capacitor value=(TKMnRO[9:0]×50pF)/1024 • TKMnC0 Register Bit Name 7 6 5 4 2 1 0 MnSOF1 MnSOF0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 MnMXS1~MnMXS0: Touch key module n Multiplexer Key selection Bit Rev. 1.00 3 MnMXS1 MnMXS0 MnDFEN MnFILEN MnSOFC MnSOF2 Module Number MnMXS1 MnMXS0 M0 M1 0 0 KEY 1 KEY 5 0 1 KEY 2 KEY 6 1 0 KEY 3 KEY 7 1 1 KEY 4 KEY 8 84 October 27, 2017 BS84B08C Touch A/D Flash MCU Bit 5 MnDFEN: Touch key module n Multi-frequency control 0: Disable 1: Enable This bit is used to control the touch key oscillator frequency doubling function. When this bit is set to 1, the key oscillator frequency will be doubled. Bit 4 MnFILEN: Touch key module n filter function control 0: Disable 1: Enable Bit 3 MnSOFC: Touch key module n 16-bit C/F oscillator frequency hopping function control 0: The frequency hopping function is controlled by MnSOF2~MnSOF0 bits 1: The frequency hopping function is controlled by hardware regardless of what is the state of MnSOF2~MnSOF0 bits This bit is used to select the touch key oscillator frequency hopping function control method. When this bit is set to 1, the key oscillator frequency hopping function is controlled by the hardware circuit regardless of the MSOF2~MSOF0 bits value. Bit 2~0 MnSOF2~MnSOF0: Touch Key module n Reference and Key oscillators hopping frequency selection 000: 1.020MHz 001: 1.040MHz 010: 1.059MHz 011: 1.074MHz 100: 1.085MHz 101: 1.099MHz 110: 1.111MHz 111: 1.125MHz These bits are used to select the Touch Key oscillator frequency for the hopping function. Note that these bits are only available when the MnSOFC bit is cleared to 0. The frequency which is mentioned here will be changed when the external or internal capacitor is with different value. If the Touch Key operates at 1MHz frequency, users can adjust the frequency in scale when select other frequency. • TKMnC1 Register Bit 7 6 Name MnTSS — R/W R/W — R/W R/W POR 0 — 0 0 4 3 2 1 0 MnK3EN MnK2EN MnK1EN R/W R/W R/W R/W 0 0 0 0 Bit 7 MnTSS: Touch key module n time slot counter clock source selection 0: Touch key module n reference oscillator 1: fSYS/4 Bit 6 Unimplemented, read as "0" Bit 5 MnROEN: Touch key module n reference oscillator enable control bit 0: Disable 1: Enable Bit 4 MnKOEN: Touch key module n Key oscillator enable control bit 0: Disable 1: Enable Bit 3 MnK4EN: Touch key module n Key 4 enable control MnK4EN 0: Disable 1: Enable Rev. 1.00 5 MnROEN MnKOEN MnK4EN Touch Key Module n – Mn M0 M1 I/O or other functions KEY4 85 KEY8 October 27, 2017 BS84B08C Touch A/D Flash MCU Bit 2 MnK3EN: Touch key module n Key 3 enable control MnK3EN Touch Key Module n – Mn M0 0: Disable 1: Enable Bit 1 KEY3 KEY7 MnK2EN: Touch key module n Key 2 enable control MnK2EN Touch Key Module n – Mn M0 0: Disable 1: Enable Bit 0 M1 I/O or other functions M1 I/O or other functions KEY2 KEY6 MnK1EN: Touch key module n Key 1 enable control MnK1EN 0: Disable 1: Enable Touch Key Module n – Mn M0 M1 I/O or other functions KEY1 KEY5 Touch Key Operation When a finger touches or is in proximity to a touch pad, the capacitance of the pad will increase. By using this capacitance variation to change slightly the frequency of the internal sense oscillator, touch actions can be sensed by measuring these frequency changes. Using an internal programmable divider the reference clock is used to generate a fixed time period. By counting a number of generated clock cycles from the sense oscillator during this fixed time period Touch Key actions can be determined. The Touch Key sense oscillator and reference oscillator timing diagram is shown in the following figure: TKST MnK�EN MnR�EN Ha�dwa�e set to “0” KEY �SC CLK Refe�en�e �SC CLK fCFTMCK ena�le Time slot �ounte� ove�flow time fCFTMCK (MnDFEN=0) fCFTMCK (MnDFEN=1) TKRC�V Set Tou�h Key inte��upt �equest flag Touch Key Timing Diagram Rev. 1.00 86 October 27, 2017 BS84B08C Touch A/D Flash MCU Each Touch Key module contains four Touch Key inputs which are shared with logical I/O pins, and the desired function is selected using register bits. Each Touch Key has its own independent sense oscillator. There are therefore four sense oscillators within each Touch Key module. During this reference clock fixed interval, the number of clock cycles generated by the sense oscillator is measured, and it is this value that is used to determine if a touch action has been made or not. At the end of the fixed reference clock time interval a Touch Key interrupt signal will be generated. Using the TSCS bit in the TKC0 register can select the module 0 time slot counter as the time slot counter for all modules. All modules use the same started signal, TKST, in the TKC0 register. The touch key module n 16-bit C/F counter, touch key function 16-bit counter, 5-bit time slot unit period counter in all modules will be automatically cleared when this bit is cleared to zero, but the 8-bit programmable time slot counter will not be cleared. The overflow time is setup by user. When this bit changes from low to high, the touch key module n 16-bit C/F counter, touch key function 16-bit counter, 5-bit time slot unit period counter and 8-bit time slot timer counter will be automatically switched on. The key oscillator and reference oscillator in all modules will be automatically stopped and the touch key module n 16-bit C/F counter, touch key function 16-bit counter, 5-bit time slot unit period counter and 8-bit time slot timer counter will be automatically switched off when the 5-bit time slot unit period counter overflows. The clock source for the time slot counter and 8+5 bit counter, is sourced from the reference oscillator or fSYS/4. The reference oscillator and key oscillator will be enabled by setting the MnROEN bit and MnKOEN bits in the TKMnC1 register. When the time slot counter in all the Touch Key modules or in the Touch Key module 0 overflows, an actual Touch Key interrupt will take place. The Touch Keys mentioned here are the keys which are enabled. Each Touch Key module consists of four Touch Keys, KEY 1~KEY 4 are contained in module 0, KEY 5~KEY 8 are contained in module 1. Each Touch Key module has an identical structure. Touch Key Interrupt The Touch Key only has single interrupt, when the time slot counter in all the Touch Key modules or in the Touch Key module 0 overflows, an actual Touch Key interrupt will take place. The Touch Keys mentioned here are the keys which are enabled. The touch key module n 16-bit C/F counter, touch key function 16-bit counter, 5-bit time slot unit period counter and 8-bit time slot counter in all modules will be automatically cleared. The TKCFOV flag which is the touch key module n 16-bit C/F counter overflow flag will go high when the Touch Key Module n 16-bit C/F counter overflows. As this flag will not be automatically cleared, it has to be cleared by the application program. The TK16OV flag which is the touch key function 16-bit counter overflow flag will go high when the touch key function 16-bit counter overflows. As this flag will not be automatically cleared, it has to be cleared by the application program. More details regarding the Touch Key interrupt is located in the interrupt section of the datasheet. Programming Considerations After the relevant registers are setup, the Touch Key detection process is initiated the changing the TKST bit from low to high. This will enable and synchronise all relevant oscillators. The TKRCOV flag, which is the time slot counter flag will go high and remain high until the counter overflows. When this happens an interrupt signal will be generated. When the external Touch Key size and layout are defined, their related capacitances will then determine the sensor oscillator frequency. Rev. 1.00 87 October 27, 2017 BS84B08C Touch A/D Flash MCU Serial Interface Module – SIM The device contains a Serial Interface Module, which includes both the four-line SPI interface or two-line I2C interface types, to allow an easy method of communication with external peripheral hardware. Having relatively simple communication protocols, these serial interface types allow the microcontroller to interface to external SPI or I2C based hardware such as sensors, Flash or EEPROM memory, etc. The SIM interface pins are pin-shared with other I/O pins and therefore the SIM interface functional pins must first be selected using the SIMEN bit in the SIMC0 register. As both interface types share the same pins and registers, the choice of whether the SPI or I2C type is used is made using the SIM operating mode control bits, named SIM2~SIM0, in the SIMC0 register. These pull-high resistors of the SIM pin-shared I/O pins are selected using pull-high control registers when the SIM function is enabled and the corresponding pins are used as SIM input pins. SPI Interface The SPI interface is often used to communicate with external peripheral devices such as sensors, Flash or EEPROM memory devices, etc. Originally developed by Motorola, the four line SPI interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices. The communication is full duplex and operates as a slave/master type, where the device can be either master or slave. Although the SPI interface specification can control multiple slave devices from a single master, the device provides only one SCS pin. If the master needs to control multiple slave devices from a single master, the master can use I/O pin to select the slave devices. SPI Interface Operation The SPI interface is a full duplex synchronous serial data link. It is a four line interface with pin names SDI, SDO, SCK and SCS. Pins SDI and SDO are the Serial Data Input and Serial Data Output lines, SCK is the Serial Clock line and SCS is the Slave Select line. As the SPI interface pins are pin-shared with normal I/O pins and with the I2C function pins, the SPI interface pins must first be selected by setting the correct bits in the SIMC0 and SIMC2 registers. After the desired SPI configuration has been set it can be disabled or enabled using the SIMEN bit in the SIMC0 register. Communication between devices connected to the SPI interface is carried out in a slave/master mode with all data transfer initiations being implemented by the master. The Master also controls the clock signal. As the device only contains a single SCS pin only one slave device can be utilized. The SCS pin is controlled by software, set CSEN bit to 1 to enable SCS pin function, set CSEN bit to 0 the SCS pin will be floating state. The SPI function in this device offers the following features: • Full duplex synchronous data transfer • Both Master and Slave modes • LSB first or MSB first data transmission modes • Transmission complete flag • Rising or falling active clock edge The status of the SPI interface pins is determined by a number of factors such as whether the device is in the master or slave mode and upon the condition of certain control bits such as CSEN and SIMEN. Rev. 1.00 88 October 27, 2017 BS84B08C Touch A/D Flash MCU SPI Maste� SPI Slave SCK SCK SD� SDI SDI SD� SCS SCS SPI Master/Slave Connection Data Bus SIMD SDI Pin TX/RX Shift Registe� SD� Pin Clo�k Edge/Pola�ity Cont�ol CKEG CKP�LB Busy Status SCK Pin Clo�k Sou��e Sele�t fSYS fSUB PTM CCRP mat�h f�equen�y/� SCS Pin WC�L TRF SIMICF CSEN SPI Block Diagram SPI Registers There are three internal registers which control the overall operation of the SPI interface. These are the SIMD data register and two registers SIMC0 and SIMC2. Note that the SIMC1 register is only used by the I2C interface. Bit Register Name 7 6 5 4 SIMC0 SIM2 SIM1 SIM0 — SIMC2 D7 D6 CKPOLB CKEG MLS SIMD D7 D6 D5 D4 D3 3 2 1 0 SIMEN SIMICF CSEN WCOL TRF D2 D1 D0 SIMDEB1 SIMDEB0 SPI Register List • SIMD Register The SIMD register is used to store the data being transmitted and received. The same register is used by both the SPI and I2C functions. Before the device writes data to the SPI bus, the actual data to be transmitted must be placed in the SIMD register. After the data is received from the SPI bus, the device can read it from the SIMD register. Any transmission or reception of data from the SPI bus must be made via the SIMD register. Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x "x": Unknown Rev. 1.00 89 October 27, 2017 BS84B08C Touch A/D Flash MCU There are also two control registers for the SPI interface, SIMC0 and SIMC2. Note that the SIMC2 register also has the name SIMA which is used by the I2C function. The SIMC1 register is not used by the SPI function, only by the I2C function. Register SIMC0 is used to control the enable/disable function and to set the data transmission clock frequency. Register SIMC2 is used for other control functions such as LSB/MSB selection, write collision flag, etc. • SIMC0 Register Bit 7 6 5 4 Name SIM2 SIM1 SIM0 — R/W R/W R/W R/W — R/W POR 1 1 1 — 0 Bit 7~5 Bit 4 Bit 3~2 Bit 1 Bit 0 Rev. 1.00 3 2 1 0 SIMEN SIMICF R/W R/W R/W 0 0 0 SIMDEB1 SIMDEB0 SIM2~SIM0: SIM Operating Mode Control 000: SPI master mode; SPI clock is fSYS /4 001: SPI master mode; SPI clock is fSYS /16 010: SPI master mode; SPI clock is fSYS /64 011: SPI master mode; SPI clock is fSUB 100: SPI master mode; SPI clock is PTM CCRP match frequency/2 101: SPI slave mode 110: I2C slave mode 111: Non SIM function These bits setup the overall operating mode of the SIM function. As well as selecting if the I2C or SPI function, they are used to control the SPI Master/Slave selection and the SPI Master clock frequency. The SPI clock is a function of the system clock but can also be chosen to be sourced from PTM and fSUB. If the SPI Slave Mode is selected then the clock will be supplied by an external Master device. Unimplemented, read as "0" SIMDEB1~SIMDEB0: I2C Debounce Time Selection 00: No debounce 01: 2 system clock debounce 1x: 4 system clock debounce SIMEN: SIM Enable Control 0: Disable 1: Enable The bit is the overall on/off control for the SIM interface. When the SIMEN bit is cleared to zero to disable the SIM interface, the SDI, SDO, SCK and SCS, or SDA and SCL lines will lose their SPI or I2C function and the SIM operating current will be reduced to a minimum value. When the bit is high the SIM interface is enabled. The SIM configuration option must have first enabled the SIM interface for this bit to be effective.If the SIM is configured to operate as an SPI interface via the SIM2~SIM0 bits, the contents of the SPI control registers will remain at the previous settings when the SIMEN bit changes from low to high and should therefore be first initialised by the application program. If the SIM is configured to operate as an I2C interface via the SIM2~SIM0 bits and the SIMEN bit changes from low to high, the contents of the I2C control bits such as HTX and TXAK will remain at the previous settings and should therefore be first initialised by the application program while the relevant I2C flags such as HCF, HAAS, HBB, SRW and RXAK will be set to their default states. SIMICF: SIM Incomplete Flag 0: SIM incomplete condition not occurred 1: SIM incomplete condition occured This bit is only available when the SIM is configured to operate in an SPI slave mode. If the SPI operates in the slave mode with the SIMEN and CSEN bits both being set to 1 but the SCS line is pulled high by the external master device before the SPI data transfer is completely finished, the SIMICF bit will be set to 1 together with the TRF bit. When this condition occurs, the corresponding interrupt will occur if the interrupt function is enabled. However, the TRF bit will not be set to 1 if the SIMICF bit is set to 1 by software application program. 90 October 27, 2017 BS84B08C Touch A/D Flash MCU • SIMC2 Register Rev. 1.00 Bit 7 6 5 4 3 2 1 0 Name D7 D6 CKPOLB CKEG MLS CSEN WCOL TRF R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 D7~D6: Undefined bits These bits can be read or written by the application program. Bit 5 CKPOLB: SPI clock line base condition selection 0: The SCK line will be high when the clock is inactive 1: The SCK line will be low when the clock is inactive The CKPOLB bit determines the base condition of the clock line, if the bit is high, then the SCK line will be low when the clock is inactive. When the CKPOLB bit is low, then the SCK line will be high when the clock is inactive. Bit 4 CKEG: SPI SCK clock active edge type selection CKPOLB=0 0: SCK is high base level and data capture at SCK rising edge 1: SCK is high base level and data capture at SCK falling edge CKPOLB=1 0: SCK is low base level and data capture at SCK falling edge 1: SCK is low base level and data capture at SCK rising edge The CKEG and CKPOLB bits are used to setup the way that the clock signal outputs and inputs data on the SPI bus. These two bits must be configured before data transfer is executed otherwise an erroneous clock edge may be generated. The CKPOLB bit determines the base condition of the clock line, if the bit is high, then the SCK line will be low when the clock is inactive. When the CKPOLB bit is low, then the SCK line will be high when the clock is inactive. The CKEG bit determines active clock edge type which depends upon the condition of CKPOLB bit. Bit 3 MLS: SPI data shift order 0: LSB first 1: MSB first This is the data shift select bit and is used to select how the data is transferred, either MSB or LSB first. Setting the bit high will select MSB first and low for LSB first. Bit 2 CSEN: SPI SCS pin control 0: Disable 1: Enable The CSEN bit is used as an enable/disable for the SCS pin. If this bit is low, then the SCS pin will be disabled and placed into I/O pin or other pin-shared functions. If the bit is high, the SCS pin will be enabled and used as a select pin. Bit 1 WCOL: SPI write collision flag 0: No collision 1: Collision The WCOL flag is used to detect whether a data collision has occurred or not. If this bit is high, it means that data has been attempted to be written to the SIMD register duting a data transfer operation. This writing operation will be ignored if data is being transferred. This bit can be cleared to zero by the application program. Bit 0 TRF: SPI Transmit/Receive complete flag 0: SPI data is being transferred 1: SPI data transfer is completed The TRF bit is the Transmit/Receive Complete flag and is set to 1 automatically when an SPI data transfer is completed, but must cleared to 0 by the application program. It can be used to generate an interrupt. 91 October 27, 2017 BS84B08C Touch A/D Flash MCU SPI Communication After the SPI interface is enabled by setting the SIMEN bit high, then in the Master Mode, when data is written to the SIMD register, transmission/reception will begin simultaneously. When the data transfer is complete, the TRF flag will be set automatically, but must be cleared using the application program. In the Slave Mode, when the clock signal from the master has been received, any data in the SIMD register will be transmitted and any data on the SDI pin will be shifted into the SIMD register. The master should output a SCS signal to enable the slave devices before a clock signal is provided. The slave data to be transferred should be well prepared at the appropriate moment relative to the SCS signal depending upon the configurations of the CKPOLB bit and CKEG bit. The accompanying timing diagram shows the relationship between the slave data and SCS signal for various configurations of the CKPOLB and CKEG bits. The SPI master mode will continue to function even in the IDLE Mode if the selected SPI clock source is running. SIMEN=1� CSEN=0 (Exte�nal Pull-high) SCS SIMEN� CSEN=1 SCK (CKP�LB=1� CKEG=0) SCK (CKP�LB=0� CKEG=0) SCK (CKP�LB=1� CKEG=1) SCK (CKP�LB=0� CKEG=1) SD� (CKEG=0) D�/D0 D6/D1 D5/D� D4/D3 D3/D4 D�/D5 D1/D6 D0/D� SD� (CKEG=1) D�/D0 D6/D1 D5/D� D4/D3 D3/D4 D�/D5 D1/D6 D0/D� SDI Data Captu�e W�ite to SIMD SPI Master Mode Timing SCS SCK (CKP�LB=1) SCK (CKP�LB=0) SD� D�/D0 D6/D1 D5/D� D4/D3 D3/D4 D�/D5 D1/D6 D0/D� SDI Data Captu�e W�ite to SIMD (SD� does not �hange until fi�st SCK edge) SPI Slave Mode Timing – CKEG = 0 Rev. 1.00 92 October 27, 2017 BS84B08C Touch A/D Flash MCU SCS SCK (CKP�LB=1) SCK (CKP�LB=0) SD� D�/D0 D6/D1 D5/D� D4/D3 D3/D4 D�/D5 D1/D6 D0/D� SDI Data Captu�e W�ite to SIMD (SD� �hanges as soon as w�iting o��u�s; SD� is floating if SCS=1) Note: Fo� SPI slave mode� if SIMEN=1 and CSEN=0� SPI is always ena�led and igno�es the SCS level. SPI Slave Mode Timing – CKEG = 1 SPI T�ansfe� Maste� Maste� o� Slave ? A W�ite Data into SIMD Clea� WC�L Slave Y SIM[�:0]=000� 001� 010� 011 o� 100 WC�L=1? SIM[�:0]=101 N N Configu�e CKP�LB� CKEG� CSEN and MLS T�ansmission �ompleted? (TRF=1?) Y SIMEN=1 Read Data f�om SIMD A Clea� TRF T�ansfe� finished? N Y END SPI Transfer Control Flow Chart Rev. 1.00 93 October 27, 2017 BS84B08C Touch A/D Flash MCU SPI Bus Enable/Disable To enable the SPI bus, set CSEN=1 and SCS=0, then wait for data to be written into the SIMD (TXRX buffer) register. For the Master Mode, after data has been written to the SIMD (TXRX buffer) register, then transmission or reception will start automatically. When all the data has been transferred, the TRF bit should be set. For the Slave Mode, when clock pulses are received on SCK, data in the TXRX buffer will be shifted out or data on SDI will be shifted in. When the SPI bus is disabled, SCK, SDI, SDO and SCS can become I/O pins or other pin-shared functions using the corresponding control bits. SPI Operation Steps All communication is carried out using the 4-line interface for either Master or Slave Mode. The CSEN bit in the SIMC2 register controls the overall function of the SPI interface. Setting this bit high will enable the SPI interface by allowing the SCS line to be active, which can then be used to control the SPI interface. If the CSEN bit is low, the SPI interface will be disabled and the SCS line will be in a floating condition and can therefore not be used for control of the SPI interface. If the CSEN bit and the SIMEN bit in the SIMC0 are set high, this will place the SDI line in a floating condition and the SDO line high. If in Master Mode the SCK line will be either high or low depending upon the clock polarity selection bit CKPOLB in the SIMC2 register. If in Slave Mode the SCK line will be in a floating condition. If the SIMEN bit is low, then the bus will be disabled and SCS, SDI, SDO and SCK will all become I/O pins or the other functions using the corresponding control bits. In the Master Mode the Master will always generate the clock signal. The clock and data transmission will be initiated after data has been written into the SIMD register. In the Slave Mode, the clock signal will be received from an external master device for both data transmission and reception. The following sequences show the order to be followed for data transfer in both Master and Slave Mode. Master Mode • Step 1 Select the SPI Master mode and clock source using the SIM2~SIM0 bits in the SIMC0 control register. • Step 2 Setup the CSEN bit and setup the MLS bit to choose if the data is MSB or LSB first, this setting must be the same with the Slave devices. • Step 3 Setup the SIMEN bit in the SIMC0 control register to enable the SPI interface. • Step 4 For write operations: write the data to the SIMD register, which will actually place the data into the TXRX buffer. Then use the SCK and SCS lines to output the data. After this, go to step 5. For read operations: the data transferred in on the SDI line will be stored in the TXRX buffer until all the data has been received at which point it will be latched into the SIMD register. • Step 5 Check the WCOL bit if set high then a collision error has occurred so return to step 4. If equal to zero then go to the following step. • Step 6 Check the TRF bit or wait for a SPI serial bus interrupt. • Step 7 Read data from the SIMD register. • Step 8 Clear TRF. • Step 9 Go to step 4. Rev. 1.00 94 October 27, 2017 BS84B08C Touch A/D Flash MCU Slave Mode • Step 1 Select the SPI Slave mode using the SIM2~SIM0 bits in the SIMC0 control register. • Step 2 Setup the CSEN bit and setup the MLS bit to choose if the data is MSB or LSB first, this setting must be the same with the Master devices. • Step 3 Setup the SIMEN bit in the SIMC0 control register to enable the SPI interface. • Step 4 For write operations: write the data to the SIMD register, which will actually place the data into the TXRX buffer. Then wait for the master clock SCK and SCS signal. After this, go to step 5. For read operations: the data transferred in on the SDI line will be stored in the TXRX buffer until all the data has been received at which point it will be latched into the SIMD register. • Step 5 Check the WCOL bit if set high then a collision error has occurred so return to step 4. If equal to zero then go to the following step. • Step 6 Check the TRF bit or wait for a SPI serial bus interrupt. • Step 7 Read data from the SIMD register. • Step 8 Clear TRF. • Step 9 Go to step 4. Error Detection The WCOL bit in the SIMC2 register is provided to indicate errors during data transfer. The bit is set by the SPI serial Interface but must be cleared by the application program. This bit indicates that a data collision has occurred which happens if a write to the SIMD register takes place during a data transfer operation and will prevent the write operation from continuing. I2C Interface The I 2C interface is used to communicate with external peripheral devices such as sensors, EEPROM memory etc. Originally developed by Philips, it is a two line low speed serial interface for synchronous serial data transfer. The advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications. VDD SDA SCL Devi�e Slave Devi�e Maste� Devi�e Slave I2C Master Slave Bus Connection Rev. 1.00 95 October 27, 2017 BS84B08C Touch A/D Flash MCU I2C interface Operation The I2C serial interface is a two line interface, a serial data line, SDA, and serial clock line, SCL. As many devices may be connected together on the same bus, their outputs are both open drain types. For this reason it is necessary that external pull-high resistors are connected to these outputs. Note that no chip select line exists, as each device on the I2C bus is identified by a unique address which will be transmitted and received on the I2C bus. When two devices communicate with each other on the bidirectional I2C bus, one is known as the master device and one as the slave device. Both master and slave can transmit and receive data, however, it is the master device that has overall control of the bus. For the device, which only operates in slave mode, there are two methods of transferring data on the I2C bus, the slave transmit mode and the slave receive mode. Data Bus I�C Data Registe� (SIMD) fSYS SCL Pin SDA Pin HTX De�oun�e Ci��uit�y SIMDEB[1:0] I�C Add�ess Registe� (SIMA) Add�ess Add�ess Mat�h–HAAS Compa�ato� Di�e�tion Cont�ol Data in MSB M U X Shift Registe� Read/W�ite Slave SRW Data out MSB TXAK 8-�it Data T�ansfe� Complete–HCF T�ansmit/ Re�eive Cont�ol Unit fSUB SIMT�EN I�C Inte��upt Dete�t Sta�t o� Stop HBB SIMT�F Time-out Cont�ol Add�ess Mat�h I2C Block Diagram START signal f�om Maste� Send slave add�ess and R/W �it f�om Maste� A�knowledge f�om slave Send data �yte f�om Maste� A�knowledge f�om slave ST�P signal f�om Maste� Rev. 1.00 96 October 27, 2017 BS84B08C Touch A/D Flash MCU The SIMDEB1 and SIMDEB0 bits determine the debounce time of the I2C interface. This uses the system clock to in effect add a debounce time to the external clock to reduce the possibility of glitches on the clock line causing erroneous operation. The debounce time, if selected, can be chosen to be either 2 or 4 system clocks. To achieve the required I2C data transfer speed, there exists a relationship between the system clock, fSYS, and the I2C debounce time. For either the I2C Standard or Fast mode operation, users must take care of the selected system clock frequency and the configured debounce time to match the criterion shown in the following table. I2C Debounce Time Selection I2C Standard Mode (100kHz) I2C Fast Mode (400kHz) No Devounce fSYS > 2MHz fSYS > 5MHz 2 system clock debounce fSYS > 4MHz fSYS > 10MHz 4 system clock debounce fSYS > 8MHz fSYS > 20MHz I C Minimum fSYS Frequency Requirements 2 I2C Registers There are three control registers associated with the I2C bus, SIMC0, SIMC1 and SIMTOC, one slave address register, SIMA, and one data register, SIMD. The SIMD register, which is shown in the above SPI section, is used to store the data being transmitted and received on the I2C bus. Before the microcontroller writes data to the I2C bus, the actual data to be transmitted must be placed in the SIMD register. After the data is received from the I2C bus, the microcontroller can read it from the SIMD register. Any transmission or reception of data from the I2C bus must be made via the SIMD register. Note that the SIMA register also has the name SIMC2 which is used by the SPI function. Bit SIMEN and bits SIM2~SIM0 in register SIMC0 are used by the I2C interface. Bit Register Name 7 6 5 4 SIMC0 SIM2 SIM1 SIM0 — SIMC1 HCF HAAS HBB HTX TXAK SIMA SIMA6 SIMA5 SIMA4 SIMA3 SIMD D7 D6 D5 D4 3 2 1 0 SIMEN SIMICF SRW IAMWU RXAK SIMA2 SIMA1 SIMA0 D0 D3 D2 D1 D0 SIMDEB1 SIMDEB0 SIMTOC SIMTOEN SIMTOF SIMTOS5 SIMTOS4 SIMTOS3 SIMTOS2 SIMTOS1 SIMTOS0 I2C Register List • SIMD Register The SIMD register is used to store the data being transmitted and received. The same register is used by both the SPI and I2C functions. Before the device writes data to the I2C bus, the actual data to be transmitted must be placed in the SIMD register. After the data is received from the I2C bus, the device can read it from the SIMD register. Any transmission or reception of data from the I2C bus must be made via the SIMD register. Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x "x": Unknown Rev. 1.00 97 October 27, 2017 BS84B08C Touch A/D Flash MCU • SIMA Register The SIMA register is also used by the SPI interface but has the name SIMC2. The SIMA register is the location where the 7-bit slave address of the slave device is stored. Bits 7~1 of the SIMA register define the device slave address. Bit 0 is not defined. When a master device, which is connected to the I2C bus, sends out an address, which matches the slave address in the SIMA register, the slave device will be selected. Note that the SIMA register is the same register address as SIMC2 which is used by the SPI interface. Bit 7 6 5 4 3 2 1 0 Name SIMA6 SIMA5 SIMA4 SIMA3 SIMA2 SIMA1 SIMA0 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x "x": Unknown SIMA6~SIMA0: I2C slave address SIMA6~SIMA0 is the I2C slave address bit 6~bit 0 Bit 0 D0: Undefined bit The bit can be read or written by the application program. There are also three control registers for the I2C interface, SIMC0, SIMC1 and SIMTOC. The register SIMC0 is used to control the enable/disable function and to set the data transmission clock frequency.The SIMC1 register contains the relevant flags which are used to indicate the I2C communication status. The SIMTOC register is used to control the I2C bus time-out function which is described in the I2C Time-out Control section. Bit 7~1 • SIMC0 Register Bit 7 6 5 4 Name SIM2 SIM1 SIM0 — R/W R/W R/W R/W — R/W R/W POR 1 1 1 — 0 0 Bit 7~5 Bit 4 Bit 3~2 Bit 1 Rev. 1.00 3 2 SIMDEB1 SIMDEB0 1 0 SIMEN SIMICF R/W R/W 0 0 SIM2~SIM0: SIM Operating Mode Control 000: SPI master mode; SPI clock is fSYS/4 001: SPI master mode; SPI clock is fSYS/16 010: SPI master mode; SPI clock is fSYS/64 011: SPI master mode; SPI clock is fSUB 100: SPI master mode; SPI clock is PTM CCRP match frequency/2 101: SPI slave mode 110: I2C slave mode 111: Non SIM function These bits setup the overall operating mode of the SIM function. As well as selecting if the I2C or SPI function, they are used to control the SPI Master/Slave selection and the SPI Master clock frequency. The SPI clock is a function of the system clock but can also be chosen to be sourced from PTM or fSUB. If the SPI Slave Mode is selected then the clock will be supplied by an external Master device. Unimplemented, read as "0" SIMDEB1~SIMDEB0: I2C Debounce Time Selection 00: No debounce 01: 2 system clock debounce 1x: 4 system clock debounce SIMEN: SIM Enable Control 0: Disable 1: Enable The bit is the overall on/off control for the SIM interface. When the SIMEN bit is cleared to zero to disable the SIM interface, the SDI, SDO, SCK and SCS, or SDA and SCL lines will lose their SPI or I2C function and the SIM operating current will be reduced to a minimum value. When the bit is high the SIM interface is enabled. The SIM configuration option must have first enabled the SIM interface for this bit to be 98 October 27, 2017 BS84B08C Touch A/D Flash MCU Bit 0 effective.If the SIM is configured to operate as an SPI interface via the SIM2~SIM0 bits, the contents of the SPI control registers will remain at the previous settings when the SIMEN bit changes from low to high and should therefore be first initialised by the application program. If the SIM is configured to operate as an I2C interface via the SIM2~SIM0 bits and the SIMEN bit changes from low to high, the contents of the I2C control bits such as HTX and TXAK will remain at the previous settings and should therefore be first initialised by the application program while the relevant I2C flags such as HCF, HAAS, HBB, SRW and RXAK will be set to their default states. SIMICF: SIM Incomplete Flag 0: SIM incomplete condition not occurred 1: SIM incomplete condition occured This bit is only available when the SIM is configured to operate in an SPI slave mode. If the SPI operates in the slave mode with the SIMEN and CSEN bits both being set to 1 but the SCS line is pulled high by the external master device before the SPI data transfer is completely finished, the SIMICF bit will be set to 1 together with the TRF bit. When this condition occurs, the corresponding interrupt will occur if the interrupt function is enabled. However, the TRF bit will not be set to 1 if the SIMICF bit is set to 1 by software application program. • SIMC1 Register Rev. 1.00 Bit 7 6 5 4 3 2 1 0 Name HCF HAAS HBB HTX TXAK SRW IAMWU RXAK R/W R R R R/W R/W R/W R/W R POR 1 0 0 0 0 0 0 1 Bit 7 HCF: I C Bus data transfer completion flag 0: Data is being transferred 1: Completion of an 8-bit data transfer The HCF flag is the data transfer flag. This flag will be zero when data is being transferred. Upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated. Bit 6 HAAS: I2C Bus data transfer completion flag 0: Not address match 1: Address match The HAAS flag is the address match flag. This flag is used to determine if the slave device address is the same as the master transmit address. If the addresses match then this bit will be high, if there is no match then the flag will be low. Bit 5 HBB: I2C Bus busy flag 0: I2C Bus is not busy 1: I2C Bus is busy The HBB flag is the I2C busy flag. This flag will be "1" when the I2C bus is busy which will occur when a START signal is detected. The flag will be set to "0" when the bus is free which will occur when a STOP signal is detected. Bit 4 HTX: I2C slave device transmitter/receiver selection 0: Slave device is the receiver 1: Slave device is the transmitter Bit 3 TXAK: I2C bus transmit acknowledge flag 0: Slave send acknowledge flag 1: Slave does not send acknowledge flag The TXAK bit is the transmit acknowledge flag. After the slave device receipt of 8-bits of data, this bit will be transmitted to the bus on the 9th clock from the slave device. The slave device must always set TXAK bit to "0" before further data is received. 2 99 October 27, 2017 BS84B08C Touch A/D Flash MCU Bit 2 SRW: I2C slave read/write flag 0: Slave device should be in receive mode 1: Slave device should be in transmit mode The SRW flag is the I 2C Slave Read/Write flag. This flag determines whether the master device wishes to transmit or receive data from the I2C bus. When the transmitted address and slave address is match, that is when the HAAS flag is set high, the slave device will check the SRW flag to determine whether it should be in transmit mode or receive mode. If the SRW flag is high, the master is requesting to read data from the bus, so the slave device should be in transmit mode. When the SRW flag is zero, the master will write data to the bus, therefore the slave device should be in receive mode to read this data. Bit 1 IAMWU: I2C Address Match Wake-Up control 0: Disable 1: Enable – must be cleared by the application program after wake-up This bit should be set to 1 to enable the I2C address match wake up from the SLEEP or IDLE Mode. If the IAMWU bit has been set before entering either the SLEEP or IDLE mode to enable the I2C address match wake up, then this bit must be cleared to zero by the application program after wake-up to ensure correction device operation. Bit 0 RXAK: I2C bus receive acknowledge flag 0: Slave receives acknowledge flag 1: Slave does not receive acknowledge flag The RXAK flag is the receiver acknowledge flag. When the RXAK flag is "0", it means that a acknowledge signal has been received at the 9th clock, after 8 bits of data have been transmitted. When the slave device in the transmit mode, the slave device checks the RXAK flag to determine if the master receiver wishes to receive the next byte. The slave transmitter will therefore continue sending out data until the RXAK flag is "1". When this occurs, the slave transmitter will release the SDA line to allow the master to send a STOP signal to release the I2C Bus. I2C Bus Communication Communication on the I2C bus requires four separate steps, a START signal, a slave device address transmission, a data transmission and finally a STOP signal. When a START signal is placed on the I2C bus, all devices on the bus will receive this signal and be notified of the imminent arrival of data on the bus. The first seven bits of the data will be the slave address with the first bit being the MSB. If the address of the slave device matches that of the transmitted address, the HAAS bit in the SIMC1 register will be set and an I2C interrupt will be generated. After entering the interrupt service routine, the slave device must first check the condition of the HAAS and SIMTOF bits to determine whether the interrupt source originates from an address match, 8-bit data transfer completion or I2C bus time-out occurrence. During a data transfer, note that after the 7-bit slave address has been transmitted, the following bit, which is the 8th bit, is the read/write bit whose value will be placed in the SRW bit. This bit will be checked by the slave device to determine whether to go into transmit or receive mode. Before any transfer of data to or from the I2C bus, the microcontroller must initialise the bus, the following are steps to achieve this: • Step 1 Set the SIM2~SIM0 bits to "110" and SIMEN bit to "1" in the SIMC0 register to enable the I2C bus. • Step 2 Write the slave address of the device to the I2C bus address register SIMA. • Step 3 Set the SIME interrupt enable bit of the interrupt control register to enable the SIM interrupt. Rev. 1.00 100 October 27, 2017 BS84B08C Touch A/D Flash MCU Sta�t Set SIM[�:0]=110 Set SIMEN W�ite Slave Add�ess to SIMA No I�C Bus Inte��upt=? Yes CLR SIME Poll SIMF to de�ide when to go to I�C Bus ISR SET SIME Wait fo� Inte��upt Goto Main P�og�am Goto Main P�og�am I2C Bus Initialisation Flow Chart I2C Bus Start Signal The START signal can only be generated by the master device connected to the I2C bus and not by the slave device. This START signal will be detected by all devices connected to the I2C bus. When detected, this indicates that the I2C bus is busy and therefore the HBB bit will be set. A START condition occurs when a high to low transition on the SDA line takes place when the SCL line remains high. I2C Slave Address The transmission of a START signal by the master will be detected by all devices on the I2C bus. To determine which slave device the master wishes to communicate with, the address of the slave device will be sent out immediately following the START signal. All slave devices, after receiving this 7-bit address data, will compare it with their own 7-bit slave address. If the address sent out by the master matches the internal address of the microcontroller slave device, then an internal I2C bus interrupt signal will be generated. The next bit following the address, which is the 8th bit, defines the read/write status and will be saved to the SRW bit of the SIMC1 register. The slave device will then transmit an acknowledge bit, which is a low level, as the 9th bit. The slave device will also set the status flag HAAS when the addresses match. As an I2C bus interrupt can come from three sources, when the program enters the interrupt subroutine, the HAAS and SIMTOF bits should be examined to see whether the interrupt source has come from a matching slave address, the completion of a data byte transfer or the I2C bus time-out occurrence. When a slave address is matched, the device must be placed in either the transmit mode and then write data to the SIMD register, or in the receive mode where it must implement a dummy read from the SIMD register to release the SCL line. I2C Bus Read/Write Signal The SRW bit in the SIMC1 register defines whether the slave device wishes to read data from the I2C bus or write data to the I2C bus. The slave device should examine this bit to determine if it is to be a transmitter or a receiver. If the SRW flag is "1" then this indicates that the master device wishes to read data from the I2C bus, therefore the slave device must be setup to send data to the I2C bus as a transmitter. If the SRW flag is "0" then this indicates that the master wishes to send data to the I2C bus, therefore the slave device must be setup to read data from the I2C bus as a receiver. Rev. 1.00 101 October 27, 2017 BS84B08C Touch A/D Flash MCU I2C Bus Slave Address Acknowledge Signal After the master has transmitted a calling address, any slave device on the I 2C bus, whose own internal address matches the calling address, must generate an acknowledge signal. The acknowledge signal will inform the master that a slave device has accepted its calling address. If no acknowledge signal is received by the master then a STOP signal must be transmitted by the master to end the communication. When the HAAS flag is high, the addresses have matched and the slave device must check the SRW flag to determine if it is to be a transmitter or a receiver. If the SRW flag is high, the slave device should be setup to be a transmitter so the HTX bit in the SIMC1 register should be set to "1". If the SRW flag is low, then the microcontroller slave device should be setup as a receiver and the HTX bit in the SIMC1 register should be set to "0". I2C Bus Data and Acknowledge Signal The transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged receipt of its slave address. The order of serial bit transmission is the MSB first and the LSB last. After receipt of 8-bits of data, the receiver must transmit an acknowledge signal, level "0", before it can receive the next data byte. If the slave transmitter does not receive an acknowledge bit signal from the master receiver, then the slave transmitter will release the SDA line to allow the master to send a STOP signal to release the I2C Bus. The corresponding data will be stored in the SIMD register. If setup as a transmitter, the slave device must first write the data to be transmitted into the SIMD register. If setup as a receiver, the slave device must read the transmitted data from the SIMD register. When the slave receiver receives the data byte, it must generate an acknowledge bit, known as TXAK, on the 9th clock. The slave device, which is setup as a transmitter will check the RXAK bit in the SIMC1 register to determine if it is to send another data byte, if not then it will release the SDA line and await the receipt of a STOP signal from the master. SCL Slave Add�ess Sta�t 1 0 1 SDA 1 0 1 SRW ACK 1 0 0 Data SCL 1 0 0 1 0 ACK 1 0 Stop 0 SDA S=Sta�t (1 �it) SA=Slave Add�ess (� �its) SR=SRW �it (1 �it) M=Slave devi�e send a�knowledge �it (1 �it) D=Data (8 �its) A=ACK (RXAK �it fo� t�ansmitte�� TXAK �it fo� �e�eive�� 1 �it) P=Stop (1 �it) S SA SR M D A D A …… S SA SR M D A D A …… P I2C Communication Timing Diagram Note: When a slave address is matched, the device must be placed in either the transmit mode and then write data to the SIMD register, or in the receive mode where it must implement a dummy read from the SIMD register to release the SCL line. Rev. 1.00 102 October 27, 2017 BS84B08C Touch A/D Flash MCU Sta�t No No No HTX=1? Yes HAAS=1? Yes SIMT�F=1? Yes Yes SET SIMT�EN CLR SIMT�F SRW=1? No RETI Read f�om SIMD to �elease SCL Line RETI Yes SET HTX CLR HTX CLR TXAK W�ite data to SIMD to �elease SCL Line Dummy �ead f�om SIMD to �elease SCL Line RETI RETI RXAK=1? No CLR HTX CLR TXAK W�ite data to SIMD to �elease SCL Line Dummy �ead f�om SIMD to �elease SCL Line RETI RETI I2C Bus ISR Flow Chart I2C Time-out Control In order to reduce the I2C lockup problem due to reception of erroneous clock sources, a time-out function is provided. If the clock source connected to the I2C bus is not received for a while, then the I2C circuitry and registers will be reset after a certain time-out period. The time-out counter starts to count on an I2C bus "START" & "address match"condition, and is cleared by an SCL falling edge. Before the next SCL falling edge arrives, if the time elapsed is greater than the time-out period specified by the SIMTOC register, then a time-out condition will occur. The time-out function will stop when an I2C "STOP" condition occurs. Rev. 1.00 103 October 27, 2017 BS84B08C Touch A/D Flash MCU SCL Sta�t Slave Add�ess 1 SDA 0 1 1 0 1 SRW ACK 1 0 0 I�C time-out �ounte� sta�t Stop SCL 1 0 0 1 0 1 0 0 SDA I�C time-out �ounte� �eset on SCL negative t�ansition I2C Time-out When an I2C time-out counter overflow occurs, the counter will stop and the SIMTOEN bit will be cleared to zero and the SIMTOF bit will be set high to indicate that a time-out condition has occurred. The time-out condition will also generate an interrupt which uses the I2C interrrupt vector. When an I2C time-out occurs, the I2C internal circuitry will be reset and the registers will be reset into the following condition: Register After I2C Time-out SIMD, SIMA, SIMC0 No change SIMC1 Reset to POR condition I2C Register after Time-out The SIMTOF flag can be cleared by the application program. There are 64 time-out period selections which can be selected using the SIMTOS5~SIMTOS0 bits in the SIMTOC register. The time-out duration is calculated by the formula: ((1~64) × (32/fSUB)). This gives a time-out period which ranges from about 1ms to 64ms. • SIMTOC Register Rev. 1.00 Bit 7 6 5 4 3 2 1 0 Name SIMTOEN R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 SIMTOF SIMTOS5 SIMTOS4 SIMTOS3 SIMTOS2 SIMTOS1 SIMTOS0 Bit 7 SIMTOEN: SIM I C Time-out function control 0: Disable 1: Enable Bit 6 SIMTOF: SIM I2C Time-out flag 0: No time-out occurred 1: Time-out occurred Bit 5~0 SIMTOS5~SIMTOS0: SIM I2C Time-out period selection I2C Time-out clock source is fSUB/32. I2C time-out time is equal to (SIMTOS[5:0]+1) × (32/fSUB). 2 104 October 27, 2017 BS84B08C Touch A/D Flash MCU Interrupts Interrupts are an important part of any microcontroller system. When an external event or an internal function such as a Touch action or Timer Module requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. The device contains several external interrupt and internal interrupt functions. The external interrupt is generated by the action of the external INT pin, while the internal interrupts are generated by various internal functions such as the Touch Keys, TM, Time base, A/D converter and SIM, etc. Interrupt Registers Overall interrupt control, which basically means the setting of request flags when certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is controlled by a series of registers, located in the Special Purpose Data Memory, as shown in the accompanying table. The number of registers falls into three categories. The first is the INTC0~INTC1 registers which setup the primary interrupts, the second is the MFI register which setup the Multi-function interrupt. Finally there is an INTEG register to setup the external interrupt trigger edge type. Each register contains a number of enable bits to enable or disable individual registers as well as interrupt flags to indicate the presence of an interrupt request. The naming convention of these follows a specific pattern. First is listed an abbreviated interrupt type, then that interrupt followed by either an "E" for enable/disable bit or "F" for request flag. Function Enable Bit Request Flag Global EMI — INT Pin INTE INTF Touch Key Module TKME TKMF Time Base TBE TBF Multi-function MFE MFF EEPROM DEE DEF SIM SIME SIMF PTMPE PTMPF PTMAE PTMAF ADE ADF PTM A/D Converter Interrupt Register Bit Naming Conventions Bit Register Name 7 6 5 4 3 2 1 0 INTEG — — — — — — INTS1 INTS0 INTC0 — MFF TKMF INTF MFE TKME INTE EMI INTC1 ADF DEF TBF SIMF ADE DEE TBE SIME MFI — — PTMAF PTMPF — — PTMAE PTMPE Interrupt Register List • INTEG Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — INTS1 INTS0 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7~2 Rev. 1.00 Unimplemented, read as "0" 105 October 27, 2017 BS84B08C Touch A/D Flash MCU Bit 1~0 INTS1~INTS0: External Interrupt edge control for INT pin 00: Disable 01: Rising edge 10: Falling edge 11: Rising and falling edges • INTC0 Register Bit 7 6 5 4 3 2 1 0 Name — MFF TKMF INTF MFE TKME INTE EMI R/W — R/W R/W R/W R/W R/W R/W R/W POR — 0 0 0 0 0 0 0 Bit 7 Unimplemented, read as "0" Bit 6 MFF: Multi-function interrupt request flag 0: No request 1: Interrupt request Bit 5 TKMF: Touch Key Module interrupt request flag 0: No request 1: Interrupt request Bit 4 INTF: INT interrupt request flag 0: No request 1: Interrupt request Bit 3 MFE: Multi-function interrupt control 0: Disable 1: Enable Bit 2 TKME: Touch Key Module interrupt control 0: Disable 1: Enable Bit 1 INTE: INT interrupt control 0: Disable 1: Enable Bit 0 EMI: Global interrupt control 0: Disable 1: Enable • INTC1 Register Rev. 1.00 Bit 7 6 5 4 3 2 1 0 Name ADF DEF TBF SIMF ADE DEE TBE SIME R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 ADF: A/D Converter interrupt request flag 0: No request 1: Interrupt request Bit 6 DEF: Data EEPROM interrupt request flag 0: No request 1: Interrupt request Bit 5 TBF: Time Base interrupt request flag 0: No request 1: Interrupt request Bit 4 SIMF: SIM interrupt request flag 0: No request 1: Interrupt request 106 October 27, 2017 BS84B08C Touch A/D Flash MCU Bit 3 ADE: A/D Converter Interrupt control 0: Disable 1: Enable Bit 2 DEE: Data EEPROM interrupt control 0: Disable 1: Enable Bit 1 TBE: Time Base interrupt control 0: Disable 1: Enable Bit 0 SIME: SIM interrupt control 0: Disable 1: Enable • MFI Register Bit 7 6 5 4 3 2 1 0 Name — — PTMAF PTMPF — — PTMAE PTMPE R/W — — R/W R/W — — R/W R/W POR — — 0 0 — — 0 0 Bit 7~6 Unimplemented, read as "0" Bit 5 PTMAF: PTM Comparator A match interrupt request flag 0: No request 1: Interrupt request Bit 4 PTMPF: PTM Comparator P match interrupt request flag 0: No request 1: Interrupt request Bit 3~2 Unimplemented, read as "0" Bit 1 PTMAE: PTM Comparator A match interrupt control 0: Disable 1: Enable Bit 0 PTMPE: PTM Comparator P match interrupt control 0: Disable 1: Enable Interrupt Operation When the conditions for an interrupt event occur, such as a Touch Key counter overflow, TM Comparator P or Comparator A match, etc, the relevant interrupt request flag will be set. Whether the request flag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enable bit. If the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the interrupt request flag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector. The global interrupt enable bit, if cleared to zero, will disable all interrupts. When an interrupt is generated, the Program Counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. The Program Counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. The microcontroller will then fetch its next instruction from this interrupt vector. The instruction at this vector will usually be a "JMP" which will jump to another section of program which is known as the interrupt service routine. Here is located the code to control the appropriate interrupt. The interrupt service routine must be terminated with a "RETI", which retrieves the original Program Counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. Rev. 1.00 107 October 27, 2017 BS84B08C Touch A/D Flash MCU The various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagrams with their order of priority. Some interrupt sources have their own individual vector while others share the same multi-function interrupt vector. Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit, EMI bit will be cleared automatically. This will prevent any further interrupt nesting from occurring. However, if other interrupt requests occur during this interval, although the interrupt will not be immediately serviced, the request flag will still be recorded. If an interrupt requires immediate servicing while the program is already in another interrupt service routine, the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full. In case of simultaneous requests, the accompanying diagram shows the priority that is applied. All of the interrupt request flags when set will wake-up the device if it is in SLEEP or IDLE Mode, however to prevent a wake-up from occurring the corresponding flag should be set before the device is in SLEEP or IDLE Mode. xxF Legend Request Flag� no auto �eset in ISR xxF Request Flag� auto �eset in ISR xxE Ena�le Bits Inte��upt Name Request Flags Ena�le Bits PTM P PTMPF PTMPE PTM A PTMAF PTMAE Inte��upts �ontained within Multi-Fun�tion Inte��upts EMI auto disa�led in ISR Inte��upt Name Request Flags Ena�le Bits Maste� Ena�le Vector INT Pin INTF INTE EMI 04H Tou�h Key Module TKMF TKME EMI 08H M. Fun�t MFF MFE EMI 0CH SIM SIMF SIME EMI 10H Time Base TBF TBE EMI 14H EEPR�M DEF DEE EMI 18H A/D Conve�te� ADF ADE EMI 1CH P�io�ity High Low Interrupt Structure External Interrupt The external interrupt is controlled by signal transitions on the pin INT. An external interrupt request will take place when the external interrupt request flag, INTF, is set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pin. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and respective external interrupt enable bit, INTE, must first be set. Additionally the correct interrupt edge type must be selected using the INTEG register to enable the external interrupt function and to choose the trigger edge type. As the external interrupt pin is pin-shared with I/O pin, its can only be configured as external interrupt pin if its external interrupt enable bit in the corresponding interrupt register has been set. The pin must also be setup as an input by setting the corresponding bit in the port control register. When the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector, will take place. When the interrupt is serviced, the external interrupt request flag, Rev. 1.00 108 October 27, 2017 BS84B08C Touch A/D Flash MCU INTF, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Note that any pull-high resistor selections on the external interrupt pin will remain valid even if the pin is used as an external interrupt input. The INTEG register is used to select the type of active edge that will trigger the external interrupt. A choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. Note that the INTEG register can also be used to disable the external interrupt function. Touch Key Interrupt For a Touch Key interrupt to occur, the global interrupt enable bit, EMI, and the Touch Key interrupt enable bit TKME must be first set. An actual Touch Key interrupt will take place when the Touch Key request flag. TKMF, is set, a situation that will occur when the time slot counter overflows. When the interrupt is enabled, the stack is not full and the Touch Key time slot counter overflow occurs, a subroutine call to the relevant timer interrupt vector, will take place. When the interrupt is serviced, the Touch Key interrupt request flag, TKMF, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. The TKCFOV flag which is the touch key module n 16-bit C/F counter overflow flag will go high when the Touch Key Module n 16-bit C/F counter overflows. As this flag will not be automatically cleared, it has to be cleared by the application program. The TK16OV flag which is the touch key function 16-bit counter overflow flag will go high when the touch key function 16-bit counter overflows. As this flag will not be automatically cleared, it has to be cleared by the application program. Time Base Interrupt The function of the Time Base Interrupt is to provide regular time signal in the form of an internal interrupt. It is controlled by the overflow signal from its timer function. When this happens its interrupt request flag, TBF will be set. To allow the program to branch to its interrupt vector address, the global interrupt enable bit, EMI and Time Base enable bit, TBE, must first be set. When the interrupt is enabled, the stack is not full and the Time Base overflow, a subroutine call to its vector location will take place. When the interrupt is serviced, the interrupt request flag, TBF, will be automatically reset and the EMI bit will be cleared to disable other interrupts. The purpose of the Time Base Interrupt is to provide an interrupt signal at fixed time periods. Its clock source, fPSC, originates from the internal clock source fSYS, fSYS/4, fSUB or fH and then passes through a divider, the division ratio of which is selected by programming the appropriate bits in the TBC register to obtain longer interrupt periods whose value ranges. The clock source which in turn controls the Time Base interrupt period is selected using the CLKSEL1~CLKSEL0 bits in the PSCR register. fSYS fSYS/4 fSUB fH M U X fPSC P�es�ale� fPSC/�8 ~ fPSC/�15 TB�N CLKSEL[1:0] M U X Time Base Inte��upt TB[�:0] Time Base Interrupt Rev. 1.00 109 October 27, 2017 BS84B08C Touch A/D Flash MCU • PSCR Register Bit 7 6 5 4 3 2 Name — — — — — — 1 0 R/W — — — — — — R/W R/W POR — — — — — — 0 0 CLKSEL1 CLKSEL0 Bit 7~2 Unimplemented, read as "0" Bit 1~0 CLKSEL1~CLKSEL0: Time Base prescaler clock source fPSC selection 00: fSYS 01: fSYS/4 10: fSUB 11: fH • TBC Register Bit 7 6 5 4 3 2 1 0 Name — — — — TBON TB2 TB1 TB0 R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as "0" Bit 3 TBON: Time Base Control 0: Disable 1: Enable Bit 2~0 TB2~TB0: Select Time Base Time-out Period 000: 28/fPSC 001: 29/fPSC 010: 210/fPSC 011: 211/fPSC 100: 212/fPSC 101: 213/fPSC 110: 214/fPSC 111: 215/fPSC A/D Converter Interrupt An A/D Converter Interrupt request will take place when the A/D Converter Interrupt request flag, ADF, is set, which occurs when the A/D conversion process finishes. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and A/D Interrupt enable bit, ADE, must first be set. When the interrupt is enabled, the stack is not full and the A/D conversion process has ended, a subroutine call to the A/D Interrupt vector, will take place. When the A/D Converter Interrupt is serviced, the A/D Interrupt flag, ADF, will be automatically cleared. The EMI bit will also be automatically cleared to disable other interrupts. Multi-function Interrupt Within this device there is one Multi-function interrupt. Unlike the other independent interrupts, this interrupt has no independent source, but rather is formed from other existing interrupt sources, namely the PTM interrupts. A Multi-function interrupt request will take place when the Multi-function interrupt request flag, MFF is set. The Multi-function interrupt flag will be set when any of their included functions generate an interrupt request flag. To allow the program to branch to its respective interrupt vector address, when the Multi-function interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of Multi-function interrupt occurs, a subroutine call to one of the Multi-function interrupt vectors will take place. When the interrupt is serviced, the related Multi- Rev. 1.00 110 October 27, 2017 BS84B08C Touch A/D Flash MCU Function request flag will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. However, it must be noted that, although the Multi-function Interrupt flag will be automatically reset when the interrupt is serviced, the request flag from the original source of the Multi-function interrupt, namely the PTM interrupts, will not be automatically reset and must be manually reset by the application program. Serial Interface Module Interrupt The Serial Interface Module Interrupt, also known as the SIM interrupt, is controlled by the SPI or I2C data transfer. A SIM Interrupt request will take place when the SIM Interrupt request flag, SIMF, is set, which occurs when a byte of data has been received or transmitted by the SIM interface, an I2C slave address match or I2C bus time-out occurrence. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI and the Serial Interface Interrupt enable bit, SIME, must first be set. When the interrupt is enabled, the stack is not full and any of the above described situations occurs, a subroutine call to the respective SIM Interrupt vector, will take place. When the Serial Interface Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts. The SIMF flag will also be automatically cleared. EEPROM Interrupt An EEPROM Interrupt request will take place when the EEPROM Interrupt request flag, DEF, is set, which occurs when an EEPROM Write cycle ends. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and EEPROM Interrupt enable bit, DEE, must first be set. When the interrupt is enabled, the stack is not full and an EEPROM Write cycle ends, a subroutine call to the respective EEPROM Interrupt vector, will take place. When the EEPROM Interrupt is serviced, the DEF flag will be automatically cleared and the EMI bit will be automatically cleared to disable other interrupts. TM Interrupt The Periodic TM has two interrupts, one comes from the comparator A match situation and the other comes from the comparator P match situation. All of the TM interrupts are contained within the Multi-function Interrupt. There are two interrupt request flags and two enable control bits. A TM interrupt request will take place when any of the TM request flags are set, a situation which occurs when a TM comparator P or A match situation happens. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, respective TM Interrupt enable bit, and Multi-function Interrupt enable bit, MFE, must first be set. When the interrupt is enabled, the stack is not full and a TM comparator match situation occurs, a subroutine call to the Multi-function Interrupt vector location, will take place. When the TM interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts. However, only the MFF flag will be automatically cleared. As the TM interrupt request flags will not be automatically cleared, they have to be cleared by the application program. Rev. 1.00 111 October 27, 2017 BS84B08C Touch A/D Flash MCU Interrupt Wake-up Function Each of the interrupt functions has the capability of waking up the microcontroller when in the SLEEP or IDLE Mode. A wake-up is generated when an interrupt request flag changes from low to high and is independent of whether the interrupt is enabled or not. Therefore, even though the device is in the SLEEP or IDLE Mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pins or a low power supply voltage may cause their respective interrupt flag to be set high and consequently generate an interrupt. Care must therefore be taken if spurious wake-up situations are to be avoided. If an interrupt wake-up function is to be disabled then the corresponding interrupt request flag should be set high before the device enters the SLEEP or IDLE Mode. The interrupt enable bits have no effect on the interrupt wake-up function. Programming Considerations By disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request flag is cleared by the application program. Where a certain interrupt is contained within a Multi-function interrupt, then when the interrupt service routine is executed, as only the Multi-function interrupt request flag, MFF, will be automatically cleared, the individual request flag for the function needs to be cleared by the application program. It is recommended that programs do not use the "CALL" instruction within the interrupt service subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately. If only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a CALL subroutine is executed in the interrupt subroutine. Every interrupt has the capability of waking up the microcontroller when it is in the SLEEP or IDLE Mode, the wake up being generated when the interrupt request flag changes from low to high. If it is required to prevent a certain interrupt from waking up the microcontroller then its respective request flag should be first set high before enter SLEEP or IDLE Mode. As only the Program Counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator, status register or other registers are altered by the interrupt service program, their contents should be saved to the memory at the beginning of the interrupt service routine. To return from an interrupt subroutine, either a RET or RETI instruction may be executed. The RETI instruction in addition to executing a return to the main program also automatically sets the EMI bit high to allow further interrupts. The RET instruction however only executes a return to the main program leaving the EMI bit in its present zero state and therefore disabling the execution of further interrupts. Rev. 1.00 112 October 27, 2017 BS84B08C Touch A/D Flash MCU Application Circuits VDD PAD PB0/KEY1 PAD PB1/KEY2 PAD PB2/KEY3 VDD Rev. 1.00 0.1μF VSS PAD PB3/KEY4 PAD PB4/KEY5 PAD PB5/KEY6 PAD PB6/KEY7 PAD PB7/KEY8 PA0/SDI/SDA PA1/PTP/SDO PA2/SCK/SCL PA3/PTCK/SCS PA4/PTPI/[SDI/SDA]/INT PA7/PTPB/[SCK/SCL] PD7/AN7 PD6/AN6 PD5/AN5 PD4/AN4 PD3/AN3 PD2/AN2 PD1/AN1 PD0/AN0/VREF 113 October 27, 2017 BS84B08C Touch A/D Flash MCU Instruction Set Introduction Central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontroller, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. For easier understanding of the various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be implemented within 0.5μs and branch or call instructions would be implemented within 1μs. Although instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct jump to that new address, one more cycle will be required. Examples of such instructions would be "CLR PCL" or "MOV PCL, A". For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Moving and Transferring Data The transfer of data within the microcontroller program is one of the most frequently used operations. Making use of three kinds of MOV instructions, data can be transferred from registers to the Accumulator and vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. Arithmetic Operations The ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. Within the Holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC and DECA provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. Rev. 1.00 114 October 27, 2017 BS84B08C Touch A/D Flash MCU Logical and Rotate Operation The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the Carry bit from where it can be examined and the necessary serial bit set high or low. Another application which rotate data operations are used is to implement multiplication and division calculations. Branches and Control Transfer Program branching takes the form of either jumps to specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. This is done by placing a return instruction "RET" in the subroutine which will cause the program to jump back to the address right after the CALL instruction. In the case of a JMP instruction, the program simply jumps to the desired location. There is no requirement to jump back to the original jumping off point as in the case of the CALL instruction. One special and extremely useful set of branch instructions are the conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. These instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits. Bit Operations The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek microcontrollers. This feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the "SET [m].i" or "CLR [m]. i" instructions respectively. The feature removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used. Table Read Operations Data storage is normally implemented by using registers. However, when working with large amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program Memory to be set as a table where data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the Program Memory. Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the "HALT" instruction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electromagnetic environments. For their relevant operations, refer to the functional related sections. Rev. 1.00 115 October 27, 2017 BS84B08C Touch A/D Flash MCU Instruction Set Summary The following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. Table Conventions x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Mnemonic Description Cycles Flag Affected Add Data Memory to ACC Add ACC to Data Memory Add immediate data to ACC Add Data Memory to ACC with Carry Add ACC to Data memory with Carry Subtract immediate data from the ACC Subtract Data Memory from ACC Subtract Data Memory from ACC with result in Data Memory Subtract Data Memory from ACC with Carry Subtract Data Memory from ACC with Carry, result in Data Memory Decimal adjust ACC for Addition with result in Data Memory 1 1Note 1 1 1Note 1 1 1Note 1 1Note 1Note Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV C 1 1 1 1Note 1Note 1Note 1 1 1 1Note 1 Z Z Z Z Z Z Z Z Z Z Z Increment Data Memory with result in ACC Increment Data Memory Decrement Data Memory with result in ACC Decrement Data Memory 1 1Note 1 1Note Z Z Z Z Rotate Data Memory right with result in ACC Rotate Data Memory right Rotate Data Memory right through Carry with result in ACC Rotate Data Memory right through Carry Rotate Data Memory left with result in ACC Rotate Data Memory left Rotate Data Memory left through Carry with result in ACC Rotate Data Memory left through Carry 1 1Note 1 1Note 1 1Note 1 1Note None None C C None None C C Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Logic Operation AND A,[m] Logical AND Data Memory to ACC OR A,[m] Logical OR Data Memory to ACC XOR A,[m] Logical XOR Data Memory to ACC ANDM A,[m] Logical AND ACC to Data Memory ORM A,[m] Logical OR ACC to Data Memory XORM A,[m] Logical XOR ACC to Data Memory AND A,x Logical AND immediate Data to ACC OR A,x Logical OR immediate Data to ACC XOR A,x Logical XOR immediate Data to ACC CPL [m] Complement Data Memory CPLA [m] Complement Data Memory with result in ACC Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Rev. 1.00 116 October 27, 2017 BS84B08C Touch A/D Flash MCU Mnemonic Description Cycles Flag Affected Move Data Memory to ACC Move ACC to Data Memory Move immediate data to ACC 1 1Note 1 None None None Clear bit of Data Memory Set bit of Data Memory 1Note 1Note None None Jump unconditionally Skip if Data Memory is zero Skip if Data Memory is zero with data movement to ACC Skip if bit i of Data Memory is zero Skip if bit i of Data Memory is not zero Skip if increment Data Memory is zero Skip if decrement Data Memory is zero Skip if increment Data Memory is zero with result in ACC Skip if decrement Data Memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1Note 1Note 1Note 1Note 1Note 1Note 1Note 1Note 2 2 2 2 None None None None None None None None None None None None None Read table (specific page) to TBLH and Data Memory Read table (current page) to TBLH and Data Memory Read table (last page) to TBLH and Data Memory 2Note 2Note 2Note None None None No operation Clear Data Memory Set Data Memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of Data Memory Swap nibbles of Data Memory with result in ACC Enter power down mode 1 1Note 1Note 1 1 1 1Note 1 1 None None None TO, PDF TO, PDF TO, PDF None None TO, PDF Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Branch Operation JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read Operation TABRD [m] TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Notes: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution. 3. For the "CLR WDT1" and "CLR WDT2" instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both "CLR WDT1" and "CLR WDT2" instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged. Rev. 1.00 117 October 27, 2017 BS84B08C Touch A/D Flash MCU Instruction Definition ADC A,[m] Description Operation Affected flag(s) ADCM A,[m] Description Operation Affected flag(s) ADD A,[m] Description Add Data Memory to ACC with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. ACC ← ACC + [m] + C OV, Z, AC, C Add ACC to Data Memory with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. [m] ← ACC + [m] + C OV, Z, AC, C Add Data Memory to ACC The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. Operation Affected flag(s) ACC ← ACC + [m] OV, Z, AC, C ADD A,x Description Add immediate data to ACC The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator. ACC ← ACC + x OV, Z, AC, C Operation Affected flag(s) ADDM A,[m] Description Operation Affected flag(s) AND A,[m] Description Operation Affected flag(s) AND A,x Description Operation Affected flag(s) ANDM A,[m] Description Operation Affected flag(s) Rev. 1.00 Add ACC to Data Memory The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory. [m] ← ACC + [m] OV, Z, AC, C Logical AND Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ← ACC ″AND″ [m] Z Logical AND immediate data to ACC Data in the Accumulator and the specified immediate data perform a bit wise logical AND operation. The result is stored in the Accumulator. ACC ← ACC ″AND″ x Z Logical AND ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory. [m] ← ACC ″AND″ [m] Z 118 October 27, 2017 BS84B08C Touch A/D Flash MCU Affected flag(s) Subroutine call Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruction. Stack ← Program Counter + 1 Program Counter ← addr None CLR [m] Description Operation Affected flag(s) Clear Data Memory Each bit of the specified Data Memory is cleared to 0. [m] ← 00H None CLR [m].i Description Operation Affected flag(s) Clear bit of Data Memory Bit i of the specified Data Memory is cleared to 0. [m].i ← 0 None CLR WDT Description Operation Clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. WDT cleared TO ← 0 PDF ← 0 TO, PDF CALL addr Description Operation Affected flag(s) CLR WDT1 Description Operation Affected flag(s) CLR WDT2 Description Operation Affected flag(s) CPL [m] Description Operation Affected flag(s) Rev. 1.00 Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no effect. WDT cleared TO ← 0 PDF ← 0 TO, PDF Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no effect. WDT cleared TO ← 0 PDF ← 0 TO, PDF Complement Data Memory Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. [m] ← [m] Z 119 October 27, 2017 BS84B08C Touch A/D Flash MCU CPLA [m] Description Operation Affected flag(s) Complement Data Memory with result in ACC Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC ← [m] Z Affected flag(s) Decimal-Adjust ACC for addition with result in Data Memory Convert the contents of the Accumulator value to a BCD (Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. [m] ← ACC + 00H or [m] ← ACC + 06H or [m] ← ACC + 60H or [m] ← ACC + 66H C DEC [m] Description Operation Affected flag(s) Decrement Data Memory Data in the specified Data Memory is decremented by 1. [m] ← [m] − 1 Z DECA [m] Description Decrement Data Memory with result in ACC Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC ← [m] − 1 Z DAA [m] Description Operation Operation Affected flag(s) Affected flag(s) Enter power down mode This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. TO ← 0 PDF ← 1 TO, PDF INC [m] Description Operation Affected flag(s) Increment Data Memory Data in the specified Data Memory is incremented by 1. [m] ← [m] + 1 Z INCA [m] Description Increment Data Memory with result in ACC Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC ← [m] + 1 Z HALT Description Operation Operation Affected flag(s) Rev. 1.00 120 October 27, 2017 BS84B08C Touch A/D Flash MCU Operation Affected flag(s) Jump unconditionally The contents of the Program Counter are replaced with the specified address. Program execution then continues from this new address. As this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. Program Counter ← addr None MOV A,[m] Description Operation Affected flag(s) Move Data Memory to ACC The contents of the specified Data Memory are copied to the Accumulator. ACC ← [m] None MOV A,x Description Operation Affected flag(s) Move immediate data to ACC The immediate data specified is loaded into the Accumulator. ACC ← x None MOV [m],A Description Operation Affected flag(s) Move ACC to Data Memory The contents of the Accumulator are copied to the specified Data Memory. [m] ← ACC None NOP Description Operation Affected flag(s) No operation No operation is performed. Execution continues with the next instruction. No operation None OR A,[m] Description Logical OR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ← ACC ″OR″ [m] Z JMP addr Description Operation Affected flag(s) OR A,x Description Operation Affected flag(s) ORM A,[m] Description Operation Affected flag(s) RET Description Operation Affected flag(s) Rev. 1.00 Logical OR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ← ACC ″OR″ x Z Logical OR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory. [m] ← ACC ″OR″ [m] Z Return from subroutine The Program Counter is restored from the stack. Program execution continues at the restored address. Program Counter ← Stack None 121 October 27, 2017 BS84B08C Touch A/D Flash MCU RET A,x Description Operation Affected flag(s) RETI Description Operation Affected flag(s) RL [m] Description Operation Affected flag(s) RLA [m] Description Operation Affected flag(s) RLC [m] Description Operation Affected flag(s) RLCA [m] Description Operation Affected flag(s) RR [m] Description Operation Affected flag(s) Rev. 1.00 Return from subroutine and load immediate data to ACC The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address. Program Counter ← Stack ACC ← x None Return from interrupt The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program. Program Counter ← Stack EMI ← 1 None Rotate Data Memory left The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. [m].(i+1) ← [m].i; (i=0~6) [m].0 ← [m].7 None Rotate Data Memory left with result in ACC The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) ← [m].i; (i=0~6) ACC.0 ← [m].7 None Rotate Data Memory left through Carry The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. [m].(i+1) ← [m].i; (i=0~6) [m].0 ← C C ← [m].7 C Rotate Data Memory left through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) ← [m].i; (i=0~6) ACC.0 ← C C ← [m].7 C Rotate Data Memory right The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. [m].i ← [m].(i+1); (i=0~6) [m].7 ← [m].0 None 122 October 27, 2017 BS84B08C Touch A/D Flash MCU RRA [m] Description Operation Affected flag(s) RRC [m] Description Operation Affected flag(s) RRCA [m] Description Operation Affected flag(s) SBC A,[m] Description Operation Affected flag(s) SBCM A,[m] Description Operation Affected flag(s) SDZ [m] Description Operation Affected flag(s) Rev. 1.00 Rotate Data Memory right with result in ACC Data in the specified Data Memory is rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← [m].0 None Rotate Data Memory right through Carry The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. [m].i ← [m].(i+1); (i=0~6) [m].7 ← C C ← [m].0 C Rotate Data Memory right through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← C C ← [m].0 C Subtract Data Memory from ACC with Carry The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − [m] − C OV, Z, AC, C Subtract Data Memory from ACC with Carry and result in Data Memory The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ← ACC − [m] − C OV, Z, AC, C Skip if decrement Data Memory is 0 The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] ← [m] − 1 Skip if [m]=0 None 123 October 27, 2017 BS84B08C Touch A/D Flash MCU Affected flag(s) Skip if decrement Data Memory is zero with result in ACC The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. ACC ← [m] − 1 Skip if ACC=0 None SET [m] Description Operation Affected flag(s) Set Data Memory Each bit of the specified Data Memory is set to 1. [m] ← FFH None SET [m].i Description Operation Affected flag(s) Set bit of Data Memory Bit i of the specified Data Memory is set to 1. [m].i ← 1 None SIZ [m] Description Skip if increment Data Memory is 0 The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] ← [m] + 1 Skip if [m]=0 None SDZA [m] Description Operation Operation Affected flag(s) SIZA [m] Description Operation Affected flag(s) SNZ [m].i Description Operation Affected flag(s) SUB A,[m] Description Operation Affected flag(s) Rev. 1.00 Skip if increment Data Memory is zero with result in ACC The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC ← [m] + 1 Skip if ACC=0 None Skip if bit i of Data Memory is not 0 If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m].i ≠ 0 None Subtract Data Memory from ACC The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − [m] OV, Z, AC, C 124 October 27, 2017 BS84B08C Touch A/D Flash MCU SUBM A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with result in Data Memory The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ← ACC − [m] OV, Z, AC, C Operation Affected flag(s) Subtract immediate data from ACC The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − x OV, Z, AC, C SWAP [m] Description Operation Affected flag(s) Swap nibbles of Data Memory The low-order and high-order nibbles of the specified Data Memory are interchanged. [m].3~[m].0 ↔ [m].7~[m].4 None SWAPA [m] Description Swap nibbles of Data Memory with result in ACC The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC.3~ACC.0 ← [m].7~[m].4 ACC.7~ACC.4 ← [m].3~[m].0 None SUB A,x Description Operation Affected flag(s) SZ [m] Description Operation Affected flag(s) SZA [m] Description Operation Affected flag(s) SZ [m].i Description Operation Affected flag(s) Rev. 1.00 Skip if Data Memory is 0 If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Skip if [m]=0 None Skip if Data Memory is 0 with data movement to ACC The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC ← [m] Skip if [m]=0 None Skip if bit i of Data Memory is 0 If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Skip if [m].i=0 None 125 October 27, 2017 BS84B08C Touch A/D Flash MCU TABRD [m] Description Operation Affected flag(s) TABRDC [m] Description Operation Affected flag(s) TABRDL [m] Description Operation Affected flag(s) XOR A,[m] Description Operation Affected flag(s) XORM A,[m] Description Operation Affected flag(s) XOR A,x Description Operation Affected flag(s) Rev. 1.00 Read table (specific page) to TBLH and Data Memory The low byte of the program code (specific page) addressed by the table pointer pair (TBHP and TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None Read table (current page) to TBLH and Data Memory The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None Read table (last page) to TBLH and Data Memory The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None Logical XOR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ← ACC ″XOR″ [m] Z Logical XOR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory. [m] ← ACC ″XOR″ [m] Z Logical XOR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ← ACC ″XOR″ x Z 126 October 27, 2017 BS84B08C Touch A/D Flash MCU Package Information Note that the package information provided here is for consultation purposes only. As this information may be updated at regular intervals users are reminded to consult the Holtek website for the latest version of the Package/Carton Information. Additional supplementary information with regard to packaging is listed below. Click on the relevant section to be transferred to the relevant website page. • Further Package Information (include Outline Dimensions, Product Tape and Reel Specifications) • Packing Meterials Information • Carton information Rev. 1.00 127 October 27, 2017 BS84B08C Touch A/D Flash MCU 16-pin NSOP (150mil) Outline Dimensions Symbol Dimensions in inch Min. Nom. Max. A — 0.236 BSC — B — 0.154 BSC — 0.020 C 0.012 — C’ — 0.390 BSC — D — — 0.069 E — 0.050 BSC — F 0.004 — 0.010 G 0.016 — 0.050 H 0.004 — 0.010 α 0° — 8° Symbol Rev. 1.00 Dimensions in mm Min. Nom. Max. A — 6 BSC — B — 3.9 BSC — C 0.31 — 0.51 C’ — 9.9 BSC — D — — 1.75 E — 1.27 BSC — F 0.10 — 0.25 G 0.40 — 1.27 H 0.10 — 0.25 α 0° — 8° 128 October 27, 2017 BS84B08C Touch A/D Flash MCU 16-pin SSOP (150mil) Outline Dimensions Symbol Dimensions in inch Min. Nom. Max. A — 0.236 BSC — B — 0.154 BSC — C 0.008 — 0.012 C’ — 0.193 BSC — D — — 0.069 E — 0.025 BSC — F 0.004 — 0.010 G 0.016 — 0.050 H 0.004 — 0.010 α 0° — 8° Symbol A Rev. 1.00 Dimensions in mm Min. Nom. Max. — 6.0 BSC — B — 3.9 BSC — C 0.20 — 0.30 C’ — 4.9 BSC — D — — 1.75 E — 0.635 BSC — F 0.10 — 0.25 G 0.41 — 1.27 H 0.10 — 0.25 α 0° — 8° 129 October 27, 2017 BS84B08C Touch A/D Flash MCU 20-pin SOP (300mil) Outline Dimensions Symbol Dimensions in inch Min. Nom. Max. A — 0.406 BSC — B — 0.295 BSC — C 0.012 — 0.020 C’ — 0.504 BSC — D — — 0.104 E — 0.050 BSC — F 0.004 — 0.012 G 0.016 — 0.050 H 0.008 — 0.013 α 0° — 8° Symbol A Rev. 1.00 Dimensions in mm Min. Nom. Max. — 10.30 BSC — B — 7.5 BSC — C 0.31 — 0.51 C’ — 12.8 BSC — D — — 2.65 E — 1.27 BSC — F 0.10 — 0.30 G 0.40 — 1.27 H 0.20 — 0.33 α 0° — 8° 130 October 27, 2017 BS84B08C Touch A/D Flash MCU 20-pin NSOP (150mil) Outline Dimensions Symbol Dimensions in inch Min. Nom. Max. A 0.228 0.236 0.244 B 0.146 0.154 0.161 C 0.009 — 0.012 C’ 0.382 0.390 0.398 D — — 0.069 E — 0.032 BSC — F 0.002 — 0.009 G 0.020 — 0.031 H 0.008 — 0.010 α 0° — 8° Symbol Rev. 1.00 Dimensions in mm Min. Nom. Max. A 5.80 6.00 6.20 B 3.70 3.90 4.10 C 0.23 — 0.30 C’ 9.70 9.90 10.10 D — — 1.75 E — 0.80 BSC — F 0.05 — 0.23 G 0.50 — 0.80 H 0.21 — 0.25 α 0° — 8° 131 October 27, 2017 BS84B08C Touch A/D Flash MCU 20-pin SSOP (150mil) Outline Dimensions Symbol Dimensions in inch Min. Nom. Max. A — 0.236 BSC — B — 0.155 BSC — C 0.008 — 0.012 C’ — 0.341 BSC — D — — 0.069 E — 0.025 BSC — F 0.004 — 0.0098 G 0.016 — 0.05 H 0.004 — 0.01 α 0° — 8° Symbol A Rev. 1.00 Dimensions in mm Min. Nom. Max. — 6 BSC — B — 3.9 BSC — C 0.20 — 0.30 C’ — 8.66 BSC — D — — 1.75 E — 0.635 BSC — F 0.10 — 0.25 G 0.41 — 1.27 H 0.10 — 0.25 α 0° — 8° 132 October 27, 2017 BS84B08C Touch A/D Flash MCU 24-pin SOP (236mil) Outline Dimensions Symbol Dimensions in inch Min. Nom. Max. A 0.303 0.315 0.327 B 0.228 0.236 0.244 C 0.012 0.016 0.020 C’ 0.504 0.512 0.520 D — — 0.075 E — 0.039 BSC — F 0.002 0.004 0.008 G 0.010 0.018 0.026 H 0.004 0.006 0.010 α 0° — 8° Symbol Rev. 1.00 Dimensions in mm Min. Nom. Max. A 7.70 8.00 8.30 6.20 B 5.80 6.00 C 0.30 0.40 0.50 C’ 12.80 13.00 13.20 D — — 1.90 E — 1.0 BSC — F 0.05 0.10 0.20 G 0.25 0.45 0.65 H 0.10 0.15 0.25 α 0° — 8° 133 October 27, 2017 BS84B08C Touch A/D Flash MCU 24-pin SSOP (150mil) Outline Dimensions Symbol Dimensions in inch Min. Nom. Max. A — 0.236 BSC — B — 0.154 BSC — C 0.008 — 0.012 C’ — 0.341 BSC — D — — 0.069 E — 0.025 BSC — F 0.004 — 0.010 G 0.016 — 0.050 H 0.004 — 0.010 α 0° — 8° Symbol A Rev. 1.00 Dimensions in mm Min. Nom. Max. — 6.0 BSC — B — 3.9 BSC — C 0.20 — 0.30 C’ 0.20 — 0.30 D — — 1.75 E — 0.635 BSC — F 0.10 — 0.25 G 0.41 — 1.27 H 0.10 — 0.25 α 0° — 8° 134 October 27, 2017 BS84B08C Touch A/D Flash MCU Copyright© 2017 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek's products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com/en/. Rev. 1.00 135 October 27, 2017