MC10E1652 5V, -5V Dual ECL Output Comparator with Latch The MC10E1652 is fabricated using ON Semiconductor’s advanced MOSAIC III process and is output compatible with 10H logic devices. In addition, the device is available in a 20-pin surface mount package. However, the MC10E1652 provides user programmable hysteresis. The latch enable (LENa and LENb) input pins operate from standard ECL 10H logic levels. When the latch enable is at a logic high level, the MC10E1652 acts as a comparator; hence, Q will be at a logic high level if V1 > V2 (V1 is more positive than V2). Q is the complement of Q. When the latch enable input goes to a low logic level, the outputs are latched in their present state, providing the latch enable setup and hold time constraints are met. The level of input hysteresis is controlled by applying a bias voltage to the HYS pin. Features • • • • • • • • • • http://onsemi.com MARKING DIAGRAM 1 20 20 1 PLCC−20 FN SUFFIX CASE 775 MC10E 1652FNG AWLYYWW Typical 3.0 dB Bandwidth > 1.0 GHz A WL YY WW G Typical V to Q Propagation Delay of 775 ps Typical Output Rise/Fall of 350 ps Common Mode Range −2.0 V to +3.0 V Individual Latch Enables = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package Differential Outputs Operating Mode: VCC = 5.0 V, VEE = −5.2 V, GND = 0 V ORDERING INFORMATION Programmable Input Hysteresis See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. No Internal Input Pulldown Resistors ESD Protection: Human Body Model; > 2 kV, Machine Model; > 100 V Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test • • Moisture Sensitivity Level 3 For Additional Information, see Application Note AND8003/D • Flammability Rating: UL 94 V−O @ 0.125 in, Oxygen Index: 28 to 34 Transistor Count = 85 devices • • These are Pb−Free Devices* *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2013 April, 2013 − Rev. 10 1 Publication Order Number: MC10E1652/D MC10E1652 Qb LENb NC 18 17 16 V1b V2b 15 14 Qb 19 13 VCC GND 20 12 HYS NC 1 Pinout: 20-Lead PLCC 11 NC GND 2 10 VEE Qa 3 9 VCC (Top View) 4 5 6 Qa LENa NC 7 8 V2a V1a * All VCC and VCCO pins are NOT tied together on the die. Warning: All VCC, GND, and VEE pins must be externally connected to Power Supply to guarantee proper operation. Figure 1. Logic Diagrams and Pinout Assignments V1a Qa V2a LENa Qa HYS V1b Qb V2b Qb LENb VEE = -5.2 V VCC = +5.0 V Figure 2. Logic Diagram Table 2. FUNCTION TABLE Table 1. PIN DESCRIPTION PIN FUNCTION Qa, Qa ECL Differential Outputs (a) Qb, Qb ECL Differential Outputs (b) LENa, LENb ECL Latch Enable V1a, V1b Input Comparator 1 V2a, V2b Input Comparator 2 HYS Hysteresis Bias Voltage Control Input VCC Positive Supply VEE Negative Supply NC No Connect GND Ground LEN V1, V2 Function H H L V1 > V2 V1 < V2 X H L Latched http://onsemi.com 2 MC10E1652 Table 3. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Units |VEE| + |VCC| 12.0 V |V1 − V2| 3.7 V VEE v VI v VCC V 50 100 mA mA ± 0.5 mA VSUP Total Supply Voltage VPP Differential Input Voltage VI Input Voltage Iout Output Current IBB VBB Sink/Source TA Operating Temperature Range Tstg Storage Temperature Range qJA Thermal Resistance (Junction to Ambient) 0 LFPM 500 LFPM 28 PLCC 28 PLCC qJC Thermal Resistance (Junction to Case) std bd 28 PLCC VEE Operating Range GND = 0 V Tsol Wave Solder Continuous Surge Pb−Free 0 to +85 °C −65 to +150 °C 63.5 43.5 °C/W °C/W 22 to 26 °C/W −4.2 to −5.7 V 265 °C v 3 sec @ 260°C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table 4. DC CHARACTERISTICS VCC = +5.0 V ±5%; VEE = −5.2 V ±5%, VCC = 0 V (Note 1) 0°C Symbol Characteristic Min 25°C Typ Max Min Typ 85°C Max Min Typ Max Unit VOH Output HIGH Voltage (Note 2) −1020 −840 −980 −810 −920 −735 mV VOL Output Low Voltage (Note 2) −1950 −1630 −1950 −1630 −1950 −1600 mV VIL Input LOW Voltage (LEN) −1.95 −1.48 −1.95 −1.48 −1.95 −1.45 mV VIH Input HIGH Voltage (LEN) −1.17 −0.84 −1.13 −0.81 −1.07 −0.735 mV II IIH Input Current (V1, V2) Input HIGH Current (LEN) 65 150 65 150 65 150 mA ICC IEE Positive Supply Current Negative Supply Current 50 −55 50 −55 50 −55 mA VCMR Common Mode Range (Note 3) 3.0 V Hys Hysteresis (Note 4) Vskew Hysteresis Skew (Note 5) Cin Input Capacitance −2.0 3.0 −2.0 3.0 −2.0 27 27 30 mV −1.0 −1.0 0 mV PLCC 2 2 2 pF NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. Input VIL and VIH parameters vary 1:1 with VCC. Output VOH and VOL parameters vary 1:1 with GND. 2. Outputs are terminated through a 50 ohm resistor to GND−2 volts. 3. VCMR Min varies 1:1 with VEE; Max varies 1:1 with VCC. 4. The HYS pin programming characterization information is shown in Figure 2. The hysteresis values indicated in the data sheet are for the condition in which the voltage on the HYS pin is set to VEE. 5. Hysteresis skew (Vskew) is provided to indicate the offset of the hysteresis window. For example, at 25°C the nominal hysteresis value is 27 mV and the Vskew value indicates that the hysteresis was skewed from the reference level by 1 mV in the negative direction. Hence the hysteresis window ranged from 14 mV below the reference level to 13 mV above the reference level. All hysteresis measurements were determined using a reference voltage of 0 mV. The hysteresis skew values apply over the programming range shown in Figure 2. http://onsemi.com 3 MC10E1652 40 -1.0 HYSTERESIS, (mV) Q, OUTPUT VOLTAGE (V) -0.8 HYSTERESIS -1.2 -1.4 -1.6 -1.8 -20 -16 -12 -8 -4 Vref 4 8 12 16 30 T= 25°C 20 T = 0°C 10 0 -0.2 20 Vin, DIFFERENTIAL INPUT VOLTAGE (mV) T= 85°C -0.1 0.0 0.1 0.2 0.3 0.4 0.5 PROGRAMMING VOLTAGE (VOLTAGE ABOVE VEE) Figure 3. Typical Hysteresis Curve Figure 4. Hysteresis Programming Voltage Table 5. AC CHARACTERISTICS VCC = +5.0 V ±5%; VEE = −5.2 V ±5%, VCC = 0 V (Note 6) 0°C Symbol Characteristic Min fMAX Maximum Toggle Frequency tPLH tPHL Propagation Delay to Output (Note 7) ts Setup Time th Enable Hold Time tpw Minimum Pulse Width tskew Within Device Skew (Note 8) tJITTER Cycle−to−Cycle Jitter TDE Delay Dispersion TDL Delay Dispersion VPP Differential Input Voltage tr tf Rise/Fall Times (20-80%) Typ 25°C Max Min TBD Typ 85°C Max Min > 1.0 Typ Max TBD Unit GHz ps V to Q LEN to Q 750 550 900 725 V 450 V −50 LEN 400 1050 900 775 550 925 750 300 450 −250 −50 1075 900 850 650 1025 825 300 550 350 −250 −100 −250 1200 1000 ps ps ps 400 400 15 15 15 ps TBD TBD TBD ps ps (ECL Levels) (Notes 9 10) (Notes 9, 11) 100 60 (TTL Levels) (Notes 12, 13) (Notes 11, 12) 350 100 ps |V1 − V2| 3.7 3.7 3.7 V ps 225 325 475 225 325 475 250 375 500 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 6. Input VIL and VIH parameters vary 1:1 with VCC. Output VOH and VOL parameters vary 1:1 with GND. 7. The propagation delay is measured from the crosspoint of the input signal and the threshold value to the crosspoint of the Q and Q output signals. For propagation delay measurements the threshold level (VTHR) is centered about an 850 mV input logic swing with a slew rate of 0.75 V/NS. There is an insignificant change in the propagation delay over the input common mode range. 8. tskew is the propagation delay skew between comparator A and comparator B for a particular part under identical input conditions. 9. Refer to Figure 4 and note that the input is at 850 mV ECL levels with the input threshold range between the 20% and 80% points. The delay is measured from the crosspoint of the input signal and the threshold value to the crosspoint of the Q and Q output signals. 10. The slew rate is 0.25 V/NS for input rising edges. 11. The slew rate is 0.75 V/NS for input rising edges. 12. Refer to Figure 5 and note that the input is at 2.5 V TTL levels with the input threshold range between the 20% and 80% points. The delay is measured from the crosspoint of the input signal and the threshold value to the crosspoint of the Q and Q output signals. 13. The slew rate is 0.3 V/NS for input rising edges. http://onsemi.com 4 MC10E1652 APPLICATIONS INFORMATION The timing diagram (Figure 5.) is presented to illustrate the MC10E1652’s compare and latch features. When the signal on the LEN pin is at a logic high level, the device is operating in the “compare mode,” and the signal on the input arrives at the output after a nominal propagation delay (tPHL, tPLH). The input signal must be asserted for a time, ts, prior to the negative going transition on LEN and held for a time, th, after the LEN transition. After time th, the latch is operating in the “latch mode,” thus transitions on the input do not appear at the output. The device continues to operate in the “latch mode” until the latch is asserted once again. Moreover, the LEN pulse must meet the minimum pulse width (tpw) requirement to effect the correct input-output relationship. Note that the LEN waveform in Figure 5. shows the LEN signal swinging around a reference labeled VBBINT; this waveform emphasizes the requirement that LEN follow typical ECL 10KH logic levels because VBBINT is the internally generated reference level, hence is nominally at the ECL VBB level. Finally, VOD is the input voltage overdrive and represents the voltage level beyond the threshold level (VTHR) to which the input is driven. As an example, if the threshold level is set on one of the comparator inputs as 80 mV and the input signal swing on the complementary input is from zero to 100 mV, the positive going overdrive would be 20 mV and the negative going overdrive would be 80 mV. The result of differing overdrive levels is that the devices have shorter propagation delays with greater overdrive because the threshold level is crossed sooner than the case of lower overdrive levels. Typically, semiconductor manufactures refer to the threshold voltage as the input offset voltage (VOS) since the threshold voltage is the sum of the externally supplied reference voltage and inherent device offset voltage. VBBINT LEN tpw ts V VIN th VOD VTHR tPLH(LEN) tPHL Q Q Figure 5. Input/Output Timing Diagram http://onsemi.com 5 MC10E1652 DELAY DISPERSION Under a constant set of input conditions comparators have a specified nominal propagation delay. However, since propagation delay is a function of input slew rate and input voltage overdrive the delay dispersion parameters, TDE and TDT, are provided to allow the user to adjust for these variables (where TDE and TDT apply to inputs with standard ECL and TTL levels, respectively). Figure 6. and Figure 7. define a range of input conditions which incorporate varying input slew rates and input voltage overdrive. For input parameters that adhere to these constraints the propagation delay can be described as: TNOM ± TDE (or TDT) where TNOM is the nominal propagation delay. TNOM accounts for nonuniformity introduced by temperature and voltage variability, whereas the delay dispersion parameter takes into consideration input slew rate and input voltage overdrive variability. Thus a modified propagation delay can be approximated to account for the effects of input conditions that differ from those under which the parts where tested. For example, an application may specify an ECL input with a slew rate of 0.25 V/NS, an overdrive of 17 mV and a temperature of 25°C, the delay dispersion parameter would be 100 ps. The modified propagation delay would be 775 ps ± 100 ps -0.9 V - 1.07 V INPUT THRESHOLD RANGE 2.5 V 2.0 V SLEW RATE = 0.25 V/NS INPUT THRESHOLD RANGE SLEW RATE = 0.75 V/NS - 1.58 V - 1.75 V SLEW RATE = 0.30 V/NS SLEW RATE = 0.75 V/NS 0.5 V 0V Figure 6. ECL Dispersion Test Input Conditions Figure 7. TTL Dispersion Test Input Conditions http://onsemi.com 6 MC10E1652 Zo = 50 W Q D Receiver Device Driver Device Q D Zo = 50 W 50 W 50 W VTT VTT = GND − 2.0 V Figure 8. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020 − Termination of ECL Logic Devices.) ORDERING INFORMATION Package Shipping† MC10E1652FNG PLCC−20 (Pb−Free) 46 Units / Rail MC10E1652FNR2G PLCC−20 (Pb−Free) 500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ECL AN1672/D − The ECL Translator Guide AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices http://onsemi.com 7 MC10E1652 PACKAGE DIMENSIONS 20 LEAD PLLC CASE 775−02 ISSUE F B 0.007 (0.180) Y BRK −N− M T L-M 0.007 (0.180) U M N S T L-M S G1 0.010 (0.250) S N S D −L− −M− Z W 20 D 1 X V S T L-M S N S VIEW D−D A 0.007 (0.180) M T L-M S N S R 0.007 (0.180) M T L-M S N S Z C H −T− VIEW S G1 0.010 (0.250) S T L-M SEATING PLANE F 0.007 (0.180) VIEW S S N T L-M S N S K 0.004 (0.100) J M K1 E G 0.007 (0.180) S NOTES: 1. DIMENSIONS AND TOLERANCING PER ANSI Y14.5M, 1982. 2. DIMENSIONS IN INCHES. 3. DATUMS −L−, −M−, AND −N− DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 4. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM −T−, SEATING PLANE. 5. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 6. DIMENSIONS IN THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). http://onsemi.com 8 DIM A B C E F G H J K R U V W X Y Z G1 K1 INCHES MIN MAX 0.385 0.395 0.385 0.395 0.165 0.180 0.090 0.110 0.013 0.021 0.050 BSC 0.026 0.032 0.020 −−− 0.025 −−− 0.350 0.356 0.350 0.356 0.042 0.048 0.042 0.048 0.042 0.056 −−− 0.020 2_ 10 _ 0.310 0.330 0.040 −−− MILLIMETERS MIN MAX 9.78 10.03 9.78 10.03 4.20 4.57 2.29 2.79 0.33 0.53 1.27 BSC 0.66 0.81 0.51 −−− 0.64 −−− 8.89 9.04 8.89 9.04 1.07 1.21 1.07 1.21 1.07 1.42 −−− 0.50 2_ 10 _ 7.88 8.38 1.02 −−− M T L-M S N S MC10E1652 ECLinPS is a trademark of Semiconductor Components INdustries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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