ON LV8813G-AH Motor driver 3-phase pwm full-wave bldc Datasheet

LV8811G, LV8813G, LV8814J
Motor Driver, 3-Phase, PWM,
Full-Wave, BLDC
Overview
The LV8811G, LV8813G, and LV8814J are 3-phase BLDC motor drivers
which are controlled with single Hall sensor. A 180 degrees sinusoidal driving
method is adopted and the IC can control motor with low vibration and the low
noise. Lead-angle adjustment is possible by external pins. The lead-angle base
and lead-angle slope can be adjusted independently. Thus, the device can be
driven by high efficiency and low noise with various motors. The power element
to drive a motor is built-in and contributes to high efficiency by low on
resistance (0.5 Ω). The Hall sensor bias driver is equipped, and a Hall IC is
supported as well. As a method of the rotary speed control of the motor,
direct-PWM pulse input or DC-voltage input can be chosen.
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LV8811G, LV8813G : 20-pin TSSOP
with exposed pad
CASE 948AZ
Features
∙3-phase full wave (sinusoidal) drive
∙Any practical combination of slot and pole can be handled. (e.g. 3S2P, 3S4P,
6S4P, 6S8P, 12S8P, 9S12P and so on)
∙Built-in power FETs (P-MOS/N-MOS)
∙Speed control function by direct PWM or DC voltage input
∙Minimum input PWM duty cycle can be configured by voltage input
∙Soft start-up function and soft shutdown function
∙Soft PWM duty cycle transitions
∙Built-in current limit circuit and thermal protection circuit
∙Regulated voltage output pin for Hall sensor bias
∙Built-in locked rotor protection and auto recovery circuit
∙FG signal output
∙Dynamic lead angle adjustment with respect to rotational speed
∙Lead-angle control parameters can be configured by voltage inputs.
Typical Applications
LV8814J: 20-pin SSOP
CASE 565AN
MARKING DIAGRAM
XXXX = Specific Device Code
Y = Year
M = Month
DDD = Additional Traceability Data
ORDERING INFORMATION
∙Refrigerator
∙PC
∙Games
Ordering Code:
LV8811G-AH
LV8813G-AH
LV8814J-AH
Package
LV8811G, LV8813G
TSSOP20J
(Pb-Free / Halogen Free)
LV8814J
SSOP20
(Pb-Free / Halogen Free)
Shipping (Qty / packing)
2000 / Tape & Reel
† For information on tape and reel specifications, including part
orientation and tape sizes, please refer to our Tape and Reel
Packaging Specifications Brochure, BRD8011/D.
http://www.onsemi.com/pub_link/Collateral/BRD8011-D.PDF
© Semiconductor Components Industries, LLC, 2016
June 2016- Rev. 0
1
Publication Order Number:
LV8811G_LV8813G_LV8814J/D
LV8811G, LV8813G, LV8814J
BLOCK DIAGRAM
Figure 1. LV8811G, LV8813G, and LV8814J Block Diagram
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LV8811G, LV8813G, LV8814J
APPLICATION CIRCUIT DIAGRAM
UO
Hall
WO
VO
Power
Supply
VO
PGND
20
2
UO
(NC)
19
3
RF
WO
18
4
RFS
SGND
17
R1
R2
CM
ZD1
D1
1
C1
R11
5
VCC
CPWM
16
R12
C2
R3
R6
VTH
15
7
PH1
MDS
14
8
PH2
IN2
13
R8
Pull up
power
C3
Exposed-PAD
R7
( )
Rotation
Signal
Output
REG
R5
R4
PWM
Signal
Input
6
9
PWM
10 FG
HB
12
IN1
11
Hall
R9
(R10 )
Notice: LV8814J do not include the exposed-PAD.
Figure 2. Three-phase BLDC Motor Drive with LV8811G, LV8813G, and LV8814J using One Hall Sensor
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LV8811G, LV8813G, LV8814J
UO
Hall
WO
VO
Power
Supply
D1
1
VO
PGND
20
2
UO
(NC)
19
3
RF
WO
18
4
RFS
SGND
17
R2
CM
ZD1
R1
C1
R11
5
VCC
CPWM
16
R12
C2
R3
6
REG
VTH
15
7
PH1
MDS
14
R5
R4
R13
8
R6
R8
Pull up
power
Rotation
Signal
Output
IN2
13
C3
Exposed-PAD
R7
( )
PWM
Signal
Input
PH2
9
PWM
10 FG
R9
HB
12
IN1
11
R14
Hall
IC
R15
(R10 )
Notice: LV8814J do not include the exposed-PAD.
Figure 3. Three-phase BLDC Motor Drive with LV8811G, LV8813G, and LV8814J using One Hall IC
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4
LV8811G, LV8813G, LV8814J
UO
Hall
WO
VO
Power
Supply
D1
1
VO
PGND
20
2
UO
(NC)
19
3
RF
WO
18
4
RFS
SGND
17
5
VCC
CPWM
16
R2
CM
ZD1
R1
C1
R14
C2
R3
6
REG
15
7
PH1
MDS
14
8
PH2
IN2
13
R15
C4
R17
R18
R16
MN1
R5
R4
R6
Pull up
power
PWM
10 FG
R9
R11
C3
Exposed-PAD
9
Rotation
Signal
Output
VTH
C5
HB
12
IN1
11
R12
Hall
PWM
Signal
Input
(R10 )
R13
Notice: LV8814J do not include the exposed-PAD.
Figure 4. Three-phase BLDC Motor Drive with LV8811G, LV8813G, and LV8814J using input PWM to DC conversion for
speed control
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LV8811G, LV8813G, LV8814J
EXAMPLE COMPONENT VALUE
Device
D1
ZD1
Value
MBRA340T3G (ON semi)
MNSZ5247BT1G (ON semi)
CM
C1
C2
C3
C4
C5
4.7µF
1500pF
1µF
0.1µF
1µF
330pF
R1
R2
R3
R4
0.22Ω // 0.22Ω (0.5W)
1kΩ
0 to 50kΩ
50k to 0Ω
Device
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
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Value
0 to 50kΩ
50k to 0Ω
1kΩ
NC
1k to 10kΩ
1kΩ
0 to 50kΩ
50k to 0Ω
10kΩ
30kΩ
7.5kΩ
62kΩ
68kΩ
1kΩ
LV8811G, LV8813G, LV8814J
PIN ASSIGNMENT
VO
1
20
PGND
UO
2
19
(NC)
RF
3
18
WO
RFS
4
17
SGND
VCC
5
16
CPWM
REG
6
15
VTH
PH1
7
14
MDS
PH2
8
13
IN2
Exposed-PAD
PWM
9
12
HB
FG
10
11
IN1
Notice: LV8814J do not include the exposed-PAD.
Figure 5. LV8811G, LV8813G, and LV8814J Pin Assignment
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LV8811G, LV8813G, LV8814J
LV8811G, LV8813G, and LV8814J COMPARISION
ASSUME APPLICATION
-LV8811G: Wide operation supply voltage range. Suitable rotate for small-size fans.
-LV8813G: Stable start-up even with a large load. Suitable rotate for large-size fans.
-LV8814J: Stable start-up even with a large load. Suitable rotate for large-size fans.
DIFFERENT CHARACTERISTICS
LV8811G
LV8813G
LV8814J
VCC/RF operating
Supply
voltage
range
3.6V to 16V
6.0V to 16V
3.6V to 16V
Alignment
cycle
6%->5%->
20%->15%
50%->25%
Alignment time
0.8ms
1.0s
Lock
time
0.33s
0.77s
5.8s
5.4s
1:5
1:3
duty
detection
Lock-Stop
Release Time
Lock/Release time
ratio
Package type
TSSOP20J
SSOP20
Comment
LV8811G and LV8814J have a wide operation voltage
range.
LV8811 and LV8814J have different lower Vcc limit in
comparison with the LV8813 to support larger fans.
LV8813G and LV8814J have stronger alignment to
secure the start-up of large-size fans.
LV8813G and LV8814J have longer alignment time to
secure the start-up of large-size fans.
LV8813G and LV8814J have longer detection time to
prevent false Lock detection on large-size fans at the
start-up.
Pin Name
VO
UO
RF
RFS
VCC
REG
PH1
PH2
PWM
FG
IN1
HB
IN2
MDS
VTH
CPWM
SGND
WO
NC
PGND
10
20
10, 20,
23,25
10, 23, 25
This characteristic is different due to a different Lock
detection time.
23, 25
TSSOP20J has the Exposed-PAD on back. SSOP20
don’t have Exposed-PAD. Foot pattern is same.
34, 35
PIN FUNCTION DISCRIPTION
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Reference
page
Description
V-phase output pin
U-phase output pin
Inverter power supply and Motor current sense resistor pin
Motor Current Sense
Power supply pin
Internal regulator output pin
Lead-angle adjustment pin 1
Lead-angle adjustment pin 2
Speed reference input PWM pin
Motor speed feedback output pin
Hall sensor input pin 1
Hall sensor bias output pin
Hall sensor input pin 2
Minimum output PWM duty cycle setting pin
Speed reference input DC voltage pin
PWM clock frequency control pin
System ground pin
W-phase output pin
No connection
Power ground pin
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LV8811G, LV8813G, LV8814J
MAXIMUM RATINGS (Note 1)
Parameter
Symbol
Value
Unit
Maximum supply voltage (Note2)
VCCMAX
20
V
Maximum output voltage (Note3)
VOUTMAX
20
V
Maximum output current (Note3, Note4)
IOUTMAX
2.0
A
REG pin maximum load current
IREGMAX
20
mA
HB pin maximum load current
IHBMAX
10
mA
PWM pin maximum input voltage
VPWMMAX
6
V
FG pin maximum voltage
VFGMAX
17
V
Input pins maximum voltage (Note5)
(Note 6)
3.6
V
Allowable Power Dissipation (Note7)
PdMAX
2.5
W
Storage Temperature
Tstg
−55 to 150
ºC
Junction Temperature
TJMAX
150
ºC
Moisture Sensitivity Level (MSL) (Note8)
MSL
3
-
Lead Temperature Soldering Pb-Free Versions (30sec or less) (Note 9)
TSLD
255
ºC
ESD Human body Model : HBM (Note10)
ESDHBM
±2000
V
1.
Stresses exceeding those listed in the Maximum Rating table may damage the device. If any of these limits are exceeded, device
functionality should not be assumed, damage may occur and reliability may be affected.
2. VCC supply pins are VCC (5pin), RF (3pin), and RFS (4pin).
3. Motor power supply pins are UO (2pin), VO (1pin), and WO (18pin).
4. IOUTMAX is the peak value of the motor supply current.
5. Input pins are PH1 (7pin), PH2 (8pin), IN1 (11pin), IN2 (13pin), MDS (14pin), VTH (15pin), and CPWM (16pin).
6. Pin : Symbol PH1:VPH1MAX, PH2:VPH2MAX, IN1:VIN1MAX, IN2:VIN2MAX, MDS:VMDSMAX, VTH:VVTHMAX, CPWM:VCPWMMAX
7. Specified circuit board: 57.0mm×57.0mm×1.6mm, glass epoxy 2-layer board. It has 1 oz copper traces on top and bottom of the board.
Please refer to Thermal Test Conditions of page 32.
8. Moisture Sensitivity Level (MSL): 3 per IPC/JEDEC standard: J-STD-020A
9. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D
http://www.onsemi.com/pub_link/Collateral/SOLDERRM-D.PDF
10. ESD Human Body Model is based on JEDEC standard: JESD22-A114
THERMAL CHARACTERISTICS
Parameter
Symbol
Thermal Resistance, Junction-to-Ambient (Note7)
RθJA
Thermal Resistance, Junction-to-Case (Top) (Note7)
RΨJT
Condition
Value
Unit
Case of the LV8811G and LV8813G
50.0
ºC/W
Case of the LV8814J
95.0
ºC/W
Case of the LV8811G and LV8813G
15.5
ºC/W
Case of the LV8814J
35.0
ºC/W
Allowable power dissipation Pdmax - W
2.8
2.5
2.4
θja : LV8811G, LV8813G
2
(TSSOP20J)
1.6
1.31
1.2
0.9
θja : LV8814J
0.8
(SSOP20)
0.47
0.4
0
-40
-20
0
20
40
60
80
100
120
Ambient temperature, Ta - ˚C
Figure 6. Power Dissipation vs Ambient Temperature Characteristic
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140
LV8811G, LV8813G, LV8814J
RECOMMENDED OPERATING RANGES (Note11)
Parameter
Symbol
VCC supply voltage Range at LV8811G and LV8814J (Note2)
VCCOP
VCC supply voltage Range at LV8813G (Note2)
Ratings
Unit
3.6 to 16.0
V
6.0 to 16.0
V
PWM input frequency range
fPWM
20 to 50
kHz
PWM input duty cycle range
DPWM
0 to 100
%
PWM input voltage range
VPWM
0 to 5
V
IN1 input voltage range
VIN1
0 to VREG
V
IN2 input voltage range
VIN2
0.3 to 1.8
V
Control input Voltage Range (Note12)
(Note 13)
0 to VREG
V
Ambient Temperature
TA
−40 to 105
ºC
11. Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses
beyond the Recommended Operating Ranges limits may affect device reliability.
12. Control input pins are PH1, PH2, MDS, and VTH
13. Pin : Symbol PH1:VPH1, PH2:VPH2, MDS:VMDS, VTH:VVTH
ELECTRICAL CHARACTERISTICS
TA=25ºC, VCCOP = 12V UNLESS OTHERWISE NOTED. (NOTE 14)
Parameter
Symbol
Condition
Min
Typ
Max
Unit
4.5
7.0
mA
0.198
V
Circuit Current
Supply Current
ICC0
PWM = 3V, CPWM=0V, IO=0A
Over Current Detection Voltage
VTHCLM
The voltage between VCC - RF
0.162
0.180
Over Voltage Detection Voltage
VTHOVP
VCC pin, Guaranteed by design
19
20
V
Over Voltage Detection Hysteresis
ΔVTHOVP
VCC pin, Guaranteed by design
2
V
Lock Detection Time
TLD
Protection (Note15)
Lock Protection Time
Thermal Protection Detection
Temperature
Thermal Protection Detection
Hysteresis
Case of the LV8811G
0.23
0.32
0.41
S
Case of the LV8813G and LV8814J
0.55
0.76
0.97
S
Case of the LV8811G
4.15
5.68
7.21
S
Case of the LV8813G and LV8814J
3.82
5.23
6.64
S
TTHP
Guaranteed by design
150
180
˚C
ΔTTHP
Guaranteed by design
15
˚C
TLP
Regulator
REG Pin Output Voltage
VREG
2.7
3.0
3.3
V
0.5
0.65
Ω
Output
UO/VO/WO Output Resistance
ROUTON
IO=0.8A, High-side + Low-side
FG Pin Low Level Output Voltage
VFGL
IFG=5mA
0.3
V
FG Pin Leak Current
IFGLK
VFG=16V
1
μA
HB Pin Output Voltage
VHB
IHB=5mA
1.30
V
IN1/IN2 Input Current
IH
1
μA
Hall Signal Input Hysteresis
ΔVH
FG Output (Note16)
Hall Bias & Hall Signal Input
Guaranteed by design
1.06
1.18
+/-10
mV
Continued on next page.
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LV8811G, LV8813G, LV8814J
Continued from preceding page.
Parameter
Symbol
Condition
Min
Typ
Max
Unit
PWM Input
PWM Pin Low Level Input
Voltage
PWM Pin High Level Input
Voltage
PWM On Time
PWM Off Time
VPWML
0
0.6
V
VPWMH
2.3
5.5
V
TPWMON
Guaranteed by design
200
ns
TPWMOFF
Guaranteed by design
200
ns
CPWM Input
CPWM Minimum Output
Ratio (Note17)
CPWM Maximum Output
Ratio (Note17)
VCPWML
× 100
VREG
VCPWMH
× 100
VREG
16
18
20
%
65
67
69
%
CPWM Source Current
ICPWMSO
VCPWM=1.3V
17
29
41
μA
CPWM Sink Current
ICPWMSI
VCPWM=1.3V
-41
-29
-17
μA
14. Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted.
Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.
15. Refer to the protection circuit explanation in the function description. Refer to page 23.
16. For FG output pin, it is recommended to connect pull-up resistor between the pin and power supply of the controller.
17. VCPWMH and VCPWML are peak voltage of triangle wave in CPWM pin.
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LV8811G, LV8813G, LV8814J
TYPICAL CHARACTERISTICS
Figure 7. Supply current vs VCC voltage
Figure 10. Current limiter detection voltage vs VCC
voltage
Figure 8. VREG output voltage vs VCC voltage
Figure 11. VREG output voltage vs REG load current
Figure 9. Output ON resistance vs Output current
Figure 12. FG output voltage vs FG input current
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LV8811G, LV8813G, LV8814J
Figure 13. FG leakage current vs FG input voltage
Figure 16. VHB output voltage vs VCC voltage
Figure 14. VHB output voltage vs HB load current
Figure 17. IN1/IN2 input current vs IN1/IN2 input voltage
Figure 15. PWM threshold voltage vs VCC voltage
Figure 18. CPWM charge/discharge current
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LV8811G, LV8813G, LV8814J
Functional Description
POWER SUPPLY PINS (VCC, RF)
RF is output power supply whereas VCC is other circuit
supply. The RF pin supplies large current to built-in
power MOS FTEs. (Figure 23)
*Please refer to page.15 ‘Motor Current Sense Resistor
Pin (RF)’ about the CLM sense resistance of RF
terminal.
GND PIN (SGND, PGND)
PGND is power ground whereas SGND is other circuit
ground. Since PGND has to tolerate surge of current,
separate it from the SGND as far away as possible and
connect it point-to-point to the ground side of the
capacitor (CM) between power supply and ground.
Internal 3.0V Voltage Regulator Pin (REG)
An internal 3.0V voltage regulator acts a power source
for internal logic, oscillator, and protection circuits.
When MDS and PH1 and PH2 are used, it is
recommended that application circuits are made using
this output. In addition, the application circuit of VTH is
same, too. The maximum load current of REG is 10mA.
Warn not to exceed this. Place capacity of 1uF degree
and the 0.1uF degree in the close this pin. (Figure 19)
Figure 20. Equivalent circuit of FG
MOTOR DRIVE OUTPUT PINS (UO, VO, WO)
These pins are output of built-in three-phase MOSFET
based inverter that drives the motor. Each leg of the
inverter is having high side P-MOSFET and low side
N-MOSFET. (Figure 21)
Figure 21. Equivalent circuit of U/V/W
HALL-SENSOR BIAS OUTPUT PIN (HB)
The LV811G, LV8813G, and LV8814 provide a bias
regulator output (1.18V typ.) for a hall sensor. It is
recommended that this output used only for hall sensor
bias.
Figure 19. Equivalent circuit of REG
ROTATIONAL SIGNAL PIN (FG)
Frequency of the FG output represents the motor’s
electrical rotational speed (the same rectangular waves
as the UO). It is an open drain output. Recommended
pull up resistor value is 1kΩ to 10kΩ. Leave the pin
open when not in use. (Figure 20)
HALL-SENSOR INPUT PINS (IN1, IN2)
Differential output signals of the Hall sensor are
connected to IN1 and IN2 individually. Its polarity is
determined by a combination of the number of slot and
poles. (Figure 29)
It is recommended to add 0.1uF capacitor between
them to filter system noise.
Topologies, in the case of a Hall IC, are shown in Figure
30 on page18. The topology (including polarity) is also
determined by the combination of the number of slot
and poles.
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LV8811G, LV8813G, LV8814J
When the pin IN1 is connected to the output of the Hall
IC, the pin IN2 must be kept in the middle level of the
Hall IC power supply voltage. When the pin IN2 is
connected to the output of the Hall IC, the pin IN1 must
be kept in the middle level of the Hall IC power supply
voltage. Because of the input circuit (Figure 22), the
input voltage of IN2 must be higher than 0.3V.
Therefore, the resistance ratio must be decided so that
IN2 voltage is higher than 0.3V. (Figure 30)
Regarding the polarity of a Hall sensor and IC, refer
‘Rotation Direction’ on page18.
The sense resistor value is calculated as follows.
Sense Resistor[Ω] =
VTHCLM [V]
ICLM [A]
For example, to set the CLM current threshold at 1.5A,
the sense resistor value is
Sense Resistor =
Res = 0.12[Ω]
0.18(typ)
1.5
MOTOR CURRENT SENSE PIN (RFS)
This pin reads voltage across the series sense resistor
and compares with internal VTHCLM. When the
measured voltage exceeds VTHCLM, CLM is triggered
and when it falls below VTHCLM, the LV8811G,
LV8813G, and LV8814J exits from the CLM mode. A
series RC filter is recommended to avoid false detection
due to switching noise. (Figure 24)
Vcc
LPF
∆V
RFS
Vcc
Figure 22 Equivalent circuit of IN1, IN2
V = VTHOCP
MOTOR CURRENT SENSE RESISTOR PIN (RF)
This is also the power supply pin for the built-in power
inverter. Voltage across the sense resistor represents the
motor current and is compared against the internal
VTHOVC (0.18Vtyp.) for setting the over-current limiter
(CLM). (Figure 23)
The serise resistor (Sence resistor)
Vcc
U
V
W
RF
∙∆V < VTHOCP ‫׃‬
The OCP mode is ineffictive.
∙ ∆V > VTHOCP ‫׃‬
The OCP mode is effictive.
Control to OCP
Figure 24. Schematic view of the CLM circuit
RF
PGND
The power MOS FETs
Figure 23. Schematic view of power current route
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LV8811G, LV8813G, LV8814J
COMMAND INPUT (PWM)
PWM FREQUENCY SETTING PIN (CPWM)
This pin reads the duty cycle of the PWM pulse and
controls rotational speed. The PWM input signal level is
supported from 2.5V to 5V. The combination with the
rotational speed control by DC voltage is impossible.
When the pin is not used, it must be connected to ground.
The minimum pulse width is 200ns. (Figure 25)
When rotational speed is controlled with the DC voltage,
this pin is used. The frequency of the triangle wave
which the pin generates at external capacity can be
changed. The frequency of this triangle wave equals
frequency of the PWM control that the output works.
The relations between the external capacitor and
frequency are shown in the next equation.
PWM Frequency fPWM [Hz] is,
fPWM =
ICPWMSI/O [A]
2 × (VCPWMH − VCPWML )[V] × CPWM [pF]
Where,
ICPWMSI/O = ICPWMSO = −ICPWMSI ∶ 29[uA](typ. )
Charge/discharge current
VCPWMH: 2.01[V] (typ.) Upper peak voltage of CPWM
triangle waveform. 67% of 3V VREG
VCPWML: 0.54[V] (typ.) Lower peak voltage of CPWM
triangle waveform. 18% of 3V VREG
Figure 25. Equivalent circuit of PWM
MINIMUM DUTY CYCLE SETTING PIN (MDS)
The too small duty cycle of the input PWM can be
blanked out. The threshold of the minimum duty cycle
is configurable. The DC voltage level applied to this pin
is converted to this threshold. The voltage is fetched
right after the power-on-reset. Because the internal
conversion circuit works inside REG power rail, it is
recommended that the MDS voltage is made from VREG.
This pin is also used for setting of FG frequency. Refer
‘Parameter Setting by Constant Voltage’ on page 28,
and ‘Setting Minimum PWM Duty Cycle’ on page 29.
For example, the capacitance of CPWM, to make the
PWM frequency 30 kHz, can be determined by the
followings
29u
30k =
2.94 × CPWM
CPWM ≅ 330[pF]
CPWM decides output PWM frequency. Thus, this value
must choose appropriately. The range from 220pF to
330pF is recommended. CPWM is represented C5 in the
application circuit diagram, Figure 4 on page 5.
The combination with the rotational speed control by
PWM is impossible. When this pin is not used, it must
be connected to GND. Refer ‘PWM duty CYCLE
control by analog voltage’ on page 26. (Figure 26)
LEAD-ANGLE SETTING PIN (PH1, PH2)
LV8811G, LV8813G, and LV8814J provide the
dynamic lead angle adjustment. To match the motor
characteristics, the base angle and change ratio with
respect to the rotation speed can be configured. The DC
voltage levels applied to these pins are converted to the
lead angle parameter. The voltages are fetched right
after the power-on-reset. Because the internal
conversion circuit works inside REG power rail, it is
recommended that the PH1 and PH2 voltages are made
from VREG. Refer ‘Parameter Setting by Constant
Voltage’ on page 28, and ‘Setting Lead Angle’ on page
30.
Figure 26. Equivalent circuit of CPWM
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16
LV8811G, LV8813G, LV8814J
ROTATIONAL CONTROL PIN BY DC VOLTAGE (VTH)
This pin reads the input DC voltage and controls
rotational speed. The VTH voltage is compared with the
CPWM triangle wave with an internal comparator and
generates PWM pulse and controls rotational speed with
frequency and duty cycle of this pulse.
If the external control signal is the pulse type, it should
be flattening by the filter and be shifted to suitable level.
The external circuit example is shown in Figure 4.
VTH input level flatten by the filter is calculated in the
following equation.
VVTH = VREG × �
R15 + R16 R14 × R16 DPWM
−
×
�
RA
RA × RB
100
Where
R A = R14 + R15 + R16
R B = R14 + R15
VVTH = VTH input level
Figure 27. Equivalent circuit of VTH
NC PIN (NC)
This pin is not connection to the internal circuit.
This calculation is justified by the condition that Rds of
MN1 << R16. So, a large value of resistor should be
selected to R16.
For example, when the input PWM duty cycle is set in
50%, can be determined by follows.
50[%]
)
VVTH = 3[V] × (0.698 − 0.498 ×
100
VVTH = 1.35[V]
Where
R14=7.5[kΩ], R15=30[kΩ], R16=62[kΩ]
The cut-off frequency fc by C4 and R18 is calculated in
the following equation.
fc =
1
2𝜋𝜋 × 𝐶𝐶4 × 𝑅𝑅18
The actual value of C4 or R18 is better to select more than
50 times the above calculation value to be flatten
thoroughly. Furthermore, it is better to do it by the value
of C3 because of the effect of input impedance at VTH
pin.
If the external control signal is the DC type, it inputs
into direct VTH pin. However, It is recommended that
the filter (C4 and R18) is kept because rid of the influence
of the noise.
The CPWM amplitude is decided by VREF. Thus, VTH
recommends that it is made from VREG. The
combination with the rotational speed control by PWM
is impossible. When the pin is not used, it must be
OPEN. Refer ‘PWM duty CYCLE control by analog
voltage’ on page 26. (Figure 27)
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17
LV8811G, LV8813G, LV8814J
DETAILED DESCRIPTION
As for all numerical value used in this description, the design value or the typical value is used.
ROTATION DIRECTION
The motor type can be categorized into two groups as
3S2P and 3S4P. (S: Slot, P: Pole). The 3S2P group
contains 3S2P, 6S4P and 12S8P, for instance, and 3S4P
groups contains 3S4P, 6S8P and 9S12P. The rotate
3S2P
3S4P
direction of 3S2P group is CW, that of 3S4P group is
CCW. The direction can be changed by exchanging
connection between U and W, in the case where the hall
sensor is between U coil and W coil. (Figure 28)
6S4P
12S8P
6S8P
9S12P
Figure 28. Schematic diagram of motor
Hall output polarity also needs to be set with the type of SP motors. It is shown in Figure 29, Figure 30
3S2P
6S4P
12S8P
3S4P
6S8P
9S12P
IN2 13
+
HB 12
Hall
-
IN1 11
3S2P
6S4P
REG
6
IN2
13
Open
HB
12
IN1
11
12S8P
Hall
IC
IN2 13
VDD
VSS
+
HB 12
Hall
-
IN1 11
Figure 29. Hall element use connection
REG
6
IN2
13
3S4P
6S8P
9S12P
Open
HB
12
IN1
11
Hall
IC
VDD
VSS
Figure 30. Hall IC use connection
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18
LV8811G, LV8813G, LV8814J
DEVICE START-UP
OUTPUT WAVEFORM
The LV8811G, LV8813G, and LV8814J will start driving,
when the PWM signal is input at the PWMIN pin after a
power supply is turned on.
The output PWM duty cycle is modulated so that the
phase-to-phase voltage waveform is sinusoidal. Two
phases are driven with PWM, while the other phase sunk
to ground.
It can handle the rotational speed up to the 250Hz of FG
frequency (electrical cycle). However, for high speed case,
it depends on motor mechanical parameters. Low speed
side recommends the rotational speed down to the 30Hz
of FG frequency.
A wave pattern example is shown in Figure 31.
COMMUTATION
The commutation timing is determined with respect to the
one Hall sensor or Hall-IC signal, while conventional
sensor-based BLDC motor drivers need three sensors.
IN1 +
IN1 IN1
L
L
L
H
H
H
L
L
L
H
H
H
hall
comparator
FG
Max
UO
0%
Max
VO
0%
Max
WO
0%
Figure 31. Timing chart example: Normal Rotation
The amplitude of current waveform is controlled with input PWM duty cycle while the sinusoidal waveform is kept.
FG
U-out
Current of U-out
Input PWM duty-cycle 50%
Input PWM duty-cycle 100%
Figure 32. Normal Rotation (Output pin)
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LV8811G, LV8813G, LV8814J
DETAIL OF THE ROTOR START POSITION ALIGNMENT
After detecting input PWM, the motor-rotor is aligned
to the start position. The start position alignment is
independent on the input PWM duty cycle, and applies
the preset duty cycle described below.
[LV8811G] The output PWM duty cycle sequence for
the rotor alignment consists of the three steps.
Alignment duty cycle 1st: 6%, 2nd: 5%, 3rd: 20%
[LV8813G, LV8814J] The output PWM duty cycle
sequence for the rotor alignment consists of the single
step.
Alignment duty cycle 50%
(Figure 33)
60%
Input duty [%]
Output duty [%]
Input frequency [kHz]
30kHz
50%
LV8813G, LV8814J
25%
20%
15%
LV8811G
6%
5%
0%
60ms
LV8811G Alignment time
800ms
1s
Time
LV8813G and LV8814J Alignment time
30kHz
Output frequency [kHz]
Figure 33. Timing chart example: Alignment duty cycle
ROTATION START-UP AND SOFT-START
After the adjustment of the start position, the output
duty-cycle begin from 15% (LV8811G) or 25%
(LV8813G, LV8814J). The motor starts to rotate in
sinusoidal drives, increasing output duty cycle (increment
slope is 26[%/s]) till the output duty cycle reaches the
target duty cycle. In case the input PWM duty cycle is
under 20%, the output duty cycle decreases to the target
duty cycle (decrement slope is 26[%/s]) after reaching
20%. After 32 FG pulses the lead angle increases to the
target lead angle (tuned from PH1/PH2) by 1 degree steps
at every FG edge. (Figure 34)
Output duty [%](Duty was set more than 20%)
LV8813G
LV8814J
Target duty( > 20% )
LV8811G
Alignment term
20%
Δ= 26[%/sec]
Output duty [%](Duty was set less than 20%)
Alignment term
20%
LV8813G
LV8814J
LV8811G
Lead angle [deg]
FG count
= 32
Δ= - 26[%/sec]
Lead angle
adjusting
Δ= 1 [deg/FG]
0
Target duty( < 20% )
Target Lead angle
Time
0.8s / 1.0s
Positioning drive
Sinusoidal drive
Figure 34. Timing chart example: Positioning and Soft start
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LV8811G, LV8813G, LV8814J
PWM
FG
U out
Current
of U-out
Input PWM duty-cycle 18%
Input PWM duty-cycle 50%
Figure 35. Alignment and Soft start (Case of the LV8811G)
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LV8811G, LV8813G, LV8814J
DUTY CYCLE DECREASING AND STOP
When input PWM duty cycle is changed from high to low,
the output duty cycle decreases gradually to low with the
Input
duty [%]
decrement slope of 26[%/s]. The target duty cycle is
always updated at positive edge of FG. (Figure 36)
80%
20%
Output duty [%]
LV8813G
LV8814J
80%
60%
0%
80%
60%
60%
Δ= 26[%/sec]
Alignment term
20%
20%
LV8811G
0
Time [sec]
0.8s / 1.0s
Input PWM duty
80%
20%
FG pulse
Target PWM duty
80%
20%
Figure 36. Timing chart example: When PWM Duty cycle changed (80% -> 20% -> 60% -> 0%)
PWM
80%
20%
50%
0%
FG
U-Out
Current
of U-Out
Figure 37. Input duty cycle changing (Case of the LV8811G)
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LV8811G, LV8813G, LV8814J
OUTPUT FREQUENCY
When input PWM duty cycle is 100%, the output
frequency is 66kHz generated from the internal oscillator.
When input PWM duty cycle is changed from 100% to
low (e.g. 50% with 30kHz), output frequency is changed
Input duty [%]
Output duty [%]
Input frequency [kHz]
100%
Alignment term
from 66kHz to input PWM frequency (this case is 30kHz).
When input PWM duty cycle is changed to 100% again,
output frequency will remain last input frequency (this
case is 30kHz). (Figure 38)
100%
50%
100%
(DC)
30kHz
(DC)
100%
100%
LV8813G
LV8814J
LV8811G
50%
50%
25%
20%
15%
Time
66kHz (Initial freq)
Output frequency [kHz]
30kHz
30kHz
Figure 38. Timing chart example: Output frequency changing
PROTECTIONS
When THP (Thermal Protection) or CLM (Current
Limiter) is detected, the output duty cycle decreases to the
minimum duty cycle rapidly. After exiting the protection
mode, the output duty cycle increases with 26 [%/s] slope.
When OVP (Over Voltage Protection) or LVD (Low
Voltage Detection) signal is detected, all outputs are
turned off. After OVP and LVD are released, outputs are
turned on. (Figure 39)
When the current limiter is detected, the output duty cycle
may be restricted before achieving target duty cycle. The
output duty cycle decreases immediately by the current
limiter. The current limiter is release, because the output
duty cycle decreases. Herewith, the output duty cycle
increases to the target duty cycle. And the current limiter
is detected again, and the output duty cycle decreases.
On/off of the current limiter is repeated, and the output
duty cycle is limited. When the PWM input changes to
low duty cycle that release CLM, the output duty cycle
decreases gradually with normal slope rate of 26[%/s].
(Figure 40)
When current limiter activates with 100% input duty
cycle, the output duty cycle is restricted before achieving
target duty cycle (100%). When the PWM input changes
from less than low duty cycle, the output duty cycle
decreases to the input duty cycle immediately without
slope rate.
(Figure 41)
The level of current limiter is adjustable using the value of
RF resistor.
The value of RF resistor should be set higher than the
current drawn at 100% input duty cycle.
Lock detection and Lock protection
[LV8811G] It takes 5.68s for Lock protection time. Lock
start time is 1.12s. This equals to the total of lock detect
time and the alignment time. The protection-start time
ratio is approx. 1:5. Output under lock protection is in
Hi-Z state.
(Figure 43)
[LV8813G, LV8814J] The lock protection behavior is
same as LV8811G. However, the release time and restart
time are changed as follows:
Lock protection time: 5.23s Lock start time: 1.76s
Protection-start ratio: approx. 1:3 (Figure 44)
When the lock start time, heat is generated that because IC
turned on electricity to the motor. On the other, when the
lock protection time, radiated heat that because IC turned
off electricity to the motor.
Output duty [%]
80%
20%
Input duty
80%
20%
THP or CLM
OVP
LVD
Figure 39. Timing chart example: Protections
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23
PWM OFF
PWM OFF
50%
50%
Time
LV8811G, LV8813G, LV8814J
Input duty [%]
Input frequency [kHz]
80%
50%
30kHz
30kHz
Output duty [%]
LV8813G, LV8814J
80%
Target 80%
Alignment term
20%
25%
Limit Duty
LV8811G
50%
15%
Time
30kHz
30kHz
Output frequency [kHz]
CLM (Current limitter)
*In the case of LV8811G
Figure 40. Timing chart example: Normal current limiter (e.g. input duty cycle 80% -> 50%)
Input duty [%]
Output duty [%]
Input frequency [kHz]
100%
50%
(DC)
30kHz
LV8813G, LV8814J
100%
Limit Duty
LV8811G
Alignment term
20%
Target 100%
50%
25%
15%
Time
66kHz (Initial)
Output frequency [kHz]
30kHz
CLM (Current limitter)
*In the case of LV8811G
Figure 41. Timing chart example: Current limiter at input duty cycle 100%
PWM
100% Duty
50% Duty
100% Duty
50% Duty
FG
U-Out
Current
of U-Out
CLM ON at PWM duty-cycle 100%
CLM OFF at PWM duty-cycle 100%
Figure 42. Inputting 100% with and without CLM (Case of the LV8811G)
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LV8811G, LV8813G, LV8814J
0.80s
0.32s
Alignment
Drive
Lock
Detect
5.68s
Lock Protect
Lock start time
1.12sec
( Hi-Z state )
Lock protection time
5.68sec
0.80s
0.32s
Alignment
Drive
Lock
Detect
Time
[sec]
Lock start time
1.12sec
Lock start time : Lock protection time = 1.12 : 5.68 ≈ 1: 5 (Protection-start ratio)
Figure 43. Timing chart example: Lock Protection for LV8811G
1.00s
0.76s
Alignment
Drive
5.23s
Lock
Detect
Lock Protect
Lock start time
1.76sec
( Hi-Z state )
Lock protection time
5.23sec
1.00s
0.76s
Alignment
Drive
Lock
Detect
Lock start time
1.76sec
Lock start time : Lock protection time = 1.76 : 5.23 ≈ 1: 3 (Protection-start ratio)
Figure 44. Timing chart example: Lock Protection for LV8813G and LV8814J
PWM
FG
Lock protect
Alignment
&
Lock detect
U-Out
Lock protect
Current
of U-Out
Re-start
Figure 45. Lock Protection (Case of the LV8811G)
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25
Time
[sec]
LV8811G, LV8813G, LV8814J
PWM DUTY CYCLE CONTROL BY ANALOG VOLTAGE
The duty cycle of PWM output is determined by
comparison of CPWM oscillation and DC level which is
input to VTH pin. When CPWM level is lower than VTH,
the PWM output applies the voltage to the coil from the
power supply. When CPWM level is higher than VTH,
the PWM output is switched to the current circulation
state with self-induction of the coil.
The DC level of VTH can control between VREG×18% and
VREG×67%. But the PWM pulse width must not make less
than 200ns. The pulse width of 0s is accepted. (Figure 46)
VTH
VREG x 67%
CPWM
VREG x 18%
PWM
The pulse width
200ns and more.
The pulse width
200ns and more.
Controllable duty by VHT input
Fixed duty by
MDS setting
Figure 46. PWM Duty cycle control by CPWM and the VTH voltage
The relations of VVTH and output PWM duty cycle are
clculated by following equation.
VVTH = VCPWMH − (VCPWMH − VCPWML ) ×
Where
DOUT = Output PWM duty cycle
DOUT
100
h′ =
For example, when the output PWM duty cycle is set in
30%, it can be determined by follows.
VVTH = 2.01[V] − (2.01[V] − 0.54[V]) ×
= 1.569[V]
The input range of VTH is calculated in the following
equation. (Figure 47)
30[%]
100
t′
×h
t
VTH control range[V] = 0.18VREG + h′ ~ 0.67VREG − h′
Where,
h = VCPWMH [V] − VCPWML [V]
t=
When the output PWM duty cycle is set in 100%, it is
recommended to set the VTH input level lower than
VCPWML. In addition, when the output PWM duty cycle
is set in 0%, it is recommended to set the VTH input
level higher than VCPWMH.
(VCPWMH −VCPWML)[V]×C5 [pF]
ICPWMSI/O [A]
t ′ = 200ns ÷ 2 = 100ns
*C5 is the CPWM pin external capacity. Refer to page.5 and 17
For example, when 330[pF] is used for CPWM capacity, can
be determined by followings
0.1[us]
h′ =
× 1.47[V] = 8.79[mV]
16.73[us]
From the above-mentioned result, the range of the VTH input
voltage is
∙Full speed
0.18VREG or less than,
∙ Rotational speed control
0.18VREG+8.79[mV] to 0.67VREG-8.79[mV],
∙ Motor stop
0.67VREG or more than
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26
LV8811G, LV8813G, LV8814J
A
CPWM
h'
VTH
h
D
Ө
∆ABC ~ ∆ADE
BC : DE = AC : AE
h'
E
h
→ t : t' = h : h'
t'
∴ h' = × h
t
t
PWM
B
2t'
Ө
Pulse width(200ns and more)
t
t'
C
Figure 47. Reference of the calculation of the VTH input range
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LV8811G, LV8813G, LV8814J
PARAMETER SETTING BY CONSTANT VOLTAGE
PH1, PH2 and MDS can be set by the external DC voltage
levels. PH1 and PH2 are used for setting the lead angle.
MDS is for setting minimum duty cycle. The input span of
these pins is 0 to 3V (VREG). The full scale is divided by
64 steps, thus the resolution is 47mV/step. Excluding the
lowest 3 steps and the highest 2 steps, the DC voltage is
translated to the parameters linearly. Hence, the linear
setting range is 0.141V to 2.906V. The voltage within the
lowest 3 steps (0 to 0.141V) selects the default value.
As for the highest 2 steps is below.
MIN SET
0.141V
3/64 x VREG
0V
VPH1[V]
VPH2[V]
VMDS[V]
MDS
•Lowest 3 steps are FG cycle 1 electrical, and default
setting for MDS.
•Highest 2 steps is FG cycle 2 electrical, and default
setting for MDS.
PH1/PH2
•Highest 2 steps is prohibit.
(Figure 48)
1.0V
2.0V
1/3 VREG
2/3 VREG
MAX SET
2.906V
62/64 x VREG
3.0V
VREG
64 step
3 step
2 step
Default setup
Prohibit
Adjustable range (60 step)
PH1
Lead angle axis intercepts[deg]
-30deg
0deg
15deg
30deg
60deg
15deg
PH2
Lead angle gradients[deg/Hz]
(Lead angle vs FG frequency)
0.15deg/Hz
0deg/Hz
0.15deg/Hz
0.3deg/Hz
FG freq 1/2
14%
Enable
4%
6%
14%
26%
34%
48%
Hys
6% 1%
4%
6%
6%
6%
6%
Disable
8% 3%
2%
8%
20%
28%
42%
MDS
Minimum input duty [%]
Figure 48. Pin-set PH1, PH2 and MDS
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28
14
8%
LV8811G, LV8813G, LV8814J
SETTING MINIMUM PWM DUTY CYCLE
When the input PWM duty cycle is less than the minimum
duty cycle, which is set by MDS pin voltage, the output
duty cycle becomes 0%. And, this threshold has
hysteresis. In the meantime, MDS pin is also used for the
FG frequency setting.
(Figure 49, Figure 50)
0~0.141
0.141~ 0.282
0.282~
0.752
0.752~
2.906
Minimum input duty cycle hysteresis [%]
6
1
4
6
Minimum input duty cycle for enable [%]
14
Minimum input duty cycle for disable [%]
8
VMDS range [V]
6
15.9𝑉𝑉𝑀𝑀𝑀𝑀𝑀𝑀 + 1.763
14
15.9𝑉𝑉𝑀𝑀𝑀𝑀𝑀𝑀 + 1.763 − ℎ𝑦𝑦𝑦𝑦
FG cycle
8
1 electrical
2 electrical
Output Duty
Default setting
100%
<EXAMPLE>
Disable 8%
Enable 14%
MDS
48%
VREG
MDS
VMDS
VMDS
47k
47k
14%
*FG cycle
8%
0%
= 2 electrical
VMDS[V]
0V
Ajustment
Range
141mV
(4%)
2.906V
(48%)
VREG(3.0V)
Figure 49. Example Setting Minimum PWM duty cycle (case of default setting)
Output Duty
100%
VREG
<EXAMPLE>
Disable 20%
Enable 26%
RMDS_A
47k
MDS
48%
VMDS
RMDS_B
47k
26%
VMDS =
VREG * (RMDS_ B / (RMDS_ A + RMDS_ B)) = 1/2 VREG
20%
0%
0V
141mV
(4%)
VMDS[V]
Ajustment
Range
2.906V
(48%)
VREG(3.0V)
Figure 50. Example Setting Minimum PWM duty cycle (case of 1/2 VREG setting)
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2.906 ~ 3.0
LV8811G, LV8813G, LV8814J
SETTING LEAD ANGLE
where 𝑓𝑓𝐹𝐹𝐹𝐹 is FG frequency [Hz]
when VPH1 and 𝑉𝑉𝑃𝑃𝑃𝑃2 = 0
𝐴𝐴 = 0.15[deg/Hz]
𝐵𝐵 = 15[deg]
Note: The equations above are based on the ideal case as a
reference for the user application design. It must be
readjusted by an experimental confirmation with the
actual movement and the motor to be used.
PH1 and PH2 pin determine the optimum lead angle for a
specific speed range. PH1 provides lead angle at the low
speed, The PH2 pin provides lead angle slant for speed
(FG frequency). Both pins become the initial value in
GND. (Figure 51, Figure 52, Figure 53)
The lead angle P (typ.) is determined by the following
equation.
𝑃𝑃 = 𝐴𝐴𝑓𝑓𝐹𝐹𝐹𝐹 + 𝐵𝐵
𝐴𝐴 = 0.1081𝑉𝑉𝑃𝑃𝑃𝑃2 − 0.015
𝐵𝐵 = 32.54𝑉𝑉𝑃𝑃𝑃𝑃1 − 34.58
Lead Angle[deg]
VPH1[V]
MAX
120deg
Lead Angle = A x fFG + B
A : Tuned from VPH2
B : Tuned from VPH1
<EXAMPLE (4-pole motor)>
Default setup
30Hz(450rpm) 20deg
100Hz(3000rpm) 30deg
200Hz(6000rpm) 45deg
VPH1 = MAX
VPH2 = MAX
Default
VPH1 = 0V
VPH2 = 0V
60deg
VPH1 = MAX
VPH2 = MIN
VREG
(100Hz, 30deg)
15deg
VPH1
MIN
-30deg
VPH2
47k
FG
Frequency[Hz]
VPH1 = MIN
VPH2 = MIN
0V
PH2
PH1
VPH1 = MIN
VPH2 = MAX
1/2
VREG
Default setup
47k
400Hz
20step
Figure 51. Example Setting Lead Angle (case of default setting)
Lead Angle[deg]
VPH1[V]
<EXAMPLE (4-pole motor)>
Adjustment setup
30Hz(450rpm)
0deg
100Hz(3000rpm) 22deg
200Hz(6000rpm) 47deg
VPH1 = MAX
VPH2 = MAX
120deg
VPH1 = 1V
VPH2 = 2.4V
60deg
VPH1 = MAX
VPH2 = MIN
VREG
(100Hz, 22deg)
0deg
-30deg
VREG
Fixed from
VPH2= 4/5 x VREG
VREG
RPH1_A
30k
PH1
VPH1
RPH2_A
11k
PH2
RPH1_B
15k
1/3
VREG
VPH1 = MIN
VPH2 = MIN
0V
20step
FG
Frequency[Hz]
400Hz
RPH2_B
43k
VPH1 = VREG * (RPH1_B / (RPH1_A + RPH1_B)) = 1/3 VREG
VPH2 = VREG * (RPH2_B / (RPH2_A + RPH2_B)) = 4/5 VREG
Figure 52. Example Setting Lead Angle (case of 1/3VREG and 4/5VREG setting)
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VPH2
LV8811G, LV8813G, LV8814J
Sinusoidal PWM signals are generated from 1-hall signal, handling the lead angle parameters.
IN1 +
IN1 IN1
L
hall
comparator
L
H
L
H
H
L
L
L
H
H
H
Lead angle
FG
Max
UO
0%
Max
VO
0%
Max
WO
0%
Figure 53. Timing chart example: Lead Angle
Efficiency and sinusoidal waveform can be optimized by
changing the voltage levels of PH1 and PH2. First, adjust
PH1 in low speed (low PWM duty cycle) such as 20%. In
the examples below, VPH1 = ~1.5V is the best case for
efficiency and the shape of sinusoidal wave. After
optimizing VPH1, adjust VPH2 adjusted in high speed
(high PWM duty cycle) such as 100%.
(Figure 54)
PWM
FG
U-Out
Current
of U-Out
Input PWM duty-cycle 20%, VPH1 = 0.3V
Input PWM duty-cycle 20%, VPH1 = 1.5V
PWM
FG
U-Out
Current
of U-Out
Input PWM duty-cycle 100%, VPH2 = 2.8V
Figure 54. Relations of the lead angle and rotational speed, waveform and efficiency (Case of the LV8811G)
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LV8811G, LV8813G, LV8814J
PCB GUIDELINES
VCC AND GROUND ROUTING
RF ROUTING
Make sure to short-circuit VCC line externally by a low
impedance route on one side of PCB. As high current
flows into PGND, connect it to GND through a low
impedance route.
The capacitance connected between the VCC pin and the
opposite ground is to stabilize the battery. Make sure to
connect an electrolytic capacitor with capacitance value
of about 10uF (4.7uF or greater) to eliminate low
frequency noise. Also, to eliminate high frequency noise,
connect a capacitor of superior frequency characteristics,
with capacitance value of about 0.1uF and make sure that
the capacitor is connected as close to the pin as possible.
Allow enough room in the design so the impact of PWM
drive and kick-back does not affect other components.
Especially, when the coil inductance is large and/or the
coil resistance is small, current ripple will rise so it is
necessary to use a high-capacity capacitor with superior
frequency characteristics. Please note that if the battery
voltage rises due to the impact of the coil kick-back as a
result of the use of diode for preventing the break down
caused by reverse connection, it is necessary to either
increase the capacitance value or place Zener diode
between the battery and the ground so that the voltage
does not exceed absolute maximum voltage.
When the electrolytic capacitor cannot be used, add the
resistor with the value of about 1Ω (R20) and a ceramic
capacitor with the capacitor value of about 10μF (C20) in
series for the alternative use. When the battery line is
extended, (20-30 cm to 2-3 m), the battery voltage may
overshoot when the power is supplied due to the impact of
the routing of the inductance. Make sure that the voltage
does not exceed the absolute maximum standard voltage
when the power supply turns on.
These capacitance values are just for reference, so the
confirmation with the actual application is essential to
determine the values appropriately.
Power current (output current) flows through the RF line.
Make sure to short-circuit the line from VCC through RF
as well as VCC. The RF resistance must choose the
enough power rating.
EXPOSED PAD
The exposed pad is connected to the frame of the
LV8811G, LV8813G, and LV8814J. Therefore, do not
connect it to anywhere else other than ground. If GND and
PGND are in the same plane, connect the exposed pad to
the ground plane. Else, if GND and PGND are separated,
connect the exposed pad to GND.
NC PIN UTILIZATION
NC pins are not connected internally inside the LV8811G,
LV8813G, and LV8814J. If the NC pin has to be
connected to another pin for the development of the PCB
board, make sure to assign the pin using wires of stable
voltage and current with lower impedance value.
MOTOR DRIVER OUTPUT PINS
Since the pins have to tolerate surge of current, make sure
that the wires are thick and short enough when designing
the PCB board.
THERMAL TEST CONDITIONS
Size: 57.0mm × 57.0mm × 1.6mm (Double layer PCB)
Material: Glass epoxy
Copper wiring density: L1 = 80% / L2 = 85%
RECOMMENDATION
The thermal data provided is for the thermal test condition
where 95% or more of the exposed die pad is soldered.
It is recommended to derate critical rating parameters for
a safe design. Electrical parameters that are recommended
to be derated are operating voltage, operating current,
junction temperature, and device power dissipation. The
recommended derating for a safe design is as shown
below:
Maximum 80% or less for operating voltage
Maximum 80% or less for operating current
Maximum 80% or less for junction temperature
Check solder joints and verify reliability of solder joints
for critical areas such as exposed die pad, power pins and
grounds.
Any void or deterioration, if observed, in solder joint of
these critical areas parts, may cause deterioration in
thermal conduction and that may lead to thermal
destruction of the device.
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LV8811G, LV8813G, LV8814J
L1 : Copper wiring pattern diagram (top)
L2 : Copper wiring pattern diagram (bottom)
Figure 55. Pattern Diagram of Top and Bottom Layer
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LV8811G, LV8813G, LV8814J
PACKAGE DIMENSIONS
Figure 56 LV8811G and LV8813G Package
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LV8811G, LV8813G, LV8814J
Figure 57 LV8814J Package
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LV8811G, LV8813G, LV8814J
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