Am29PDL128G Data Sheet July 2003 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both AMD and Fujitsu. Continuity of Specifications There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary. Continuity of Ordering Part Numbers AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM.” To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions. Publication Number 25685 Issue Date October 13, 2004 Publication Number 25685Revision RevisionBB Amendment Amendment ++4 +4 Issue Date October 13, 2004 THIS PAGE LEFT INTENTIONALLY BLANK. 2 October 13, 2004 Am29PDL128G 128 Megabit (8 M x 16-Bit/4 M x 32-Bit) CMOS 3.0 Volt-only, Simultaneous Read/ Write Flash Memory with VersatileIOTM Control DISTINCTIVE CHARACTERISTICS ARCHITECTURAL ADVANTAGES SOFTWARE FEATURES 128Mbit Page Mode device Software command-set compatible with JEDEC 42.4 — Word (16-bit) or double word (32-bit) mode selectable via WORD# input — Page size of 8 words/4 double words: Fast page read access from random locations within the page Single power supply operation — Full Voltage range: 2.7 to 3.6 volt read, erase, and program operations for battery-powered applications Simultaneous Read/Write Operation — Data can be continuously read from one bank while executing erase/program functions in another bank — Zero latency switching from write to read operations FlexBank Architecture — 4 separate banks, with up to two simultaneous operations per device — Organized as two 16 Mbit banks (Bank 1 & 4) and two 48 Mbit banks (Bank 2 & 3) VersatileI/OTM (VIO) Control — Output voltage generated and input voltages tolerated on the device is determined by the voltage on the VIO pin SecSi (Secured Silicon) Sector region — 128 words (64 double words) accessible through a command sequence Both top and bottom boot blocks in one device Manufactured on 0.17 µm process technology 20-year data retention at 125°C Minimum 1 million erase cycle guarantee per sector PERFORMANCE CHARACTERISTICS standard — Backward compatible with Am29F and Am29LV families CFI (Common Flash Interface) complaint — Provides device-specific information to the system, allowing host software to easily reconfigure for different Flash devices Erase Suspend / Erase Resume — Suspends an erase operation to allow read or program operations in other sectors of same bank Unlock Bypass Program command — Reduces overall programming time when issuing multiple program command sequences HARDWARE FEATURES Ready/Busy# pin (RY/BY#) — Provides a hardware method of detecting program or erase cycle completion Hardware reset pin (RESET#) — Hardware method to reset the device to reading array data WP# (Write Protect) input — At VIL, protects the two top and two bottom sectors, regardless of sector protect/unprotect status — At VIH, allows removal of sector protection — An internal pull up to Vcc is provided Persistent Sector Protection — A command sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector — Sectors can be locked and unlocked in-system at VCC level Password Sector Protection High Performance — Page access times as fast as 25 ns — Random access times as fast as 70 ns Power consumption (typical values at 10 MHz) — 38 mA active read current — 17 mA program/erase current — 1.5 µA typical standby mode current — A sophisticated sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector using a user-defined 64-bit password ACC (Acceleration) input provides faster programming times in a factory setting Package options — 80-ball Fortified BGA This Data Sheet states AMD’s current specifications regarding the Products described herein. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. Publication# 25685 Rev: B Amendment/+4 Issue Date: October 28, 2004 Refer to AMD’s Website (www.amd.com) for the latest information. P R E L I M I N A R Y GENERAL DESCRIPTION The Am29PDL128G is a 128 Mbit, 3.0 volt-only Page Mode and Simultaneous Read/Write Flash memory device organized as 8 Mwords or 4 M double words (One word is equal to two bytes). The device is offered in an 80-ball Fortified BGA package. The word-wide data (x16) appears on DQ15-DQ0; the double word mode data (x32) appears on DQ31-DQ0. This device can be programmed in-system or in standard EPROM programmers. A 12.0 V VPP is not required for write or erase operations. The device offers fast page access times of 25 and 30 ns, with corresponding random access times of 70 and 80 ns, respectively, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. Simultaneous Read/Write Operation with Zero Latency The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into 4 banks, which can be considered to be four separate memory arrays as far as certain operations are concerned. The device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from another bank with zero latency (with 2 simultaneous operations operating at any one time). This releases the system from waiting for the completion of a program or erase operation, greatly improving system performance. The device can be organized in both top and bottom sector configurations (see Table 1). Bank/Sector Sizes Bank 1 2 3 4 Number of Sectors 8 31 96 96 8 31 Sector Size (Word/Dbl. Word) 4/2 32/16 32/16 32/16 4/2 32/16 Bank Size 16 Mbit 48 Mbit 48 Mbit 16 Mbit Page Mode Features The device is AC timing, input/output, and package compatible with 8 Mbit x16 page mode mask ROM. The page size is 8 words or 4 double words. After initial page access is accomplished, the page mode operation provides fast read access speed of random locations within that page. October 28, 2004 Standard Flash Memory Features The device requires a single 3.0 volt power supply (2.7 V to 3.6 V) for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC 42.4 single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timing. Register contents serve as inputs to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase command sequence. The host system can detect whether a program or erase operation is complete by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. If a read is needed from the SecSi Sector area (One Time Program area) after an erase suspend, then the user must use the proper command sequence to enter and exit this region. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes. AMD’s Flash technology combined years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection. Am29PDL128G 3 P R E L I M I N A R Y TABLE OF CONTENTS Continuity of Specifications ...................................................... 1 Continuity of Ordering Part Numbers ....................................... 1 For More Information ................................................................ 1 Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 6 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Simultaneous Read/Write Block Diagram . . . . . . 7 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 8 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Ordering Information . . . . . . . . . . . . . . . . . . . . . . 10 Device Bus Operations . . . . . . . . . . . . . . . . . . . . 11 Table 1. Am29PDL128G Device Bus Operations ...........................11 Word/Double Word Configuration........................................... 11 Requirements for Reading Array Data ................................... 11 Random Read (Non-Page Read) ........................................... 11 Page Mode Read .................................................................... 12 Table 2. Page Select, Double Word Mode ......................................12 Table 3. Page Select, Word Mode ..................................................12 Table 11. System Interface String................................................... 32 Table 12. Device Geometry Definition................................. 33 Table 13. Primary Vendor-Specific Extended Query........... 34 Command Definitions. . . . . . . . . . . . . . . . . . . . . . 35 Reading Array Data ................................................................ 35 Reset Command ..................................................................... 35 Autoselect Command Sequence ............................................ 35 Enter SecSi Sector/Exit SecSi Sector Command Sequence .............................................................. 35 Double Word/Word Program Command Sequence ................ 36 Unlock Bypass Command Sequence ..................................... 36 Figure 4. Program Operation ......................................................... 37 Chip Erase Command Sequence ........................................... 37 Sector Erase Command Sequence ........................................ 37 Simultaneous Operation ......................................................... 12 Figure 5. Erase Operation.............................................................. 38 Table 4. Bank Select .......................................................................12 Erase Suspend/Erase Resume Commands ........................... 38 Password Program Command ................................................ 38 Password Verify Command .................................................... 39 Password Protection Mode Locking Bit Program Command .. 39 Persistent Sector Protection Mode Locking Bit Program Command ............................................................................... 39 SecSi Sector Protection Bit Program Command .................... 39 PPB Lock Bit Set Command ................................................... 39 DYB Write Command ............................................................. 40 Password Unlock Command .................................................. 40 PPB Program Command ........................................................ 40 All PPB Erase Command ........................................................ 40 DYB Write Command ............................................................. 40 PPB Lock Bit Set Command ................................................... 41 PPB Lock Bit Status Command .............................................. 41 Sector Protection Status Command ....................................... 41 Command Definitions Tables.................................................. 42 Writing Commands/Command Sequences ............................ 12 Accelerated Program Operation ............................................. 13 Autoselect Functions .............................................................. 13 Standby Mode ........................................................................ 13 Automatic Sleep Mode ........................................................... 13 RESET#: Hardware Reset Pin ............................................... 13 Output Disable Mode .............................................................. 13 Table 5. Sector Address Table ........................................................14 Table 6. SecSi™ Sector Addresses ................................................21 Autoselect Mode..................................................................... 21 Table 7. Autoselect Codes (High Voltage Method) ........................21 Table 8. Sector Block Addresses for Protection/Unprotection ........22 Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . 24 Persistent Sector Protection ................................................... 25 Persistent Protection Bit (PPB) ............................................... 25 Persistent Protection Bit Lock (PPB Lock) ............................. 25 Dynamic Protection Bit (DYB) ................................................ 25 Table 9. Sector Protection Schemes ...............................................26 Persistent Sector Protection Mode Locking Bit ...................... 26 Password Protection Mode ..................................................... 26 Password and Password Mode Locking Bit ........................... 26 64-bit Password ...................................................................... 27 Write Protect (WP#) ................................................................ 27 Persistent Protection Bit Lock ................................................. 27 High Voltage Sector Protection .............................................. 27 Figure 1. In-System Sector Protection/Sector Unprotection Algorithms 28 Temporary Sector Unprotect .................................................. 29 Figure 2. Temporary Sector Unprotect Operation........................... 29 SecSi™ (Secured Silicon) Sector Flash Memory Region ............................................................ 29 SecSi Sector Protection Bit .................................................... 30 Utilizing Password and SecSi Sector Concurrently ................ 30 Figure 3. SecSi Sector Protect Verify.............................................. 30 Hardware Data Protection ...................................................... 30 Low VCC Write Inhibit ............................................................ 31 Write Pulse “Glitch” Protection ............................................... 31 4 Logical Inhibit .......................................................................... 31 Power-Up Write Inhibit ............................................................ 31 Common Flash Memory Interface (CFI) . . . . . . . 31 Table 10. CFI Query Identification String ............................ 31 Table 14. Memory Array Command Definitions (x32 Mode) .......... 42 Table 15. Sector Protection Command Definitions (x32 Mode) ..... 43 Table 16. Memory Array Command Definitions (x16 Mode) .......... 44 Table 17. Sector Protection Command Definitions (x16 Mode) ..... 45 Write Operation Status . . . . . . . . . . . . . . . . . . . . . 46 DQ7: Data# Polling ................................................................. 46 Figure 6. Data# Polling Algorithm .................................................. 46 RY/BY#: Ready/Busy#............................................................ 47 DQ6: Toggle Bit I .................................................................... 47 Figure 7. Toggle Bit Algorithm........................................................ 47 DQ2: Toggle Bit II ................................................................... 48 Reading Toggle Bits DQ6/DQ2 ............................................... 48 DQ5: Exceeded Timing Limits ................................................ 48 DQ3: Sector Erase Timer ....................................................... 48 Table 18. Write Operation Status ................................................... 49 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 50 Figure 8. Maximum Negative Overshoot Waveform ...................... 50 Figure 9. Maximum Positive Overshoot Waveform........................ 50 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 51 Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 10. Test Setup.................................................................... 52 Am29PDL128G October 28, 2004 P R E L I M I N A R Y Figure 11. Input Waveforms and Measurement Levels .................. 52 Temporary Sector Unprotect .................................................. 62 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 53 Read-Only Operations ........................................................... 53 Figure 24. Temporary Sector Unprotect Timing Diagram .............. 62 Figure 25. Sector/Sector Block Protect and Unprotect Timing Diagram ............................................................. 63 Figure 12. Read Operation Timings ................................................ 53 Figure 13. Page Read Operation Timings....................................... 54 Hardware Reset (RESET#) .................................................... 55 Figure 14. Reset Timings ................................................................ 55 Word/Double Word Configuration (WORD#) .......................... 56 Figure 15. WORD# Timings for Read Operations........................... 56 Figure 16. WORD# Timings for Write Operations........................... 56 Erase and Program Operations .............................................. 57 Figure 17. Program Operation Timings........................................... 58 Figure 18. Accelerated Program Timing Diagram........................... 58 Figure 19. Chip/Sector Erase Operation Timings ........................... 59 Figure 20. Back-to-back Read/Write Cycle Timings ....................... 60 Figure 21. Data# Polling Timings (During Embedded Algorithms).. 60 Figure 22. Toggle Bit Timings (During Embedded Algorithms)....... 61 Figure 23. DQ2 vs. DQ6.................................................................. 61 October 28, 2004 Alternate CE# Controlled Erase and Program Operations ..... 64 Figure 26. Alternate CE# Controlled Write (Erase/Program) Operation Timings.......................................................................... 65 Erase And Programming Performance. . . . . . . . 66 Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 66 BGA Ball Capacitance . . . . . . . . . . . . . . . . . . . . . 66 Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 67 LAB080—80-Ball Fortified Ball Grid Array 15 x 10 mm package .............................................................. 67 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 68 Am29PDL128G 5 P R E L I M I N A R Y PRODUCT SELECTOR GUIDE Part Number Am29PDL128G Voltage Range: VCC = 3.0–3.6 V 70R Voltage Range: VCC = 2.7–3.6 V 70 80 90 Max Access Time, ns (tACC) 70 80 90 Max CE# Access, ns (tCE) 70 80 90 Max Page Access, ns (tPACC) 25 30 35 Max OE# Access, ns (tOE) 25 30 40 Speed Option Note: See “AC Characteristics” on page 53 for full specifications. BLOCK DIAGRAM DQ31–DQ0 RY/BY# (Note 2) VCC VSS Sector Switches VIO RESET# Input/Output Buffers Erase Voltage Generator WE# State Control Command Register PGM Voltage Generator Chip Enable Output Enable Logic CE# OE# STB Data Latch A3, A4 A21–A2 Timer Address Latch VCC Detector Y-Decoder STB X-Decoder Y-Gating Cell Matrix A1–A0 (A-1) Notes: 1. In double word mode, input/outputs are DQ31-DQ0, address range is A21-A0. In word mode, input/outputs are DQ15-DQ0, address range is A21-A-1. 2. 6 RY/BY# is an open drain output. Am29PDL128G October 28, 2004 P R E L I M I N A R Y SIMULTANEOUS READ/WRITE BLOCK DIAGRAM VCC VSS OE# DW/W# Mux Bank 1 Bank 2 X-Decoder A21–A0 CE# DW/W# WP# ACC STATE CONTROL & COMMAND REGISTER Status DQ31–DQ0 Control Mux DQ31–DQ0 RESET# WE# DQ0–DQ15 Bank 3 Address Bank 3 X-Decoder Bank 4 Address Y-gate A21–A0 X-Decoder A21–A0 DQ31–DQ0 Bank 2 Address DQ31–DQ0 RY/BY# DQ31–DQ0 A21–A0 X-Decoder Y-gate Bank 1 Address A21–A0 Bank 4 Mux October 28, 2004 Am29PDL128G 7 P R E L I M I N A R Y CONNECTION DIAGRAMS 80-Ball Fortified BGA Top View, Balls Facing Down A8 B8 C8 D8 E8 F8 G8 H8 J8 K8 OE# VSS DQ30 VIO DQ28 DQ11 VSS DQ9 VCC A18 A7 B7 C7 D7 E7 F7 G7 H7 J7 K7 WORD# CE# DQ15 VSS DQ13 DQ26 VIO DQ24 A19 A17 A6 B6 C6 D6 E6 F6 G6 H6 J6 K6 A21 A20 DQ12 DQ27 DQ25 DQ8 A16 A15 A5 B5 C5 D5 E5 F5 G5 H5 J5 K5 RFU WP# WE# DQ29 ACC RFU DQ10 A14 A13 RFU A4 B4 C4 D4 E4 F4 G4 H4 J4 K4 RY/BY# A0 A1 DQ18 RESET# RFU VSS A12 RFU RFU A3 B3 C3 D3 E3 F3 G3 H3 J3 K3 A2 A3 DQ16 VSS DQ4 DQ20 DQ22 VSS A10 A11 A2 B2 C2 D2 E2 F2 G2 H2 J2 K2 A4 VCC DQ1 VIO DQ3 DQ21 DQ6 DQ23 A7 A9 A1 B1 C1 D1 E1 F1 G1 H1 J1 K1 A5 DQ0 DQ17 DQ2 DQ19 DQ5 VIO DQ7 A6 A8 DQ31/A-1 DQ14 Special Handling Instructions for BGA Packages Special handling is required for Flash Memory products in molded packages (BGA). The package and/or data 8 integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. Am29PDL128G October 28, 2004 P R E L I M I N A R Y PIN DESCRIPTION A21–A0 = LOGIC SYMBOL 22 Addresses 22 DQ30–DQ0 = 31 Data Inputs/Outputs DQ31/A-1 = DQ31 (Data Input/Output, double word mode), A-1 (LSB Address Input, word mode) CE# = Chip Enable OE# = Output Enable WE# = Write Enable WP# = Hardware Write Protect Input ACC = Acceleration Input RESET# = Hardware Reset Pin, Active Low WORD# = Word Enable Input At VIL, selects 16-bit mode, At VIH, selects 32-bit mode A21–A0 32 or 16 DQ31–DQ0 (A-1) CE# OE# WE# WP# ACC RESET# WORD# VIO RY/BY# = Ready/Busy Output VCC = 3.0 Volt-only Single Power Supply (see Product Selector Guide for speed options and voltage supply tolerances) VIO = Output Buffer Power Supply VSS = Device Ground NC = Pin Not Connected Internally RFU = Reserved for Future Use October 28, 2004 RY/BY# Am29PDL128G 9 P R E L I M I N A R Y ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following: Am29PDL128G 70 PE I OPTIONAL PROCESSING Blank = Standard Processing N = 16-byte ESN devices (Contact an AMD representative for more information) TEMPERATURE RANGE I = Industrial (–40°C to +85°C) E = Extended (–55°C to +125°C) F = Industrial (–40°C to +85°C) for Pb-free Package K = Extended (-55C to +125C) for Pb-free Package PACKAGE TYPE PE = 80-Ball Fortified Ball Grid Array (fBGA) 1 mm pitch, 15 x 10 mm package (LAB080) SPEED OPTION See Product Selector Guide and Valid Combinations DEVICE NUMBER/DESCRIPTION Am29PDL128G 128 Megabit (8 M x 16-Bit/4 M x 32-Bit) CMOS Flash Memory 3.0 Volt-only Read, Program, and Erase Valid Combinations Valid Combinations for BGA Packages Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Order Number Am29PDL128G70R Am29PDL128G70 Am29PDL128G80 Am29PDL128G90 10 Am29PDL128G Package Marking PEF PEI PEI, PEE, PEF, PEK PD128G70R PD128G70V I,F PD128G80V PD128G90V I, E F, K October 28, 2004 P R E L I M I N A R Y DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The contents of the Table 1. register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels required, and the resulting output. The following subsections describe each of these operations in further detail. Am29PDL128G Device Bus Operations DQ31–DQ16 CE# OE# WE# RESET# WP# Addresses (Note 1) WORD# = VIH WORD# = VIL DQ15– DQ0 Read L L H H X AIN DOUT DOUT Write L H L H X AIN DIN DQ30–DQ16 = High-Z, DQ31 = A-1 VCC ± 0.3 V X X VCC ± 0.3 V X X High-Z High-Z High-Z Output Disable L H H H X X High-Z High-Z High-Z Reset X X X L X X High-Z High-Z High-Z Temporary Sector Unprotect (High Voltage) X X X VID X AIN DIN X DIN Operation Standby DIN Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out Notes: 1. Addresses are A21–A0 in double word mode (WORD# = VIH), A21–A-1 in word mode (WORD# = VIL). 2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See “Sector Protection” on page 24. Word/Double Word Configuration The WORD# pin controls whether the device data I/O pins operate in the word or double word configuration. If the WORD# pin is set at VIH, the device is in double word configuration, DQ31–DQ0 are active and controlled by CE# and OE#. If the WORD# pin is set at VIL , the device is in word configuration, and only data I/O pins DQ15–DQ0 are active and controlled by CE# and OE#. The data I/O pins DQ30–DQ16 are tri-stated, and the DQ31 pin is used as an input for the least significant address bit (LSB) function, which is named A-1. Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at V IH . The WORD# pin determines whether the device outputs array data in words or double words. October 28, 2004 The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. Each bank remains enabled for read access until the command register contents are altered. Refer to the AC Read-Only Operations table on page 53 for timing specifications and to Table 12 for the timing diagram. ICC1 in the DC Characteristics table represents the active current specification for reading array data. Random Read (Non-Page Read) Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (t CE ) is the delay from the stable addresses and stable CE# to valid data at the output inputs. The output enable access time is the delay from the falling edge of the OE# to valid data at the output Am29PDL128G 11 P R E L I M I N A R Y inputs (assuming the addresses have been stable for at least tACC–tOE time). Page Mode Read The device is capable of fast page mode read and is compatible with the page mode Mask ROM read operation. This mode provides faster read access speed for random locations within a page. The page size of the device is 8 words, or 4 double words, with the appropriate page being selected by the higher address bits A21–A2 and the LSB bits A1–A0 (in the double word mode) and A1 to A-1 (in the word mode) determining the specific word/double word within that page. This is an asynchronous operation with the microprocessor supplying the specific word or double word location. The random or initial page access is equal to tACC or tCE and subsequent page read accesses (as long as the locations specified by the microprocessor falls within that page) is equivalent to tPACC. When CE# is deasserted and reasserted for a subsequent access, the access time is tACC or tCE. Here again, CE# selects the device and OE# is the output control and should be used to gate data to the output inputs if the device is selected. Fast page mode accesses are obtained by keeping A21–A2 constant and changing A1 to A0 to select the specific double word, or changing A1 to A-1 to select the specific word, within that page. Table 2. Page Select, Double Word Mode Word A1 A0 Double Word 0 0 0 Double Word 1 0 1 Double Word 2 1 0 Double Word 3 1 1 Table 3. 12 Simultaneous Operation The device is capable of reading data from one bank of memory while a program or erase operation is in progress in another bank of memory (simultaneous operation), in addition to the conventional features (read, program, erase-suspend read, and erase-suspend program). The bank selected can be selected by bank addresses (A21–A19) with zero latency. The simultaneous operation can execute multi-function mode in the same bank. Table 4. Bank Select Bank A21–A19 Bank 1 000 Bank 2 001, 010, 011 Bank 3 100, 101, 110 Bank 4 111 Writing Commands/Command Sequences To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH. For program operations, the WORD# pin determines whether the device accepts program data in double words or words. Refer to “Word/Double Word Configuration” for more information. The device features an Unlock Bypass mode to facilitate faster programming. Once a bank enters the Unlock Bypass mode, only two write cycles are required to program a double word or word, instead of four. See “Double Word/Word Program Command Sequence” on page 36 for details on programming data to the device using both standard and Unlock Bypass command sequences. Page Select, Word Mode Word A1 A0 A-1 Word 0 0 0 0 Word 1 0 0 1 Word 2 0 1 0 Word 3 0 1 1 Word 4 1 0 0 Word 5 1 0 1 Word 6 1 1 0 Word 7 1 1 1 An erase operation can erase one sector, multiple sectors, or the entire device. Table 5 indicates the address space that each sector occupies. A “bank address” is the address bits required to uniquely select a bank. Similarly, a “sector address” refers to the address bits required to uniquely select a sector. The “Command Definitions” section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. ICC2 in the DC Characteristics table represents the active current specification for the write mode. See “AC Characteristics” on page 53 for timing specification tables and timing diagrams for write operations. Am29PDL128G October 28, 2004 P R E L I M I N A R Y Accelerated Program Operation The device offers accelerated program operations through the ACC function. This function is primarily intended to allow faster manufacturing throughput at the factory. If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the ACC pin returns the device to normal operation. Note that VHH must not be asserted on ACC for operations other than accelerated programming, or device damage may result. Autoselect Functions If the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ15–DQ0. Standard read cycle timings apply in this mode. See “Autoselect Mode” on page 21 and “Autoselect Command Sequence” on page 35 for more information. Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VCC ± 0.3 V. (Note: This is a more restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within VCC ± 0.3 V, the device is in the standby mode, but the standby current is greater. The device requires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. ICC3 in the DC Characteristics table represents the CMOS standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables October 28, 2004 this mode when addresses remain stable for t ACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. Note that during automatic sleep mode, OE# must be at VIH before the device reduces current to the stated sleep mode specification. ICC5 in the DC Characteristics table represents the automatic sleep mode current specification. RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS±0.3 V, the standby current is greater. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET# pin returns to VIH. Refer to tables in AC Characteristics for RESET# parameters and to Figure 13 for the timing diagram. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The output pins (except for RY/BY#) are placed in the high impedance state. Am29PDL128G 13 P R E L I M I N A R Y Table 5. Bank 1 Bank 14 Sector Address Table (Sheet 1 of 7) Sector Sector Address (A21-A11) Sector Size (Kwords/ Kdoublewords) Address Range (x16) Address Range (x32) SA0 00000000000 4/2 00000h–00FFFh 000000h–0007FFh SA1 00000000001 4/2 01000h–01FFFh 000800h–000FFFh SA2 00000000010 4/2 02000h–02FFFh 001000h–0017FFh SA3 00000000011 4/2 03000h–03FFFh 001800h–001FFFh SA4 00000000100 4/2 04000h–04FFFh 002000h–0027FFh SA5 00000000101 4/2 05000h–05FFFh 002800h–002FFFh SA6 00000000110 4/2 06000h–06FFFh 003000h–0037FFh SA7 00000000111 4/2 07000h–07FFFh 003800h–003FFFh SA8 00000001XXX 32/16 08000h–0FFFFh 004000h–007FFFh SA9 00000010XXX 32/16 10000h–17FFFh 008000h–00BFFFh SA10 00000011XXX 32/16 18000h–1FFFFh 00C000h–00FFFFh SA11 00000100XXX 32/16 20000h–27FFFh 010000h–013FFFh SA12 00000101XXX 32/16 28000h–2FFFFh 014000h–017FFFh SA13 00000110XXX 32/16 30000h–37FFFh 018000h–01BFFFh SA14 00000111XXX 32/16 38000h–3FFFFh 01C000h–01FFFFh SA15 00001000XXX 32/16 40000h–47FFFh 020000h–023FFFh SA16 00001001XXX 32/16 48000h–4FFFFh 024000h–027FFFh SA17 00001010XXX 32/16 50000h–57FFFh 028000h–02BFFFh SA18 00001011XXX 32/16 58000h–5FFFFh 02C000h–02FFFFh SA19 00001100XXX 32/16 60000h–67FFFh 030000h–033FFFh SA20 00001101XXX 32/16 68000h–6FFFFh 034000h–037FFFh SA21 00001110XXX 32/16 70000h–77FFFh 038000h–03BFFFh SA22 00001111XXX 32/16 78000h–7FFFFh 03C000h–03FFFFh SA23 00010000XXX 32/16 80000h–87FFFh 040000h–043FFFh SA24 00010001XXX 32/16 88000h–8FFFFh 044000h–047FFFh SA25 00010010XXX 32/16 90000h–97FFFh 048000h–04BFFFh SA26 00010011XXX 32/16 98000h–9FFFFh 04C000h–04FFFFh SA27 00010100XXX 32/16 A0000h–A7FFFh 050000h–053FFFh SA28 00010101XXX 32/16 A8000h–AFFFFh 054000h–057FFFh SA29 00010110XXX 32/16 B0000h–B7FFFh 058000h–05BFFFh SA30 00010111XXX 32/16 B8000h–BFFFFh 05C000h–05FFFFh SA31 00011000XXX 32/16 C0000h–C7FFFh 060000h–063FFFh SA32 00011001XXX 32/16 C8000h–CFFFFh 064000h–067FFFh SA33 00011010XXX 32/16 D0000h–D7FFFh 068000h–06BFFFh SA34 00011011XXX 32/16 D8000h–DFFFFh 06C000h–06FFFFh SA35 00011100XXX 32/16 E0000h–E7FFFh 070000h–073FFFh SA36 00011101XXX 32/16 E8000h–EFFFFh 074000h–077FFFh SA37 00011110XXX 32/16 F0000h–F7FFFh 078000h–07BFFFh SA38 00011111XXX 32/16 F8000h–FFFFFh 07C000–07FFFFh Am29PDL128G October 28, 2004 P R E L I M I N A R Y Table 5. Bank 2 Bank Sector Address Table (Sheet 2 of 7) Sector Sector Address (A21-A11) Sector Size (Kwords/ Kdoublewords) Address Range (x16) Address Range (x32) SA39 00100000XXX 32/16 100000h–107FFFh 080000h–083FFFh SA40 00100001XXX 32/16 108000h–10FFFFh 084000h–087FFFh SA41 00100010XXX 32/16 110000h–117FFFh 088000h–08BFFFh SA42 00100011XXX 32/16 118000h–11FFFFh 08C000h–08FFFFh SA43 00100100XXX 32/16 120000h–127FFFh 090000h–093FFFh SA44 00100101XXX 32/16 128000h–12FFFFh 094000h–097FFFh SA45 00100110XXX 32/16 130000h–137FFFh 098000h–09BFFFh SA46 00100111XXX 32/16 138000h–13FFFFh 09C000h–09FFFFh SA47 00101000XXX 32/16 140000h–147FFFh 0A0000h–0A3FFFh SA48 00101001XXX 32/16 148000h–14FFFFh 0A4000h–0A7FFFh SA49 00101010XXX 32/16 150000h–157FFFh 0A8000h–0ABFFFh SA50 00101011XXX 32/16 158000h–15FFFFh 0AC000h–0AFFFFh SA51 00101100XXX 32/16 160000h–167FFFh 0B0000h–0B3FFFh SA52 00101101XXX 32/16 168000h–16FFFFh 0B4000h–0B7FFFh SA53 00101110XXX 32/16 170000h–177FFFh 0B8000h–0BBFFFh SA54 00101111XXX 32/16 178000h–17FFFFh 0BC000h–0BFFFFh SA55 00110000XXX 32/16 180000h–187FFFh 0C0000h–0C3FFFh SA56 00110001XXX 32/16 188000h–18FFFFh 0C4000h–0C7FFFh SA57 00110010XXX 32/16 190000h–197FFFh 0C8000h–0CBFFFh SA58 00110011XXX 32/16 198000h–19FFFFh 0CC000h–0CFFFFh SA59 00110100XXX 32/16 1A0000h–1A7FFFh 0D0000h–0D3FFFh SA60 00110101XXX 32/16 1A8000h–1AFFFFh 0D4000h–0D7FFFh SA61 00110110XXX 32/16 1B0000h–1B7FFFh 0D8000h–0DBFFFh SA62 00110111XXX 32/16 1B8000h–1BFFFFh 0DC000h–0DFFFFh SA63 00111000XXX 32/16 1C0000h–1C7FFFh 0E0000h–0E3FFFh SA64 00111001XXX 32/16 1C8000h–1CFFFFh 0E4000h–0E7FFFh SA65 00111010XXX 32/16 1D0000h–1D7FFFh 0E8000h–0EBFFFh SA66 00111011XXX 32/16 1D8000h–1DFFFFh 0EC000h–0EFFFFh SA67 00111100XXX 32/16 1E0000h–1E7FFFh 0F0000h–0F3FFFh SA68 00111101XXX 32/16 1E8000h–1EFFFFh 0F4000h–0F7FFFh SA69 00111110XXX 32/16 1F0000h–1F7FFFh 0F8000h–0FBFFFh SA70 00111111XXX 32/16 1F8000h–1FFFFFh 0FC000h–0FFFFFh SA71 01000000XXX 32/16 200000h–207FFFh 100000h–103FFFh SA72 01000001XXX 32/16 208000h–20FFFFh 104000h–107FFFh SA73 01000010XXX 32/16 210000h–217FFFh 108000h–10BFFFh SA74 01000011XXX 32/16 218000h–21FFFFh 10C000h–10FFFFh SA75 01000100XXX 32/16 220000h–227FFFh 110000h–113FFFh SA76 01000101XXX 32/16 228000h–22FFFFh 114000h–117FFFh SA77 01000110XXX 32/16 230000h–237FFFh 118000h–11BFFFh SA78 01000111XXX 32/16 238000h–23FFFFh 11C000h–11FFFFh SA79 01001000XXX 32/16 240000h–247FFFh 120000h–123FFFh SA80 01001001XXX 32/16 248000h–24FFFFh 124000h–127FFFh October 28, 2004 Am29PDL128G 15 P R E L I M I N A R Y Table 5. Bank 2 (continued) Bank 16 Sector Address Table (Sheet 3 of 7) Sector Sector Address (A21-A11) Sector Size (Kwords/ Kdoublewords) Address Range (x16) Address Range (x32) SA81 01001010XXX 32/16 250000h–257FFFh 128000h–12BFFFh SA82 01001011XXX 32/16 258000h–25FFFFh 12C000h–12FFFFh SA83 01001100XXX 32/16 260000h–267FFFh 130000h–133FFFh SA84 01001101XXX 32/16 268000h–26FFFFh 134000h–137FFFh SA85 01001110XXX 32/16 270000h–277FFFh 138000h–13BFFFh SA86 01001111XXX 32/16 278000h–27FFFFh 13C000h–13FFFFh SA87 01010000XXX 32/16 280000h–287FFFh 140000h–143FFFh SA88 01010001XXX 32/16 288000h–28FFFFh 144000h–147FFFh SA89 01010010XXX 32/16 290000h–297FFFh 148000h–14BFFFh SA90 01010011XXX 32/16 298000h–29FFFFh 14C000h–14FFFFh SA91 01010100XXX 32/16 2A0000h–2A7FFFh 150000h–153FFFh SA92 01010101XXX 32/16 2A8000h–2AFFFFh 154000h–157FFFh SA93 01010110XXX 32/16 2B0000h–2B7FFFh 158000h–15BFFFh SA94 01010111XXX 32/16 2B8000h–2BFFFFh 15C000h–15FFFFh SA95 01011000XXX 32/16 2C0000h–2C7FFFh 160000h–163FFFh SA96 01011001XXX 32/16 2C8000h–2CFFFFh 164000h–167FFFh SA97 01011010XXX 32/16 2D0000h–2D7FFFh 168000h–16BFFFh SA98 01011011XXX 32/16 2D8000h–2DFFFFh 16C000h–16FFFFh SA99 01011100XXX 32/16 2E0000h–2E7FFFh 170000h–173FFFh SA100 01011101XXX 32/16 2E8000h–2EFFFFh 174000h–177FFFh SA101 01011110XXX 32/16 2F0000h–2F7FFFh 178000h–17BFFFh SA102 01011111XXX 32/16 2F8000h–2FFFFFh 17C000h–17FFFFh SA103 01100000XXX 32/16 300000h–307FFFh 180000h–183FFFh SA104 01100001XXX 32/16 308000h–30FFFFh 184000h–187FFFh SA105 01100010XXX 32/16 310000h–317FFFh 188000h–18BFFFh SA106 01100011XXX 32/16 318000h–31FFFFh 18C000h–18FFFFh SA107 01100100XXX 32/16 320000h–327FFFh 190000h–193FFFh SA108 01100101XXX 32/16 328000h–32FFFFh 194000h–197FFFh SA109 01100110XXX 32/16 330000h–337FFFh 198000h–19BFFFh SA110 01100111XXX 32/16 338000h–33FFFFh 19C000h–19FFFFh SA111 01101000XXX 32/16 340000h–347FFFh 1A0000h–1A3FFFh SA112 01101001XXX 32/16 348000h–34FFFFh 1A4000h–1A7FFFh SA113 01101010XXX 32/16 350000h–357FFFh 1A8000h–1ABFFFh SA114 01101011XXX 32/16 358000h–35FFFFh 1AC000h–1AFFFFh SA115 01101100XXX 32/16 360000h–367FFFh 1B0000h–1B3FFFh SA116 01101101XXX 32/16 368000h–36FFFFh 1B4000h–1B7FFFh SA117 01101110XXX 32/16 370000h–377FFFh 1B8000h–1BBFFFh SA118 01101111XXX 32/16 378000h–37FFFFh 1BC000h–1BFFFFh SA119 01110000XXX 32/16 380000h–387FFFh 1C0000h–1C3FFFh Am29PDL128G October 28, 2004 P R E L I M I N A R Y Table 5. Bank 3 Bank 2 (continued) Bank Sector Address Table (Sheet 4 of 7) Sector Sector Address (A21-A11) Sector Size (Kwords/ Kdoublewords) Address Range (x16) Address Range (x32) SA120 01110001XXX 32/16 388000h–38FFFFh 1C4000h–1C7FFFh SA121 01110010XXX 32/16 390000h–397FFFh 1C8000h–1CBFFFh SA122 01110011XXX 32/16 398000h–39FFFFh 1CC000h–1CFFFFh SA123 01110100XXX 32/16 3A0000h–3A7FFFh 1D0000h–1D3FFFh SA124 01110101XXX 32/16 3A8000h–3AFFFFh 1D4000h–1D7FFFh SA125 01110110XXX 32/16 3B0000h–3B7FFFh 1D8000h–1DBFFFh SA126 01110111XXX 32/16 3B8000h–3BFFFFh 1DC000h–1DFFFFh SA127 01111000XXX 32/16 3C0000h–3C7FFFh 1E0000h–1E3FFFh SA128 01111001XXX 32/16 3C8000h–3CFFFFh 1E4000h–1E7FFFh SA129 01111010XXX 32/16 3D0000h–3D7FFFh 1E8000h–1EBFFFh SA130 01111011XXX 32/16 3D8000h–3DFFFFh 1EC000h–1EFFFFh SA131 01111100XXX 32/16 3E0000h–3E7FFFh 1F0000h–1F3FFFh SA132 01111101XXX 32/16 3E8000h–3EFFFFh 1F4000h–1F7FFFh SA133 01111110XXX 32/16 3F0000h–3F7FFFh 1F8000h–1FBFFFh SA134 01111111XXX 32/16 3F8000h–3FFFFFh 1FC000h–1FFFFFh SA135 10000000XXX 32/16 400000h–407FFFh 200000h–203FFFh SA136 10000001XXX 32/16 408000h–40FFFFh 204000h–207FFFh SA137 10000010XXX 32/16 410000h–417FFFh 208000h–20BFFFh SA138 10000011XXX 32/16 418000h–41FFFFh 20C000h–20FFFFh SA139 10000100XXX 32/16 420000h–427FFFh 210000h–213FFFh SA140 10000101XXX 32/16 428000h–42FFFFh 214000h–217FFFh SA141 10000110XXX 32/16 430000h–437FFFh 218000h–21BFFFh SA142 10000111XXX 32/16 438000h–43FFFFh 21C000h–21FFFFh SA143 10001000XXX 32/16 440000h–447FFFh 220000h–223FFFh SA144 10001001XXX 32/16 448000h–44FFFFh 224000h–227FFFh SA145 10001010XXX 32/16 450000h–457FFFh 228000h–22BFFFh SA146 10001011XXX 32/16 458000h–45FFFFh 22C000h–22FFFFh SA147 10001100XXX 32/16 460000h–467FFFh 230000h–233FFFh SA148 10001101XXX 32/16 468000h–46FFFFh 234000h–237FFFh SA149 10001110XXX 32/16 470000h–477FFFh 238000h–23BFFFh SA150 10001111XXX 32/16 478000h–47FFFFh 23C000h–23FFFFh SA151 10010000XXX 32/16 480000h–487FFFh 240000h–243FFFh SA152 10010001XXX 32/16 488000h–48FFFFh 244000h–247FFFh SA153 10010010XXX 32/16 490000h–497FFFh 248000h–24BFFFh SA154 10010011XXX 32/16 498000h–49FFFFh 24C000h–24FFFFh SA155 10010100XXX 32/16 4A0000h–4A7FFFh 250000h–253FFFh SA156 10010101XXX 32/16 4A8000h–4AFFFFh 254000h–257FFFh SA157 10010110XXX 32/16 4B0000h–4B7FFFh 258000h–25BFFFh SA158 10010111XXX 32/16 A48000h–4BFFFFh 25C000h–25FFFFh October 28, 2004 Am29PDL128G 17 P R E L I M I N A R Y Table 5. Bank 3 (continued) Bank 18 Sector Address Table (Sheet 5 of 7) Sector Sector Address (A21-A11) Sector Size (Kwords/ Kdoublewords) Address Range (x16) Address Range (x32) SA159 10011000XXX 32/16 4C0000h–4C7FFFh 260000h–263FFFh SA160 10011001XXX 32/16 4C8000h–4CFFFFh 264000h–267FFFh SA161 10011010XXX 32/16 4D0000h–4D7FFFh 268000h–26BFFFh SA162 10011011XXX 32/16 4D8000h–4DFFFFh 26C000h–26FFFFh SA163 10011100XXX 32/16 4E0000h–4E7FFFh 270000h–273FFFh SA164 10011101XXX 32/16 4E8000h–4EFFFFh 274000h–277FFFh SA165 10011110XXX 32/16 4F0000h–4F7FFFh 278000h–27BFFFh SA166 10011111XXX 32/16 4F8000h–4FFFFFh 27C000h–27FFFFh SA167 10100000XXX 32/16 500000h–507FFFh 280000h–283FFFh SA168 10100001XXX 32/16 508000h–50FFFFh 284000h–287FFFh SA169 10100010XXX 32/16 510000h–517FFFh 288000h–28BFFFh SA170 10100011XXX 32/16 518000h–51FFFFh 28C000h–28FFFFh SA171 10100100XXX 32/16 520000h–527FFFh 290000h–293FFFh SA172 10100101XXX 32/16 528000h–52FFFFh 294000h–297FFFh SA173 10100110XXX 32/16 530000h–537FFFh 298000h–29BFFFh SA174 10100111XXX 32/16 538000h–53FFFFh 29C000h–29FFFFh SA175 10101000XXX 32/16 540000h–547FFFh 2A0000h–2A3FFFh SA176 10101001XXX 32/16 548000h–54FFFFh 2A4000h–2A7FFFh SA177 10101010XXX 32/16 550000h–557FFFh 2A8000h–2ABFFFh SA178 10101011XXX 32/16 558000h–55FFFFh 2AC000h–2AFFFFh SA179 10101100XXX 32/16 560000h–567FFFh 2B0000h–2B3FFFh SA180 10101101XXX 32/16 568000h–56FFFFh 2B4000h–2B7FFFh SA181 10101110XXX 32/16 570000h–577FFFh 2B8000h–2BBFFFh SA182 10101111XXX 32/16 578000h–57FFFFh 2BC000h–2BFFFFh SA183 10110000XXX 32/16 580000h–587FFFh 2C0000h–2C3FFFh SA184 10110001XXX 32/16 588000h–58FFFFh 2C4000h–2C7FFFh SA185 10110010XXX 32/16 590000h–597FFFh 2C8000h–2CBFFFh SA186 10110011XXX 32/16 598000h–59FFFFh 2CC000h–2CFFFFh SA187 10110100XXX 32/16 5A0000h–5A7FFFh 2D0000h–2D3FFFh SA188 10110101XXX 32/16 5A8000h–5AFFFFh 2D4000h–2D7FFFh SA189 10110110XXX 32/16 5B0000h–5B7FFFh 2D8000h–2DBFFFh SA190 10110111XXX 32/16 5B8000h–5BFFFFh 2DC000h–2DFFFFh SA191 10111000XXX 32/16 5C0000h–5C7FFFh 2E0000h–2E3FFFh SA192 10111001XXX 32/16 5C8000h–5CFFFFh 2E4000h–2E7FFFh SA193 10111010XXX 32/16 5D0000h–5D7FFFh 2E8000h–2EBFFFh SA194 10111011XXX 32/16 5D8000h–5DFFFFh 2EC000h–2EFFFFh SA195 10111100XXX 32/16 5E0000h–5E7FFFh 2F0000h–2F3FFFh SA196 10111101XXX 32/16 5E8000h–5EFFFFh 2F4000h–2F7FFFh SA197 10111110XXX 32/16 5F0000h–5F7FFFh 2F8000h–2FBFFFh Am29PDL128G October 28, 2004 P R E L I M I N A R Y Table 5. Bank 3 (continued) Bank Sector Address Table (Sheet 6 of 7) Sector Sector Address (A21-A11) Sector Size (Kwords/ Kdoublewords) Address Range (x16) Address Range (x32) SA198 10111111XXX 32/16 5F8000h–5FFFFFh 2FC000h–2FFFFFh SA199 11000000XXX 32/16 600000h–607FFFh 300000h–303FFFh SA200 11000001XXX 32/16 608000h–60FFFFh 304000h–307FFFh SA201 11000010XXX 32/16 610000h–617FFFh 308000h–30BFFFh SA202 11000011XXX 32/16 618000h–61FFFFh 30C000h–30FFFFh SA203 11000100XXX 32/16 620000h–627FFFh 310000h–313FFFh SA204 11000101XXX 32/16 628000h–62FFFFh 314000h–317FFFh SA205 11000110XXX 32/16 630000h–637FFFh 318000h–31BFFFh SA206 11000111XXX 32/16 638000h–63FFFFh 31C000h–31FFFFh SA207 11001000XXX 32/16 640000h–647FFFh 320000h–323FFFh SA208 11001001XXX 32/16 648000h–64FFFFh 324000h–327FFFh SA209 11001010XXX 32/16 650000h–657FFFh 328000h–32BFFFh SA210 11001011XXX 32/16 658000h–65FFFFh 32C000h–32FFFFh SA211 11001100XXX 32/16 660000h–667FFFh 330000h–333FFFh SA212 11001101XXX 32/16 668000h–66FFFFh 334000h–337FFFh SA213 11001110XXX 32/16 670000h–677FFFh 338000h–33BFFFh SA214 11001111XXX 32/16 678000h–67FFFFh 33C000h–33FFFFh SA215 11010000XXX 32/16 680000h–687FFFh 340000h–343FFFh SA216 11010001XXX 32/16 688000h–68FFFFh 344000h–347FFFh SA217 11010010XXX 32/16 690000h–697FFFh 348000h–34BFFFh SA218 11010011XXX 32/16 698000h–69FFFFh 34C000h–34FFFFh SA219 11010100XXX 32/16 6A0000h–6A7FFFh 350000h–353FFFh SA220 11010101XXX 32/16 6A8000h–6AFFFFh 354000h–357FFFh SA221 11010110XXX 32/16 6B0000h–6B7FFFh 358000h–35BFFFh SA222 11010111XXX 32/16 6B8000h–6BFFFFh 35C000h–35FFFFh SA223 11011000XXX 32/16 6C0000h–6C7FFFh 360000h–363FFFh SA224 11011001XXX 32/16 6C8000h–6CFFFFh 364000h–367FFFh SA225 11011010XXX 32/16 6D0000h–6D7FFFh 368000h–36BFFFh SA226 11011011XXX 32/16 6D8000h–6DFFFFh 36C000h–36FFFFh SA227 11011100XXX 32/16 6E0000h–6E7FFFh 370000h–373FFFh SA228 11011101XXX 32/16 6E8000h–6EFFFFh 374000h–377FFFh SA229 11011110XXX 32/16 6F0000h–6F7FFFh 378000h–37BFFFh SA230 11011111XXX 32/16 6F8000h–6FFFFFh 37C000h–37FFFFh October 28, 2004 Am29PDL128G 19 P R E L I M I N A R Y Table 5. Bank 4 Bank Sector Address Table (Sheet 7 of 7) Sector Sector Address (A21-A11) Sector Size (Kwords/ Kdoublewords) Address Range (x16) Address Range (x32) SA231 11100000XXX 32/16 700000h–707FFFh 380000h–383FFFh SA232 11100001XXX 32/16 708000h–70FFFFh 384000h–387FFFh SA233 11100010XXX 32/16 710000h–717FFFh 388000h–38BFFFh SA234 11100011XXX 32/16 718000h–71FFFFh 38C000h–38FFFFh SA235 11100100XXX 32/16 720000h–727FFFh 390000h–393FFFh SA236 11100101XXX 32/16 728000h–72FFFFh 394000h–397FFFh SA237 11100110XXX 32/16 730000h–737FFFh 398000h–39BFFFh SA238 11100111XXX 32/16 738000h–73FFFFh 39C000h–39FFFFh SA239 11101000XXX 32/16 740000h–747FFFh 3A0000h–3A3FFFh SA240 11101001XXX 32/16 748000h–74FFFFh 3A4000h–3A7FFFh SA241 11101010XXX 32/16 750000h–757FFFh 3A8000h–3ABFFFh SA242 11101011XXX 32/16 758000h–75FFFFh 3AC000h–3AFFFFh SA243 11101100XXX 32/16 760000h–767FFFh 3B0000h–3B3FFFh SA244 11101101XXX 32/16 768000h–76FFFFh 3B4000h–3B7FFFh SA245 11101110XXX 32/16 770000h–777FFFh 3B8000h–3BBFFFh SA246 11101111XXX 32/16 778000h–77FFFFh 3BC000h–3BFFFFh SA247 11110000XXX 32/16 780000h–787FFFh 3C0000h–3C3FFFh SA248 11110001XXX 32/16 788000h–78FFFFh 3C4000h–3C7FFFh SA249 11110010XXX 32/16 790000h–797FFFh 3C8000h–3CBFFFh SA250 11110011XXX 32/16 798000h–79FFFFh 3CC000h–3CFFFFh SA251 11110100XXX 32/16 7A0000h–7A7FFFh 3D0000h–3D3FFFh SA252 11110101XXX 32/16 7A8000h–7AFFFFh 3D4000h–3D7FFFh SA253 11110110XXX 32/16 7B0000h–7B7FFFh 3D8000h–3DBFFFh SA254 11110111XXX 32/16 7B8000h–7BFFFFh 3DC000h–3DFFFFh SA255 11111000XXX 32/16 7C0000h–7C7FFFh 3E0000h–3E3FFFh SA256 11111001XXX 32/16 7C8000h–7CFFFFh 3E4000h–3E7FFFh SA257 11111010XXX 32/16 7D0000h–7D7FFFh 3E8000h–3EBFFFh SA258 11111011XXX 32/16 7D8000h–7DFFFFh 3EC000h–3EFFFFh SA259 11111100XXX 32/16 7E0000h–7E7FFFh 3F0000h–3F3FFFh SA260 11111101XXX 32/16 7E8000h–7EFFFFh 3F4000h–3F7FFFh SA261 11111110XXX 32/16 7F0000h–7F7FFFh 3F8000h–3FBFFFh SA262 11111111000 4/2 7F8000h–7F8FFFh 3FC000h–3FC7FFh SA263 11111111001 4/2 7F9000h–7F9FFFh 3FC800h–3FCFFFh SA264 11111111010 4/2 7FA000h–7FAFFFh 3FD000h–3FD7FFh SA265 11111111011 4/2 7FB000h–7FBFFFh 3FD800h–3FDFFFh SA266 11111111100 4/2 7FC000h–7FCFFFh 3FE000h–3FE7FFh SA267 11111111101 4/2 7FD000h–7FDFFFh 3FE800h–3FEFFFh SA268 11111111110 4/2 7FE000h–7FEFFFh 3FF000h–3FF7FFh SA269 11111111111 4/2 7FF000h–7FFFFFh 3FF800h–3FFFFFh Note: The address range is A21:A-1 in word mode (WORD#=VIL) or A21:A0 in double word mode (WORD#=VIH). Address bits A21:A11 uniquely select a sector; address bits A21:A19 uniquely select a bank. 20 Am29PDL128G October 28, 2004 P R E L I M I N A R Y Table 6. SecSi™ Sector Addresses Device Sector Size Am29PDL128G 128 words/64 double words Autoselect Mode When using programming equipment, the autoselect mode requires VID on address pin A9. Address pins must be as shown in Table 7. In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see Table 5). Table 7 shows the remaining address bits that are don’t care. When all necessary bits have been set as required, the programming equipment may then Description CE# OE# WE# Device ID Manufacturer ID: AMD L L H L H A21 to A11 A10 A9 A8 A7 X X VID X X X X VID X L Read Cycle 3 Sector Protection Verification SecSi Indicator Bit (DQ7) A6 A5 to A4 A3 A2 A1 A0 (Word/Double Word) DQ7 to DQ0 L X L L L L 000000h 01h L L L H 22h/ 222222h 7Eh H H H L 22h/ 222222h 0Dh H H H H 22h/ 222222h 00h H L H L 00h/ 000000h 01h (protected), 00h (unprotected) H 00h/ 000000h 80h (factory locked), 00h (not factory locked) L L L L L L L H H SA X 000000h–00007Fh To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 16. This method does not require VID. Refer to “Autoselect Command Sequence” for more information. L L 000000h–00003Fh Autoselect Codes (High Voltage Method) Read Cycle 1 Read Cycle 2 (x16) Address Range read the corresponding identifier code on DQ7–DQ0. However, the autoselect codes can also be accessed in-system through the command register, for instances when the device is erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is illustrated in Table 14 and Table 16. Note that if a Bank Address (BA) on address bits A21, A20, and A19 is asserted during the third write cycle of the autoselect command, the host system can read autoselect data that bank and then immediately read array data from the other bank, without exiting the autoselect mode. The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programm ing algorithm. However, the autoselect codes can also be accessed in-system through the command register. Table 7. (x32) Address Range X X VID VID X X L X L L H X DQ31 to DQ8 L L H Legend: L = Logic Low = VIL, H = Logic High = VIH, BA = Bank Address, SA = Sector Address, X = Don’t care. Note: The autoselect codes may also be accessed in-system via command sequences. October 28, 2004 Am29PDL128G 21 P R E L I M I N A R Y Table 8. Sector Group A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Sectors SGA0 0 0 0 0 0 0 0 0 0 0 0 SA0 SGA1 0 0 0 0 0 0 0 0 0 0 1 SA1 SGA2 0 0 0 0 0 0 0 0 0 1 0 SA2 SGA3 0 0 0 0 0 0 0 0 0 1 1 SA3 SGA4 0 0 0 0 0 0 0 0 1 0 0 SA4 SGA5 0 0 0 0 0 0 0 0 1 0 1 SA5 SGA6 0 0 0 0 0 0 0 0 1 1 0 SA6 SGA7 0 0 0 0 0 0 0 0 1 1 1 SA7 0 1 1 0 X X X SA8 to SA10 1 1 SGA8 22 Sector Block Addresses for Protection/Unprotection (Sheet 1 of 3) 0 0 0 0 0 0 SGA9 0 0 0 0 0 1 X X X X X SA11 to SA14 SGA10 0 0 0 0 1 0 X X X X X SA15 to SA18 SGA11 0 0 0 0 1 1 X X X X X SA19 to SA22 SGA12 0 0 0 1 0 0 X X X X X SA23 to SA26 SGA13 0 0 0 1 0 1 X X X X X SA27 to SA30 SGA14 0 0 0 1 1 0 X X X X X SA31 to SA34 SGA15 0 0 0 1 1 1 X X X X X SA35 to SA38 SGA16 0 0 1 0 0 0 X X X X X SA39 to SA42 SGA17 0 0 1 0 0 1 X X X X X SA43 to SA46 SGA18 0 0 1 0 1 0 X X X X X SA47 to SA50 SGA19 0 0 1 0 1 1 X X X X X SA51 to SA54 SGA20 0 0 1 1 0 0 X X X X X SA55 to SA58 SGA21 0 0 1 1 0 1 X X X X X SA59 to SA62 SGA22 0 0 1 1 1 0 X X X X X SA63 to SA66 SGA23 0 0 1 1 1 1 X X X X X SA67 to SA70 SGA24 0 1 0 0 0 0 X X X X X SA71 to SA74 SGA25 0 1 0 0 0 1 X X X X X SA75 to SA78 SGA26 0 1 0 0 1 0 X X X X X SA79 to SA82 SGA27 0 1 0 0 1 1 X X X X X SA83 to SA86 SGA28 0 1 0 1 0 0 X X X X X SA87 to SA90 SGA29 0 1 0 1 0 1 X X X X X SA91 to SA94 SGA30 0 1 0 1 1 0 X X X X X SA95 to SA98 SGA31 0 1 0 1 1 1 X X X X X SA99 to SA102 Am29PDL128G October 28, 2004 P R E L I M I N A R Y Table 8. Sector Block Addresses for Protection/Unprotection (Sheet 2 of 3) Sector Group A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Sectors SGA32 0 1 1 0 0 0 X X X X X SA103 to SA106 SGA33 0 1 1 0 0 1 X X X X X SA107 to SA110 SGA34 0 1 1 0 1 0 X X X X X SA111 to SA114 SGA35 0 1 1 0 1 1 X X X X X SA115 to SA118 SGA36 0 1 1 1 0 0 X X X X X SA119 to SA122 SGA37 0 1 1 1 0 1 X X X X X SA123 to SA126 SGA38 0 1 1 1 1 0 X X X X X SA127 to SA130 SGA39 0 1 1 1 1 1 X X X X X SA131 to SA134 SGA40 1 0 0 0 0 0 X X X X X SA135 to SA138 SGA41 1 0 0 0 0 1 X X X X X SA139 to SA142 SGA42 1 0 0 0 1 0 X X X X X SA143 to SA146 SGA43 1 0 0 0 1 1 X X X X X SA147 to SA150 SGA44 1 0 0 1 0 0 X X X X X SA151 to SA154 SGA45 1 0 0 1 0 1 X X X X X SA155 to SA158 SGA46 1 0 0 1 1 0 X X X X X SA159 to SA162 SGA47 1 0 0 1 1 1 X X X X X SA163 to SA166 SGA48 1 0 1 0 0 0 X X X X X SA167 to SA170 SGA49 1 0 1 0 0 1 X X X X X SA171 to SA174 SGA50 1 0 1 0 1 0 X X X X X SA175 to SA178 SGA51 1 0 1 0 1 1 X X X X X SA179 to SA182 SGA52 1 0 1 1 0 0 X X X X X SA183 to SA186 SGA53 1 0 1 1 0 1 X X X X X SA187 to SA190 SGA54 1 0 1 1 1 0 X X X X X SA191 to SA194 SGA55 1 0 1 1 1 1 X X X X X SA195 to SA198 SGA56 1 1 0 0 0 0 X X X X X SA199 to SA202 SGA57 1 1 0 0 0 1 X X X X X SA203 to SA206 SGA58 1 1 0 0 1 0 X X X X X SA207 to SA210 SGA59 1 1 0 0 1 1 X X X X X SA211 to SA214 SGA60 1 1 0 1 0 0 X X X X X SA215 to SA218 SGA61 1 1 0 1 0 1 X X X X X SA219 to SA222 SGA62 1 1 0 1 1 0 X X X X X SA223 to SA226 SGA63 1 1 0 1 1 1 X X X X X SA227 to SA230 SGA64 1 1 1 0 0 0 X X X X X SA231 to SA234 SGA65 1 1 1 0 0 1 X X X X X SA235 to SA238 October 28, 2004 Am29PDL128G 23 P R E L I M I N A R Y Table 8. Sector Block Addresses for Protection/Unprotection (Sheet 3 of 3) Sector Group A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Sectors SGA66 1 1 1 0 1 0 X X X X X SA239 to SA242 SGA67 1 1 1 0 1 1 X X X X X SA243 to SA246 SGA68 1 1 1 1 0 0 X X X X X SA247 to SA250 SGA69 1 1 1 1 0 1 X X X X X SA251 to SA254 SGA70 1 1 1 1 1 0 X X X X X SA255 to SA258 0 0 0 1 X X X SA259 to SA261 1 0 SGA71 1 1 1 1 1 1 SGA72 1 1 1 1 1 1 1 1 0 0 0 SA262 SGA73 1 1 1 1 1 1 1 1 0 0 1 SA263 SGA74 1 1 1 1 1 1 1 1 0 1 0 SA264 SGA75 1 1 1 1 1 1 1 1 0 1 1 SA265 SGA76 1 1 1 1 1 1 1 1 1 0 0 SA266 SGA77 1 1 1 1 1 1 1 1 1 0 1 SA267 SGA78 1 1 1 1 1 1 1 1 1 1 0 SA268 SGA79 1 1 1 1 1 1 1 1 1 1 1 SA269 SECTOR PROTECTION The Am29PDL128G features several levels of sector protection, which can disable both the program and erase operations in certain sectors or sector groups: Persistent Sector Protection A command sector protection method that replaces the old 12 V controlled protection method. Password Sector Protection A highly sophisticated protection method that requires a password before changes to certain sectors or sector groups are permitted WP# Hardware Protection A write protect pin that can prevent program or erase operations in sectors 0, 1, 268, and 269. All parts default to operate in the Persistent Sector Protection mode. The customer must then choose if the Persistent or Password Protection method is most desirable. There are two one-time programmable non-volatile bits that define which sector protection method is used. If the customer decides to continue using the Persistent Sector Protection method, the Persistent Sector Protection Mode Locking Bit must be set. This permanently sets the part to operate only using Persistent Sector Protection. If the cus- 24 tomer decides to use the password method, the Password Mo de Lo cking Bit must be set. This permanently sets the part to operate only using password sector protection. It is important to remember that setting either the Persistent Sector Protection Mode Locking Bit or the Password Mode Locking Bit permanently selects the protection mode. It is not possible to switch between the two methods once a locking bit has been set. It is important that one mode is explicitly selected when the device is first programmed, rather than relying on the default mode alone. This is so that it is not possible for a system program or virus to later set the Password Mode Locking Bit, which would cause an unexpected shift from the default Persistent Sector Protection Mode into the Password Protection Mode. The WP# Hardware Protection feature is always available, independent of the software managed protection method chosen. The device is shipped with all sectors unprotected. AMD offers the option of programming and protecting sectors at the factory prior to shipping the device through AMD’s ExpressFlash™ Service. Contact an AMD representative for details. Am29PDL128G October 28, 2004 P R E L I M I N A R Y It is possible to determine whether a sector is protected or unprotected. See “Autoselect Mode” on page 21 for details. Persistent Sector Protection The Persistent Sector Protection method replaces the old 12 V controlled protection method while at the same time enhancing flexibility by providing three different sector protection states: Persistently Locked—A sector is protected and cannot change. Dynamically Locked—The sector is protected and can change by a simple command Unlocked—The sector is unprotected and can change by a simple command To achieve these states, three types of “bits” are used: Persistent Protection Bit (PPB) A single Persistent (non-volatile) Protection Bit is assigned to a maximum four sectors (see the sector address tables for specific sector protection groupings). All 8 Kbyte boot-block sectors have individual sector Persistent Protection Bits (PPBs) for greater flexibility. Each PPB is individually modifiable through the PPB Write Command. Note: If a PPB requires erasure, all of the sector PPBs must first be preprogrammed prior to PPB erasing. All PPBs erase in parallel, unlike programming where individual PPBs are programmable. It is the responsibility of the us er to perfor m the preprogramming operation. Otherwise, an already erased sector PPBs has the potential of being over-erased. There is no h a rd wa re m ec ha n i sm t o pr even t se cto r P PB s over-erasure. Persistent Protection Bit Lock (PPB Lock) A global volatile bit. When set to “1”, the PPBs cannot change. When cleared (“0”), the PPBs are changeable. There is only one PPB Lock bit per device. The PPB Lock is cleared after power-up or hardware reset. There is no command sequence to unlock the PPB Lock. Dynamic Protection Bit (DYB) A volatile protection bit is assigned for each sector. After power-up or hardware reset, the contents of all DYBs is “0”. Each DYB is individually modifiable through the DYB Write Command. When the par ts are first shipped, the PPBs are cleared, the DYBs are cleared, and PPB Lock is defaulted to power up in the cleared state – meaning the PPBs are changeable. When the device is first powered on the DYBs power up cleared (sectors not protected). The Protection October 28, 2004 State for each sector is determined by the logical OR of the PPB and the DYB related to that sector. For the sectors that have the PPBs cleared, the DYBs control whether or not the sector is protected or unprotected. By issuing the DYB Write command sequences, the DYBs are set or cleared, thus placing each sector in the protected or unprotected state. These are the so-called Dynamic Locked or Unlocked states. The states are called dynamic because it is very easy to switch back and forth between the protected and unprotected conditions. This allows software to easily protect sectors against inadvertent changes yet does not prevent the easy removal of protection when changes are needed. The DYBs maybe set or cleared as often as needed. The PPBs allow for a more static, and difficult to change, level of protection. The PPBs retain the state across power cycles because the PPBs are Non-Volatile. Individual PPBs are set with a command, but all must be cleared as a group through a complex sequence of program and erasing commands. The PPBs are also limited to 100 erase cycles. The PPB Lock bit adds an additional level of protection. Once all PPBs are programmed to the desired settings, the PPB Lock may be set to “1”. Setting the PPB Lock disables all program and erase commands to the Non-Volatile PPBs. In effect, the PPB Lock Bit locks the PPBs into the current state. The only way to clear the PPB Lock is to go through a power cycle. System boot code can determine if any changes to the PPB are needed e.g. to allow new system code to be downloaded. If no changes are needed then the boot code can set the PPB Lock to disable any further changes to the PBBs during system operation. The WP# protects the top two and bottom two sectors when at VIL. These sectors generally hold system boot code. The WP# pin can prevent any changes to the boot code that could override the choices made while setting up sector protection during system initialization. It is possible to have sectors that have been persistently locked, and sectors that are left in the dynamic state. The sectors in the dynamic state are all unprotected. If there is a need to protect some of them, a simple DYB Write command sequence is all that is necessary. The DYB write command for the dynamic sectors switch the DYBs to signify protected and unprotected, respectively. If there is a need to change the status of the persistently locked sectors, a few more steps are required. First, the PPB Lock bit must be disabled by either putting the device through a power-cycle, or hardware reset. The PPBs can then be changed to reflect the desired settings. Setting the PPB lock bit once again locks the PPBs, and the device operates normally again. Am29PDL128G 25 P R E L I M I N A R Y Note: To achieve the best protection, it is recommended to execute the PPB lock bit set command early in the boot code, and protect the boot code by holding WP# = VIL. Table 9. Sector Protection Schemes DYB PPB PPB Lock 0 0 0 Unprotected—PPB and DYB are changeable 0 0 1 Unprotected—PPB not changeable, DYB is changeable 0 1 0 1 0 0 1 1 0 0 1 1 1 0 1 1 1 1 Sector State The Password Sector Protection Mode method allows an even higher level of security than the Persistent Sector Protection Mode. There are two main differences between the Persistent Sector Protection and the Password Sector Protection Mode: When the device is first powered on, or comes out of a reset cycle, the PPB Lock bit set to the locked state, rather than cleared to the unlocked state. The only means to clear the PPB Lock bit is by writing a unique 64-bit Password to the device. The Password Sector Protection method is otherwise identical to the Persistent Sector Protection method. Protected—PPB and DYB are changeable Protected—PPB not changeable, DYB is changeable Table 9 contains all possible combinations of the DYBDYB, PPB, and PPB lock relating to the status of the sector. In summary, if the PPB is set, and the PPB lock is set, the sector is protected and the protection can not be removed until the next power cycle clears the PPB lock. If the PPB is cleared, the sector can be dynamically locked or unlocked. The DYB then controls whether or not the sector is protected or unprotected. If the user attempts to program or erase a protected sector, the device ignores the command and returns to read mode. A program command to a protected sector enables status polling for approximately 1 µs before the device returns to read mode without having modified the contents of the protected sector. An erase command to a protected sector enables status polling for approximately 50 µs after which the device returns to read mode without having erased the protected sector. The programming of the DYB, PPB, and PPB lock for a g i v e n s e c t o r c a n b e ve r i f i e d b y w r i t i n g a DYB/PPB/PPB lock verify command to the device. Persistent Sector Protection Mode Locking Bit Like the password mode locking bit, a Persistent Sector Protection mode locking bit exists to guarantee that the device remain in software sector protection. Once set, the Persistent Sector Protection locking bit prevents programming of the password protection mode locking bit. This guarantees that a hacker could not place the device in password protection mode. 26 Password Protection Mode A 64-bit password is the only additional tool utilized in this method. The password is stored in the first eight bytes of the SecSi Sector. Once the Password Mode Locking Bit is set, the password is permanently set with no means to read, program, or erase it. The password is used to clear the PPB Lock bit. The Password Unlock command must be written to the flash, along with a password. The flash device internally compares the given password with the pre-programmed password. If the passwords match, the PPB Lock bit is cleared, and the PPBs can be altered. If the passwords do not match, the flash device does nothing. There is a built-in 2 µs delay for each “password check.” This delay is intended to thwart any efforts to run a program that tries all possible combinations to crack the password. Because the password occupies the first eight bytes of the SecSi Sector, the password must be programmed before either the password protection mode is selected or the SecSi Sector protection bit is programmed (to use both the SecSi Sector and Password Protection at the same time). See “Utilizing Password and SecSi Sector Concurrently” on page 30 for more information. Password and Password Mode Locking Bit To select the Password sector protection scheme, the customer must first program the password. AMD recommends that the password be somehow correlated to the unique Electronic Serial Number (ESN) of the particular flash device. Each ESN is different for every flash device; therefore each password should be different for every flash device. While programming in the password region, the customer may perform Password Verify operations. Once the desired password is programmed in, the customer must then set the Password Mode Locking Bit. This operation achieves two objectives: Am29PDL128G October 28, 2004 P R E L I M I N A R Y 1. It permanently sets the device to operate using the Password Protection Mode. It is not possible to reverse this function. 268, and 269 independent of whether it was previously protected or unprotected using “High Voltage Sector Protection” on page 27. 2. It also disables all further commands to the password region. All program, and read operations are ignored. If the system asserts VIH on the WP# pin, the device reverts to whether sectors 0, 1, 268, and 269 were last set to be protected or unprotected. That is, sector protection or unprotection for these sectors depends on whether the sectors were previously protected or unprotected using “High Voltage Sector Protection” on page 27. Both of these objectives are important, and if not carefully considered, may lead to unrecoverable errors. The user must be sure that the Password Protection method is desired when setting the Password Mode Locking Bit. More importantly, the user must be sure that the password is correct when the Password Mode Locking Bit is set. Due to the fact that read operations are disabled, there is no means to verify what the password is afterwards. If the password is lost after setting the Password Mode Locking Bit, there is no way to clear the PPB Lock bit. The Password Mode Locking Bit, once set, prevents reading the 64-bit password on the DQ bus and further password programming. The Password Mode Locking Bit is not erasable. Once Password Mode Locking Bit is programmed, the Persistent Sector Protection Locking Bit is disabled from programming, guaranteeing that no changes to the protection scheme are allowed. 64-bit Password The 64-bit Password is located in its own memory space and is accessible through the use of the Password Program and Verify commands (see “Password Verify Command”). The password function works in conjunction with the Password Mode Locking Bit, which when set, prevents the Password Verify command from reading the contents of the password on the pins of the device. Write Protect (WP#) The Write Protect feature provides a hardware method of protecting sectors 0, 1, 268, and 269 without using VID. This function is provided by the WP# pin and overrides the previously discussed Sector Protection/Unprotection method. Persistent Protection Bit Lock The Persistent Protection Bit (PPB) Lock is a volatile bit that reflects the state of the Password Mode Locking Bit after power-up reset. If the Password Mode Lock Bit is also set after a hardware reset (RESET# asserted) or a power-up reset. The ONLY means for clearing the PPB Lock Bit in Password Protection Mode is to issue the Password Unlock command. Successful execution of the Password Unlock command clears the PPB Lock Bit, allowing for sector PPBs modifications. Asserting RESET#, taking the device through a power-on reset, or issuing the PPB Lock Bit Set command sets the PPB Lock Bit to a “1” when the Password Mode Lock Bit is not set. If the Password Mode Locking Bit is not set, including Persistent Protection Mode, the PPB Lock Bit is cleared after power-up or hardware reset. The PPB Lock Bit is set by issuing the PPB Lock Bit Set command. Once set the only means for clearing the PPB Lock Bit is by issuing a hardware or power-up reset. The Password Unlock command is ignored in Persistent Protection Mode. High Voltage Sector Protection Sector protection and unprotection may also be implemented using programming equipment. The procedure requires high voltage (VID ) to be placed on the RESET# pin. Refer to Table 1 for details on this procedure. Note: For sector unprotect, all unprotected sectors must first be protected prior to the first sector write cycle. If the system asserts VIL on the WP# pin, the device disables program and erase functions in sectors 0, 1, October 28, 2004 Am29PDL128G 27 P R E L I M I N A R Y START START Protect all sectors: The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address PLSCNT = 1 RESET# = VID Wait 1 µs Temporary Sector Unprotect Mode No PLSCNT = 1 RESET# = VID Wait 1 µs No First Write Cycle = 60h? First Write Cycle = 60h? Yes Yes Set up sector address No All sectors protected? Sector Protect: Write 60h to sector address with A6-A0 = 0111010 Yes Set up first sector address Sector Unprotect: Write 60h to sector address with A6-A0 = 1111010 Wait 150 µs Increment PLSCNT Temporary Sector Unprotect Mode Verify Sector Protect: Write 40h to sector address with A6-A0 = 0111010 Reset PLSCNT = 1 Read from sector address with A6-A0 = 0111010 Wait 15 ms Verify Sector Unprotect: Write 40h to sector address with A6-A0 = 1111010 Increment PLSCNT No No PLSCNT = 25? Yes Yes No Yes Device failed Protect another sector? PLSCNT = 1000? No Yes Remove VID from RESET# Device failed Write reset command Sector Protect Algorithm Read from sector address with A6-A0 = 1111010 Data = 01h? Sector Protect complete Set up next sector address No Data = 00h? Yes Last sector verified? No Yes Sector Unprotect Algorithm Remove VID from RESET# Write reset command Sector Unprotect complete Figure 1. In-System Sector Protection/Sector Unprotection Algorithms Note:These algorithms are valid only in Persistent Sector Protection mode, and are not valid in Password Protection Mode. 28 Am29PDL128G October 28, 2004 P R E L I M I N A R Y Temporary Sector Unprotect This feature allows temporary unprotection of previously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once VID is removed from the RESET# pin, all the previously protected sectors are protected again. Figure 2 shows the algorithm, and Figure 23 shows the timing diagrams, for this feature. AMD offers the device with the SecSi Sector either fa c t or y l o cke d or c u s t om e r lo cka bl e. T he fac tory-locked version is always protected when shipped from the factory, and has the SecSi Sector Indicator Bit permanently set to a “1.” The customer-lockable version is shipped with the SecSi Sector unprotected, allowing customers to utilize the that sector in any manner. The customer-lockable version has the SecSi Sector Indicator Bit permanently set to a “0.” Thus, the SecSi Sector Indicator Bit prevents customer-lockable devices from being used to replace devices that are factory locked. The system accesses the SecSi Sector through a command sequence. (See “Enter SecSi Sector/Exit SecSi Sector Command Sequence” on page 35). After the system has written the Enter SecSi Sector command sequence, it may read the SecSi Sector by using the addresses normally occupied by the boot sectors. This mode of operation continues until the system issues the Exit SecSi Sector command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to the normal address space. Note: The ACC function and unlock bypass modes are not available when the SecSi Sector is enabled. START RESET# = VID (Note 1) Perform Erase or Program Operations RESET# = VIH Factory Locked: SecSi Sector Programmed and Protected At the Factory Temporary Sector Unprotect Completed (Note 2) Notes: 1. All protected sectors unprotected (If WP# = VIL, sectors 0, 1, 268, and 269 remain protected). 2. All previously protected sectors are protected once again. In a factory locked device, the SecSi Sector is protected when the device is shipped from the factory. The SecSi Sector cannot be modified in any way. The device is preprogrammed with both a random number and a secure ESN. The SecSi Sector is located at add r e s se s 0 0 0 0 0 0 h – 0 0 0 0 7 F h i n wo r d m o d e ( o r 000000h–00003Fh in double word mode). The device is available preprogrammed with one of the following: A random, secure ESN only Customer code through the ExpressFlash service Figure 2. Temporary Sector Unprotect Operation SecSi™ (Secured Silicon) Sector Flash Memory Region The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The SecSi Sector is 128 words (64 double words) in length, and uses a SecSi Sector Indicator Bit (DQ7) to indicate whether or not the SecSi Sector is locked when shipped from the factory. This bit is permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. This ensures the security of the ESN once the product is shipped to the field. October 28, 2004 Both a random, secure ESN and customer code through the ExpressFlash service. Customers may opt to have the code programmed by AMD through the AMD ExpressFlash service. AMD programs the customer’s code, with or without the random ESN. The devices are then shipped from AMD’s factory with the SecSi Sector permanently locked. Contact an AMD representative for details on using AMD’s ExpressFlash service. Customer Lockable: SecSi Sector NOT Programmed or Protected At the Factory If the security feature is not required, the SecSi Sector can be treated as an additional Flash memory space. The SecSi Sector can be read any number of times, but can be programmed and locked only once. Note: The accelerated programming (ACC) and unlock by- Am29PDL128G 29 P R E L I M I N A R Y pass functions are not available when programming the SecSi Sector. 5. Lock the SecSi Sector by issuing the SecSi Sector Protection Bit Program command. The SecSi Sector area can be protected using one of the following procedures: 6. Exit the SecSi Sector by issuing the SecSi Sector Exit or Reset command Write the three-cycle Enter SecSi Sector Region command sequence, and then follow the in-system sector protect algorithm as shown in Figure 1, except that RESET# may be at either VIH or VID. This allows in-system protection of the SecSi Sector Region without raising any device pin to a high voltage. Note: This method is only applicable to the SecSi Sector. Note: Step 4 may be performed prior to Step 2. To verify the protect/unprotect status of the SecSi Sector, follow the algorithm shown in Figure 3. Once the SecSi Sector is locked and verified, the system must write the Exit SecSi Sector Region command sequence to return to reading and writing the remainder of the array. Method 2 1. Enter the SecSi Sector by issuing the SecSi Sector Entry command. 2. Program the entire SecSi Sector, including the first eight bytes contain the 64-bit password. 3. Lock the password by issuing the Password Protection Mode Locking Bit Program command. 4. Lock the SecSi Sector by issuing the SecSi Sector Protection Bit Program command. 5. Exit the SecSi Sector by issuing the SecSi Sector Exit or Reset command Note: Step 4 may be performed prior to Step 3. The SecSi Sector lock must be used with caution since, once locked, there is no procedure available for unlocking the SecSi Sector area and none of the bits in the SecSi Sector memory space can be modified in any way. START RESET# = VIH or VID SecSi Sector Protection Bit The SecSi Sector Protection Bit prevents programming of the SecSi Sector memory area. Once set, the SecSi Sector memory area contents are non-modifiable. Wait 1 µs Write 60h to any address Utilizing Password and SecSi Sector Concurrently The password must be stored in the first eight bytes of the SecSi Sector. Once the device is permanently locked into the Password Protection Mode, the erase, program, and read operation no longer work on those eight bytes of password in the SecSi Sector. Once the SecSi Sector protection bit is programmed, no location in the SecSi Sector may be programmed. To use both Password Protection and the SecSi Sector concurrently, the user must always program the password into the first eight bytes of the SecSi Sector before either the Password Protection Mode is selected or the SecSi Sector protection bit is programmed. Write 40h to SecSi Sector address with A6 = 0, A1 = 1, A0 = 0 Read from SecSi Sector address with A6 = 0, A1 = 1, A0 = 0 Method 1 Figure 3. 1. Enter the SecSi Sector by issuing the SecSi Sector Entry command. 2. Program the 64-bit password by issuing the Password Program and Password Verify commands 3. Lock the password by issuing the Password Protection Mode Locking Bit Program command. 4. Program the SecSi Sector, excluding bytes 0–7. 30 If data = 00h, SecSi Sector is unprotected. If data = 01h, SecSi Sector is protected. Remove VIH or VID from RESET# Write reset command SecSi Sector Protect Verify complete SecSi Sector Protect Verify Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes. In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise. Am29PDL128G October 28, 2004 P R E L I M I N A R Y Low VCC Write Inhibit When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to the read mode. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when V CC is greater than VLKO. Write Pulse “Glitch” Protection Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit If WE# = CE# = VIL and OE# = V IH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up. COMMON FLASH MEMORY INTERFACE (CFI) handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize the existing interfaces used for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h in word mode (or address AAh in byte mode), any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 10, 11, 12, and 13. To terminate reading CFI data, the system must write the reset command. The CFI Query mode is not accessible when the device is executing an Embedded Program or embedded Erase algorithm. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 10, 11, 12, and 13. The system must write the reset command to return the device to reading array data. For further information, please refer to the CFI Specification and CFI Publication 100, available via the World Wide Web at http://www.amd.com/flash/cfi. Alternatively, contact an AMD representative for copies of these documents. The Common Flash Interface (CFI) specification outlines device and host system software interrogation Table 10. CFI Query Identification String Addresses (Double Word Mode) Addresses (Word Mode) Data 10h 11h 12h 20h 22h 24h 0051h 0052h 0059h Query Unique ASCII string “QRY” 13h 14h 26h 28h 0002h 0000h Primary OEM Command Set 15h 16h 2Ah 2Ch 0040h 0000h Address for Primary Extended Table 17h 18h 2Eh 30h 0000h 0000h Alternate OEM Command Set (00h = none exists) 19h 1Ah 32h 34h 0000h 0000h Address for Alternate OEM Extended Table (00h = none exists) October 28, 2004 Description Am29PDL128G 31 P R E L I M I N A R Y Table 11. System Interface String Addresses (Double Word Mode) Addresses (Word Mode) Data 1Bh 36h 0027h VCC Min. (write/erase) D7–D4: volt, D3–D0: 100 millivolt 1Ch 38h 0036h VCC Max. (write/erase) D7–D4: volt, D3–D0: 100 millivolt 1Dh 3Ah 0000h VPP Min. voltage (00h = no VPP pin present) 1Eh 3Ch 0000h VPP Max. voltage (00h = no VPP pin present) 1Fh 3Eh 0004h Typical timeout per single byte/word write 2N µs 20h 40h 0000h Typical timeout for Min. size buffer write 2N µs (00h = not supported) 21h 42h 000Ah Typical timeout per individual block erase 2N ms 22h 44h 0000h Typical timeout for full chip erase 2N ms (00h = not supported) 23h 46h 0005h Max. timeout for byte/word write 2N times typical 24h 48h 0000h Max. timeout for buffer write 2N times typical 25h 4Ah 0004h Max. timeout per individual block erase 2N times typical 26h 4Ch 0000h Max. timeout for full chip erase 2N times typical (00h = not supported) 32 Description Am29PDL128G October 28, 2004 P R E L I M I N A R Y Table 12. Device Geometry Definition Addresses (Double Word Mode) Addresses (Word Mode) Data 27h 4Eh 0018h Device Size = 2N byte 28h 29h 50h 52h 0005h 0000h Flash Device Interface description (refer to CFI publication 100) 2Ah 2Bh 54h 56h 0000h 0000h Max. number of byte in multi-byte write = 2N (00h = not supported) 2Ch 58h 0003h Number of Erase Block Regions within device 2Dh 2Eh 2Fh 30h 5Ah 5Ch 5Eh 60h 0007h 0000h 0020h 0000h Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100) 31h 32h 33h 34h 62h 64h 66h 68h 00FDh 0000h 0000h 0001h Erase Block Region 2 Information (refer to the CFI specification or CFI publication 100) 35h 36h 37h 38h 6Ah 6Ch 6Eh 70h 0007h 0000h 0020h 0000h Erase Block Region 3 Information (refer to the CFI specification or CFI publication 100) 39h 3Ah 3Bh 3Ch 72h 74h 76h 78h 0000h 0000h 0000h 0000h Erase Block Region 4 Information (refer to the CFI specification or CFI publication 100) October 28, 2004 Description Am29PDL128G 33 P R E L I M I N A R Y Table 13. Primary Vendor-Specific Extended Query Addresses (Double Word Mode) Addresses (Word Mode) Data 40h 41h 42h 80h 82h 84h 0050h 0052h 0049h Query-unique ASCII string “PRI” 43h 86h 0031h Major version number, ASCII (reflects modifications to the silicon) 44h 88h 0033h Minor version number, ASCII (reflects modifications to the CFI table) 45h 8Ah 0004h Address Sensitive Unlock (Bits 1-0) 0 = Required, 1 = Not Required Description Silicon Revision Number (Bits 7-2) 46h 8Ch 0002h Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write 47h 8Eh 0001h Sector Protect 0 = Not Supported, X = Number of sectors in per group 48h 90h 0001h Sector Temporary Unprotect 00 = Not Supported, 01 = Supported 49h 92h 0007h Sector Protect/Unprotect scheme 01 =29F040 mode, 02 = 29F016 mode, 03 = 29F400, 04 = 29LV800 mode 4Ah 94h 00E7h Simultaneous Operation 00 = Not Supported, X = Number of Sectors excluding Bank 1 4Bh 96h 0000h Burst Mode Type 00 = Not Supported, 01 = Supported 4Ch 98h 0002h Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page 4Dh 9Ah 00B5h 4Eh 9Ch 0005h 4Fh 9Eh 0001h 50h A0h 0000h 57h AEh 0004h 58h B0h *0027h 59h B2h *0060h 5Ah B4h *0060h 5Bh B6h 0027h ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV Top/Bottom Boot Sector Flag 34 00h = Uniform device, 01h = Uniform, 8 x 8 Kbit Top and Bottom, 02h = Bottom Boot Device, 03h = Top Boot Device, 04h = Both Top and Bottom Program Suspend 0 = Not supported, 1 = Supported Bank Organization 00 = Data at 4Ah is zero, X = Number of Banks Bank 1 Region Information X = Number of Sectors in Bank 1 Bank 2 Region Information X = Number of Sectors in Bank 2 Bank 3 Region Information X = Number of Sectors in Bank 3 Bank 4 Region Information X = Number of Sectors in Bank 4 Am29PDL128G October 28, 2004 P R E L I M I N A R Y COMMAND DEFINITIONS Writing specific address and data commands or sequences into the command register initiates device operations. Tables 14, 15, 16, and 17 define the valid register command sequences. Writing incorrect address and data values or writing them in the imp ro pe r se qu en ce m ay p lace the device in a n unknown state. A reset command is then required to return the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. See “AC Characteristics” on page 53 for timing diagrams. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. Each bank is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the corresponding ban k enters the erase-suspend-read mode, after which the system can read data from any non-erase-suspended sector within the same bank. The system can read array data using the standard read timing, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See “Erase Suspend/Erase Resume Commands” on page 38 for more information. The system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase operation, or if the bank is in the autoselect mode. See the next section, Reset Command, for more information. See also See “Requirements for Reading Array Data” on page 11 in the Device Bus Operations section for more information. See “Read-Only Operations” table for the read parameters, and Figure 12 shows the timing diagram. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the bank to which the system was writing to the read mode. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset co m m an d re tur ns th a t ba nk to the e ra se- suspend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If a bank entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode (or erase-suspend-read mode if that bank was in Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. The autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. The autoselect command cannot be written while the device is actively programming or erasing in the other bank. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the bank address and the autoselect command. The bank then enters the autoselect mode. The system may read any number of autoselect codes without reinitiating the command sequence. Reset Command Table 14 and Table 16 show the address and data requirements. To determine sector protection information, the system must write to the appropriate bank address (BA) and sector address (SA). Table 5 shows the address range and bank number associated with each sector. Writing the reset command resets the banks to the read or erase-suspend-read mode. Address bits are don’t cares for this command. The system must write the reset command to return to the read mode (or erase-suspend-read mode if the bank was previously in Erase Suspend). The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the bank to which the system was writing to the read mode. Once erasure begins, however, the device ignores reset commands until the operation is complete. October 28, 2004 Enter SecSi Sector/Exit SecSi Sector Command Sequence The SecSi Sector region provides a secured data area containing a random, eight word/four double word electronic serial number (ESN). The system can ac- Am29PDL128G 35 P R E L I M I N A R Y cess the SecSi Sector region by issuing the three-cycle Enter SecSi Sector command sequence. The device continues to access the SecSi Sector region until the system issues the four-cycle Exit SecSi Sector command sequence. The Exit SecSi Sector comm a n d s e q ue n c e r e tu r ns t h e d ev ic e t o n o r m a l operation. The SecSi Sector is not accessible when the device is executing an Embedded Program or embedded Erase algorithm. Table 15 and Table 17 show the address and data requirements for both command sequences. See also “SecSi™ (Secured Silicon) Sector Flash Memory Region” for further information. Note: The ACC function and unlock bypass modes are not available when the SecSi Sector is enabled. Double Word/Word Program Command Sequence The system may program the device by double word or word, depending on the state of the WORD# pin. Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Table 14 and Table 16 show the address and data requirements for the program command sequence. When the Embedded Program algorithm is complete, that bank then returns to the read mode and addresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. See “Write Operation Status” on page 46 for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note: A hardware reset immediately terminates the program operation. Note: the SecSi Sector, autoselect, and CFI functions are unavailable when a [program/erase] operation is in progress. The program command sequence should be reinitiated once that bank has returned to the read mode, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed 36 from “0” back to a “1.” Attempting to do so may cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was successful. However, a succeeding read shows that the data is still “0.” Only erase operations convert a “0” to a “1.” Unlock Bypass Command Sequence The unlock bypass feature allows the system to program data to a bank faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. That bank then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Table 14 and Table 16 show the requirements for the command sequence. During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. (See Table 14). The device offers accelerated program operations through the ACC pin. When the system asserts VHH on the ACC pin, the device automatically enters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the ACC pin to accelerate the operation. Note: The ACC pin must not be at VHH any operation other than accelerated programming, or device damage may result. In addition, the ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Figure 3 illustrates the algorithm for the program operation. See the table, “Erase and Program Operations” on page 57 in “AC Characteristics” for parameters, and Figure 16 for timing diagrams. Am29PDL128G October 28, 2004 P R E L I M I N A R Y operation is in progress. Note: A hardware reset immediately terminates the erase operation. If that occurs, the chip erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. START Figure 4 illustrates the algorithm for the erase operation. Refer to the “Erase and Program Operations” tables in “AC Characteristics” on page 53 for parameters, and Figure 18 for timing diagrams. Write Program Command Sequence Sector Erase Command Sequence Data Poll from System Embedded Program algorithm in progress Verify Data? No Yes Increment Address No The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Last Address? Yes Programming Completed Note: See Table 14 and Table 16 for program command sequence. Figure 4. Program Operation Chip Erase Command Sequence Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Table 14 and Table 16 show the address and data requirements for the chip erase command sequence. When the Embedded Erase algorithm is complete, that bank returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. See “Write Operation Status” on page 46 for information on these status bits. Any commands written during the chip erase operation are ignored. Note: The SecSi Sector, autoselect, and CFI functions are unavailable when a [program/erase] October 28, 2004 Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. Table 14 and Table 16 show the address and data requirements for the sector erase command sequence. After the command sequence is written, a sector erase time-out of 80 µs occurs. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 80 µs, otherwise erasure may begin. Any sector erase address and command following the exceeded time-out may or may not be accepted. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. Any command other than Sector Erase or Erase Suspend during the time-out period resets that bank to the read mode. Note: The SecSi Sector, autoselect, and CFI functions are unavailable when a [program/erase] operation is in progress. The system must rewrite the command sequence and any additional addresses and commands. The system can monitor DQ3 to determine if the sector erase timer has timed out (See the section on DQ3: Sector Erase Timer.) The time-out begins from the rising edge of the final WE# pulse in the command sequence. When the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. Note: While the Embedded Erase operation is in progress, the system can read data from the non-erasing bank. The system can determine Am29PDL128G 37 P R E L I M I N A R Y the status of the erase operation by reading DQ7, DQ6, DQ2, or RY/BY# in the erasing bank. See “Write Operation Status” on page 46 for information on these status bits. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. Note: A hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. Figure 4 illustrates the algorithm for the erase operation. Refer to the “Erase and Program Operations” tables in “AC Characteristics” on page 53 for parameters, and Figure 18 for timing diagrams. START Write Erase Command Sequence (Notes 1, 2) Data Poll to Erasing Bank from System No Embedded Erase algorithm in progress After the erase operation has been suspended, the bank enters the erase-suspend-read mode. The system can read data from or program data to any sector not selected for erasure. (The device “erase suspends” all sectors selected for erasure.) Reading at any address within erase-suspended sectors produces status information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. See “Write Operation Status” on page 46 for information on these status bits. In the erase-suspend-read mode, the system can also issue the autoselect command sequence. The device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. See “Autoselect Mode” on page 21 and “Autoselect Command Sequence” on page 35 for details. Yes Erasure Completed 1. See Table 14 and Table 14 for erase command sequence. 2. See the section on DQ3 for information on the sector erase timer Erase Operation Erase Suspend/Erase Resume Commands To resume the sector erase operation, the system must write the Erase Resume command (address bits are don’t care). The bank address of the erase-suspended bank is required when writing this command. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the chip has resumed erasing. Password Program Command The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. The bank address is required when writing this command. This command is valid only during the sector erase operation, including the 80 µs time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written dur- 38 When the Erase Suspend command is written during the sector erase operation, the device requires a maximum of 20 µs to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. Addresses are “don’t-cares” when writing the Erase suspend command. After an erase-suspended program operation is complete, the bank returns to the erase-suspend-read mode. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard Double Word/Word Program operation. See “Write Operation Status” on page 46 for more information. Data = FFh? Figure 5. ing the chip erase operation or Embedded Program algorithm. The Password Program Command permits programming the password that is used as part of the hardware protection scheme. The actual password is 64-bits long. Depending upon the state of the WORD# pin, multiple Password Program Commands are required. For a x16 bit data bus, 4 Password Program commands are required to program the password. For a x32 bit data bus, 2 Password Program commands are required. The user must enter the unlock cycle, Am29PDL128G October 28, 2004 P R E L I M I N A R Y password program command (38h) and the program address/data for each portion of the password when programming. There is no special addressing order required for programming the password. Also, when the password is undergoing programming, Simultaneous Operation is disabled. Read operations to any memory location returns the programming status. Once program m i n g is co m pl et e, the u se r mus t i ssu e a Read/Reset command to return the device to normal operation. Once the Password is written and verified, the Password Mode Locking Bit must be set to prevent verification. The Password Program Command is only capable of programming “0”s. Programming a “1” after a cell is programmed as a “0” results in a time-out by the Embedded Program Algorithm™ with the cell remaining as a “0”. The password is all F’s when shipped from the factory. All 64-bit password combinations are valid as a password. Password Programming is permitted if the SecSi sector is enabled. Password Verify Command The Password Verify Command is used to verify the Password. The Password is verifiable only when the Password Mode Locking Bit is not programmed. If the Password Mode Locking Bit is programmed and the user attempts to verify the Password, the device always drives all F’s onto the DQ data bus. The Password Verify command is permitted if the SecSi sector is enabled. Also, the device does not operate in Simultaneous Operation when the Password Verify command is executed. Only the password is returned regardless of the bank address. The lower two address bits (A0:A-1) are valid during the Password Verify. Writing the Read/Reset command returns the device back to normal operation. Password Protection Mode Locking Bit Program Command The Password Protection Mode Locking Bit Program Command programs the Password Protection Mode Locking Bit, which prevents further verifies or updates to the Password. Once programmed, the Password Protection Mode Locking Bit cannot be erased! If the Password Protection Mode Locking Bit is verified as program without margin, the Password Protection Mode Locking Bit Program command can be executed to improve the program margin. Once the Password Protection Mode Locking Bit is programmed, the Persistent Sector Protection Locking Bit program circuitry is disabled, thereby forcing the device to remain in the Password Protection mode. Exiting the Mode Locking Bit Program command is accomplished by writing the Read/Reset command. October 28, 2004 The Password Protection Mode Locking Bit Program command is permitted if the SecSi sector is enabled. Persistent Sector Protection Mode Locking Bit Program Command The Persistent Sector Protection Mode Locking Bit Program Command programs the Persistent Sector Protection Mode Locking Bit, which prevents the Password Mode Locking Bit from ever being programmed. If the Persistent Sector Protection Mode Locking Bit is verified as programmed without margin, the Persistent Sector Protection Mode Locking Bit Program Command should be reissued to improve program margin. By disabling the program circuitry of the Password Mode Locking Bit, the device is forced to remain in the Persistent Sector Protection mode of operation, once this bit is set. Exiting the Persistent Protection Mode Locking Bit Program command is accomplished by writing the Read/Reset command. The Persistent Sector Protection Mode Locking Bit Program command is permitted if the SecSi sector is enabled. SecSi Sector Protection Bit Program Command The SecSi Sector Protection Bit Program Command programs the SecSi Sector Protection Bit, which prevents the SecSi sector memory from being cleared. If the SecSi Sector Protection Bit is verified as programmed without margin, the SecSi Sector Protection Bit Program Command should be reissued to improve program margin. Exiting the V CC-level SecSi Sector Protection Bit Program Command is accomplished by writing the Read/Reset command. The SecSi Sector Protection Bit Program command is permitted if the SecSi sector is enabled. PPB Lock Bit Set Command The PPB Lock Bit Set command is used to set the PPB Lock bit if it is cleared either at reset or if the Password Unlock command was successfully executed. There is no PPB Lock Bit Clear command. Once the PPB Lock Bit is set, it cannot be cleared unless the device is taken through a power-on clear or the Password Unlock command is executed. Upon setting the PPB Lock Bit, the PPBs are latched into the DYBs. If the Password Mode Locking Bit is set, the PPB Lock Bit status is reflected as set, even after a power-on reset cycle. In the Persistent Sector Protection mode, exiting the PPB Lock Bit Set command is accomplished by writing the Read/Reset command. The PPB Lock Bit Set command is permitted if the SecSi sector is enabled. Am29PDL128G 39 P R E L I M I N A R Y DYB Write Command PPB Program Command The DYB Write command is used to set or clear a DYB for a given sector. The high order address bits (A21–A11) are issued at the same time as the code 01h or 00h on DQ7-DQ0. All other DQ data bus pins are ignored during the data write cycle. The DYBs are modifiable at any time, regardless of the state of the PPB or PPB Lock Bit. The DYBs are cleared at power-up or hardware reset.Exiting the DYB Write command is accomplished by writing the Read/Reset command. The PPB Program command is used to program, or set, a given PPB. Each PPB is individually programmed (but is bulk erased with the other PPBs). The specific sector address (A21–A11) are written at the same time as the program command 60h with A6 = 0. If the PPB Lock Bit is set and the corresponding PPB is set for the sector, the PPB Program command does not execute and the command times-out without programming the PPB. The DYB Write command is permitted if the SecSi sector is enabled. Password Unlock Command The Password Unlock command is used to clear the PPB Lock Bit so that the PPBs can be unlocked for modification, thereby allowing the PPBs to become accessible for modification. The exact password must be entered in order for the unlocking function to occur. This command cannot be issued any faster than 2 µs at a time to prevent a hacker from running through the all 64-bit combinations in an attempt to correctly match a password. If the command is issued before the 2 µs execution window for each portion of the unlock, the command is ignored. The Password Unlock function is accomplished by writing Password Unlock command and data to the device to perform the clearing of the PPB Lock Bit. The password is 64 bits long, so the user must write the Password Unlock command 2 times for a x32 bit data bus and 4 times for a x16 data bus. Once the Password Unlock command is entered, the RY/BY# pin goes LOW indicating that the device is busy. Approximately 2 µs is required for each portion of the unlock. Once the first portion of the password unlock completes (RY/BY# is not driven and DQ6 does not toggle when read), the Password Unlock command is issued again, only this time with the next part of the password. If WORD# = 1, the second Password Unlock command is the final command before the PPB Lock Bit is cleared (assuming a valid password). If WORD# = 0, this is the fourth Password Unlock command. In x16 mode, four Password Unlock commands are required to successfully clear the PPB Lock Bit. As with the first Password Unlock command, the RY/BY# signal goes LOW and reading the device results in the DQ6 pin toggling on successive read operations until complete. It is the responsibility of the microprocessor to keep track of the number of Password Unlock commands (2 for x32 bus and 4 for x16 bus), the order, and when to read the PPB Lock bit to confirm successful password unlock The Password Unlock command is permitted if the SecSi sector is enabled. 40 After programming a PPB, two additional cycles are needed to determine whether the PPB has been programmed with margin. If the PPB has been programmed without margin, the program command should be reissued to improve the program margin. The PPB Program command is permitted if the SecSi sector is enabled. The PPB Program command does not follow the Embedded Program algorithm. All PPB Erase Command The All PPB Erase command is used to erase all PPBs in bulk. There is no means for individually erasing a specific PPB. Unlike the PPB program, no specific sector address is required. However, when the PPB erase command is written (60h) and A6 = 1, all Sector PPBs are erased in parallel. If the PPB Lock Bit is set, the ALL PPB Erase command does not execute and the command times-out without erasing the PPBs. After erasing the PPBs, two additional cycles are needed to determine whether the PPB has been erased with margin. If the PPBs has been erased without margin, the erase command should be reissued to improve the program margin. It is the responsibility of the user to preprogram all PPBs prior to issuing the All PPB Erase command. If the user attempts to erase a cleared PPB, over-erasure may occur making it difficult to program the PPB at a later time. Note: The total number of PPB program/erase cycles is limited to 100 cycles. Cycling the PPBs beyond 100 cycles is not guaranteed. The All PPB Erase command is permitted if the SecSi sector is enabled. DYB Write Command The DYB Write command is used for setting the DYB, which is a volatile bit that is cleared at hardware reset. There is one DYB per sector. If the PPB is set, the sector is protected regardless of the value of the DYB. If the PPB is cleared, setting the DYB to a 1 protects the sector from programs or erases. Since this is a volatile bit, removing power or resetting the device clears the DYBs. The bank address is latched when the command is written. Am29PDL128G October 28, 2004 P R E L I M I N A R Y The DYB Write command is permitted if the SecSi sector is enabled. Sector Protection Status Command PPB Lock Bit Set Command The programming of either the PPB or DYB for a given sector or sector group can be verified by writing a Sector Protection Status command to the device. The PPB Lock Bit set command is used for setting the PPB lock bit. During Password Protection mode, only the Password Unlock command can reset the PPB Lock Bit to 0. Otherwise, a power-up or hardware reset resets the PPB Lock Bit to 0. Note: There is no single command to independently verify the programming of a DYB or PPB for a given sector group. PPB Lock Bit Status Command The programming of the PPB Lock Bit can be verified by writing a PPB Lock Bit status verify command to the device. October 28, 2004 Am29PDL128G 41 P R E L I M I N A R Y Command Definitions Tables Memory Array Command Definitions (x32 Mode) Bus Cycles (Notes 1, 2, 3, and 4) Command (Notes) Cycles Table 14. Read (5) 1 RA Reset (6) Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data (BA)X0E 0D (BA)X0F 00 RD 1 XXX F0 Manufacturer ID 4 555 AA 2AA 55 555 90 (BA)X00 01 Device ID (10) 6 555 AA 2AA 55 555 90 (BA)X01 7E SecSi Sector Factory Protect (8) 4 555 AA 2AA 55 555 90 X03 (Note 8) Sector Group Protect Verify (9) 4 555 AA 2AA 55 555 90 SA02 XX00/ XX01 Program 4 555 AA 2AA 55 555 A0 PA PD Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10 Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30 Program/Erase Suspend (11) 1 BA B0 Program/Erase Resume (12) 1 BA 30 CFI Query (13) 1 55 98 Accelerated Program (14) 2 XX A0 PA PD Unlock Bypass Entry (15) 3 555 AA 2AA 55 555 20 Unlock Bypass Program (15) 2 XX A0 PA PD XX 10 XX 00 Autoselect (Note 7) Unlock Bypass Erase (15) 2 XX 80 Unlock Bypass CFI (13, 15) 1 XX 98 Unlock Bypass Reset (15) 2 XXX 90 Legend: BA = Address of bank switching to autoselect mode, bypass mode, or erase operation. Determined by A21:A19, see Table 4 and Table 5 for more details. PA = Program Address (A21:A0). Addresses latch on falling edge of WE# or CE# pulse, whichever happens later. PD = Program Data (DQ15:DQ0) written to location PA. Data latches on rising edge of WE# or CE# pulse, whichever happens first. Notes: 1. See Table 1 for description of bus operations. 2. All values are in hexadecimal. 3. Shaded cells in the able denote read cycles. All other cycles are write operations. 4. During unlock and command cycles, when lower address bits are 555 or 2AAh as shown in the table, address bits higher than A11 (except where BA is required) and data bits higher than DQ7 are don’t cares. 5. No unlock or command cycles required when bank is reading array data. 6. Reset command is required to return to reading array (or to erase-suspend-read mode if previously in Erase Suspend) when bank is in autoselect mode, or if DQ5 goes high (while bank is providing status information). 7. Cycle 4 of autoselect command sequence is a read cycle. See “Autoselect Command Sequence” on page 35 for more information. 42 RA = Read Address (A21:A0). RD = Read Data (DQ15:DQ0) from location RA. SA = Sector Address (A21:A12) for verifying (in autoselect mode) or erasing. WD = Write Data. See “Configuration Register” definition for specific write data. Data latched on rising edge of WE#. X = Don’t care 8. The data is 80h for factory locked and 00h for not factory locked. 9. The data is 00h for an unprotected sector group and 01h for a protected sector group. 10. Device ID must be read across cycles 4, 5, and 6. 11. System may read and program in non-erasing sectors, or enter autoselect mode, when in Program/Erase Suspend mode. Program/Erase Suspend command is valid only during a sector erase operation, and requires bank address. 12. Program/Erase Resume command valid only during Erase Suspend mode, and requires bank address. 13. Command valid when device is ready to read array data or when device is in autoselect mode. 14. ACC must be at VID during entire operation of command. 15. Unlock Bypass Entry command is required prior to any Unlock Bypass operation. Unlock Bypass Reset command is required to return to reading array. Am29PDL128G October 28, 2004 P R E L I M I N A R Y Command (Notes) Reset Sector Protection Command Definitions (x32 Mode) Cycles Table 15. Addr Data Addr Data 1 XXX F0 Bus Cycles (Notes 1, 2, 3, and 4) Addr Data 88 Addr Data SecSi Sector Entry 3 555 AA 2AA 55 (BA)555 SecSi Sector Exit 4 555 AA 2AA 55 (BA)555 90 XX 00 SecSi Protection Bit Program (5, 6) 6 555 AA 2AA 55 (BA)555 60 SSA 68 Password Program (5, 7, 8) 4 555 AA 2AA 55 555 38 XX[0-1] PD[0-1] Password Verify (8, 9) 4 555 AA 2AA 55 555 C8 PWA[0-1] PWD[0-1] Password Unlock (7, 10, 11) 4 555 AA 2AA 55 555 28 PWA[0-1] PWD[0-1] Addr Data Addr Data SSA 48 XX RD(0) PPB Program (6, 12) 6 555 AA 2AA 55 555 60 (SA)WP 68 (SA)WP 48 (SA)WP RD(0) All PPB Erase (13, 14) 6 555 AA 2AA 55 555 60 (SA)EP 60 (SA)EP 40 (SA)WP RD(0) PPB Lock Bit Set 3 555 AA 2AA 55 555 78 PPB Lock Bit Status (15) 4 555 AA 2AA 55 555 58 SA RD(1) DYB Write (7) 4 555 AA 2AA 55 555 48 SA X1 DYB Erase (7) 4 555 AA 2AA 55 555 48 SA X0 DYB or PPB Status 4 555 AA 2AA 55 555 58 SA RD(0) PL 48 XX RD(0) SL 48 XX RD(0) PPMLB Program (6, 12) 6 555 AA 2AA 55 555 60 PL 68 PPMLB Status (5) 4 555 AA 2AA 55 555 60 PL RD(0) SPMLB Program (6, 12) 6 555 AA 2AA 55 555 60 SL 68 SPMLB Status (5) 4 555 AA 2AA 55 555 60 SL RD(0) Legend: DYB = Dynamic Protection Bit SSA = SecSi Sector Address (A6:A0) is (0011010). PD[1:0] = Program Data. Password written in 2 portions. PPB = Persistent Protection Bit PWA = Password Address. A0 selects portion of password. PWD = Password Data being verified. PL = Password Protection Mode Lock Address (A5:A0) is (001010) RD(0) = Read Data DQ0 for protection indicator bit. 9. Command sequence returns FFh if PPMLB is set. 1. See Table 1 for description of bus operations. 2. All values are in hexadecimal. 3. Shaded cells in the able denote read cycles. All other cycles are write operations. 4. During unlock and command cycles, when lower address bits are 555 or 2AAh as shown in the table, address bits higher than A11 (except where BA is required) and data bits higher than DQ7 are don’t cares. 5. Reset command returns device to reading array. 6. Cycle 4 programs addressed locking bit. Cycles 5 and 6 validate bit has been fully programmed when DQ0 = 1. If DQ0 = 0 in cycle 6, entire command sequence must be issued and verified again. 7. Data is latched on rising edge of WE#. 8. Entire command sequence must be executed for each portion of password. October 28, 2004 RD(1) = Read Data DQ1 for PPB Lock bit status. SA = Sector Address where security command applies. Address bits A21:A11 uniquely select any sector. SL = Persistent Protection Mode Lock Address (A5:A0) is (010010) WP = PPB Address (A6:A0) is (0111010) (Note 16) EP = PPB Erase Address (A6:A0) is (1111010) (Note 16) X = Don’t care PPMLB = Password Protection Mode Locking Bit SPMLB = Persistent Protection Mode Locking Bit 10. Password is written over four consecutive cycles at addresses 0-3. 11. A 2 µs timeout is required between any two portions of password. 12. A 100 µs timeout is required between cycles 4 and 5. 13. A 1.2 ms timeout is required between cycles 4 and 5. 14. Cycle 4 erases all PPBs. Cycles 5 and 6 validate bits have been fully erased when DQ0 = 0. If DQ0 = 1 in cycle 6, entire command sequence must be issued and verified again. Before issuing erase command, all PPBs should be programmed to prevent PPBs overerasure. 15. DQ1 = 1 if PPB locked, 0 if unlocked. 16. For all other parts that use the Persistent Protection Bit (excluding PDL640G), the WP address is 00000010 and the EP address is 01000010. Am29PDL128G 43 P R E L I M I N A R Y Command (Notes) Cycles Table 16. Memory Array Command Definitions (x16 Mode) Bus Cycles (Notes 1, 2, 3, and 4) Addr Data Addr Data Addr Data Addr Data Read (5) 1 RA Reset (6) 1 XXX F0 Manufacturer ID 4 555 AA 2AA 55 555 90 (BA)X00 01 Device ID (10) 6 555 AA 2AA 55 555 90 (BA)X01 7E SecSi Sector Factory Protect (8) 4 555 AA 2AA 55 555 90 X03 (Note 8) Sector Group Protect Verify (9) 4 555 AA 2AA 55 555 90 SA02 XX00/ XX01 PD Autoselect (Note 7) Addr Data Addr Data (BA)X0E 0D (BA)X0F 00 RD Program 4 555 AA 2AA 55 555 A0 PA Chip Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10 Sector Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 SA 30 Program/Erase Suspend (11) 1 BA B0 Program/Erase Resume (12) 1 BA 30 CFI Query (13) 1 55 98 Accelerated Program (14) 2 XX A0 PA PD Unlock Bypass Entry (15) 3 AAA AA 555 55 AAA 20 Unlock Bypass Program (15) 2 XX A0 PA PD XX 10 XX 00 Unlock Bypass Erase (15) 2 XX 80 Unlock Bypass CFI 13, 15) 1 XX 98 Unlock Bypass Reset (15) 2 XXX 90 Legend: BA = Address of bank switching to autoselect mode, bypass mode, or erase. Determined by A21:A19, see Table 4 and Table 5 for more details. PA = Program Address (A21:A-1). Addresses latch on falling edge of WE# or CE# pulse, whichever happens later. PD = Program Data (DQ15:DQ0) written to location PA. Data latches on rising edge of WE# or CE# pulse, whichever happens first. Notes: 1. See Table 1 for description of bus operations. 2. All values are in hexadecimal. RA = Read Address (A21:A-1). RD = Read Data (DQ15:DQ0) from location RA. SA = Sector Address (A21:A12) for verifying (in autoselect mode) or erasing. WD = Write Data. See “Configuration Register” definition for specific write data. Data latched on rising edge of WE#. X = Don’t care 8. The data is 80h for factory locked and 00h for not factory locked. 9. The data is 00h for an unprotected sector group and 01h for a protected sector group. 3. Shaded cells in the table denote read cycles. All other cycles are write operations. 10. Device ID must be read across cycles 4, 5, and 6. 4. During unlock and command cycles, when lower address bits are 555 or AAAh as shown in the table, address bits higher than A11 (except where BA is required) and data bits higher than DQ7 are don’t cares. 11. System may read and program in non-erasing sectors, or enter autoselect mode, when in Program/Erase Suspend mode. Program/Erase Suspend command valid only during a sector erase operation, and requires bank address. 5. No unlock or command cycles required when bank is reading array data. 12. Program/Erase Resume command valid only during Erase Suspend mode, and requires bank address. 6. Reset command is required to return to reading array (or to erase-suspend-read mode if previously in Erase Suspend) when a bank is in autoselect mode, or if DQ5 goes high (while bank is providing status information). 13. Command is valid when device is ready to read array data or when device is in autoselect mode. 7. Cycle 4 of auto command sequence is a read cycle. See “Autoselect Command Sequence” on page 35 for more information. 44 14. ACC must be at VID during entire operation of this command. 15. Unlock Bypass Entry command required prior to any Unlock Bypass operation. Unlock Bypass Reset command is required to return to reading array. Am29PDL128G October 28, 2004 P R E L I M I N A R Y Sector Protection Command Definitions (x16 Mode) Command (Notes) Cycles Table 17. Addr Data Addr Data Reset 1 XXX Bus Cycles (Notes 1, 2, 3, and 4) Addr Data Addr Data Addr Data Addr Data SSA 48 XX RD(0) F0 SecSi Sector Entry 3 AAA AA 555 55 (BA)AAA 88 SecSi Sector Exit 4 AAA AA 555 55 (BA)AAA 90 XX 00 SecSi Protection Bit Program (5, 6) 6 AAA AA 555 55 (BA)AAA 60 SSA 68 Password Program (5, 7, 8) 4 AAA AA 555 55 AAA 38 XX[0-3] PD[0-3] Password Verify (8, 9) 4 AAA AA 555 55 AAA C8 PWA[0-3] PWD[0-3] Password Unlock (7, 10, 11) 4 AAA AA 555 55 AAA 28 PWA[0-3] PWD[0-3] PPB Program (6, 12) 6 AAA AA 555 55 AAA 60 (SA)WP 68 (SA)WP 48 (SA)WP RD(0) All PPB Erase (13, 14) 6 AAA AA 555 55 AAA 60 (SA)EP 60 (SA)EP 40 (SA)WP RD(0) PPB Lock Bit Set 3 AAA AA 555 55 AAA 78 PPB Lock Bit Status (15) 4 AAA AA 555 55 AAA 58 SA RD(1) DYB Write (7) 4 AAA AA 555 55 AAA 48 SA X1 DYB Erase (7) 4 AAA AA 555 55 AAA 48 SA X0 DYB or PPB Status 4 AAA AA 555 55 AAA 58 SA RD(0) PPMLB Program (5, 6, 12) 6 AAA AA 555 55 AAA 60 PL 68 PL 48 XX RD(0) PPMLB Status (5) 4 AAA AA 555 55 AAA 60 PL RD(0) SPMLB Program (5, 6, 12) 6 AAA AA 555 55 AAA 60 SL 68 SL 48 XX RD(0) SPMLB Status (5) 4 AAA AA 555 55 AAA 60 SL RD(0) Legend: DYB = Dynamic Protection Bit SSA = SecSi Sector Address (A6:A0) is (0011010). PD[3:0] = Program Data. Password written as four 16-bit sections. PPB = Persistent Protection Bit PWA = Password Address. A0:A-1 selects portion of password. PWD = Password Data being verified. PL = Password Protection Mode Lock Address (A5:A0) is (001010) RD(0) = Read Data DQ0 for protection indicator bit. 9. Command sequence returns FFh if PPMLB is set. 1. See Table 1 for description of bus operations. 2. All values are in hexadecimal. 3. Shaded cells in the table denote read cycles. All other cycles are write operations. 4. During unlock and command cycles, when lower address bits are 555 or AAAh as shown in the table, address bits higher than A11 (except where BA is required) and data bits higher than DQ7 are don’t cares. 5. Reset command returns device to reading array. 6. Cycle 4 programs addressed locking bit. Cycles 5 and 6 validate the bit has been fully programmed when DQ0 = 1. If DQ0 = 0 in cycle 6, the program command must be issued and verified again. 7. Data is latched on rising edge of WE#. 8. Entire command sequence must be executed for each portion of password. October 28, 2004 RD(1) = Read Data DQ1 for PPB Lock bit status. SA = Sector Address where security command applies. Address bits A21:A11 uniquely select any sector. SL = Persistent Protection Mode Lock Address (A5:A0) is (010010) WP = PPB Address (A6:A0) is (0111010) (Note 16) EP = PPB Erase Address (A6:A0) is (1111010) (Note 16) X = Don’t care PPMLB = Password Protection Mode Locking Bit SPMLB = Persistent Protection Mode Locking Bit 10. Password is written over four consecutive cycles, at addresses 0-3. 11. A 2 µs timeout is required between any two portions of password. 12. A 100 µs timeout is required between cycles 4 and 5. 13. A 1.2 ms timeout is required between cycles 4 and 5. 14. Cycle 4 erases all PPBs. Cycles 5 and 6 validate bits have been fully erased when DQ0 = 0. If DQ0 = 1 in cycle 6, erase command must be issued and verified again. Before issuing erase command, all PPBs should be programmed to prevent PPB overerasure. 15. DQ1 = 1 if PPB locked, 0 if unlocked. 16. For all other parts that use the Persistent Protection Bit (excluding PDL640G), the WP address is 00000010 and the EP address is 01000010. Am29PDL128G 45 P R E L I M I N A R Y WRITE OPERATION STATUS The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 18 and the following subsections describe the function of these bits. DQ7 and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. The device also provides a hardware-based output signal, RY/BY#, to determine whether an Embedded Program or Erase operation is in progress or has been completed. vice has completed the program or erase operation a n d D Q 7 h a s va l i d d a ta , th e d a t a o u t p u ts o n D Q3 1–D Q0 may be s ti ll i nva lid . Val id d ata o n DQ31–DQ0 (or DQ15–DQ0 for word mode) appears on successive read cycles. Table 18 shows the outputs for Data# Polling on DQ7. Figure 5 shows the Data# Polling algorithm. Figure 20 in “AC Characteristics” shows the Data# Polling timing diagram. DQ7: Data# Polling The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm is in progress or completed, or whether a bank is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command sequence. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 µs, then that bank returns to the read mode. START Read DQ7–DQ0 Addr = VA DQ7 = Data? No No During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7. When the Embedded Erase algorithm is complete, or if the bank enters the Erase Suspend mode, Data# Polling produces a “1” on DQ7. The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. 46 DQ5 = 1? Yes Read DQ7–DQ0 Addr = VA After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 100 µs, then the bank returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may not be valid. When the system detects DQ7 has changed from the complement to true data, it can read valid data at DQ31–DQ0 (or DQ15–DQ0 for word mode) on the following read cycles. Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with DQ31–DQ16 (DQ15–DQ0 for word mode) while Output Enable (OE#) is asserted low. That is, the device may change from providing status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the de- Yes DQ7 = Data? Yes No FAIL PASS Notes: 1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. Am29PDL128G Figure 6. Data# Polling Algorithm October 28, 2004 P R E L I M I N A R Y RY/BY#: Ready/Busy# The RY/BY# is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC. Table 18 shows the outputs for Toggle Bit I on DQ6. Figure 6 shows the toggle bit algorithm. Figure 21 in the “AC Characteristics” on page 53 shows the toggle bit timing diagrams. Figure 22 shows the differences between DQ2 and DQ6 in graphical form. Also see “DQ2: Toggle Bit II” on page 48. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is in the read mode, the standby mode, or one of the banks is in the erase-suspend-read mode. START Read Byte (DQ0–DQ7) Address =VA Table 18 shows the outputs for RY/BY#. Read Byte (DQ0–DQ7) Address =VA DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. The system may use either OE# or CE# to control the read cycles. When the operation is complete, DQ6 stops toggling. Toggle Bit = Toggle? Yes No If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs after the program command sequence is written, then returns to reading array data. DQ5 = 1? Yes Read Byte Twice (DQ0–DQ7) Address = VA After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 µs, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7. (See “DQ7: Data# Polling” on page 46). No Toggle Bit = Toggle? No Yes Program/Erase Operation Not Complete, Write Reset Command Program/Erase Operation Complete Note: The system should recheck the toggle bit even if DQ5 = “1” because the toggle bit may stop toggling as DQ5 changes to “1.” See “DQ6: Toggle Bit I” and “DQ2: Toggle Bit II” on page 48 for more information. Figure 7. Toggle Bit Algorithm DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. October 28, 2004 Am29PDL128G 47 P R E L I M I N A R Y DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 6). DQ5: Exceeded Timing Limits DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 18 to compare outputs for DQ2 and DQ6. DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a “1,” indicating that the program or erase cycle was not successfully completed. Figure 6 shows the toggle bit algorithm in flowchart form, and “DQ2: Toggle Bit II” on page 48 explains the algorithm. Figure 21 shows the toggle bit timing diagram. Figure 22 shows the differences between DQ2 and DQ6 in graphical form. Under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if a bank was previously in the erase-suspend-program mode). Reading Toggle Bits DQ6/DQ2 After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out period is complete, DQ3 switches from a “0” to a “1.” If the time between additional sector erase commands from the system can be assumed to be less than 50 µs, the system need not monitor DQ3. Also see “Sector Erase Command Sequence” on page 37. Refer to Figure 6 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ31–DQ0 (or DQ15–DQ0 for word mode) at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ31–DQ0 (or DQ15–DQ0 for word mode) on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see “DQ5: Exceeded Timing Limits” on page 48). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor 48 The device may output a “1” on DQ5 if the system tries to program a “1” to a location that was previously programmed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 produces a “1.” DQ3: Sector Erase Timer After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is “1,” the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is “0,” the device accepts additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 18 shows the status of DQ3 relative to the other status bits. Am29PDL128G October 28, 2004 P R E L I M I N A R Y Table 18. Standard Mode Erase Suspend Mode Status Embedded Program Algorithm Embedded Erase Algorithm Erase Erase-Suspend- Suspended Sector Read Non-Erase Suspended Sector Erase-Suspend-Program Write Operation Status DQ7 (Note 2) DQ7# 0 DQ6 Toggle Toggle DQ5 (Note 1) 0 0 DQ3 N/A 1 DQ2 (Note 2)) No toggle Toggle RY/BY# 0 0 1 No toggle 0 N/A Toggle 1 Data Data Data Data Data 1 DQ7# Toggle 0 N/A N/A 0 Notes: 1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to “DQ5: Exceeded Timing Limits” on page 48 for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm is in progress. The device outputs array data if the system addresses a non-busy bank. October 28, 2004 Am29PDL128G 49 P R E L I M I N A R Y ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C 20 ns Ambient Temperature with Power Applied. . . . . . . . . . . . . . –65°C to +125°C +0.8 V Voltage with Respect to Ground –0.5 V VCC (Note 1) . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V A9, OE#, RESET#, and ACC (Note 2) . . . . . . . . . . . . . . . . . . . .–0.5 V to +12.5 V 20 ns –2.0 V 20 ns All other pins (Note 1) . . . . . . –0.5 V to VCC +0.5 V Output Short Circuit Current (Note 3) . . . . . . 200 mA Notes: 1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may overshoot V SS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC +0.5 V. See Figure 7. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 8. 2. Minimum DC input voltage on pins A9, OE#, RESET#, and ACC is –0.5 V. During voltage transitions, A9, OE#, ACC, and RESET# may overshoot V SS to –2.0 V for periods of up to 20 ns. See Figure 7. Maximum DC input voltage on pin A9, OE#, RESET#, and ACC is +12.5 V which may overshoot to +14.0 V for periods up to 20 ns. Figure 8. Maximum Negative Overshoot Waveform 20 ns VCC +2.0 V VCC +0.5 V 2.0 V 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. 20 ns 20 ns Figure 9. Maximum Positive Overshoot Waveform OPERATING RANGES Industrial (I) Devices Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C Extended (E) Devices Ambient Temperature (TA) . . . . . . . . –55°C to +125°C Supply Voltages VCC for full regulated range . . . . . . . . . . 3.0 V to 3.6 V VCC for full voltage range . . . . . . . . . . . . 2.7 V to 3.6 V VIO (see Note) . . . . . . . . . . . . . . . . . . . . 2.7 V to 3.6 V Note: For all AC and DC specifications, VIO = VCC; contact AMD for other VIO options. Operating ranges define those limits between which the functionality of the device is guaranteed. 50 Am29PDL128G October 28, 2004 P R E L I M I N A R Y DC CHARACTERISTICS CMOS Compatible Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit ±1.0 µA ILI Input Load Current VIN = VSS to VCC, VCC = VCC max ILIT A9, OE#, RESET# Input Load Current VCC = VCC max; VID= 12.5 V 35 µA ILR Reset Leakage Current VCC = VCC max; VID= 12.5 V 35 µA ILO Output Leakage Current VOUT = VSS to VCC, OE# = VIH VCC = VCC max ±1.0 µA 1 MHz 4.5 9 5 MHz 20 40 10 MHz 38 45 1 MHz 1 18 5 MHz 3.5 45 ICC2 VCC Active Write Current (Notes 2, 3) CE# = VIL, OE# = VIH, WE# = VIL 17 35 mA ICC3 VCC Standby Current (Note 2) CE#, RESET# = VCC ± 0.3 V 1.5 5 µA ICC4 VCC Reset Current (Note 2) RESET# = VSS ± 0.3 V 1.5 5 µA ICC5 Automatic Sleep Mode (Notes 2, 4) VIH = VCC ± 0.3 V; VIL = VSS ± 0.3 V 1.5 5 µA ICC6 VCC Active Read-While-Program Current (Notes 1, 2) CE# = VIL, OE# = VIH Word 30 45 Dbl. Word 30 45 ICC7 VCC Active Read-While-Erase Current (Notes 1, 2) CE# = VIL, OE# = VIH Word 21 45 Dbl. Word 21 45 ICC8 VCC Active Program-While-EraseSuspended Current (Notes 2, 5) CE# = VIL, OE# = VIH 17 35 mA VIL Input Low Voltage –0.5 0.8 V VIH Input High Voltage 0.7 x VCC VCC + 0.3 V VHH Voltage for ACC Program Acceleration VCC = 3.0 V ± 10% 11.5 12.5 V VID Voltage for Autoselect and Temporary VCC = 3.0 V ± 10% Sector Unprotect 11.5 12.5 V VOL Output Low Voltage 0.45 V ICC1 VOH1 VCC Active Inter-page Read Current, Word/Double Word Modes (Notes 1, 2) CE# = VIL, OE# = VIH VCC Active Intra-page Read Current, Word/Double Word Modes (Note 2) CE# = VIL, OE# = VIH Output High Voltage VOH2 VLKO IOL = 4.0 mA, VCC = VCC min IOH = –2.0 mA, VCC = VCC min 0.85 VIO IOH = –100 µA, VCC = VCC min VIO–0.4 Low VCC Lock-Out Voltage (Note 5) 2.3 mA mA mA mA V 2.5 V Notes: 1. The ICC current listed is typically less than 4mA/MHz, with OE# at VIH. 2. Maximum ICC specifications are tested with VCC = VCCmax. 3. ICC active while Embedded Erase or Embedded Program is in progress. 4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is 200 nA. 5. Not 100% tested. October 28, 2004 Am29PDL128G 51 P R E L I M I N A R Y TEST CONDITIONS Table 19. 3.3 V Test Condition 2.7 kΩ Device Under Test CL Test Specifications 6.2 kΩ 70R, 70, 80, 90 Output Load 1 TTL gate Output Load Capacitance, CL (including jig capacitance) 30 pF Input Rise and Fall Times 5 ns 0.0–3.0 V Input timing measurement reference levels 1.5 V Output timing measurement reference levels 1.5 V Input Pulse Levels Note: Diodes are IN3064 or equivalent Figure 10. Unit Test Setup KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Steady Changing from H to L Changing from L to H Don’t Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is High Impedance State (High Z) KS000010-PAL 3.0 V Input 1.5 V Measurement Level 1.5 V Output 0.0 V Figure 11. 52 Input Waveforms and Measurement Levels Am29PDL128G October 28, 2004 P R E L I M I N A R Y AC CHARACTERISTICS Read-Only Operations Parameter Speed Options JEDEC Std. tAVAV tRC Read Cycle Time (Note 1) tAVQV tACC Address to Output Delay tELQV tCE Chip Enable to Output Delay tPACC Description Test Setup 70R, 70 80 90 Unit Min 70 80 90 ns CE#, OE# = VIL Max 70 80 90 ns OE# = VIL Max 70 80 90 ns Page Access Time Max 25 30 35 ns 25 30 35 ns tGLQV tOE Output Enable to Output Delay Max tEHQZ tDF Chip Enable to Output High Z (Notes 1, 3) Max 16 ns tGHQZ tDF Output Enable to Output High Z (Notes 1, 3) Max 16 ns tAXQX tOH Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First Min 5 ns Read Min 0 ns tOEH Output Enable Hold Time (Note 1) Toggle and Data# Polling Min 10 ns Notes: 1. Not 100% tested. 2. See Figure 12 and Table 19 for test specifications 3. Measurements performed by placing a 50 ohm termination on the data pin with a bias of VCC/2. The time from OE# high to the data bus driven to VCC/2 is taken as tDF. . tRC Addresses Stable Addresses tACC CE# tRH tRH tDF tOE OE# tOEH WE# tCE tOH HIGH Z HIGH Z Output Valid Outputs RESET# RY/BY# 0V Figure 12. October 28, 2004 Read Operation Timings Am29PDL128G 53 P R E L I M I N A R Y AC CHARACTERISTICS Same Page A21-A3 A2-A-1 Aa tACC Data Bus Ab tPACC Qa Ad Ac tPACC Qb tPACC Qc Qd CE# OE# Figure 13. 54 Page Read Operation Timings Am29PDL128G October 28, 2004 P R E L I M I N A R Y AC CHARACTERISTICS Hardware Reset (RESET#) Parameter JEDEC Std Description All Speed Options Unit tReady RESET# Pin Low (During Embedded Algorithms) to Read Mode (See Note) Max 20 µs tReady RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode (See Note) Max 500 ns tRP RESET# Pulse Width Min 500 ns tRH Reset High Time Before Read (See Note) Min 50 ns tRPD RESET# Low to Standby Mode Min 20 µs tRB RY/BY# Recovery Time Min 0 ns Note: Not 100% tested. RY/BY# CE#, OE# tRH RESET# tRP tReady Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms tReady RY/BY# tRB CE#, OE# RESET# tRP Figure 14. October 28, 2004 Reset Timings Am29PDL128G 55 P R E L I M I N A R Y AC CHARACTERISTICS Word/Double Word Configuration (WORD#) Parameter JEDEC Std Speed Options Description 70R, 70 80 90 Unit tELFL/tELFH CE# to WORD# Switching Low or High Max 5 ns tFLQZ WORD# Switching Low to Output HIGH Z Max 16 ns tFHQV WORD# Switching High to Output Active Min 70 80 90 ns CE# OE# WORD# tELFL Data Output DQ15–DQ0 Switching from double word mode to word mode DQ30–DQ16 Output DQ31/A-1 Output Output Address Input tFLQZ tELFH WORD# Switching from word mode to double word mode Output DQ30–DQ16 DQ15–DQ0 Output Address Input DQ31/A-1 Output Output tFHQV Figure 15. WORD# Timings for Read Operations CE# The falling edge of the last WE# signal WE# WORD# tSET (tAS) tHOLD (tAH) Note: Refer to the Erase and Program Operations table for tAS and tAH specifications. Figure 16. 56 WORD# Timings for Write Operations Am29PDL128G October 28, 2004 P R E L I M I N A R Y AC CHARACTERISTICS Erase and Program Operations Parameter Speed Options JEDEC Std. Description tAVAV tWC Write Cycle Time (Note 1) Min tAVWL tAS Address Setup Time Min tASO Address Setup Time to OE# low during toggle bit polling Min tAH Address Hold Time Min 45 ns tAHT Address Hold Time From CE# or OE# high during toggle bit polling Min 0 ns tDVWH tDS Data Setup Time Min tWHDX tDH Data Hold Time Min 0 ns tOEPH Output Enable High during toggle bit polling Min 20 ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tELWL tCS CE# Setup Time Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min 35 ns tWHDL tWPH Write Pulse Width High Min 30 ns tSR/W Latency Between Read and Write Operations Min 0 ns Word Typ 12.6 Double Word Typ 16 tWLAX 70R, 70 80 90 Unit 70 80 90 ns 0 12 35 15 35 ns 15 45 ns ns tWHWH1 tWHWH1 Programming Operation (Note 2) tWHWH1 tWHWH1 Accelerated Programming Operation, Double Word or Word (Note 2) Typ 10.5 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.2 sec tVCS VCC Setup Time (Note 1) Min 50 µs tRB Write Recovery Time from RY/BY# Min 0 ns Program/Erase Valid to RY/BY# Delay Max 90 ns tBUSY µs Notes: 1. Not 100% tested. 2. See the “Erase and Program Operations” on page 57 for more information. October 28, 2004 Am29PDL128G 57 P R E L I M I N A R Y AC CHARACTERISTICS Program Command Sequence (last two cycles) tAS tWC Addresses Read Status Data (last two cycles) 555h PA PA PA tAH CE# tCH OE# tWHWH1 tWP WE# tWPH tCS tDS tDH PD A0h Data Status tBUSY DOUT tRB RY/BY# VCC tVCS Notes: 1. PA = program address, PD = program data, DOUT is the true data at the program address. 2. Illustration shows device in word mode. Figure 17. Program Operation Timings VHH WP#/ACC VIL or VIH VIL or VIH tVHH Figure 18. 58 tVHH Accelerated Program Timing Diagram Am29PDL128G October 28, 2004 P R E L I M I N A R Y AC CHARACTERISTICS Erase Command Sequence (last two cycles) tAS tWC 2AAh Addresses Read Status Data VA SA VA 555h for chip erase tAH CE# tCH OE# tWP WE# tWPH tCS tWHWH2 tDS tDH Data 55h 30h Status DOUT 10 for Chip Erase tBUSY tRB RY/BY# tVCS VCC Notes: 1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (See “Write Operation Status” on page 46)”. 2. These waveforms are for the word mode. Figure 19. October 28, 2004 Chip/Sector Erase Operation Timings Am29PDL128G 59 P R E L I M I N A R Y AC CHARACTERISTICS Addresses tWC tWC tRC Valid PA Valid RA tWC tAH tAS Valid PA Valid PA tAS tCPH tACC tAH tCE CE# tCP tOE OE# tOEH tGHWL tWP WE# tDF tWPH tDS tOH tDH Valid Out Valid In Data Valid In Valid In tSR/W WE# Controlled Write Cycle Read Cycle Figure 20. CE# Controlled Write Cycles Back-to-back Read/Write Cycle Timings tRC Addresses VA VA VA tACC tCE CE# tCH tOE OE# tOEH tDF WE# tOH High Z DQ7 Complement Complement DQ6–DQ0 Status Data Status Data True Valid Data High Z True Valid Data tBUSY RY/BY# Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. Figure 21. 60 Data# Polling Timings (During Embedded Algorithms) Am29PDL128G October 28, 2004 P R E L I M I N A R Y AC CHARACTERISTICS tAHT tAS Addresses tAHT tASO CE# tCEPH tOEH WE# tOEPH OE# tDH DQ6/DQ2 tOE Valid Data Valid Status Valid Status Valid Status (first read) (second read) (stops toggling) Valid Data RY/BY# Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle Figure 22. Enter Embedded Erasing WE# Erase Suspend Erase Toggle Bit Timings (During Embedded Algorithms) Enter Erase Suspend Program Erase Suspend Read Erase Suspend Program Erase Resume Erase Suspend Read Erase Erase Complete DQ6 DQ2 Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle DQ2 and DQ6. Figure 23. October 28, 2004 DQ2 vs. DQ6 Am29PDL128G 61 P R E L I M I N A R Y AC CHARACTERISTICS Temporary Sector Unprotect Parameter JEDEC Std Description All Speed Options Unit tVIDR VID Rise and Fall Time (See Note) Min 500 ns tVHH VHH Rise and Fall Time (See Note) Min 250 ns tRSP RESET# Setup Time for Temporary Sector Unprotect Min 4 µs tRRB RESET# Hold Time from RY/BY# High for Temporary Sector Unprotect Min 4 µs Note: Not 100% tested. VID VID RESET# VIL or VIH VIL or VIH tVIDR tVIDR Program or Erase Command Sequence CE# WE# tRRB tRSP RY/BY# Figure 24. 62 Temporary Sector Unprotect Timing Diagram Am29PDL128G October 28, 2004 P R E L I M I N A R Y AC CHARACTERISTICS VID VIH RESET# SA, A6, A1, A0 Valid* Valid* Sector Group Protect/Unprotect Data 60h 60h Valid* Verify 40h Status 1 µs CE# Sector Group Protect: 150 µs Sector Group Unprotect: 15 ms WE# OE# * For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0. Figure 25. Sector/Sector Block Protect and Unprotect Timing Diagram October 28, 2004 Am29PDL128G 63 P R E L I M I N A R Y AC CHARACTERISTICS Alternate CE# Controlled Erase and Program Operations Parameter Speed Options JEDEC Std. Description 70R, 70 80 90 Unit tAVAV tWC Write Cycle Time (Note 1) Min 70 80 90 ns tAVWL tAS Address Setup Time Min tELAX tAH Address Hold Time Min 45 45 45 ns tDVEH tDS Data Setup Time Min 35 35 45 ns tEHDX tDH Data Hold Time Min 0 ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time Min 0 ns tEHWH tWH WE# Hold Time Min 0 ns tELEH tCP CE# Pulse Width Min 35 ns tEHEL tCPH CE# Pulse Width High Min 30 ns Typ 12.6 tWHWH1 Programming Operation (Note 2) Word tWHWH1 Double Word Typ 16.6 tWHWH1 tWHWH1 Accelerated Programming Operation, Double Word or Word (Note 2) Typ 10.5 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.2 sec 0 ns µs Notes: 1. Not 100% tested. 2. See the “Erase and Program Operations” on page 57 for more information. 64 Am29PDL128G October 28, 2004 P R E L I M I N A R Y AC CHARACTERISTICS 555 for program 2AA for erase PA for program SA for sector erase 555 for chip erase Data# Polling Addresses PA tWC tAS tAH tWH WE# tGHEL OE# tWHWH1 or 2 tCP CE# tWS tCPH tBUSY tDS tDH DQ7# Data tRH A0 for program 55 for erase DOUT PD for program 30 for sector erase 10 for chip erase RESET# RY/BY# Notes: 1. Figure 26 indicates last two bus cycles of a program or erase operation. 2. PA = program address, SA = sector address, PD = program data. 3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device. 4. Waveforms are for the word mode. Figure 26. October 28, 2004 Alternate CE# Controlled Write (Erase/Program) Operation Timings Am29PDL128G 65 P R E L I M I N A R Y ERASE AND PROGRAMMING PERFORMANCE Parameter Typ (Note 1) Max (Note 2) Unit Comments Sector Erase Time 0.4 5 sec Chip Erase Time 100 Excludes 00h programming prior to erasure (Note 4) Double Word Program Time 16.6 330 µs Word Program Time 12.6 210 µs Accelerated Double Word Program Time 14.5 240 µs Accelerated Word Program Time 10.5 120 µs Double Word Mode 69.6 208 Word Mode 105.7 317 Chip Program Time (Note 3) sec Excludes system level overhead (Note 5) sec Notes: 1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Tables 14, 15, 16, and 17 for further information on command definitions. 6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles. LATCHUP CHARACTERISTICS Description Min Max Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#) –1.0 V 13 V Input voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V –100 mA +100 mA VCC Current Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time. BGA BALL CAPACITANCE Parameter Symbol Parameter Description Test Setup Typ Max Unit CIN Input Capacitance VIN = 0 4.2 5.0 pF COUT Output Capacitance VOUT = 0 5.4 6.5 pF CIN2 Control Pin Capacitance VIN = 0 3.9 4.7 pF Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25°C, f = 1.0 MHz. DATA RETENTION Parameter Description Minimum Pattern Data Retention Time 66 Am29PDL128G Test Conditions Min Unit 150°C 10 Years 125°C 20 Years October 28, 2004 P R E L I M I N A R Y PHYSICAL DIMENSIONS LAB080—80-Ball Fortified Ball Grid Array 15 x 10 mm package D1 D 0.20 C 2X A eD K J H G F E D C B A 8 7 7 6 SE eE 5 E1 4 E 3 0. 50 2 φ 1 1.00 ± 0.5 A1 CORNER ID. (INK OR LASER) 6 B 0.20 C 1.00 ± 0.5 A1 CORNER NXφb φ0.25 M C A B φ0.10 M C 2X TOP VIEW SD 7 A1 CORNER BOTTOM VIEW 0.25 C SEATING PLANE C 0.15 C SIDE VIEW NOTES UNLESS OTHERWISE SPECIFIED: LAB 080 PACKAGE N/A 15.00 mm x 10.00 mm PACKAGE MIN. NOM. MAX. SYMBOL JEDEC NOTE 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 . 2. ALL DIMENSIONS ARE IN MILLIMETERS . 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT AS NOTED). PROFILE HEIGHT A --- --- 1.40 A1 0.40 --- --- STANDOFF 4. e REPRESENTS THE SOLDER BALL GRID PITCH . A2 0.60 --- --- BODY THICKNESS 5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE "E" DIRECTION. N IS THE TOTAL NUMBER OF SOLDER BALLS. D 15.00 BSC. BODY SIZE E 10.00 BSC. 9.00 BSC. BODY SIZE MATRIX FOOTPRINT 7.00 BSC. 10 MATRIX FOOTPRINT MATRIX SIZE D DIRECTION 6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C . ME 8 MATRIX SIZE E DIRECTION 7 N φb 80 BALL COUNT SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW PARALLEL TO THE D OR E DIMENSION, RESPECTIVELY, SD OR SE = 0.000. D1 E1 MD 0.50 0.60 0.70 BALL DIAMETER eD 1.00 BSC. eE 1.00 BSC. BALL PITCH - E DIRECTION SD/SE 0.50 BSC. SOLDER BALL PLACEMENT BALL PITCH - D DIRECTION DEPOPULATED SOLDER BALLS A October 28, 2004 PACKAGE OUTLINE TYPE WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. Am29PDL128G 67 P R E L I M I N A R Y REVISION SUMMARY Initial release. Password Unlock Command section: Modified second paragraph. Revision A+1 (November 13, 2001) PPB Lock Bit Set Command section: Modified entire section. Revision A (October 29, 2001) Simultaneous Operation Block Diagram Added drawing. Table 13. “Primary Vendor-Specific Extended Query” Corrected data for 4Dh and 4Eh addresses (double-word mode). Physical Dimensions Substantial modifications were made to the command definitions tables and notes, including the following: deleted the PPB Status command sequence; added bank address requirements to SecSi Sector command; separated memory array and sector protection command sequences for easier reference. DC Characteristics In Note 1 of the CMOS Compatible table, changed typical ICC current from 2 to 4mA/MHz. Changed ICC1 typical and maximum read currents, added currents for 10 MHz operation. Added specifications for intra-page read current. Changed ICC6 typical current to 30 mA. Added LAB080 package drawing. Revision A+2 (February 8, 2002) Global Added 90 ns speed option. At this speed, tDF is 30 ns and tOH is 5 ns. For all speeds, changed typical word programming time to 8.6 µs, and typical double word programming time to 12.6 µs.” Revision B+1 (June 7, 2002) Global Simultaneous Operation Block Diagram Changed data sheet status from Advance Information to Preliminary. Deleted BYTE# input. AC Characteristics: Read-only Operations table Revision B (April 26, 2002) Changed t O E for 90 ns speed from 40 to 35 ns. Changed tOH for 70 ns speeds from 4 to 5 ns. Global Added 70R (regulated voltage range) to speed options. AC Characteristics: Erase and Program Operations table, Alternate CE# Controlled Erase and Program Operations table Changed t A SO for 70 ns speed from 15 to 12 ns. Changed t DS for 80 ns speed from 45 to 35 ns. Changed tOEPH from 20 to 10 ns. Changed all typical values from tWHWH1. Ordering Information Added “V” to package marking. Device Bus Operations Corrected sector size references in sector address table. Erase and Programming Performance Added or modified typical and maximum values to all parameters in table except for typical sector erase time. Password Protection Mode section: Clarified that first 8 bytes of SecSi Sector should be reserved for the password. Added description of using password and SecSi Sector concurrently. Revision B+2 (July 29, 2002) SecSi Sector Flash Memory Region Global Added section on using password and SecSi Sector concurrently. Changed Simultaneous Operation Flash to Simultaneous Read/ Write Flash. Table 13. “Primary Vendor-Specific Extended Query” Changed all references to DPB to DYB. Corrected data for addresses 4D and 4Eh. Command Definitions Replaced TSOP Pin Capacitance with FBGA Capacitance data. Deleted PPB Status Command section. Table 7. Autoselect Codes (High Voltage Method) Password Program Command section: Modified first paragraph. Changed the A5 to A4 and A3 Sector Protection Verification fields from L to H. 68 BGA Package Capacitance Am29PDL128G October 28, 2004 P R E L I M I N A R Y Table 9. Sector Protection Schemes Command Definitions Added field: Unprotected-PPB not changeable, DYB is changeable. Figure 1. In-System Sector Protection/Sector Unprotection Algorithms Added Note Table 14. Memory Array Command Definitions (x32 Mode) Table 16. Memory Array Command Definitions (x16 Mode) Added SecSi Sector Factory Protect and Sector Group Protect Verify fields to tables. Added Notes 8 and 9 Changed the Autoselect Sector Group Protect Verify command variable from SA(3A) to SA02. Table 15. Sector Protection Command Definitions (x32 mode) Table 17. Sector Protection Command Definitions (x16 mode) Changed variables in Cycle field for Password Program (from 5 to 4), PPMLB Status (from 6 to 4), and SPMLB Status (from 6 to 4). Added Note 17 FBGA Ball Capacitance Changed wording in last sentence of first paragraph from, “...resets the device to reading array data.” to …”may place the device to an unknown state. A reset command is then required to return the device to reading array data.” Command Definition Table 14. and Table 15. Changed one of the Data bus cycles in both tables from 90 to A0. Customer Lockable: SecSi Sector NOT Programmed or Protected at the factory. Added second bullet, SecSi sector-protect verify text and figure 3. SecSi Sector Flash Memory Region and Enter SecSi Sector/Exit SecSi Sector Command Sequence Added notes, “Note that the ACC function and unlock bypass modes are not available when the SecSi sector is enabled.” Sector Erase Command Sequence and Chip Erase Command Sequence Added “Note that the SecSi Sector, autoselect, and CFI functions are unavailable when a [program/erase] operation is in progress.” Changed table from BGA Capacitance to Fortified BGA Capacitance and modified values within table to TBD. Table 14. “Memory Array Command Definitions (x32 Mode)” and Table 16. “Memory Array Command Definitions (x16 Mode)” DC Characteristics Changed the first address of the unlock bypass reset command sequence from BA to XXX. Deleted the IACC specification row. Special Package Handling Instructions Removed the Configuration Register Verify and Configuration Register Write Commands. Changed the instructions to include molded packages (BGA). Removed Note #15. CFI Absolute Maximum Ratings Modified wording of last paragraph to read ‘reading array data”. Added ACC to Voltage with Respect to Ground section and Note #2. CMOS Compatible Revision B+3 (January 9, 2003) Added ILR parameter to table. Ordering Information Deleted IACC parameter from table. Revised Order Numbers and Package Markings to reflect speed option changes. Common Flash Memory Interface (CFI) Changed wording in last sentence of third paragraph from, “...the autoselect mode.” to “...reading array data.” Changed CFI website address. October 28, 2004 Changed the typicals of the VCC Active Intra-page... 1 and 5 MHz to 1 and 3.5. Changed the min and max of the Voltage for ACC Program Acceleration to 11.5 and 12.5. Erase and Programming Performance Changed the typical and max of the Sector Erase Time to 0.4 and 5. Am29PDL128G 69 P R E L I M I N A R Y Changed the max of Accelerated Double Word Program Time to 240. Changed the max of Accelerated Word Program Time to 120. Revision B+4 (October 28, 2004) Added Pb-Free options to Ordering information and Valid Combinations. Updated hyperlinks. BGA Ball Capacitance R e p l a c e t a bl e w i t h c a p a c i t a n c e t a bl e o n t h e Am29PDL127H datasheet. Trademarks Copyright © 2000-2004 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. 70 Am29PDL128G October 28, 2004