Preliminary Datasheet HAT3019R Nch 100V, 3.5A, 115mΩmax. Pch -100V, -2.3A, 300mΩmax Silicon N/P Channel Power MOS FET Power Switching R07DS1324EJ0700 Rev.7.00 Feb 18, 2016 Features Capable of 4.5 V gate drive Low drive current High density mounting Pb-free Outline RENESAS Package code: PRSP0008DD-D (Package name: SOP-8<FP-8DAV>) 87 5 6 D D 7 8 D D 65 1 4 G 2 G 4 23 S1 S3 Nch Pch 1, 3 Source 2, 4 Gate 5, 6, 7, 8 Drain Absolute Maximum Ratings (Ta = 25°C) Item Symbol Drain to source voltage Gate to source voltage Drain current Drain peak current Body-drain diode reverse drain current VDSS VGSS ID Channel dissipation Channel dissipation Channel temperature Storage temperature ID(pulse)Note1 IDR Pch Note2 Pch Note3 Tch Tstg Ratings Nch 100 ±20 3.5 21 3.5 Pch –100 ±20 –2.3 –13.8 –2.3 2.0 3.0 150 –55 to +150 Unit V V A A A W W C C Notes: 1. PW 10 s, duty cycle 1 % 2. 1 Drive operation; When using the glass epoxy board (FR4 40 x 40 x 1.6 mm), PW 10s 3. 2 Drive operation; When using the glass epoxy board (FR4 40 x 40 x 1.6 mm), PW 10s R07DS1324EJ0700 Rev.7.00 Feb 18, 2016 Page 1 of 10 HAT3019R Preliminary Electrical Characteristics • N Channel (Ta = 25°C) Item Drain to source breakdown voltage Gate to source breakdown voltage Gate to source leak current Zero gate voltage drain current Gate to source cutoff voltage Typ — — — — — 90 Max — — ± 10 1 2.5 115 Unit V V A A V m Test Conditions ID = 10 mA, VGS = 0 IG = ±100A, VDS = 0 VGS = ±16 V, VDS = 0 VDS = 100 V, VGS = 0 VDS = 10 V, I D = 1 mA RDS(on) Min 100 ±20 — — 1.0 — RDS(on) — 120 160 m Forward transfer admittance Input capacitance Output capacitance Reverse transfer capacitance Total gate charge Gate to source charge |yfs| Ciss Coss Crss Qg Qgs 3.6 — — — — — 6 815 85 42 15 2.2 — — — — — — S pF pF pF nC nC ID = 1.75 A, VGS = 4.5 V Note4 ID = 1.75 A, VDS = 10 V Note4 Gate to drain charge Turn-on delay time Rise time Turn-off delay time Fall time Body–drain diode forward voltage Qgd td(on) tr td(off) tf VDF — — — — — — — 3.2 10 6.5 54 6.5 0.80 35 — — — — — 1.04 — nC ns ns ns ns V ns Static drain to source on state resistance Body–drain diode reverse recovery time Symbol V(BR)DSS V(BR)GSS IGSS IDSS VGS(off) trr ID = 1.75 A, VGS = 10 V Note4 VDS = 10 V VGS = 0 f = 1 MHz VDD = 50 V VGS = 10 V ID = 3.5 A VGS = 10 V, ID = 1.75 A VDD ≈ 30 V RL = 17.1 Rg = 4.7 IF = 3.5 A, VGS = 0 Note4 IF = 3.5 A, VGS = 0 diF/ dt = 100 A/ s Notes: 4. Pulse test R07DS1324EJ0700 Rev.7.00 Feb 18, 2016 Page 2 of 10 HAT3019R Preliminary • P Channel (Ta = 25°C) Item Drain to source breakdown voltage Gate to source breakdown voltage Gate to source leak current Zero gate voltage drain current Gate to source cutoff voltage Static drain to source on state resistance Forward transfer admittance Input capacitance Output capacitance Reverse transfer capacitance Total gate charge Gate to source charge Gate to drain charge Turn-on delay time Rise time Turn-off delay time Fall time Body–drain diode forward voltage Body–drain diode reverse recovery time Symbol V(BR)DSS V(BR)GSS IGSS IDSS VGS(off) RDS(on) Min –100 ±20 — — –1.0 — Typ — — — — — 240 Max — — ±10 –1 –2.5 300 Unit V V A A V m RDS(on) — 300 500 m |yfs| Ciss Coss Crss Qg Qgs Qgd td(on) 1.8 — — — — — — — 3 930 80 50 16 2.3 3.1 18 — — — — — — — — S pF pF pF nC nC nC ns tr — — — — — 16 43 5.0 –0.83 35 — — — –1.08 — ns ns ns V ns td(off) tf VDF trr Test Conditions ID = –10 mA, VGS = 0 IG = ±100A, VDS = 0 VGS = ±16 V, VDS = 0 VDS = –100 V, VGS = 0 VDS = –10 V, I D = –1 mA ID = –1.15 A, VGS = –10 V Note4 ID = –1.15 A, VGS = – 4.5 V Note4 ID = –1.15 A, VDS = –10 V Note4 VDS = –10 V VGS = 0 f = 1MHz VDD = –50 V VGS = –10 V ID = –2.3 A VGS = –10 V, ID = –1.15 A VDD ≈ –30 V RL = 26 Rg = 4.7 IF = –2.3 A, VGS = 0 Note4 IF = –2.3 A, VGS = 0 diF/ dt =100A/µs Notes: 4. Pulse test R07DS1324EJ0700 Rev.7.00 Feb 18, 2016 Page 3 of 10 HAT3019R Preliminary Main Characteristics N Channel Typical Transfer Characteristics Maximum Safe Operation Area 10 10 Drain Current 1 DC PW Op era tio 0.1 Operation in this area is limited by RDS(on) 10 μs 0μ s 1m =1 s 0m s( 1s n( PW ID (A) 5 Drain Current ID (A) 100 ho t) ≤ 1Note 0s 5 ) 0.01 VDS= 10 V Pulse Test 4 3 2 25°C 1 Tc = 75°C Ta = 25°C –25°C 0.001 1 shot Pulse 0.1 1 10 0 100 Drain to Source Voltage VDS (V) 4 Pulse Test 3.2 V Drain Current 3 3.0 V 2 2.8 V 1 VGS = 2.6 V Drain to Source Voltage VDS(on) (mV) 0 2 4 6 8 10 3 5 4 VGS (V) Static Drain to Source on State Resistance vs. Drain Current 1 Pulse Test VGS = 4.5 V 0.1 10 V 0.01 0.1 10 1 100 Drain to Source Voltage VDS (V) Drain Current ID (A) Drain to Source Saturation Voltage vs Gate to Source Voltage Forward Transfer Admittance vs. Drain Current 500 Pulse Test 400 300 200 ID = 2 A 100 1A 0.5 A 0 4 8 12 Gate to Source Voltage R07DS1324EJ0700 Rev.7.00 Feb 18, 2016 16 20 VGS (V) Forward Transfer Admittance |yfs| (S) ID (A) 4.5 V 10 V Static Drain to Source on State Resistance RDS(on) (Ω) 5 2 Gate to Source Voltage Note 5 : When using the glass epoxy board (FR4 40x40x1.6 mm) Typical Output Characteristics 1 100 10 Tc = -25°C 25°C 75°C 1 0.1 VDS = 10 V Pulse Test 0.01 0.01 0.03 0.1 0.3 1 3 10 Drain Current ID (A) Page 4 of 10 HAT3019R Preliminary Body-Drain Diode Reverse Recovery Time Typical Capacitance vs. Drain to Source Voltage 10000 di / dt = 100 A / μs VGS = 0, Ta = 25°C 500 VGS = 0 f = 1 MHz 5000 Capacitance C (pF) Reverse Recovery Time trr (ns) 1000 200 100 50 20 2000 Ciss 1000 500 200 100 Coss 50 20 10 0.1 0.3 1 3 10 Reverse Drain Current 30 10 100 Crss 0 10 VDD = 50 V 25 V 40 8 20 4 VDD = 50 V 25 V 8 12 Gate Charge 16 0 20 Reverse Drain Current IDR (A) Pulse Test 4 10 V 3 0 5V VGS = 0, -5 V 0.4 0.8 1.2 Source to Drain Voltage R07DS1324EJ0700 Rev.7.00 Feb 18, 2016 100 t d(off) 30 tr t d(on) 10 tf 1 0.1 0.3 1.6 1 3 10 Drain Current 5 1 VGS = 10 V, VDD ≈ 30 V PW = 5 μs, duty < 1 % Qg (nC) Reverse Drain Current vs. Source to Drain Voltage 2 50 3 2.0 VSD (V) Static Drain to Source on State Resistance RDS(on) (mΩ) 4 300 Switching Time t (ns) 12 (V) 16 VGS VGS 80 1000 Gate to Source Voltage VDS (V) Drain to Source Voltage 20 ID = 3.5 A 0 0 40 Switching Characteristics 100 VDS 30 Drain to Source Voltage VDS (V) IDR (A) Dynamic Input Characteristics 60 20 30 100 ID (A) Static Drain to Source on State Resistance vs. Temperature 250 Pulse Test ID = 0.5 A, 1 A, 2 A 200 150 VGS = 4.5 V 0.5 A, 1 A, 2 A 100 50 0 –25 VGS = 10 V 0 25 50 75 Case Temperature 100 125 150 Tc (°C) Page 5 of 10 HAT3019R Preliminary Main Characteristics P Channel Typical Transfer Characteristics Maximum Safe Operation Area -5 Drain Current -1 -0.1 -0.01 ID (A) -10 10 μ 10 0μ s PW 1m s =1 s DC 0m Op s( 1s era ho tio t) n( PW No ≤ 1 0 te 5 Operation in s) this area is limited by RDS(on) VDS = -10 V Pulse Test -4 -3 Drain Current ID (A) -100 -2 -1 -0.1 –25°C -1 -10 -100 0 Drain to Source Voltage VDS (V) -5 Pulse Test -10 V -3.4 V Drain Current -3 -3.0 V -2 -1 VGS = -2.6 V Drain to Source Voltage VDS(on) (mV) 0 -2 -4 -6 -8 -10 -2 -3 -5 -4 VGS (V) Static Drain to Source on State Resistance vs. Drain Current 10 Pulse Test 1 VGS = –4.5 V –10 V 0.1 -0.1 -10 -1 Drain to Source Voltage VDS (V) Drain Current ID (A) Drain to Source Saturation Voltage vs Gate to Source Voltage Forward Transfer Admittance vs. Drain Current –1.0 Pulse Test –0.8 –0.6 ID = –2 A –0.4 –1 A –0.2 0 –0.5 A –4 –8 –12 Gate to Source Voltage R07DS1324EJ0700 Rev.7.00 Feb 18, 2016 –16 –20 VGS (V) Forward Transfer Admittance |yfs| (S) ID (A) -4.5 V Static Drain to Source on State Resistance RDS(on) (Ω) Typical Output Characteristics -1 Gate to Source Voltage Note 5 : When using the glass epoxy board (FR4 40x40x1.6 mm) -4 25°C Tc = 75°C Ta = 25°C -0.001 1 shot Pulse 10 1 Tc = -25°C 25°C 75°C 0.1 VDS = -10 V Pulse Test 0.01 -0.01 -0.03 -0.1 -0.3 -1 -3 -10 Drain Current ID (A) Page 6 of 10 HAT3019R Preliminary Body-Drain Diode Reverse Recovery Time Typical Capacitance vs. Drain to Source Voltage 10000 VGS = 0 5000 f = 1 MHz di / dt = 100 A / μs VGS = 0, Ta = 25°C 500 Capacitance C (pF) Reverse Recovery Time trr (ns) 1000 200 100 50 2000 Ciss 1000 500 200 100 Coss 50 20 Crss 20 10 -0.1 -0.3 -1 -3 -10 Reverse Drain Current -30 10 -100 0 –10 (V) 1000 –4 VGS 300 –8 –12 –80 –16 ID = –2.3 A –100 0 4 8 Gate Charge 12 16 –20 20 Reverse Drain Current IDR (A) Pulse Test –4 –10 V –5 V VGS = 0, 5 V –1 0 –0.4 –0.8 –1.2 Source to Drain Voltage R07DS1324EJ0700 Rev.7.00 Feb 18, 2016 tr t d(on) 30 10 tf 3 VGS = -10 V, VDD ≈ -30 V PW = 5 μs, duty < 1 % -0.3 –1.6 -1 -3 -10 Drain Current –5 –2 –50 t d(off) Qg (nC) Reverse Drain Current vs. Source to Drain Voltage –3 100 1 -0.1 –2.0 VSD (V) Static Drain to Source on State Resistance RDS(on) (mΩ) –60 VGS Switching Time t (ns) –40 0 Gate to Source Voltage VDS (V) Drain to Source Voltage VDD = –25 V –50 V VDD = –50 V –25 V –40 Switching Characteristics 0 VDS –30 Drain to Source Voltage VDS (V) IDR (A) Dynamic Input Characteristics –20 –20 -30 -100 ID (A) Static Drain to Source on State Resistance vs. Temperature 1.2 Pulse Test 1.0 0.8 –1 A ID = –0.2 A, –0.5 A 0.6 0.4 VGS = –4.5 V –0.2 A, –0.5, -1 A 0.2 –10 V 0 –25 0 25 50 75 Case Temperature 100 125 150 Tc (°C) Page 7 of 10 HAT3019R Preliminary Common Power vs. Temperature Derating Test condition. When using the glass epoxy board. (FR4 40 x 40 x 1.6 mm), (PW ≤ 10 s) 3.0 2 Dr ive 2.0 O 50 Op n 0 ive tio 1.0 Dr ra 1 pe Channel Dissipation Pch (W) 4.0 er at ion 100 150 Normalized Transient Thermal Impedance γs (t) Ambient Temperature 200 Ta (°C) Normalized Transient Thermal Impedance vs. Pulse Width(1 Drive Operation) 10 1 D=1 0.5 0.2 0.1 0.1 θch - f(t) = γs (t) x θch - f θch - f = 100°C/W, Ta = 25°C When using the glass epoxy board (FR4 40 x 40 x 1.6 mm) 0.05 0.02 1 0.0 ulse tp o h 1s 0.01 PDM D= PW T PW T 0.001 10 μ 100 μ 1m 10 m 100 m 1 10 100 1000 10000 Normalized Transient Thermal Impedance γs (t) Pulse Width PW (s) Normalized Transient Thermal Impedance vs. Pulse Width(2 Drive Operation) 10 1 D=1 0.5 0.2 0.1 0.01 0.1 θch - f(t) = γs (t) x θch - f θch - f = 130°C/W, Ta = 25°C When using the glass epoxy board (FR4 40 x 40 x 1.6 mm) 0.05 0.02 1 0.0 ulse tp o h 1s PDM D= PW T PW T 0.001 10 μ 100 μ 1m 10 m 100 m 1 10 100 1000 10000 Pulse Width PW (s) R07DS1324EJ0700 Rev.7.00 Feb 18, 2016 Page 8 of 10 HAT3019R Preliminary N Channel Switching Time Test Circuit Vout Monitor Vin Monitor Rg Switching Time Waveform 90% D.U.T. RL Vin VDD ≈ 30 V Vin 10 V Vout 10% 10% 90% td(on) tr 10% 90% td(off) tf P Channel Switching Time Test Circuit Vout Monitor Vin Monitor Rg Vin -10 V Switching Time Waveform Vin 10% D.U.T. RL 90% Vout td(on) R07DS1324EJ0700 Rev.7.00 Feb 18, 2016 90% 90% V DD ≈ -30 V 10% 10% tr td(off) tf Page 9 of 10 HAT3019R Preliminary Package Dimensions JEITA Package Code P-SOP8-3.95 × 4.9-1.27 RENESAS Code PRSP0008DD-D Previous Code FP-8DAV MASS[Typ.] 0.085g F Package Name SOP-8 *1 D bp 1 c *2 E Index mark HE 5 8 4 Z Terminal cross section (Ni/Pd/Au plating) * 3 bp x M e NOTE) 1. DIMENSIONS "*1(Nom)" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. Reference Dimension in Millimeters Symbol Min A1 A L1 L y Detail F D E A2 A1 A bp b1 c c1 HE e x y Z L L1 Nom Max 4.90 5.3 3.95 0.10 0.14 0.25 1.75 0.34 0.40 0.46 0.15 0.20 0.25 0° 8° 5.80 6.10 6.20 1.27 0.25 0.1 0.75 0.40 0.60 1.27 1.08 Ordering Information Orderable Part Number HAT3019R-EL-E R07DS1324EJ0700 Rev.7.00 Feb 18, 2016 Quantity 2500 pcs Shipping Container Taping Page 10 of 10 Notice 1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 2. 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