Maxim MAX541AEPA 5v, serial-input, voltage-output, 16-bit dac Datasheet

19-1082; Rev 2; 12/99
+5V, Serial-Input, Voltage-Output, 16-Bit DACs
Features
♦ Full 16-Bit Performance Without Adjustments
♦ +5V Single-Supply Operation
♦ Low Power: 1.5mW
♦ 1µs Settling Time
♦ Unbuffered Voltage Output Directly Drives 60kΩ
Loads
♦ SPI/QSPI/MICROWIRE-Compatible Serial Interface
♦ Power-On Reset Circuit Clears DAC Output to 0V
(unipolar mode)
♦ Schmitt Trigger Inputs for Direct Optocoupler
Interface
Ordering Information
PART
TEMP. RANGE
MAX541ACPA
INL
(LSB)
PIN-PACKAGE
0°C to +70°C
8 Plastic DIP
±1
The MAX541 is available in 8-pin plastic DIP and SO
packages. The MAX542 is available in 14-pin plastic
DIP and SO packages.
MAX541BCPA
0°C to +70°C
8 Plastic DIP
±2
MAX541CCPA
0°C to +70°C
8 Plastic DIP
±4
MAX541ACSA
0°C to +70°C
8 SO
±1
Applications
MAX541BCSA
0°C to +70°C
8 SO
±2
MAX541CCSA
0°C to +70°C
8 SO
±4
High-Resolution Offset and Gain Adjustment
Ordering Information continued at end of data sheet.
Industrial Process Control
Automated Test Equipment
Functional Diagrams
Data-Acquisition Systems
General Description
VDD
TOP VIEW
RFB
MAX542
RFB
INV
OUT 1
AGND 2
8 VDD
MAX541
7 DGND
CS 4
14 VDD
13 INV
AGNDF 3
MAX542
AGNDS 4
5 SCLK
10 DIN
REFF 6
RINV
16-BIT DAC
9 N.C.
OUT
REFS
AGNDF
12 DGND
11 LDAC
REFS 5
6 DIN
REF 3
RFB 1
OUT 2
REFF
CS
LDAC
SCLK
DIN
16-BIT DATA LATCH
AGNDS
CONTROL
LOGIC
SERIAL INPUT REGISTER
8 SCLK
CS 7
DGND
DIP/SO
DIP/SO
Functional Diagrams continued at end of data sheet.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
MAX541/MAX542
General Description
The MAX541/MAX542 are serial-input, voltage-output,
16-bit digital-to-analog converters (DACs) that operate
from a single +5V supply. They provide 16-bit performance (±1LSB INL and DNL) over temperature without
any adjustments. The DAC output is unbuffered, resulting in a low supply current of 0.3mA and a low offset
error of 1LSB.
The DAC output range is 0V to VREF. For bipolar operation, matched scaling resistors are provided in the
MAX542 for use with an external precision op amp
(such as the MAX400), generating a ±V REF output
swing. The MAX542 also includes Kelvin-sense connections for the reference and analog ground pins to
reduce layout sensitivity.
A 16-bit serial word is used to load data into the DAC
latch. The 10MHz, 3-wire serial interface is compatible
with SPI™/QSPI™/MICROWIRE™, and it also interfaces
directly with optocouplers for applications requiring isolation. A power-on reset circuit clears the DAC output to 0V
(unipolar mode) when power is initially applied.
MAX541/MAX542
+5V, Serial-Input, Voltage-Output, 16-Bit DACs
ABSOLUTE MAXIMUM RATINGS
VDD to DGND ...........................................................-0.3V to +6V
CS, SCLK, DIN, LDAC to DGND ..............................-0.3V to +6V
REF, REFF, REFS to AGND ........................-0.3V to (VDD + 0.3V)
AGND, AGNDF, AGNDS to DGND........................-0.3V to +0.3V
OUT, INV to AGND, DGND ......................................-0.3V to VDD
RFB to AGND, DGND..................................................-6V to +6V
Maximum Current into Any Pin............................................50mA
Continuous Power Dissipation (TA = +70°C)
8-Pin Plastic DIP (derate 9.09mW/°C above +70°C) .....727mW
8-Pin SO (derate 5.88mW/°C above +70°C) .................471mW
14-Pin Plastic DIP (derate 10.00mW/°C above +70°C) ...800mW
14-Pin SO (derate 8.33mW/°C above +70°C) ...............667mW
14-Pin Ceramic SB (derate 10.00mW/°C above +70°C ..800mW
Operating Temperature Ranges
MAX541 _C_ A/MAX542_C_D. .............................0°C to +70°C
MAX541 _E_ A/MAX542_E_D............................-40°C to +85°C
MAX542CMJD .................................................-55°C to +125°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +5V ±5%, VREF = +2.5V, AGND = DGND = 0, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
TYP
MAX
MAX54_A
±0.5
±1.0
MAX54_B
±0.5
±2.0
MAX54_C
±0.5
±4.0
±0.5
±1.0
STATIC PERFORMANCE—ANALOG SECTION (RL = ∞)
Resolution
N
Integral Nonlinearity
INL
Differential Nonlinearity
DNL
Zero-Code Offset Error
ZSE
Zero-Code Tempco
ZSTC
Gain Error (Note 1)
VDD = 5V
MIN
16
Guaranteed monotonic
±1
TA = TMIN to TMAX
±2
±0.05
ROUT
±5
TA = TMIN to TMAX
±10
Bipolar Resistor Matching
MAX542
Bipolar Zero Offset Error
Bipolar Zero Tempco
(Note 2)
MAX542
BZSTC
RFB/RINV
TA = TMIN to TMAX
±20
±0.5
REFERENCE INPUT
Reference Input Range
VREF
(Note 3)
2.0
Unipolar mode
11.5
MAX542, bipolar mode
9.0
2
kΩ
±10
MAX542
1
ppm/°C
±0.015
4.75V ≤ VDD ≤ 5.25V
Output Settling Time
to ± /2LSB of FS, CL = 10pF
LSB
6.25
TA = +25°C
DYNAMIC PERFORMANCE—ANALOG SECTION (RL = ∞, unipolar mode)
Voltage-Output Slew Rate
SR
CL = 10pF (Note 5)
LSB
1.0
PSR
RREF
LSB
±0.1
Ratio error
Power-Supply Rejection
Reference Input Resistance
(Note 4)
LSB
ppm/°C
TA = +25°C
Gain-Error Tempco
DAC Output Resistance
Bits
TA = +25°C
TA = TMIN to TMAX
UNITS
%
LSB
ppm/°C
±1.0
LSB
3.0
V
kΩ
25
V/µs
1
µs
_______________________________________________________________________________________
+5V, Serial-Input, Voltage-Output, 16-Bit DACs
MAX541/MAX542
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +5V ±5%, VREF = +2.5V, AGND = DGND = 0, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DAC Glitch Impulse
Major-carry transition
10
nVs
Digital Feedthrough
Code = 0000 hex; CS = VDD; LDAC = 0;
SCLK, DIN = 0 to VDD levels
10
nVs
DYNAMIC PERFORMANCE—REFERENCE SECTION
Reference -3dB Bandwidth
BW
Reference Feedthrough
Signal-to-Noise Ratio
SNR
Reference Input Capacitance
CIN
Code = FFFF hex
1
MHz
Code = 0000 hex, VREF = 1Vp-p at 100kHz
1
mVp-p
92
dB
Code = 0000 hex
75
Code = FFFF hex
120
pF
STATIC PERFORMANCE—DIGITAL INPUTS
Input High Voltage
VIH
Input Low Voltage
VIL
Input Current
IIN
Input Capacitance
CIN
Hysteresis Voltage
VH
2.4
V
0.8
V
VIN = 0
±1
µA
(Note 6)
10
pF
0.40
V
POWER SUPPLY
Positive Supply Range
VDD
4.75
5.25
Positive Supply Current
IDD
0.3
Power Dissipation
PD
1.5
1.1
V
mA
mW
TIMING CHARACTERISTICS
(VDD = +5V ±5%, VREF = +2.5V, AGND = DGND = 0, CMOS inputs, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
10
MHz
SCLK Frequency
fCLK
SCLK Pulse Width High
tCH
45
ns
SCLK Pulse Width Low
tCL
45
ns
CS Low to SCLK High Setup
tCSS0
45
ns
CS High to SCLK High Setup
tCSS1
45
ns
SCLK High to CS Low Hold
tCSH0
30
ns
SCLK High to CS High Hold
tCSH1
45
ns
DIN to SCLK High Setup
tDS
40
ns
DIN to SCLK High Hold
tDH
0
ns
(Note 6)
LDAC Pulse Width
tLDAC
MAX542
50
ns
CS High to LDAC Low Setup
tLDACS
MAX542 (Note 6)
50
ns
VDD High to CS Low
(power-up delay)
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
20
µs
Gain Error tested at VREF = 2.0V, 2.5V, and 3.0V.
ROUT tolerance is typically ±20%.
Min/max range guaranteed by gain-error test. Operation outside min/max limits will result in degraded performance.
Reference input resistance is code dependent, minimum at 8555 hex.
Slew-rate value is measured from 0% to 63%.
Guaranteed by design. Not production tested.
_______________________________________________________________________________________
3
__________________________________________Typical Operating Characteristics
(VDD = 5V, VREF = +2.5V, TA = +25°C, unless otherwise noted.)
SUPPLY CURRENT
vs. REFERENCE VOLTAGE
SUPPLY CURRENT (mA)
0.35
0.30
0.25
0.32
0.31
0.30
0.29
-20
0
20
40
60
80
100
0
1
2
3
4
5
0.4
0.2
0
-0.2
-0.4
-0.6
-1.0
-60
6
-20
20
60
TEMPERATURE (°C)
REFERENCE VOLTAGE (V)
TEMPERATURE (°C)
INTEGRAL NONLINEARITY
vs. TEMPERATURE
DIFFERENTIAL NONLINEARITY
vs. TEMPERATURE
GAIN ERROR
vs. TEMPERATURE
0.8
0.8
0.4
0.4
DNL (LSB)
0
-0.2
-0.4
GAIN ERROR (LSB)
0.6
0.4
0.2
+DNL
0
-0.2
-DNL
-0.4
-INL
0
-0.2
-0.4
-0.6
-0.8
-0.8
-0.8
-1.0
-60
-1.0
-60
-20
20
60
100
140
-20
20
60
100
140
0.2
-0.6
-0.6
100
0.8
0.6
+INL
140
1.0
0.6
0.2
100
MAX542-06
1.0
MAX542-04
1.0
MAX542-05
-1.0
-60
140
-20
20
60
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
INTEGRAL NONLINEARITY
vs. CODE
DIFFERENTIAL NONLINEARITY
vs. CODE
REFERENCE CURRENT
vs. CODE
1.00
MAX542-07
1.00
0.75
200
0.75
MAX542-09
-40
0.6
-0.8
0.28
0.20
INL (LSB)
0.33
MAX542-08
SUPPLY CURRENT (mA)
0.40
0.8
ZERO-CODE OFFSET ERROR (LSB)
0.34
0.45
1.0
MAX542-02
0.35
MAX542-01
0.50
ZERO-CODE OFFSET ERROR
vs. TEMPERATURE
MAX542-03
SUPPLY CURRENT
vs. TEMPERATURE
0.50
0.25
0.25
DNL (LSB)
0.50
0
-0.25
-0.25
-0.50
-0.75
-0.75
10k
20k
30k
40k
DAC CODE
50k
60k
70k
120
80
40
0
-1.00
0
4
0
-0.50
-1.00
REFERENCE CURRENT (µA)
160
INL (LSB)
MAX541/MAX542
+5V, Serial-Input, Voltage-Output, 16-Bit DACs
0
10k
20k
30k
40k
DAC CODE
50k
60k
70k
0
10k
20k
30k
40k
DAC CODE
_______________________________________________________________________________________
50k
60k
70k
+5V, Serial-Input, Voltage-Output, 16-Bit DACs
FULL-SCALE STEP RESPONSE
(fSCLK = 10MHz)
CL = 10pF
RL = ∞
MAX542-10A
MAX542-10
CL = 10pF
RL = ∞
FULL-SCALE STEP RESPONSE
(fSCLK = 20MHz)
OUT
500mV/div
OUT
500mV/div
2µs/div
2µs/div
1µs/div
400ns/div
DIGITAL FEEDTHROUGH
MAX542-11
MAX542-12
MAJOR-CARRY OUTPUT GLITCH
CS
(5V/div)
SCLK
5V/div
OUT
(AC-COUPLED,
100mV/div)
OUT
(AC-COUPLED,
50mV/div)
2µs/div
2µs/div
CODE = 0000 hex
Pin Descriptions
MAX541
PIN
NAME
1
OUT
2
AGND
3
REF
Voltage Reference Input. Connect to external +2.5V reference.
4
CS
Chip-Select Input
5
SCLK
6
DIN
7
DGND
8
VDD
FUNCTION
DAC Output Voltage
Analog Ground
Serial Clock Input. Duty cycle must be between 40% and 60%.
Serial Data Input
Digital Ground
+5V Supply Voltage
_______________________________________________________________________________________
5
MAX541/MAX542
Typical Operating Characteristics (continued)
(VDD = +5V, VREF = +2.5V, TA = +25°C, unless otherwise noted.)
MAX541/MAX542
+5V, Serial-Input, Voltage-Output, 16-Bit DACs
________________________________________________Pin Descriptions (continued)
MAX542
PIN
NAME
FUNCTION
1
RFB
Feedback Resistor. Connect to external op amp’s output in bipolar mode.
2
OUT
DAC Output Voltage
3
AGNDF
Analog Ground (force)
4
AGNDS
Analog Ground (sense)
5
REFS
Voltage Reference Input (sense). Connect REFS to external +2.5V reference.
6
REFF
Voltage Reference Input (force). Connect REFF to external +2.5V reference.
7
CS
8
SCLK
Serial Clock Input. Duty cycle must be between 40% and 60%.
9
N.C.
No Connection. Not internally connected.
10
DIN
Serial Data Input
11
LDAC
LDAC Input. A falling edge updates the internal DAC latch.
12
DGND
Digital Ground
13
INV
Junction of internal scaling resistors. Connect to external op amp’s inverting input in
bipolar mode.
14
VDD
+5V Supply Voltage
Chip-Select Input
;;;;;;;;;
;;
;;;;;;
tCSH1
tLDACS
CS
tCSHO
tCSSO
tCH
tCSS1
tCL
SCLK
tDH
tDS
DIN
D15
D14
D0
LDAC*
tLDAC
*MAX542 ONLY
Figure 1. Timing Diagram
6
_______________________________________________________________________________________
+5V, Serial-Input, Voltage-Output, 16-Bit DACs
MAX541/MAX542
+2.5V
10µF
+5V
0.1µF
0.1µF
MC68XXXX
VDD
PCS0
CS
MOSI
DIN
SCLK
SCLK
(REFS)
UNIPOLAR
OUT
MAX495
OUT
MAX541/MAX542
(LDAC)
(GND)
REF (REFF)
DGND
EXTERNAL OP AMP
AGND_
( ) ARE FOR MAX542 ONLY
Figure 2a. Typical Operating Circuit—Unipolar Output
+2.5V
10µF
+5V
0.1µF
0.1µF
+5V
MC68XXXX
VDD
PCS0
CS
MOSI
DIN
SCLK
SCLK
IC1
LDAC
REFF
RFB
REFS
RINV
RFB
INV
MAX400
OUT
BIPOLAR
OUT
EXTERNAL OP AMP
MAX542
-5V
(GND)
DGND
AGNDF
AGNDS
Figure 2b. Typical Operating Circuit—Bipolar Output
Detailed Description
The MAX541/MAX542 voltage-output, 16-bit digital-toanalog converters (DACs) offer full 16-bit performance
with less than 1LSB integral linearity error and less than
1LSB differential linearity error, thus ensuring monotonic performance. Serial data transfer minimizes the number of package pins required.
The MAX541/MAX542 are composed of two matched
DAC sections, with a 12-bit inverted R-2R DAC forming
the 12 LSBs and the 4 MSBs derived from 15 identically
matched resistors. This architecture allows the lowest
glitch energy to be transferred to the DAC output on
major-carry transitions. It also lowers the DAC output
impedance by a factor of eight compared to a standard
R-2R ladder, allowing unbuffered operation in mediumload applications.
The MAX542 provides matched bipolar offset resistors,
which connect to an external op amp for bipolar output
swings (Figure 2b). For optimum performance, the
MAX542 also provides a set of Kelvin connections to
the voltage-reference and analog-ground inputs.
_______________________________________________________________________________________
7
MAX541/MAX542
+5V, Serial-Input, Voltage-Output, 16-Bit DACs
Digital Interface
External Reference
The MAX541/MAX542’s digital interface is a standard
3-wire connection compatible with SPI/QSPI/
MICROWIRE interfaces. The chip-select input (CS)
frames the serial data loading at the data-input pin
(DIN). Immediately following CS’s high-to-low transition,
the data is shifted synchronously and latched into the
input register on the rising edge of the serial clock input
(SCLK). After 16 data bits have been loaded into the
serial input register, it transfers its contents to the DAC
latch on CS’s low-to-high transition (Figure 3a). Note
that if CS is not kept low during the entire 16 SCLK
cycles, data will be corrupted. In this case, reload the
DAC latch with a new 16-bit word.
Alternatively, for the MAX542, LDAC allows the DAC
latch to update asynchronously by pulling LDAC low
after CS goes high (Figure 3b). Hold LDAC high during
the data-loading sequence.
The MAX541/MAX542 operate with external voltage references from 2V to 3V. The reference voltage determines the DAC’s full-scale output voltage. Kelvin
connections are provided with the MAX542 for optimum
performance.
Power-On Reset
The MAX541/MAX542 have a power-on reset circuit to
set the DAC’s output to 0V in unipolar mode when VDD
is first applied. This ensures that unwanted DAC output
voltages will not occur immediately following a system
power-up, such as after a loss of power. In bipolar
mode, the DAC output is set to -VREF.
; ; ;;
;;;;;;
CS
DAC
UPDATED
SCLK
DIN
D15 D14 D13 D12 D11 D10 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
MSB
LSB
Figure 3a. MAX541/MAX542 3-Wire Interface Timing Diagram (LDAC = DGND for MAX542)
CS
SCLK
DIN
D15 D14 D13 D12 D11 D10 D9 D8
MSB
D7 D6 D5 D4 D3 D2 D1 D0
LSB
LDAC
DAC
UPDATED
Figure 3b. MAX542 4-Wire Interface Timing Diagram
8
_______________________________________________________________________________________
+5V, Serial-Input, Voltage-Output, 16-Bit DACs
Reference and Analog Ground Inputs
The MAX541/MAX542 operate with external voltage references from 2V to 3V, and maintain 16-bit performance
if certain guidelines are followed when selecting and
applying the reference. Ideally, the reference’s
temperature coefficient should be less than
0.4ppm/°C to maintain 16-bit accuracy to within 1LSB
over the 0°C to +70°C commercial temperature range.
Since this converter is designed as an inverted R-2R
voltage-mode DAC, the input resistance seen by the voltage reference is code-dependent. The worst-case inputresistance variation is from 11.5kΩ (at code 8555 hex) to
200kΩ (at code 0000 hex). The maximum change in load
current for a 2.5V reference is 2.5V / 11.5k Ω = 217µA;
therefore, the required load regulation is 7ppm/mA for a
maximum error of 0.1LSB. This implies a reference
output impedance of less than 18mΩ. In addition, the
impedance of the signal path from the voltage
reference to the reference input must be kept low
because it contributes directly to the load-regulation
error.
The requirement for a low-impedance voltage reference
is met with capacitor bypassing at the reference inputs
and ground. A 0.1µF ceramic capacitor with short leads
between REFF and AGNDF (MAX542), or REF and
AGND (MAX541), provides high-frequency bypassing.
A surface-mount ceramic chip capacitor is preferred
because it has the lowest inductance. An additional
10µF between REFF and AGNDF (MAX542), or REF
and AGND (MAX541), provides low-frequency bypassing. A low-ESR tantalum, film, or organic semiconductor
capacitor works well. Leaded capacitors are acceptable because impedance is not as critical at lower frequencies. The circuit can benefit from even larger
bypassing capacitors, depending on the stability of the
external reference with capacitive loading. If separate
force and sense lines are not used, tie the appropriate
force and sense pins together close to the package.
AGND must also be low impedance, as load-regulation
errors will be introduced by excessive AGND resistance. As in all high-resolution, high-accuracy applications, separate analog and digital ground planes yield
the best results. Tie DGND to AGND at the AGND pin to
form the “star” ground for the DAC system. Always refer
remote DAC loads to this system ground for the best
possible performance.
Unbuffered Operation
Unbuffered operation reduces power consumption as
well as offset error contributed by the external output
buffer. The R-2R DAC output is available directly at
OUT, allowing 16-bit performance from +VREF to AGND
without degradation at zero scale. The DAC’s output
impedance is also low enough to drive medium loads
(RL > 60kΩ) without degradation of INL or DNL; only
the gain error is increased by externally loading the
DAC output.
External Output Buffer Amplifier
The requirements on the external output buffer amplifier
change whether the DAC is used in the unipolar or
bipolar mode of operation. In unipolar mode, the output
amplifier is used in a voltage-follower connection. In
bipolar mode (MAX542 only), the amplifier operates
with the internal scaling resistors (Figure 2b). In each
mode, the DAC’s output resistance is constant and is
independent of input code; however, the output amplifier’s input impedance should still be as high as possible
to minimize gain errors. The DAC’s output capacitance
is also independent of input code, thus simplifying stability requirements on the external amplifier.
In bipolar mode, a precision amplifier operating with
dual power supplies (such as the MAX400) provides
the ±VREF output range. In single-supply applications,
precision amplifiers with input common-mode ranges
including AGND are available; however, their output
swings do not normally include the negative rail
(AGND) without significant degradation of performance.
A single-supply op amp, such as the MAX495, is suitable if the application does not use codes near zero.
Since the LSBs for a 16-bit DAC are extremely small
(38.15µV for VREF = 2.5V), pay close attention to the
external amplifier’s input specification. The input offset
voltage can degrade the zero-scale error and might
require an output offset trim to maintain full accuracy if
the offset voltage is greater than 1/2LSB. Similarly, the
input bias current multiplied by the DAC output resistance (typically 6.25kΩ) contributes to the zero-scale
error. Temperature effects also must be taken into consideration. Over the 0°C to +70°C commercial temperature range, the offset voltage temperature coefficient
(referenced to +25°C) must be less than 0.42µV/°C to
add less than 1/2LSB of zero-scale error. The external
amplifier’s input resistance forms a resistive divider with
the DAC output resistance, which results in a gain error.
_______________________________________________________________________________________
9
MAX541/MAX542
Applications Information
MAX541/MAX542
+5V, Serial-Input, Voltage-Output, 16-Bit DACs
To contribute less than 1/2LSB of gain error, the input
resistance typically must be greater than:
1 1 
6.25kΩ ÷ 
 = 819MΩ
2  216 
The settling time is affected by the buffer input capacitance, the DAC’s output capacitance, and PC board
capacitance. The typical DAC output voltage settling
time is 1µs for a full-scale step. Settling time can be
significantly less for smaller step changes. Assuming a
single time-constant exponential settling response, a
full-scale step takes 12 time constants to settle to within
1/2LSB of the final output voltage. The time constant is
equal to the DAC output resistance multiplied by the
total output capacitance. The DAC output capacitance
is typically 10pF. Any additional output capacitance will
increase the settling time.
The external buffer amplifier’s gain-bandwidth product
is important because it increases the settling time by
adding another time constant to the output response.
The effective time constant of two cascaded systems,
each with a single time-constant response, is approximately the root square sum of the two time constants.
The DAC output’s time constant is 1µs / 12 = 83ns,
ignoring the effect of additional capacitance. If the time
constant of an external amplifier with 1MHz bandwidth
is 1 / 2π (1MHz) = 159ns, then the effective time constant of the combined system is:
2
2

 83ns + 159ns  = 180ns


(
) (
)
Unipolar Configuration
Figure 2a shows the MAX541/MAX542 configured for
unipolar operation with an external op amp. The op amp
is set for unity gain, and Table 1 lists the codes for this
circuit.
Bipolar Configuration
Figure 2b shows the MAX542 configured for bipolar
operation with an external op amp. The op amp is set
for unity gain with an offset of -1/2VREF. Table 2 lists the
offset binary codes for this circuit.
Power-Supply Bypassing and
Ground Management
For optimum system performance, use PC boards with
separate analog and digital ground planes. Wire-wrap
boards are not recommended. Connect the two ground
planes together at the low-impedance power-supply
source. Connect DGND and AGND together at the IC.
The best ground connection can be achieved by connecting the DAC’s DGND and AGND pins together and
connecting that point to the system analog ground
plane. If the DAC’s DGND is connected to the system
digital ground, digital noise may get through to the
DAC’s analog portion.
Bypass VDD with a 0.1µF ceramic capacitor connected
between V DD and AGND. Mount it with short leads
close to the device. Ferrite beads can also be used to
further isolate the analog and digital power supplies.
Table 1. Unipolar Code Table
DAC LATCH CONTENTS
This suggests that the settling time to within 1/2LSB of
the final output voltage, including the external buffer
amplifier, will be approximately 12 · 180ns = 2.15µs.
Digital Inputs and Interface Logic
The digital interface for the 16-bit DAC is based on a
3-wire standard that is compatible with SPI, QSPI, and
MICROWIRE interfaces. The three digital inputs (CS,
DIN, and SCLK) load the digital input data serially into
the DAC. LDAC (MAX542) updates the DAC output
asynchronously.
All of the digital inputs include Schmitt-trigger buffers to
accept slow-transition interfaces. This means that optocouplers can interface directly to the MAX541/MAX542
without additional external logic. The digital inputs are
compatible with TTL/CMOS-logic levels.
10
MSB
ANALOG OUTPUT, VOUT
LSB
1111 1111 1111 1111
VREF · (65,535 / 65,536)
1000 0000 0000 0000
VREF · (32,768 / 65,536) = 1/2VREF
0000 0000 0000 0001
VREF · (1 / 65,536)
0000 0000 0000 0000
0V
Table 2. Bipolar Code Table
DAC LATCH CONTENTS
MSB
ANALOG OUTPUT, VOUT
LSB
1111 1111 1111 1111
+VREF · (32,767 / 32,768)
1000 0000 0000 0001
+VREF · (1 / 32,768)
1000 0000 0000 0000
0V
0111 1111 1111 1111
-VREF · (1 / 32,768)
0000 0000 0000 0000
-VREF · (32,768 / 32,768) = -VREF
______________________________________________________________________________________
+5V, Serial-Input, Voltage-Output, 16-Bit DACs
Functional Diagrams (continued)
INL
(LSB)
PART
TEMP. RANGE
PIN-PACKAGE
MAX541AEPA
-40°C to +85°C
8 Plastic DIP
±1
MAX541BEPA
-40°C to +85°C
8 Plastic DIP
±2
MAX541CEPA
-40°C to +85°C
8 Plastic DIP
±4
MAX541AESA
-40°C to +85°C
8 SO
±1
MAX541BESA
-40°C to +85°C
8 SO
±2
MAX541CESA
-40°C to +85°C
8 SO
±4
MAX542ACPD
0°C to +70°C
14 Plastic DIP
±1
MAX542BCPD
0°C to +70°C
14 Plastic DIP
±2
MAX542CCPD
0°C to +70°C
14 Plastic DIP
±4
MAX542ACSD
0°C to +70°C
14 SO
±1
MAX542BCSD
0°C to +70°C
14 SO
±2
MAX542CCSD
0°C to +70°C
14 SO
±4
MAX542BC/D
0°C to +70°C
Dice*
±2
MAX542AEPD
-40°C to +85°C
14 Plastic DIP
±1
MAX542BEPD
-40°C to +85°C
14 Plastic DIP
±2
MAX542CEPD
-40°C to +85°C
14 Plastic DIP
±4
MAX542AESD
-40°C to +85°C
14 SO
±1
MAX542BESD
-40°C to +85°C
14 SO
±2
MAX542CESD
-40°C to +85°C
14 SO
±4
MAX542CMJD
-55°C to +125°C
14 Ceramic SB**
±4
VDD
MAX541
REF
16-BIT DAC
CS
DIN
SCLK
16-BIT DATA LATCH
OUT
AGND
CONTROL
LOGIC
SERIAL INPUT REGISTER
DGND
_____________________Chip Information
TRANSISTOR COUNT: 2209
SUBSTRATE CONNECTED TO DGND
*Dice are tested at TA = +25°C, DC parameters only.
**Contact factory for availability.
______________________________________________________________________________________
11
MAX541/MAX542
Ordering Information (continued)
SOICN.EPS
________________________________________________________Package Information
PDIPN.EPS
MAX541/MAX542
+5V, Serial-Input, Voltage-Output, 16-Bit DACs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 1999 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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