TI1 LM3208TL/NOPB 650ma miniature, adjustable, step-down dc-dc converter Datasheet

LM3208
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SNVS404B – APRIL 2006 – REVISED MARCH 2013
LM3208 650mA Miniature, Adjustable, Step-Down DC-DC Converter for RF Power
Amplifiers
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FEATURES
DESCRIPTION
•
•
The LM3208 is a DC-DC converter optimized for
powering RF power amplifiers (PAs) from a single
Lithium-Ion cell. However, it may be used in many
other applications. It steps down an input voltage in
the range from 2.7V to 5.5V to an adjustable output
voltage of 0.8V to 3.6V. Output voltage is set by
using a VCON analog input to control power levels and
efficiency of the RF PA.
1
2
•
•
•
•
•
•
•
2 MHz (typ.) PWM Switching Frequency
Operates from a Single Li-Ion Cell (2.7V to
5.5V)
Adjustable Output Voltage (0.8V to 3.6V)
Fast Output Voltage Transient (0.8V to 3.4V in
25µs typ.)
650mA Maximum Load Capability
High Efficiency (95% typ. at 3.9VIN, 3.4VOUT at
400mA)
8-pin DSBGA Package
Current Overload Protection
Thermal Overload Protection
The LM3208 offers superior performance for mobile
phones and similar RF PA applications. Fixedfrequency PWM operation minimizes RF interference.
A shutdown function turns the device off and reduces
battery consumption to 0.01 µA (typ.).
The LM3208 is available in an 8-pin lead-free DSBGA
package. A high switching frequency (2 MHz typ.)
allows use of tiny surface-mount components. Only
three small external surface-mount components, an
inductor and two ceramic capacitors, are required.
APPLICATIONS
•
•
•
•
Cellular Phones
Hand-Held Radios
RF PC Cards
Battery Powered RF Devices
TYPICAL APPLICATION
VIN
2.7V to 5.5V
PVIN
3.3 PH
0.8V to 3.6V
SW
EN
10 PF
VOUT
VDD
VOUT = 2.5 x VCON
LM3208
FB
4.7 PF
VCON
PGND
SGND
Figure 1. LM3208 Typical Application
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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LM3208
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CONNECTION DIAGRAMS
SW
SW
A2
A2
PVIN A1
A3 PGND
PGND A3
A1 PVIN
VDD B1
B3 SGND
SGND B3
B1 VDD
C3 FB
EN C1
C1 EN
FB C3
C2
C2
VCON
VCON
Top View
Bottom View
Figure 2. 8-Bump Thin DSBGA Package, Large Bump
Package Number YZR0008GNA
PIN DESCRIPTIONS
Pin #
Name
A1
PVIN
Power Supply Voltage Input to the internal PFET switch.
Description
B1
VDD
Analog Supply Input.
C1
EN
Enable Input. Set this digital input high for normal operation. For shutdown, set this pin low.
C2
VCON
C3
FB
B3
SGND
Analog and Control Ground
A3
PGND
Power Ground
A2
SW
Voltage Control Analog input. VCON controls VOUT in PWM mode.
Feedback Analog Input. Connect to the output at the output filter capacitor.
Switch node connection to the internal PFET switch and NFET synchronous rectifier.
Connect to an inductor with a saturation current rating that exceeds the maximum Switch Peak Current Limit
specification of the LM3208.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
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ABSOLUTE MAXIMUM RATINGS
(1) (2) (3)
−0.2V to +6.0V
VDD, PVIN to SGND
−0.2V to +0.2V
PGND to SGND
(SGND − 0.2V) to (VDD + 0.2V) w/6.0V max
EN, FB, VCON
(PGND − 0.2V) to (PVIN + 0.2V) w/6.0V max
SW
−0.2V to +0.2V
PVIN to VDD
Continuous Power Dissipation (4)
Internally Limited
Junction Temperature (TJ-MAX)
+150°C
−65°C to +150°C
Storage Temperature Range
Maximum Lead Temperature (Soldering, 10 sec)
ESD Rating (5) (6)
+260°C
Human Body Model
2kV
Machine Model
(1)
(2)
(3)
(4)
(5)
(6)
200V
Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under
which operation of the device is ensured. Operating Ratings do not imply specified performance limits. For specified performance limits
and associated test conditions, see the Electrical Characteristics tables.
All voltages are with respect to the potential at the GND pins. The LM3208 is designed for mobile phone applications where turn-on after
power-up is controlled by the system controller and where requirements for a small package size overrule increased die size for internal
Under Voltage Lock-Out (UVLO) circuitry. Thus, it should be kept in shutdown by holding the EN pin low until the input voltage exceeds
2.7V.
If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 150°C (typ.) and
disengages at TJ = 125°C (typ.).
The Human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin. (MIL-STD-883 3015.7) The machine
model is a 200pF capacitor discharged directly into each pin.
TI recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper ESD handling procedures
can result in damage.
OPERATING RATINGS (1) (2)
Input Voltage Range
2.7V to 5.5V
Recommended Load Current
0mA to 650mA
−30°C to +125°C
Junction Temperature (TJ) Range
Ambient Temperature (TA) Range (3)
(1)
(2)
(3)
−30°C to +85°C
Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under
which operation of the device is ensured. Operating Ratings do not imply specified performance limits. For specified performance limits
and associated test conditions, see the Electrical Characteristics tables.
All voltages are with respect to the potential at the GND pins. The LM3208 is designed for mobile phone applications where turn-on after
power-up is controlled by the system controller and where requirements for a small package size overrule increased die size for internal
Under Voltage Lock-Out (UVLO) circuitry. Thus, it should be kept in shutdown by holding the EN pin low until the input voltage exceeds
2.7V.
In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be de-rated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP =
125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the
part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX).
THERMAL PROPERTIES
Junction-to-Ambient Thermal Resistance (θJA), YZR08 Package (1)
(1)
100°C/W
Junction-to-ambient thermal resistance (θJA) is taken from thermal measurements, performed under the conditions and guidelines set
forth in the JEDEC standard JESD51-7. A 4 layer, 4" x 4", 2/1/1/2 oz. Cu board as per JEDEC standards is used for the measurements.
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ELECTRICAL CHARACTERISTICS (1) (2) (3)
Limits in standard typeface are for TA = TJ = 25°C. Limits in boldface type apply over the full operating ambient temperature
range (−30°C ≤ TA = TJ ≤ +85°C). Unless otherwise noted, all specifications apply to the LM3208 with: PVIN = VDD = EN =
3.6V.
Symbol
Parameter
Conditions
VFB,
MIN
Feedback Voltage at minimum
setting
VCON = 0.32V (3)
VFB,
MAX
Feedback Voltage at maximum
setting
VCON = 1.44V, VIN = 4.2V (3)
Min
Typ
Max
Units
0.75
0.80
0.85
V
3.537
3.600
3.683
V
(4)
ISHDN
Shutdown supply current
EN = SW = VCON = 0V,
0.01
2
µA
IQ
DC bias current into VDD
VCON = 0V, FB = 0V,
No Switching (5)
0.6
0.7
mA
RDSON(P)
Pin-pin resistance for Large PFET
ISW = 200mA, VCON = 0.5V
140
180
210
mΩ
RDSON(P)
Pin-pin resistance for Small PFET
ISW = 200mA, VCON = 0.32V
960
RDSON(N)
Pin-pin resistance for NFET
ISW = –200mA, VCON = 0.5V
ILIM
(L_PFET)
Large PFET (L) Switch peak current
limit
VCON = 0.5V (6)
ILIM
(S_PFET)
Small PFET (S) Switch peak current
limit
VCON = 0.32V (6)
FOSC
mΩ
300
375
450
mΩ
985
1100
1200
mA
650
800
900
mA
Internal oscillator frequency
1.8
2.0
2.2
MHz
VIH,EN
Logic high input threshold
1.2
VIL,EN
Logic low input threshold
IPIN,EN
EN pin pull down current
VCON,ON
VCON Threshold for turning on
switches
ICON
VCON pin leakage current
VCON = 1.0V
Gain
VCON to VOUT Gain
0.32V ≤ VCON ≤ 1.44V
(1)
(2)
(3)
(4)
(5)
(6)
4
V
5
0.5
V
10
µA
0.15
V
±1
2.5
µA
V/V
All voltages are with respect to the potential at the GND pins. The LM3208 is designed for mobile phone applications where turn-on after
power-up is controlled by the system controller and where requirements for a small package size overrule increased die size for internal
Under Voltage Lock-Out (UVLO) circuitry. Thus, it should be kept in shutdown by holding the EN pin low until the input voltage exceeds
2.7V.
Min and Max limits are specified by design, test, or statistical analysis. Typical numbers are not specified, but do represent the most
likely norm. Due to the pulsed nature of the testing TA = TJ for the electrical characteristics table.
The parameters in the electrical characteristics table are tested under open loop conditions at PVIN = VDD = 3.6V unless otherwise
specified. For performance over the input voltage range and closed-loop results, refer to the datasheet curves.
Shutdown current includes leakage current of PFET.
IQ specified here is when the part is not switching. For operating quiescent current at no load, refer to datasheet curves.
Current limit is built-in, fixed, and not adjustable. Electrical Characteristic table reflects open loop data (FB = 0V and current drawn from
SW pin ramped up until cycle by cycle limit is activated). Refer to SYSTEM CHARACTERISTICS table for maximum output current.
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SYSTEM CHARACTERISTICS
The following spec table entries are specified by design providing the component values in the typical application circuit are
used (L = 3.0µH, DCR = 0.12Ω, FDK MIPW3226D3R0M; CIN = 10µF, 6.3V, 0805, TDK C2012X5R0J106K; COUT = 4.7µF,
6.3V, 0603, TDK C1608X5R0J475M). These parameters are not specified by production testing. Min and Max values are
specified over the ambient temperature range TA = −30°C to 85°C. Typical values are specified at PVIN = VDD = EN = 3.6V
and TA = 25°C unless otherwise specified.
Symbol
TRESPONSE
Parameter
Conditions
Min
Typ
Max
Unit
Time for VOUT to rise from 0.8V
to 3.4V (to reach 3.35V)
VIN = 4.2V, RLOAD = 5.5Ω
25
40
µs
Time for VOUT to fall from 3.4V
to 0.8V
VIN = 4.2V, RLOAD = 15Ω
35
45
µs
CCON
VCON input capacitance
VCON = 1V, VIN = 2.7V to 5.5V,
Test frequency = 100kHz
5
10
pF
CEN
EN input capacitance
EN = 2V, VIN = 2.7V to 5.5V,
Test frequency = 100kHz
5
10
pF
VCON
(S>L)
RDSON(P) management threshold Threshold for PFET RDSON(P) to change
from 960mΩ to 140mΩ
0.39
0.42
0.45
V
VCON
(L>S)
RDSON(P) management threshold Threshold for PFET RDSON(P) to change
from 140mΩ to 960mΩ
0.37
0.40
0.43
V
IOUT, MAX
Maximum Output Current
VIN = 2.7V to 5.5V,
VCON = 0.45V to 1.44V,
L = MIPW3226D3R0
650
mA
VIN = 2.7V to 5.5V,
VCON = 0.32V to 0.45V,
L = MIPW3226D3R0
400
mA
–3
+3
%
−50
+50
mV
60
µs
Linearity
Linearity in control range 0.32V
to 1.44V
VIN = 3.9V (1)
Monotonic in nature
TON
Turn on time
(time for output to reach 97% of
final value after Enable low to
high transition)
EN = Low to High, VIN = 4.2V,
VOUT = 3.4V,
IOUT ≤ 1mA
40
Efficiency
VIN = 3.6V, VOUT = 0.8V, IOUT = 90mA
81
%
VIN = 3.6V, VOUT = 1.5V, IOUT = 150mA
89
%
η
VOUT_ripple
Line_tr
VIN = 3.9V, VOUT = 3.4V, IOUT = 400mA
95
%
Ripple voltage at
no pulse skip condition
VIN = 2.7V to 4.5V, VOUT = 0.8V to 3.4V,
Differential voltage = VIN – VOUT > 1V,
IOUT = 0mA to 400mA (2)
10
mVp-p
Ripple voltage at
pulse skip condition
VIN = 5.5V to dropout, VOUT = 3.4V,
IOUT = 650mA (2)
60
mVp-p
Line transient response
VIN = 3.6V to 4.2V,
TR = TF = 10µs,
VOUT = 0.8V, IOUT = 100mA
50
mVpk
VIN = 3.1 / 3.6 / 4.5V, VOUT = 0.8V,
IOUT = 50mA to 150mA
50
mVpk
Load_tr
Load transient response
Max Duty
cycle
Maximum duty cycle
(1)
(2)
100
%
Linearity limits are ±3% or ±50mV whichever is larger.
Ripple voltage should be measured at COUT electrode on a well-designed PC board and using the suggested inductor and capacitors.
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TYPICAL PERFORMANCE CHARACTERISTICS
Quiescent Current
vs
Supply Voltage
(VCON = 0V, FB = 0V, No Switching)
Shutdown Current
vs
Temperature
(VCON = 0V, EN = 0V)
Figure 3.
Figure 4.
Switching Frequency
vs
Temperature
(VOUT = 1.3V, IOUT = 200mA)
Output Voltage
vs
Supply Voltage
(VOUT = 1.3V)
3
1.312
VIN = 5.5V
IOUT = 50 mA
2
1.310
OUTPUT VOLTAGE (V)
SWITCHING FREQUENCY VARIATION (%)
(Circuit in Figure 35, PVIN = VDD = EN = 3.6V and TA = 25°C unless otherwise specified.).
VIN = 3.6V
1
VIN = 4.2V
0
-1
-2
1.308
IOUT = 300 mA
1.306
1.304
IOUT = 650 mA
1.302
VIN = 2.7V
-3
-40
-20
0
20
40
60
80
100
1.300
2.5
3.0
Figure 5.
4.5
5.0
5.5
6.0
Figure 6.
Output Voltage
vs
Temperature
= 3.6V, VOUT = 0.8V)
(VIN
Figure 7.
6
4.0
SUPPLY VOLTAGE (V)
AMBIENT TEMPERATURE (ºC)
(VIN
3.5
Output Voltage
vs
Temperature
= 4.2V, VOUT = 3.4V)
Figure 8.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
(Circuit in Figure 35, PVIN = VDD = EN = 3.6V and TA = 25°C unless otherwise specified.).
4.0
Current Limit
vs
Temperature
(Large PFET)
Current Limit
vs
Temperature
(Small PFET)
Figure 9.
Figure 10.
VCON Voltage
vs
Output Voltage
(RLOAD = 10 Ω)
VCON Voltage
vs
Output Voltage
(RLOAD = 10 Ω)
1.0
VIN = 4.7V
TA = -30ºC, 25ºC, 85ºC
VIN = 3.6V, 4.2V, 4.7V, 5.5V
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
3.5
3.0
2.5
2.0
1.5
1.0
0.8
VIN = 5.5V
0.6
VIN = 4.2V
0.4
VIN = 3.6V
0.2
0.5
0.0
0.0
0.0
0.4
0.8
1.2
1.6
100
0.0
0.1
0.2
0.3
0.4
VCON VOLTAGE (V)
VCON VOLTAGE (V)
Figure 11.
Figure 12.
Efficiency
vs
Output Voltage
(VIN = 3.9V)
EN High Threshold
vs
Supply Voltage
RLOAD = 10:
EFFICIENCY (%)
96
92
88
RLOAD = 5:
84
80
RLOAD = 15:
76
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
0
OUTPUT VOLTAGE (V)
Figure 13.
Figure 14.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
(Circuit in Figure 35, PVIN = VDD = EN = 3.6V and TA = 25°C unless otherwise specified.).
Efficiency
vs
Output Current
(VOUT = 0.8V)
Efficiency
vs
Output Current
(VOUT = 3.6V)
100
VIN = 3.9V
98
EFFICIENCY (%)
96
94
92
90
VIN = 4.5V
88
86
VIN = 5.5V
84
82
80
0
0
100
200
300
400
500
600
700
OUTPUT CURRENT (mA)
Figure 15.
Figure 16.
Efficiency
vs
Output Current
(RDSON Management)
Efficiency
vs
Output Current
(RDSON Management, VIN=4.5V)
90
90
VIN = 5.5V
VOUT = 1.0V
85
85
80
EFFICIENCY (%)
EFFICIENCY (%)
80
VIN = 3.6V
75
70
VIN = 2.7V
65
VOUT = 1.05V
60
50
10
100
V IN = 4.5V, V OUT = 1.05V
65
60
V IN = 4.5V, V OUT = 1.0V
55
When VOUT = 1.0V (typical), Small
PFET (960 m:). When VOUT = 1.05V
(typical), Large PFET (140 m:).
45
40
1000
OUTPUT CURRENT (mA)
10
100
1000
OUTPUT CURRENT (mA)
Dark curves are efficiency profiles of either large PFET
or small PFET whichever is higher.
Figure 17.
8
70
50
When VOUT = 1.0V (typical), Small
PFET (960 m:). When VOUT = 1.05V
(typical), Large PFET (140 m:).
55
75
Figure 18.
RDSON
vs
Temperature
(Large PFET, ISW = 200mA)
RDSON vs Temperature
(Small PFET, ISW = 200mA)
Figure 19.
Figure 20.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
(Circuit in Figure 35, PVIN = VDD = EN = 3.6V and TA = 25°C unless otherwise specified.).
RDSON
vs
Temperature
(N-ch, ISW = –200mA)
VIN-VOUT
vs
Output Current
(100% Duty Cycle)
Figure 21.
Figure 22.
Load Transient Response
(VOUT = 0.8V)
Load Transient Response
(VIN = 4.2V, VOUT = 3.4V)
50 mV/DIV
AC Coupled
VOUT
100 mV/DIV
AC Coupled
VOUT
VIN = 3.6V
VIN = 4.2V
VOUT = 0.8V
VOUT = 3.4V
IL
200 mA/DIV
IL
200 mA/DIV
400 mA
250 mA
IOUT
IOUT
100 mA
50 mA
10 Ps/DIV
10 Ps/DIV
Figure 23.
Figure 24.
Startup
(VIN = 3.6V, VOUT = 1.3V, RLOAD = 1kΩ)
Startup
(VIN = 4.2V, VOUT = 3.4V, RLOAD = 5kΩ)
Figure 25.
Figure 26.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
(Circuit in Figure 35, PVIN = VDD = EN = 3.6V and TA = 25°C unless otherwise specified.).
Shutdown Response
(VIN = 4.2V, VOUT = 3.4V, RLOAD = 10Ω)
Line Transient Reponse
(VIN = 3.0V to 3.6V, IOUT = 100mA)
Figure 27.
Figure 28.
VCON Transient Response
(VIN = 4.2V, VCON = 0.32V/1.44V, RLOAD = 10Ω)
Timed Current Limit Response
(VIN = 3.6V)
Figure 29.
Figure 30.
Output Voltage Ripple
(VOUT = 1.3V)
Figure 31.
10
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
(Circuit in Figure 35, PVIN = VDD = EN = 3.6V and TA = 25°C unless otherwise specified.).
Output Voltage Ripple
(VOUT = 3.4V)
Output Voltage Ripple in Pulse Skip
(VIN = 3.96V, VOUT = 3.4V, RLOAD = 5Ω)
Figure 32.
Figure 33.
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BLOCK DIAGRAM
VDD
PVIN
SMALL LARGE
PFET PFET
VCON
DELAY
LOGIC
ERROR
AMPLIFIER
FB
CURRENT
COMP
OSCILLATOR
FET SIZE
CONTROL
COMP
EN
SW
MOSFET
CONTROL
LOGIC
MAIN CONTROL
SHUTDOWN
CONTROL
PGND
GND
Figure 34. Functional Block Diagram
OPERATION DESCRIPTION
The LM3208 is a simple, step-down DC-DC converter optimized for powering RF power amplifiers (PAs) in
mobile phones, portable communicators, and similar battery powered RF devices. It is designed to allow the RF
PA to operate at maximum efficiency over a wide range of power levels from a single Li-Ion battery cell. It is
based on a current-mode buck architecture, with synchronous rectification for high efficiency. It is designed for a
maximum load capability of 650mA when VOUT > 1.05V (typ.) and 400mA when VOUT < 1.00V (typ.) in PWM
mode.
Maximum load range may vary from this depending on input voltage, output voltage and the inductor chosen.
Efficiency is typically around 95% for a 400mA load with 3.4V output, 3.9V input. The LM3208 has an RDSON
management scheme to increase efficiency when VOUT ≤ 1V. The output voltage is dynamically programmable
from 0.8V to 3.6V by adjusting the voltage on the control pin without the need for external feedback resistors.
This prolongs battery life by changing the PA supply voltage dynamically depending on its transmitting power.
Additional features include current overload protection and thermal overload shutdown.
The LM3208 is constructed using a chip-scale 8-pin DSBGA package. This package offers the smallest possible
size, for space-critical applications such as cell phones, where board area is an important design consideration.
Use of a high switching frequency (2MHz, typ.) reduces the size of external components. As shown in Figure 1,
only three external power components are required for implementation. Use of a DSBGA package requires
special design considerations for implementation. (See DSBGA Package Assembly and Use in the Application
Information section.) Its fine bump-pitch requires careful board design and precision assembly equipment. Use of
this package is best suited for opaque-case applications, where its edges are not subject to high-intensity
ambient red or infrared light. In addition, the system controller should set EN low during power-up and other low
supply voltage conditions. (See Shutdown Mode in the Device Information section.)
12
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VIN
2.7V to 5.5V
C1*
10 PF
PVIN
VDD
L1
3.3 PH
VOUT
0.8V to 3.6V
SW
SYSTEM
DAC
CONTROLLER
ON/OFF
VCON
LM3208
FB
C2
4.7 PF
EN
SGND
PGND
* Place C1 close to PVIN
Figure 35. Typical Operating System Circuit
Circuit Operation
Referring to Figure 1 and Figure 34, the LM3208 operates as follows. During the first part of each switching
cycle, the control block in the LM3208 turns on the internal PFET (P-channel MOSFET) switch. This allows
current to flow from the input through the inductor to the output filter capacitor and load. The inductor limits the
current to a ramp with a slope of around (VIN – VOUT) / L, by storing energy in a magnetic field. During the second
part of each cycle, the controller turns the PFET switch off, blocking current flow from the input, and then turns
the NFET (N-channel MOSFET) synchronous rectifier on. In response, the inductor’s magnetic field collapses,
generating a voltage that forces current from ground through the synchronous rectifier to the output filter
capacitor and load. As the stored energy is transferred back into the circuit and depleted, the inductor current
ramps down with a slope around VOUT / L. The output filter capacitor stores charge when the inductor current is
high, and releases it when low, smoothing the voltage across the load.
The output voltage is regulated by modulating the PFET switch on time to control the average current sent to the
load. The effect is identical to sending a duty-cycle modulated rectangular wave formed by the switch and
synchronous rectifier at SW to a low-pass filter formed by the inductor and output filter capacitor. The output
voltage is equal to the average voltage at the SW pin.
While in operation, the output voltage is regulated by switching at a constant frequency and then modulating the
energy per cycle to control power to the load. Energy per cycle is set by modulating the PFET switch on-time
pulse width to control the peak inductor current. This is done by comparing the signal from the current-sense
amplifier with a slope compensated error signal from the voltage-feedback error amplifier. At the beginning of
each cycle, the clock turns on the PFET switch, causing the inductor current to ramp up. When the current sense
signal ramps past the error amplifier signal, the PWM comparator turns off the PFET switch and turns on the
NFET synchronous rectifier, ending the first part of the cycle. If an increase in load pulls the output down, the
error amplifier output increases, which allows the inductor current to ramp higher before the comparator turns off
the PFET. This increases the average current sent to the output and adjusts for the increase in the load.
Before appearing at the PWM comparator, a slope compensation ramp from the oscillator is subtracted from the
error signal for stability of the current feedback loop. The minimum on time of PFET is 55ns (typ.)
Shutdown Mode
Setting the EN digital pin low (<0.5V) places the LM3208 in shutdown mode (0.01µA typ.). During shutdown, the
PFET switch, NFET synchronous rectifier, reference voltage source, control and bias circuitry of the LM3208 are
turned off. Setting EN high (>1.2V) enables normal operation.
EN should be set low to turn off the LM3208 during power-up and under voltage conditions when the power
supply is less than the 2.7V minimum operating voltage. The LM3208 is designed for compact portable
applications, such as mobile phones. In such applications, the system controller determines power supply
sequencing and requirements for small package size outweigh the additional size required for inclusion of UVLO
(Under Voltage Lock-Out) circuitry.
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Internal Synchronous Rectification
While in PWM mode, the LM3208 uses an internal NFET as a synchronous rectifier to reduce rectifier forward
voltage drop and associated power loss. Synchronous rectification provides a significant improvement in
efficiency whenever the output voltage is relatively low compared to the voltage drop across an ordinary rectifier
diode.
The internal NFET synchronous rectifier is turned on during the inductor current down slope in the second part of
each cycle. The synchronous rectifier is turned off prior to the next cycle. The NFET is designed to conduct
through its intrinsic body diode during transient intervals before it turns on, eliminating the need for an external
diode.
RDSON(P) Management
The LM3208 has a unique RDSON(P) management function to improve efficiency in the low output current region
up to 100mA. When the VCON voltage is less than 0.40V (typ.), the device uses only a small part of the PFET to
minimize drive loss of the PFET. When VCON is greater than 0.42V (typ.), the entire PFET is used to minimize
RDSON(P) loss. This threshold has about 20mV (typ.) of hysteresis.
VCON,ON
The output is disabled when VCON is below 125mV (typ.). It is enabled when VCON is above 150mV (typ.). The
threshold has about 25mV (typ.) of hysteresis.
Current Limiting
A current limit feature allows the LM3208 to protect itself and external components during overload conditions. In
PWM mode, an 1100mA (typ.) cycle-by-cycle current limit is normally used when VCON is above 0.42V (typ.), and
an 800mA (typ.) is used when VCON is below 0.40V (typ.). If an excessive load pulls the output voltage down to
approximately 0.375V, then the device switches to a timed current limit mode when VCON is above 0.42V (typ.).
In timed current limit mode the internal PFET switch is turned off after the current comparator trips and the
beginning of the next cycle is inhibited for 3.5µs to force the instantaneous inductor current to ramp down to a
safe value. The synchronous rectifier is off in timed current limit mode. Timed current limit prevents the loss of
current control seen in some products when the output voltage is pulled low in serious overload conditions.
Dynamically Adjustable Output Voltage
The LM3208 features dynamically adjustable output voltage to eliminate the need for external feedback resistors.
The output can be set from 0.8V to 3.6V by changing the voltage on the analog VCON pin. This feature is useful in
PA applications where peak power is needed only when the handset is far away from the base station or when
data is being transmitted. In other instances, the transmitting power can be reduced. Hence the supply voltage to
the PA can be reduced, promoting longer battery life. See Setting The Output Voltage in the Application
Information section for further details. The LM3208 moves into Pulse Skipping mode when duty cycle is over
92% and the output voltage ripple increases slightly.
Thermal Overload Protection
The LM3208 has a thermal overload protection function that operates to protect itself from short-term misuse and
overload conditions. When the junction temperature exceeds around 150°C, the device inhibits operation. Both
the PFET and the NFET are turned off in PWM mode. When the temperature drops below 125°C, normal
operation resumes. Prolonged operation in thermal overload conditions may damage the device and is
considered bad practice.
APPLICATION INFORMATION
Setting The Output Voltage
The LM3208 features a pin-controlled variable output voltage to eliminate the need for external feedback
resistors. It can be programmed for an output voltage from 0.8V to 3.6V by setting the voltage on the VCON pin,
as in the following formula:
VOUT = 2.5 x VCON
(1)
When VCON is between 0.32V and 1.44V, the output voltage will follow proportionally by 2.5 times of VCON.
14
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If VCON is over 1.44V (VOUT = 3.6V), sub-harmonic oscillation may occur because of insufficient slope
compensation. If VCON voltage is less than 0.32V (VOUT = 0.8V), the output voltage may not be regulated due to
the required on-time being less than the minimum on-time (55ns). The output voltage can go lower than 0.8V
providing a limited VIN range is used. Refer to datasheet curve (VCON Voltage vs Output Voltage) for details. This
curve is for a typical part and there could be part-to-part variation for output voltages less than 0.8V over the
limited VIN range. When the control pin voltage is more than 0.15V (typ.), the switches are turned on. When it is
less than 0.125V (typ.), the switches are turned off. This on/off function has 25mV (typ.) hysteresis. The
quiescent current when (VCON = 0V and VEN = Hi) is around 600µA.
Estimation of Maximum Output Current Capability
Referring to Figure 35, the Inductor peak to peak ripple current can be estimated by:
IIND_PP = (VIN – VOUT ) × VOUT / (L1 × FSW × VIN)
where
•
Fsw is switching frequency
(2)
Therefore, maximum output current can be calculated by:
IOUT_MAX = ILIM – 0.5 × IIND_PP
(3)
For the worst case calculation, the following parameters should be used:
FSW (Lowest switching frequency): 1.8MHz
ILIM (Lowest current limit value): 985mA
L1 (Lowest inductor value): refer to inductor data-sheet. Note that inductance will drop with DC bias current and
temperature. The worst case is typically at 85°C.
For example, VIN = 4.2V, VOUT = 3.2V, L1 = 2.0µH (Inductance value at 985mA DC bias current and 85°C), FSW =
1.8MHz , ILIM = 985mA.
IIND_PP = 212mA
IOUT_MAX = 985 – 106 = 876mA
(4)
(5)
The effects of switch, inductor resistance and dead time are ignored. In real application, the ripple current would
be 10% to 15% higher than ideal case. This should be taken into account when calculating maximum output
current. Special attention needs to be paid that a delta between maximum output current capability and the
current limit is necessary to satisfy transient response requirements. In practice, transient response requirements
may not be met for output current greater than 650mA.
Inductor Selection
A 3.3µH inductor with saturation current rating over 1200mA and low inductance drop at the full DC bias
condition is recommended for almost all applications. The inductor’s DC resistance should be less than 0.2Ω for
good efficiency. For low dropout voltage, lower DCR inductors are recommended. The lower limit of acceptable
inductance is 1.7µH at 1200mA over the operating temperature range. Full attention should be paid to this limit,
because some small inductors show large inductance drops at high DC bias. These cannot be used with the
LM3208. FDK MIPW3226D3R0M is an example of an inductor with the lowest acceptable limit (as of Oct./05).
Table 1 suggests some inductors and suppliers.
Table 1. Suggested Inductors And Their Suppliers
Model
Size (WxLxH) [mm]
Vendor
MIPW3226D3R0M
3.2 x 2.6 x 1.0
FDK
1098AS-3R3M
3.0 x 2.8 x 1.2
TOKO
NR3015T3R3M
3.0 x 3.0 x 1.5
Taiyo-Yuden
1098AS-2R7M
3.0 x 2.8 x 1.2
TOKO
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If a smaller inductance inductor is used in the application, the LM3208 may become unstable during line and load
transients, and VCON transient response times may be affected.
For low-cost applications, an unshielded bobbin inductor is suggested. For noise-critical applications, a toroidal or
shielded-bobbin inductor should be used. A good practice is to lay out the board with footprints accommodating
both types for design flexibility. This allows substitution of a low-noise toroidal inductor, in the event that noise
from low-cost bobbin models is unacceptable. Saturation occurs when the magnetic flux density from current
through the windings of the inductor exceeds what the inductor’s core material can support with a corresponding
magnetic field. This can cause poor efficiency, regulation errors or stress to a DC-DC converter like the LM3208.
Capacitor Selection
The LM3208 is designed for use with ceramic capacitors for its input and output filters. Use a 10µF ceramic
capacitor for input and a 4.7µF ceramic capacitor for output. They should maintain at least 50% capacitance at
DC bias and temperature conditions. Ceramic capacitor types such as X5R, X7R and B are recommended for
both filters. Table 2 lists some suggested part numbers and suppliers. DC bias characteristics of the capacitors
must be considered when selecting the voltage rating and case size of the capacitor. If it is necessary to choose
a 0603-size capacitor for CIN and COUT, the operation of the LM3208 should be carefully evaluated on the system
board. Use of multiple 2.2µF or 1µF capacitors in parallel may also be considered.
Table 2. Suggested Capacitors And Their Suppliers
Model
Vendor
C2012X5R0J106M,10µF, 6.3V
TDK
C1608X5R0J475M, 4.7µF, 6.3V
TDK
0805ZD475KA 4.7µF, 10V
AVX
The input filter capacitor supplies AC current drawn by the PFET switch of the LM3208 in the first part of each
cycle and reduces the voltage ripple imposed on the input power source. The output filter capacitor absorbs the
AC inductor current, helps maintain a steady output voltage during transient load changes and reduces output
voltage ripple. These capacitors must be selected with sufficient capacitance and sufficiently low ESR
(Equivalent Series Resistance) to perform these functions. The ESR of the filter capacitors is generally a major
factor in voltage ripple.
EN Pin Control
Drive the EN pin using the system controller to turn the LM3208 ON and OFF. Use a comparator, Schmidt trigger
or logic gate to drive the EN pin. Set EN high (>1.2V) for normal operation and low (<0.5V) for a 0.01µA (typ.)
shutdown mode.
Set EN low to turn off the LM3208 during power-up and under voltage conditions when the power supply is less
than the 2.7V minimum operating voltage. The part is out of regulation when the input voltage is less than 2.7V.
The LM3208 is designed for mobile phones where the system controller controls operation mode for maximizing
battery life and requirements for small package size outweigh the additional size required for inclusion of UVLO
(Under Voltage Lock-Out) circuitry.
DSBGA Package Assembly and Use
Use of the DSBGA package requires specialized board layout, precision mounting and careful re-flow
techniques, as detailed in TI Application Note 1112 (SNVA009). Refer to the section Surface Mount Technology
(SMD) Assembly Considerations. For best results in assembly, alignment ordinals on the PC board should be
used to facilitate placement of the device. The pad style used with DSBGA package must be the NSMD (nonsolder mask defined) type. This means that the solder-mask opening is larger than the pad size. This prevents a
lip that otherwise forms if the solder-mask and pad overlap, from holding the device off the surface of the board
and interfering with mounting. See Application Note 1112 (SNVA009) for specific instructions how to do this.
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The 8-Bump package used for LM3208 has 300micron solder balls and requires 10.82mil pads for mounting on
the circuit board. The trace to each pad should enter the pad with a 90°entry angle to prevent debris from being
caught in deep corners. Initially, the trace to each pad should be 7mil wide, for a section approximately 7mil long,
as a thermal relief. Then each trace should neck up or down to its optimal width. The important criterion is
symmetry. This ensures the solder bumps on the LM3208 re-flow evenly and that the device solders level to the
board. In particular, special attention must be paid to the pads for bumps A1 and A3. Because PGND and PVIN
are typically connected to large copper planes, inadequate thermal relief’s can result in late or inadequate re-flow
of these bumps.
The DSBGA package is optimized for the smallest possible size in applications with red or infrared opaque
cases. Because the DSBGA package lacks the plastic encapsulation characteristic of larger devices, it is
vulnerable to light. Backside metallization and/or epoxy coating, along with front-side shading by the printed
circuit board, reduce this sensitivity. However, the package has exposed die edges. In particular, DSBGA
devices are sensitive to light (in the red and infrared range) shining on the package’s exposed die edges.
Board Layout Considerations
VIN
2.7V to 5.5V
Fosc = 2 MHz
i
i
PVIN
+ C1 E
- 10 PF
L1
3.3 PH VOUT
VDD
SW
EN
FB
C2
4.7 PF
VCON
PGND
SGND
+
-
C
Figure 36. Current Loop
The LM3208 converts higher input voltage to lower output voltage with high efficiency. This is achieved with an
inductor-based switching topology. During the first half of the switching cycle, the internal PMOS switch turns on,
the input voltage is applied to the inductor, and the current flows from PVIN line into the output capacitor and the
load through the inductor. During the second half cycle, the PMOS turns off and the internal NMOS turns on. The
inductor current continues to flow via the inductor from the device PGND line into the output capacitor and the
load.
Referring to Figure 36, a pulse current flows in the left hand side loop, and a ripple current flows in the right hand
side loop. Board layout and circuit pattern design of these two loops are the key factors for reducing noise
radiation and stable operation. In other lines, such as from battery to C1 and C2 to the load, the current is mostly
DC current. Therefore, it is not necessary to take so much care. Only pattern width (current capability) and DCR
drop considerations are needed.
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3.0 ÛH
4.7 ÛF
10 ÛF
Figure 37. Evaluation Board Layout
Board Layout Flow
1. Minimize C1, PVIN, and PGND loop. These traces should be as wide and short as possible. This is the
highest priority.
2. Minimize L1, C2, SW and PGND loop. These traces also should be wide and short. This is the second
priority.
3. The above layout patterns should be placed on the component side of the PCB to minimize parasitic
inductance and resistance due to via-holes. It may be a good idea that the SW to L1 path is routed between
C1(+) and C1(–) land patterns. If vias are used in these large current paths, multiple via-holes should be
used if possible.
4. Connect C1(–), C2(–) and PGND with wide GND pattern. This pattern should be short, so C1(–), C2(–), and
PGND should be as close as possible. Then connect to a PCB common GND pattern with as many via-holes
as possible.
5. SGND should not connect directly to PGND. Connecting these pins under the device should be avoided. (If
possible, connect SGND to the common port of C1(–), C2(–) and PGND.)
6. VDD should not be connected directly to PVIN. Connecting these pins under the device should be avoided. It
is good idea to connect VDD to C1(+) to avoid switching noise injection to the VDD line.
7. The FB line should be protected from noise. It is a good idea to use an inner GND layer (if available) as a
shield.
NOTE
The evaluation board shown in Figure 37 for the LM3208 was designed with these
considerations, and it shows good performance. However some aspects have not been
optimized because of limitations due to evaluation-specific requirements. The board can
be used as a reference. Please refer questions to a TI representative.
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REVISION HISTORY
Changes from Revision A (March 2013) to Revision B
•
20
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 18
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
LM3208TL/NOPB
ACTIVE
DSBGA
YZR
8
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-30 to 85
S
33
LM3208TLX/NOPB
ACTIVE
DSBGA
YZR
8
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-30 to 85
S
33
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Mar-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
LM3208TL/NOPB
DSBGA
YZR
8
250
178.0
8.4
LM3208TLX/NOPB
DSBGA
YZR
8
3000
178.0
8.4
Pack Materials-Page 1
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
1.85
2.01
0.76
4.0
8.0
Q1
1.85
2.01
0.76
4.0
8.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Mar-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM3208TL/NOPB
DSBGA
YZR
LM3208TLX/NOPB
DSBGA
YZR
8
250
210.0
185.0
35.0
8
3000
210.0
185.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
YZR0008xxx
D
0.600±0.075
E
TLA08XXX (Rev C)
D: Max = 1.862 mm, Min =1.802 mm
E: Max = 1.712 mm, Min =1.652 mm
4215045/A
NOTES:
A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.
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12/12
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