TI1 ADC081000CIYB/NOPB High performance, low power 8-bit, 1 gsps a/d converter Datasheet

ADC081000
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SNAS209G – FEBRUARY 2004 – REVISED MAY 2013
ADC081000 High Performance, Low Power 8-Bit, 1 GSPS A/D Converter
Check for Samples: ADC081000
FEATURES
DESCRIPTION
•
•
•
•
•
The ADC081000 is a low power, high performance
CMOS analog-to-digital converter that digitizes
signals to 8 bits resolution at sampling rates up to
1.6 GSPS. Consuming a typical 1.4 Watts at 1 GSPS
from a single 1.9 Volt supply, this device is ensured
to have no missing codes over the full operating
temperature range. The unique folding and
interpolating architecture, the fully differential
comparator design, the innovative design of the
internal sample-and-hold amplifier and the selfcalibration scheme enable a very flat response of all
dynamic parameters beyond Nyquist, producing a
high 7.5 ENOB with a 500 MHz input signal and a
1 GHz sample rate while providing a 10-18 B.E.R.
Output formatting is offset binary and the LVDS
digital outputs are compliant with IEEE 1596.3-1996,
with the exception of a reduced common mode
voltage of 0.8V.
1
2
Internal Sample-and-Hold
Single +1.9V ±0.1V Operation
Adjustable Output Levels
Ensured No Missing Codes
Low Power Standby Mode
APPLICATIONS
•
•
•
•
•
Direct RF Down Conversion
Digital Oscilloscopes
Satellite Set-top boxes
Communications Systems
Test Instrumentation
APPLICATIONS
•
•
•
•
•
•
Resolution 8 Bits
Max Conversion Rate 1 GSPS (Min)
ENOB at 500 MHz Input 7.5 Bits (Typ)
DNL ±0.25 LSB (Typ)
Conversion Latency 7 and 8 Clock Cycles
Power Consumption
– Operating 1.45 W (Typ)
– Power Down Mode 9 mW (Typ)
The converter has a 1:2 demultiplexer that feeds two
LVDS buses, reducing the output data rate on each
bus to half the sampling rate. The data on these
buses are interleaved in time to provide a 500 MHz
output rate per bus and a combined output rate of
1 GSPS.
The converter typically consumes less than 10 mW in
the Power Down Mode and is available in a 128-lead
HLQFP and operates over the industrial (–40°C ≤
TA ≤ +85°C) temperature range.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2013, Texas Instruments Incorporated
ADC081000
SNAS209G – FEBRUARY 2004 – REVISED MAY 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Block Diagram
VIN+
VIN-
8-BIT
ADC
1:2
DEMUX
DOUT
DOUTD
Data Bus Output
16 LVDS Pairs
DC_Coup
VCMO
VBG
VREF
OUT-OF-RANGE
INDICATOR
OR
FSR
CLK+
2
CLK/2
CLK-
Output
Clock
Generator
DCLK+
DCLK-
OutV
OutEdge
2
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GND
VCMO
VA
GND
VINVIN+
GND
VA
DC_Coup
GND
VA
VA
CLK+
CLKVA
GND
NC
NC
GND
VA
PD
GND
VA
NC
DR GND
NC
DR GND
Dd6+
Dd6Dd7+
Dd7D0+
D0D1+
D1VDR
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
ADC081000
*
D2+
D2D3+
D3D4+
D4D5+
D5VDR
DR GND
D6+
D6D7+
D7DCLK+
DCLKOROR+
NC
NC
NC
NC
DR GND
VDR
NC
NC
NC
NC
NC
NC
NC
NC
NC
DR GND
NC
DR GND
NC
NC
NC
NC
NC
NC
NC
NC
VDR
NC
DR GND
NC
NC
NC
NC
NC
NC
NC
NC
VDR
VA
NC
FSR
NC
NC
NC
NC
VDR
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
NC
CAL
VBG
REXT
NC
DR GND
Dd2+
Dd2Dd3+
Dd3Dd4+
Dd4Dd5+
Dd5VDR
VA
OUTV
OutEdge
VA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
GND
VA
CalDly
CalRun
Dd0+
Dd0Dd1+
Dd1VDR
PIN CONFIGURATION
* Exposed pad on back of package must be soldered to ground plane to ensure rated performance.
Figure 1. 128-Lead HLQFP
See NNB0128A Package
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Pin Descriptions and Equivalent Circuits
Pin Functions
Pin No.
3
4
Symbol
Equivalent Circuit
Description
Output Voltage Amplitude set. Tie this pin high for normal
differential output amplitude. Ground this pin for a reduced
differential output amplitude and reduced power consumption.
See The LVDS Outputs.
OutV
Output Edge Select. Sets the edge of the DCLK+ (pin 82) at
which the output data transitions. The output transitions with the
DCLK+ rising edge when this pin is high or on the falling edge
when this pin is low. See Output Edge Synchronization.
OutEdge
VA
DC Coupling select. When this pin is high, the VIN+ and VINanalog inputs are d.c. coupled and the input common mode
voltage should equal the VCMO (pin 7) output voltage. When this
pin is low, the analog input pins are internally biased and the input
signal should be a.c. coupled to the analog input pins. See THE
ANALOG INPUT.
14
DC_Coup
26
PD
30
CAL
Calibration. A minimum 10 clock cycles low followed by a
minimum of 10 clock cycles high on this pin will initiate the self
calibration sequence. See Self-Calibration.
35
FSR
Full scale Range Select. With a logic low on this pin, the full-scale
differential input is 600 mVP-P. With a logic high on this pin, the
full-scale differential input is 800 mVP-P. See The Analog Inputs.
127
CalDly
Power Down Pin. A logic high on this pin puts the ADC into the
Power Down mode. A logic low on this pin allows normal
operation.
GND
Calibration Delay. This sets the number of clock cycles after
power up before calibration begins. See Self-Calibration.
VA
18
18
19
CLK+
CLK–
50k
AGND
100
VA
VBIAS
Clock input pins for the ADC. The differential clock signal must be
a.c. coupled to these pins. The input signal is sampled on the
falling edge of CLK+.
50k
19
AGND
VA
11
50k
AGND
11
10
VIN+
VIN-
VCMO
100
Control from DC_Coup
Analog Signal Differential Inputs to the ADC.
VA
50k
10
AGND
4
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Pin Functions
Pin No.
Symbol
Equivalent Circuit
Description
VD
7
12.5k
VCMO
Common Mode Output voltage for VIN+ and VIN- when d.c. input
coupling is used, in which case the voltage at this pin is required
to be the common mode input voltage at VIN+ and VIN−. See THE
ANALOG INPUT.
DGND
31
VBG
126
CalRun
Bandgap output voltage. This pin is capable of sourcing or sinking
up to 1.0 µA.
VD
Calibration Running indication. This pin is at a logic high when
calibration is running.
DGND
VA
32
V
REXT
External Bias Resistor connection. The required value is 3.3kOhms (±0.1%) to ground. See Self-Calibration.
GND
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Pin Functions
6
Pin No.
Symbol
Equivalent Circuit
Description
83
84
85
86
89
90
91
92
93
94
95
96
100
101
102
103
D7D7+
D6D6+
D5D5+
D4D4+
D3D3+
D2D2+
D1D1+
D0D0+
104
105
106
107
111
112
113
114
115
116
117
118
122
123
124
125
Dd7Dd7+
Dd6Dd6+
Dd5Dd5+
Dd4Dd4+
Dd3Dd3+
Dd2Dd2+
Dd1Dd1+
Dd0Dd0+
79
80
OR+
OR-
82
81
DCLK+
DCLK-
2, 5, 8, 13, 16,
17, 20, 25, 28,
33, 128
VA
Analog power supply pins. Bypass these pins to GND.
40, 51, 62, 73,
88, 99, 110, 121
VDR
Output Driver power supply pins. Bypass these pins to DR GND.
1, 6, 9, 12, 15,
21, 24, 27
GND
Ground return for VA
42, 53, 64, 74,
87, 97, 108, 119
DR GND
Ground return for VDR
22, 23, 29, 34,
36–39, 41,
43–50, 52,
54–61, 63,
65–72, 75–78,
98, 109, 120
NC
LVDS data output bits sampled second in time sequence. These
outputs should always be terminated with a differential 100Ω
resistance.
VDR
-
+
+
-
LVDS data output bits sampled first in time sequence. These
outputs should always be terminated with a differential 100Ω
resistance.
DR GND
Out of Range output. A differential high at these pins indicates
that the differential input is out of range (outside the range of
±300 mV or ±400 mV as defined by the FSR pin). See Out Of
Range (OR) Indication.
Differential Clock Outputs used to latch the output data. Delayed
and non-delayed data outputs are supplied synchronous to this
signal.
No Connection. Make no connection to these pins.
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ABSOLUTE MAXIMUM RATINGS (1) (2)
Analog Supply Voltage (VA, VDR)
Digital Supply above Analog Supply
2.2V
(VDR - VA)
300 mV
−0.15V to (VA +0.15V)
Voltage on Any Input Pin (Except VIN+, VIN-)
Voltage on VIN+, VIN- (Maintaining Common Mode)
Ground Difference:
-0.15V to 2.5V
|GND - DR GND|
0V to 100 mV
Input Current at Any Pin (3)
±25 mA
Package Input Current (3)
±50 mA
Power Dissipation at TA = 25°C
2.0 W
ESD Susceptibility (4)
Human Body Model
2500V
Machine Model
Soldering Temperature, Infrared, 10 seconds
250V
(5)
235°C
−65°C to +150°C
Storage Temperature
(1)
(2)
(3)
(4)
(5)
All voltages are measured with respect to GND = DR GND = 0V, unless otherwise specified.
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. There is no ensurance of operation at the
Absolute Maximum Ratings. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific
performance limits. For specifications and test conditions, see the Electrical Characteristics. The specified specifications apply only for
the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
When the input voltage at any pin exceeds the power supply limits (that is, less than GND or greater than VA), the current at that pin
should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the
power supplies with an input current of 25 mA to two. This limit is not placed upon the power, ground and digital output pins.
Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO
Ohms.
See http://www.ti.com for methods of soldering surface mount devices.
OPERATING RATINGS (1) (2)
−40°C ≤ TA ≤ +85°C
Ambient Temperature Range
Supply Voltage (VA)
+1.8V to +2.0V
Driver Supply Voltage (VDR)
+1.8V to VA
Analog Input Common Mode Voltage
1.2V to 1.3V
0V to 2.15V (100% duty cycle)
VIN+, VIN- Voltage Range (Maintaining Common Mode)
0V to 2.5V (10% duty cycle)
Ground Difference (|GND - DR GND|)
0V
CLK Pins Voltage Range
0V to VA
Differential CLK Amplitude
(1)
(2)
0.6VP-P to 2.0VP-P
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. There is no ensurance of operation at the
Absolute Maximum Ratings. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific
performance limits. For specifications and test conditions, see the Electrical Characteristics. The specified specifications apply only for
the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
All voltages are measured with respect to GND = DR GND = 0V, unless otherwise specified.
PACKAGE THERMAL RESISTANCES (1)
(1)
Package
θJ-C (Top of Package)
θJ-PAD (Thermal Pad)
128-Lead HLQFP
10°C / W
2.8°C / W
Soldering process must comply with Reflow Temperature Profile specifications. Refer to www.ti.com/packaging.
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CONVERTER ELECTRICAL CHARACTERISTICS
The following specifications apply after calibration for VA = VDR = +1.9VDC, OutV = 1.9V, VIN FSR (a.c. coupled) = differential
800mVP-P, CL = 10 pF, Differential, a.c. coupled Sinewave Clock, fCLK = 1 GHz at 0.5VP-P with 50% duty cycle, REXT = 3300Ω ±
0.1%, Analog Signal Source Impedance = 100Ω. Boldface limits apply for TA = TMIN to TMAX. All other limits TA = 25°C,
unless otherwise stated (1) (2) (3)
Symbol
Parameter
Conditions
Typical (4)
Limits (4)
Units
(Limits)
STATIC CONVERTER CHARACTERISTICS
INL
Integral Non-Linearity
±0.35
±0.9
LSB (max)
DNL
Differential Non-Linearity
±0.25
±0.7
LSB (max)
Resolution with No Missing Codes
−0.45
8
Bits
−1.5
0.5
LSB (min)
LSB (max)
VOFF
Offset Error
TC VOFF
Offset Error Tempco
PFSE
Positive Full-Scale Error (5)
−2.2
±25
mV (max)
NFSE
Negative Full-Scale Error (5)
−1.1
±25
mV (max)
TC PFSE
Positive Full Scale Error Tempco
−40°C to +85°C
20
ppm/°C
TC NFSE
Negative Full Scale Error Tempco
−40°C to +85°C
13
ppm/°C
−40°C to +85°C
−3
ppm/°C
Dynamic Converter Characteristics
FPBW
Full Power Bandwidth
B.E.R.
Bit Error Rate
Gain Flatness
ENOB
Effective Number of Bits
SINAD
Signal-to-Noise Plus Distortion Ratio
SNR
(1)
Signal-to-Noise Ratio
1.7
GHz
10-18
Error/Bit
d.c. to 500 MHz
±0.5
dBFS
d.c. to 1 GHz
±1.0
dBFS
fIN = 100 MHz, VIN = FSR − 0.5 dB
7.5
fIN = 248 MHz, VIN = FSR − 0.5 dB
7.5
7.1
Bits (min)
fIN = 498 MHz, VIN = FSR − 0.5 dB
7.5
7.1
Bits (min)
fIN = 100 MHz, VIN = FSR − 0.5 dB
47
fIN = 248 MHz, VIN = FSR − 0.5 dB
47
44.8
dB (min)
fIN = 498 MHz, VIN = FSR − 0.5 dB
47
44.8
dB (min)
fIN = 100 MHz, VIN = FSR − 0.5 dB
48
fIN = 248 MHz, VIN = FSR − 0.5 dB
48
45.5
dB (min)
fIN = 498 MHz, VIN = FSR − 0.5 dB
48
45.5
dB (min)
Bits
dB
dB
The analog inputs are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this
device.
V
A
TO INTERNAL
CIRCUITRY
I/O
GND
(2)
(3)
(4)
(5)
8
To ensure accuracy, it is required that VA and VDR be well bypassed. Each supply pin must be decoupled with separate bypass
capacitors. Additionally, achieving rated performance requires that the backside exposed pad be well grounded.
The ADC081000 has two interleaved LVDS output buses, which each clock data out at one half the sample rate. The data at each bus
is clocked out at one half the sample rate. The second bus (D0 through D7) has a pipeline latency that is one clock cycle less than the
latency of the first bus (Dd0 through Dd7).
Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are ensured to AOQL (Average Outgoing
Quality Level).
Calculation of Full-Scale Error for this device assumes that the actual reference voltage is exactly its nominal value. Full-Scale Error for
this device, therefore, is a combination of Full-Scale Error and Reference Voltage Error. See Transfer Characteristic Figure 2. For
relationship between Gain Error and Full-Scale Error, see Specification Definitions for Gain Error.
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CONVERTER ELECTRICAL CHARACTERISTICS (continued)
The following specifications apply after calibration for VA = VDR = +1.9VDC, OutV = 1.9V, VIN FSR (a.c. coupled) = differential
800mVP-P, CL = 10 pF, Differential, a.c. coupled Sinewave Clock, fCLK = 1 GHz at 0.5VP-P with 50% duty cycle, REXT = 3300Ω ±
0.1%, Analog Signal Source Impedance = 100Ω. Boldface limits apply for TA = TMIN to TMAX. All other limits TA = 25°C,
unless otherwise stated(1)(2)(3)
Symbol
THD
2nd Harm
3rd Harm
SFDR
IMD
Parameter
Total Harmonic Distortion
Second Harmonic Distortion
Third Harmonic Distortion
Spurious-Free dynamic Range
Intermodulation Distortion
Out of Range Output Code
(In addition to OR Output high)
Conditions
Typical (4)
Limits (4)
Units
(Limits)
fIN = 100 MHz, VIN = FSR − 0.5 dB
-57
fIN = 248 MHz, VIN = FSR − 0.5 dB
-57
−50
dB (max)
fIN = 498 MHz, VIN = FSR − 0.5 dB
-57
−50
dB (max)
fIN = 100 MHz, VIN = FSR − 0.5 dB
−64
dB
fIN = 248 MHz, VIN = FSR − 0.5 dB
−64
dB
fIN = 498 MHz, VIN = FSR − 0.5 dB
−64
dB
fIN = 100 MHz, VIN = FSR − 0.5 dB
−64
dB
fIN = 248 MHz, VIN = FSR − 0.5 dB
−64
dB
fIN = 498 MHz, VIN = FSR − 0.5 dB
−64
dB
fIN = 100 MHz, VIN = FSR − 0.5 dB
58.5
fIN = 248 MHz, VIN = FSR − 0.5 dB
58.5
50
dB (min)
fIN = 498 MHz, VIN = FSR − 0.5 dB
58.5
50
dB (min)
fIN1 = 121 MHz, VIN = FSR − 7 dB
fIN2 = 126 MHz, VIN = FSR − 7 dB
-51
dB
dB
dB
(VIN+) − (VIN−) > + Full Scale
255
(VIN+) − (VIN−) < − Full Scale
0
ANALOG INPUT AND REFERENCE CHARACTERISTICS
FSR pin Low
600
FSR pin High
800
Full Scale Analog Differential Input
Range
VIN
VCMI
Common Mode Analog Input Voltage
CIN
Analog Input Capacitance (6)
RIN
VCMO
Differential
0.02
Each input to ground
1.6
Differential Input Resistance
100
550
mVP-P (min)
650
mVP-P (max)
750
mVP-P (min)
850
mVP-P (max)
VCMO − 50
VCMO+ 50
mV (min)
mV (max)
pF
pF
94
Ω (min)
106
Ω (max)
0.95
1.45
V (min)
V (max)
ANALOG OUTPUT CHARACTERISTICS
VCMO
Common Mode Output Voltage
ICMO = ±1 µA
1.21
TC VCMO
Common Mode Output Voltage
Temperature Coefficient
TA = −40°C to +85°C
118
VBG
Bandgap Reference Output Voltage
IBG = ±100 µA
1.26
TC VBG
Bandgap Reference Voltage
Temperature Coefficient
TA = −40°C to +85°C,
IBG = ±100 µA
-28
(6)
ppm/°C
1.22
1.33
V (min)
V (max)
ppm/°C
The analog and clock input capacitances are die capacitances only. Additional package capacitances of 0.65 pF differential and 0.95 pF
each pin to ground are isolated from the die capacitances by lead and bond wire inductances.
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CONVERTER ELECTRICAL CHARACTERISTICS (continued)
The following specifications apply after calibration for VA = VDR = +1.9VDC, OutV = 1.9V, VIN FSR (a.c. coupled) = differential
800mVP-P, CL = 10 pF, Differential, a.c. coupled Sinewave Clock, fCLK = 1 GHz at 0.5VP-P with 50% duty cycle, REXT = 3300Ω ±
0.1%, Analog Signal Source Impedance = 100Ω. Boldface limits apply for TA = TMIN to TMAX. All other limits TA = 25°C,
unless otherwise stated(1)(2)(3)
Symbol
Typical (4)
Limits (4)
Units
(Limits)
Square Wave Clock
0.6
0.4
2.0
VP-P (min)
VP-P (max)
Sine Wave Clock
0.6
0.4
2.0
VP-P (min)
VP-P (max)
VIN = 0V or VIN = VA
±1
µA
Differential
0.02
pF
Each Input to Ground
1.5
pF
Parameter
Conditions
CLOCK INPUT CHARACTERISTICS
VID
Differential Clock Input Level
II
Input Current
CIN
Input Capacitance (7)
DIGITAL CONTROL PIN CHARACTERISTICS
VIH
Logic High Input Voltage
See (8)
1.4
V (min)
VIL
Logic Low Input Voltage
See (8)
0.5
V (max)
II
Input Current
CIN
Logic Input Capacitance
(9)
VIN = 0 or VIN = VA
±1
µA
Each input to ground
1.2
pF
OutV = VA, measured single-ended
300
OutV = GND, measured single-ended
225
DIGITAL OUTPUT CHARACTERISTICS
VOD
LVDS Differential Output Voltage
200
mVP-P (min)
450
mVP-P (max)
140
mVP-P (min)
340
mVP-P (max)
Δ VOD DIFF
Change in LVDS Output Swing
Between Logic Levels
±1
mV
VOS
Output Offset Voltage
800
mV
Δ VOS
Output Offset Voltage Change Between
Logic Levels
±1
mV
IOS
Output Short Circuit Current
ZO
Differential Output Impedance
Output+ & Output- connected to 0.8V
−4
mA
100
Ohms
POWER SUPPLY CHARACTERISTICS
IA
Analog Supply Current
IDR
Output Driver Supply Current
PD
Power Consumption
PSRR1
D.C. Power Supply Rejection Ratio
PD = Low
PD = High
646
4.5
792
mA (max)
mA
PD = Low
108
160
mA (max)
PD = High
0.1
PD = Low
1.43
PD = High
8.7
mW
Change in Offset Error with change in
VA from 1.8V to 2.0V
73
dB
TA = 85°C
1.1
TA ≤ 75°C
1.3
TA ≤ 70°C
1.6
GHz
200
MHz
mA
1.8
W (max)
AC ELECTRICAL CHARACTERISTICS
fCLK1
fCLK2
Maximum Conversion Rate
Minimum Conversion Rate
Input Clock Duty Cycle
tCL
(7)
(8)
(9)
10
200 MHz ≤ Input clock frequency < 1
GHz
Input Clock Low Time (8)
1.0
GHz (min)
GHz
50
20
80
% (min)
% (max)
500
200
ps (min)
The analog and clock input capacitances are die capacitances only. Additional package capacitances of 0.65 pF differential and 0.95 pF
each pin to ground are isolated from the die capacitances by lead and bond wire inductances.
This parameter is specified by design and characterization and is not tested in production.
The digital control pin capacitances are die capacitances only. Additional package capacitance of 1.6 pF each pin to ground are isolated
from the die capacitances by lead and bond wire inductances.
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CONVERTER ELECTRICAL CHARACTERISTICS (continued)
The following specifications apply after calibration for VA = VDR = +1.9VDC, OutV = 1.9V, VIN FSR (a.c. coupled) = differential
800mVP-P, CL = 10 pF, Differential, a.c. coupled Sinewave Clock, fCLK = 1 GHz at 0.5VP-P with 50% duty cycle, REXT = 3300Ω ±
0.1%, Analog Signal Source Impedance = 100Ω. Boldface limits apply for TA = TMIN to TMAX. All other limits TA = 25°C,
unless otherwise stated(1)(2)(3)
Symbol
tCH
Parameter
Conditions
Input Clock High Time (8)
DCLK Duty Cycle (8)
Typical (4)
Limits (4)
Units
(Limits)
500
200
ps (min)
50
45
55
% (min)
% (max)
tLHT
Differential Low to High Transition Time
10% to 90%, CL = 2.5 pF
250
ps
tHLT
Differential High to Low Transition Time
10% to 90%, CL = 2.5 pF
250
ps
tOSK
DCLK to Data Output Skew (10)
50% of DCLK transition to 50% of Data
transition
tAD
Sampling (Aperture) Delay
Input CLK+ Fall to Acquisition of Data
tAJ
Aperture Jitter
tOD
Input Clock to Data Output Delay
Pipeline Delay (Latency) (10)
tWU
PD low to Rated Accuracy Conversion
(Wake-Up Time)
tCAL
Calibration Cycle Time
50% of Input Clock transition to 50% of
Data transition
0
±200
ps (max)
930
ps
0.4
ps rms
2.7
ns
"D" Outputs
7
"Dd" Outputs
8
Clock Cycles
500
ns
46,000
Clock Cycles
(10) This parameter is specified by design and is not tested in production.
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Specification Definitions
APERTURE (SAMPLING) DELAY is that time required after the fall of the clock input for the sampling switch to
open. The Sample/Hold circuit effectively stops capturing the input signal and goes into the “hold” mode the
aperture delay time (tAD) after the clock goes low.
APERTURE JITTER (tAJ) is the variation in aperture delay from sample to sample. Aperture jitter shows up as
input noise.
Bit Error Rate (B.E.R.) is the probability of error and is defined as the probable number of errors per unit of time
divided by the number of bits seen in that amount of time. A B.E.R. of 10-18 corresponds to a statistical error in
one bit about every four (4) years.
CLOCK DUTY CYCLE is the ratio of the time that the clock wave form is at a logic high to the total time of one
clock period.
COMMON MODE VOLTAGE is the d.c. potential that is common to both pins of a differential pair. For a voltage
to be a common mode one, the signal departure from this d.c. common mode voltage at any given instant must
be the same for each of the pins, but in opposite directions from each other.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1
LSB. Measured at 1 GSPS with a ramp input.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise
and Distortion Ratio, or SINAD. ENOB is defined as (SINAD − 1.76) / 6.02 and says that the converter is
equivalent to a perfect ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH (FPBW) is a measure of the frequency at which the reconstructed output
fundamental drops 3 dB below its low frequency value for a full scale input.
GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated from Offset and
Full-Scale Errors:
•
PGE = OE − PFSE
•
NGE = −(OE − NFSE) = NFSE − OE
•
Gain Error = NFSE − PFSE = PGE + NGE
where PGE is Positive Gain Error, NGE is Negative Gain Error, OE is Offset Error, PFSE is Positive Full-Scale
Error and NFSE is Negative Full-Scale Error.
INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a straight line
through the input to output transfer function. The deviation of any given code from this straight line is measured
from the center of that code value. The best fit method is used.
INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two
sinusoidal frequencies being applied to the ADC input at the same time. it is defined as the ratio of the power in
the second and third order intermodulation products to the power in one of the original frequencies. IMD is
usually expressed in dBFS.
LSB (LEAST SIGNIFICANT BIT) is the bit that has the smallest value or weight of all bits. This value is
LSB = VFS / 2n
where
•
VFS is the differential full-scale amplitude VIN as set by the FSR input and "n" is the ADC resolution in bits,
which is 8 for the ADC081000
(1)
LVDS DIFFERENTIAL OUTPUT VOLTAGE (VOD) is this absolute value of the difference between the VD+ and
VD− outputs, each measured with respect to Ground.
LVDS OUTPUT OFFSET VOLTAGE (VOS) is the midpoint between the the D+ and D− pins' output voltages; i.e.,
[ (VD+) + (VD−) ] / 2.
12
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VD+
VD VOD
VD+
VOS
VD GND
VOD = | VD+ - VD- |
MISSING CODES are those output codes that are skipped and will never appear at the ADC outputs. These
codes cannot be reached with any input value.
MSB (MOST SIGNIFICANT BIT) is the bit that has the largest value or weight. Its value is one half of full scale.
NEGATIVE FULL-SCALE ERROR is a measure of how far the last code transition is from the ideal 1/2 LSB
above a differential −VIN/2. For the ADC081000 the reference voltage is assumed to be ideal, so this error is a
combination of full-scale error and reference voltage error.
OFFSET ERROR (VOFF) is a measure of how far the mid-scale point is from the ideal zero voltage differential
input.
OUTPUT DELAY (tOD) is the time delay after the falling edge of the DCLK before the data update is present at
the output pins.
OVER-RANGE RECOVERY TIME is the time required after the differential input voltages goes from ±1.2V to 0V
for the converter to recover and make a conversion with its rated accuracy.
PIPELINE DELAY (LATENCY) is the number of clock cycles between initiation of conversion and when that data
is presented to the output driver stage. New data is available at every clock cycle, but the data lags the
conversion by the Pipeline Delay plus the tOD.
POSITIVE FULL-SCALE ERROR (PFSE) is a measure of how far the last code transition is from the ideal 1-1/2
LSB below a differential +VIN/2. For the ADC081000 the reference voltage is assumed to be ideal, so this error is
a combination of full-scale error and reference voltage error.
POWER SUPPLY REJECTION RATIO (PSRR) can be one of two specifications. PSRR1 (DC PSRR) is the ratio
of the change in offset error that results from a power supply voltage change from 1.8V to 2.0V. PSRR2 (AC
PSRR) is a measure of how well an a.c. signal riding upon the power supply is rejected from the output and is
measured with a 248 MHz, 50 mVP-P signal riding upon the power supply. It is the ratio of the output amplitude of
that signal at the output to its amplitude on the power supply pin. PSRR is expressed in dB.
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal at the output
to the rms value of the sum of all other spectral components below one-half the sampling frequency, not
including harmonics or d.c.
SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or SINAD) is the ratio, expressed in dB, of the rms value of
the input signal at the output to the rms value of all of the other spectral components below half the clock
frequency, including harmonics but excluding d.c.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the
input signal at the output and the peak spurious signal, where a spurious signal is any signal present in the
output spectrum that is not present at the input, excluding d.c.
TOTAL HARMONIC DISTORTION (THD) is the ratio expressed in dB, of the rms total of the first nine harmonic
levels at the output to the level of the fundamental at the output. THD is calculated as
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THD = 20 x log
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A 2 +... +A 2
f2
f10
A f12
where
•
•
•
•
Af1 is the RMS power of the fundamental (output) frequency
Af2 through Af10 are the RMS power of the first 9 harmonic frequencies in the output spectrum
(2)
Second Harmonic Distortion (2nd Harm) is the difference, expressed in dB, between the RMS power in the
input frequency seen at the output and the power in its 2nd harmonic level at the output.
Third Harmonic Distortion (3rd Harm) is the difference expressed in dB between the RMS power in the
input frequency seen at the output and the power in its 3rd harmonic level at the output.
Transfer Characteristic
IDEAL POSITIVE
FULL-SCALE
TRANSITION
Output
Code
ACTUAL
POSITIVE
FULL-SCALE
TRANSITION
1111 1110 (254)
1111 1111 (255)
1111 1101 (253)
POSITIVE
FULL-SCALE
ERROR
MID-SCALE
TRANSITION
1000 0000 (128)
0111 1111 (127)
OFFSET
ERROR
IDEAL NEGATIVE
FULL-SCALE TRANSITION
NEGATIVE
FULL-SCALE
ERROR
ACTUAL NEGATIVE
FULL-SCALE TRANSITION
0000 0010 (2)
0000 0001 (1)
0000 0000 (0)
-300 mV /
-400 mV
(VIN+) < (VIN-)
(VIN+) > (VIN-)
0.0V
Differential Analog Input Voltage (VIN+) - (VIN-)
+300 mV /
+400 mV
Figure 2. Input / Output Transfer Characteristic
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Timing Diagrams
Sample N
Sample N-1
Dd
D
VIN
Sample N+1
tAD
tCL
tCH
CLK, CLK
DCLK+, DCLK(OutEdge = 0)
DCLK+, DCLK(OutEdge = 1)
tOSK
tLHT, tHLT
D, Dd
tOD
Sample N-6 and Sample N-5
Sample N-8 and Sample N-7
Figure 3. ADC081000 Timing
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TYPICAL PERFORMANCE CHARACTERISTICS
VA = VDR = +1.9V, fCLK = 1 GHz (differential clock), fIN = 248 MHz, Differential Inputs, unless otherwise stated. Parameters
shown across temperature were measured after recalibration at each temperature.
16
INL
INL vs. Temperature
Figure 4.
Figure 5.
INL vs. Supply Voltage
INL vs. Output Driver Voltage
Figure 6.
Figure 7.
INL vs. Sample Rate
DNL
Figure .
Figure 8.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VA = VDR = +1.9V, fCLK = 1 GHz (differential clock), fIN = 248 MHz, Differential Inputs, unless otherwise stated. Parameters
shown across temperature were measured after recalibration at each temperature.
DNL vs. Temperature
DNL vs. Supply Voltage
Figure 9.
Figure 10.
DNL vs. Output Driver Voltage
DNL vs. Sample Rate
Figure 11.
Figure 12.
SNR vs. Temperature
SNR vs. Supply Voltage
Figure 13.
Figure 14.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VA = VDR = +1.9V, fCLK = 1 GHz (differential clock), fIN = 248 MHz, Differential Inputs, unless otherwise stated. Parameters
shown across temperature were measured after recalibration at each temperature.
18
SN vs. Output Driver Voltage
SNR vs. Sample Rate
Figure 15.
Figure 16.
SNR vs. Clock Duty Cycle
SNR vs. Input Frequency
Figure 17.
Figure 18.
Distortion vs. Temperature
Distortion vs. Supply Voltage
Figure 19.
Figure 20.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VA = VDR = +1.9V, fCLK = 1 GHz (differential clock), fIN = 248 MHz, Differential Inputs, unless otherwise stated. Parameters
shown across temperature were measured after recalibration at each temperature.
Distortion vs. Output Driver Voltage
Distortion vs. Sample Rate
Figure 21.
Figure 22.
Distortion vs. Clock Duty Cycle
Distortion vs. Input Frequency
Figure 23.
Figure 24.
Distortion vs. Input Common Mode
SINAD vs. Temperature
Figure 25.
Figure 26.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VA = VDR = +1.9V, fCLK = 1 GHz (differential clock), fIN = 248 MHz, Differential Inputs, unless otherwise stated. Parameters
shown across temperature were measured after recalibration at each temperature.
20
SINAD vs. Supply Voltage
SINAD vs. Output Driver Voltage
Figure 27.
Figure 28.
SINAD vs. Sample Rate
SINAD vs. Clock Duty Cycle
Figure 29.
Figure 30.
SINAD vs. Input Frequency
ENOB vs. Temperature
Figure 31.
Figure 32.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VA = VDR = +1.9V, fCLK = 1 GHz (differential clock), fIN = 248 MHz, Differential Inputs, unless otherwise stated. Parameters
shown across temperature were measured after recalibration at each temperature.
ENOB vs. Supply Voltage
ENOB vs. Output Driver Voltage
Figure 33.
Figure 34.
ENOB vs. Sample Rate
ENOB vs. Clock Duty Cycle
Figure 35.
Figure 36.
ENOB vs. Input Frequency
ENOB vs. Input Common Mode
Figure 37.
Figure 38.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VA = VDR = +1.9V, fCLK = 1 GHz (differential clock), fIN = 248 MHz, Differential Inputs, unless otherwise stated. Parameters
shown across temperature were measured after recalibration at each temperature.
22
SFDR vs. Temperature
SFDR vs. Supply Voltage
Figure 39.
Figure 40.
SFDR vs. Output Driver Voltage
SFDR vs. Sample Rate
Figure 41.
Figure 42.
SFDR vs. Clock Duty Cycle
SFDR vs. Input Frequency
Figure 43.
Figure 44.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VA = VDR = +1.9V, fCLK = 1 GHz (differential clock), fIN = 248 MHz, Differential Inputs, unless otherwise stated. Parameters
shown across temperature were measured after recalibration at each temperature.
Power Consumption vs. Sample Rate
Spectral Response @ fIN = 100 MHz
Figure 45.
Figure 46.
Spectral Response @ fIN = 248 MHz
Spectral Response @ fIN = 498 MHz
Figure 47.
Figure 48.
Spectral Response @ fIN = 1.5 GHz
Figure 49.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VA = VDR = +1.9V, fCLK = 1 GHz (differential clock), fIN = 248 MHz, Differential Inputs, unless otherwise stated. Parameters
shown across temperature were measured after recalibration at each temperature.
24
Spectral Response @ fIN = 1.6 GHz
Intermodulation Distortion
Figure 50.
Figure 51.
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Functional Description
The ADC081000 is a versatile, high performance, easy to use A/D Converter with an innovative architecture
permitting very high speed operation. The controls available ease the application of the device to circuit
solutions. The ADC081000 uses a calibrated folding and interpolating architecture that achieves over 7.5
effective bits. The use of folding amplifiers greatly reduces the number of comparators and power consumption,
while Interpolation reduces the number of front-end amplifiers required, minimizing the load on the input signal
and further reducing power requirements. In addition to other things, on-chip calibration reduces the INL bow
often seen with folding architectures. The result is an extremely fast, high performance, low power converter.
Optimum performance requires adherence to the provisions discussed here and in the Applications Information
Section.
OVERVIEW
The analog input signal that is within the converter's input voltage range is digitized to eight bits at speeds of 200
MSPS to 1.6 GSPS, typical. Differential input voltages below negative full-scale will cause the output word to
consist of all zeroes. Differential input voltages above positive full-scale will cause the output word to consist of
all ones. The OR (Out of Range) output is activated whenever the correct output code would be outside of the
00h to FFh range.
The converter has a 1:2 demultiplexer that feeds two LVDS output buses. The data on these buses provide an
output word rate on each bus at half the ADC sampling rate and must be interleaved by the user to provide
output words at the full conversion rate.
The output levels may be selected to be normal or reduced. Using reduced levels saves power but could result in
erroneous data capture of some or all of the bits, especially at higher sample rates and in marginally designed
systems.
The voltage reference for the ADC081000 is derived from a 1.254V bandgap reference which is made available
to the user at the VBG pin. This output is capable of sourcing or sinking ±100 μA.
The internal bandgap derived reference voltage has a nominal value of 600 mV or 800 mV, as determined by the
FSR pin and described in The Analog Inputs. There is no provision for the use of an external reference voltage.
The fully differential comparator design and the innovative design of the sample-and-hold amplifier, together with
self calibration, enables flat SINAD/ENOB response beyond 1.0 GHz. The ADC081000 output data signaling is
LVDS and the output format is offset binary.
Self-Calibration
A self-calibration is performed upon power-up and can also be invoked by the user upon command. Calibration
trims the 100Ω analog input differential termination resistor and minimizes full-scale error, offset error, DNL and
INL, resulting in maximizing SNR, THD, SINAD (SNDR), SFDR and ENOB. Internal bias currents are also set
with the calibration process. All of this is true whether the calibration is performed upon power up or is performed
upon command.
Running the self calibration is important for this chip's functionality and is required in order to obtain adequate
performance. In addition to the requirement to be run at power-up, self calibration must be re-run whenever the
sense of the FSR pin is changed.
For best performance, we recommend that self calibration be run 20 seconds or more after application of power
and whenever the operating ambient temperature changes more than 30°C since calibration was last performed.
See On-Command Calibration for more information.
During the calibration process, the input termination resistor is trimmed to a value that is equal to REXT / 33. This
external resistor must be placed between pin 32 and ground and must be 3300 Ω ±0.1%. With this value, the
input termination resistor is trimmed to be 100 Ω. Because REXT is also used to set the proper bias current for the
Track and Hold amplifier, for the preamplifiers and for the comparators, other values of REXT should not be used.
In normal operation, calibration is performed just after application of power and whenever a valid calibration
command is given, which is holding the CAL pin low for at least 10 clock cycles, then holding it high for at least
another 10 clock cycles. There is no need to bring the CAL pin low after the 10 clock cycles of CAL high to begin
the calibration routine. Holding the CAL pin high upon power up, however, will prevent the calibration process
from running until the CAL pin experiences the above-mentioned 10 clock cycles low followed by 10 cycles high.
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The CalDly pin is used to select one of two delay times after the application of power to the start of calibration.
This calibration delay is 224 clock cycles (about 16.8 ms at 1 GSPS) with CalDly low, or 230 clock cycles (about
1.07 seconds at 1 GSPS) with CalDly high. These delay values allow the power supply to come up and stabilize
before calibration takes place. If the PD pin is high upon power-up, the calibration delay counter will be disabled
until the PD pin is brought low. Therefore, holding the PD pin high during power up will further delay the start of
the power-up calibration cycle. The best setting of the CalDly pin depends upon the power-on settling time of the
power supply.
The CalRun output is high whenever the calibration procedure is running. This is true whether the calibration is
done at power-up or on-command.
Calibration can not be initiated or run while the device is in the power-down mode. See Power Down for
information on the interaction between Power Down and Calibration.
Acquiring the Input
Data is acquired at the falling edge of CLK+ (pin 18) and the digital equivalent of that data is available at the
digital outputs 7 clock cycles later for the "D" output bus and 8 clock cycles later for the "Dd" output bus. There is
an additional internal delay called tOD before the data is available at the outputs. See the Timing Diagram. The
ADC081000 will convert as long as the clock signal is present and the PD pin is low.
The Analog Inputs
The ADC081000 must be driven with a differential input signal. It is important that the inputs either be a.c.
coupled to the inputs with the DC_Coup pin grounded or d.c. coupled with the DC_Coup pin high and have an
input common mode voltage that is equal to and tracks the VCMO output.
Two full-scale range settings are provided with the FSR pin. A high on that pin causes an input differential fullscale range setting of 800 mVP-P, while grounding that pin causes an input differential full-scale range setting of
600 mVP-P.
Clocking
The ADC081000 must be driven with an a.c. coupled, differential clock signal. THE CLOCK INPUTS describes
the use of the clock input pins. A differential LVDS output clock is available for use in latching the ADC output
data into whatever receives that data.
To help ease data capture, the output data may be caused to transition on either the positive or the negative
edge of the output data clock (DCLK). This is chosen with the OutEdge input. A high on the OutEdge input
causes the output data to transition on the rising edge of DCLK, while grounding this input causes the output to
transition on the falling edge of DCLK.
The LVDS Outputs
The data outputs, the Out Of Range (OR) and DCLK are LVDS compliant outputs. Output current sources
provide 3 mA of output current to a differential 100 Ohm load when the OutV input is high or 2.2 mA when the
OutV input is low. For short LVDS lines and low noise systems, satisfactory performance may be realized with
the OutV input low, which results in lower power consumption. If the LVDS lines are long and/or the system in
which the ADC081000 is used is noisy, it may be necessary to tie the OutV pin high.
Note that the LVDS levels are not intended to meet any given LVDS specification, but output levels are such that
interfacing with LVDS receivers is practical.
Out Of Range (OR) Indication
The input signal is out of range whenever the correct code would be above positive full-scale or below negative
full scale. When the input signal for any given sample is thus out of range, the OR output is high for that word
time.
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Power Down
The ADC081000 is in the active state when the Power Down pin (PD) is low. When the PD pin is high, the device
is in the power down mode, where the device power consumption is reduced to a minimal level and the outputs
are in a high impedance state. Upon return to normal operation, the pipeline will contain meaningless information
and must be flushed.
If the PD input is brought high while a calibration is running, the device will not go into power down until the
calibration sequence is complete. However, if power is applied and PD is already high, the device will not begin
the calibration sequence until the PD input goes low. If a manual calibration is requested while the device is
powered down, the calibration will not begin at all. That is, the manual calibration input is completely ignored in
the power down state.
Summary of Control Pins and Convenience Outputs
Table 1 and Table 2 are provided as a guide to the use of the various control and convenience pins of the
ADC081000. Note that this table is only a guide and that the rest of this data sheet should be consulted for the
full meaning and use of these pins.
Table 1. Digital Control Pins
PIN
DESCRIPTION
LOW
HIGH
3
OutV
440mV Outputs
600mV Outputs
4
OutEdge
Data Transition at DCLK Fall
Data Transition at DCLK Rise
14
DC_Coup
A.C. Coupled Inputs
D.C. Coupled Inputs
26
PD
Normal Operation
Power Down
30
CAL
Normal Operation
Run Calibration
35
FSR
600 mVP-P Full-Scale In
800 mVP-P Full-Scale In
127
CalDly
224 Clock Cycles
230 Clock Cycles
Table 2. Convenience Output Pins
PIN
DESCRIPTION
USE / INDICATION
7
VCMO
31
VBG
Common Mode Output Voltage.
1.25V Convenience Output.
79
80
OR+
OR−
Differential Out-Of-Range Indication; active high.
126
CalRun
Low is normal operation. High indicates Calibration is running.
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APPLICATIONS INFORMATION
THE REFERENCE VOLTAGE
The voltage reference for the ADC081000 is derived from a 1.254V bandgap reference which is made available
at the VBG output for user convenience and has an output current capability of ±100 μA. The VBG output should
be buffered if more current than this is required of it.
The internal bandgap-derived reference voltage causes the full-scale peak-to-peak input swing to be either 600
mV or 800 mV, as determined by the FSR pin and described in The Analog Inputs. There is no provision for the
use of an external reference voltage.
THE ANALOG INPUT
The analog input is a differential one to which the signal source may be a.c. coupled or d.c. coupled. Table 3
gives the input to output relationship with the FSR pin high. With the FSR pin grounded, the millivolt values in
Table 3 are reduced to 75% of the values indicated.
The buffered analog inputs simplify the task of driving these inputs and the RC pole that is generally used at
sampling ADC inputs is not required. If it is desired to use an amplifier circuit before the ADC, use care in
choosing an amplifier with adequate noise and distortion performance and adequate gain at the frequencies used
for the application.
Table 3. DIFFERENTIAL INPUT TO OUTPUT RELATIONSHIP (FSR High)
VIN+
VIN−
Output Code
VCM − 200 mV
VCM + 200 mV
0000 0000
VCM − 99 mV
VCM + 99 mV
0100 0000
VCM
VCM
0111 1111 / 1000 0000
VCM + 101 mV
VCM − 101 mV
1100 0000
VCM + 200mV
VCM − 200 mV
1111 1111
Note that a precise d.c. common mode voltage must be present at the ADC inputs. This common mode voltage,
VCMO, is provided on-chip when DC_Coup (pin 14) is low and the input signal is a.c. coupled to the ADC. See
Figure 52.
Ccouple
VIN+
Ccouple
VINDC_Coup
ADC081000
Figure 52. Differential Input Drive
When pin 14 is high, the analog inputs are d.c. coupled and a common mode voltage must be externally
provided at the analog input pins. This common mode voltage should track the VCMO output voltage. Note that
the VCMO output potential will change with temperature. The common mode output of the driving device should
track this change. Full-scale distortion performance falls off rapidly as the input common mode voltage deviates
from VCMO. This is a direct result of using a very low supply voltage to minimize power. Keep the input common
voltage within 50 mV of VCMO.
Performance of the ADC081000 is as good in the d.c. coupled mode as it is in the a.c. coupled mode, provided
the input common mode voltage at both analog input pins remain within 50 mV of VCMO.
If d.c. coupling is used, it is best to servo the input common mode voltage, using the VCMO pin, to maintain
optimum performance.
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Be sure that any current drawn from the VCMO output does not exceed ±1 μA.
The Input impedance in the d.c. coupled mode (DC_Coup pin high) consists of a precision 100 Ohm resistor
between VIN+ and VIN- and a capacitance from each of these inputs to ground. Driving the inputs beyond full
scale will result in saturation or clipping of the reconstructed output.
Handling Single-Ended Analog Signals
There is no provision for the ADC081000 to adequately process single-ended input signals. The best way to
handle single-ended signals is to convert them to differential signals before presenting them to the ADC. The
easiest way to accomplish single-ended to differential signal conversion is with an appropriate balun, as shown in
Figure 53.
A balun is especially designed for very high frequencies and has a wider bandwidth than does a transformer so
is perferred over a transformer for use with very high frequencies.
The ADC081000 is not designed to work with single-ended signals, so it is NOT RECOMMENDED that this be
done. However, if the resulting drop in performance is allowable, drive the ADC08100 with a single-ended signal
by bypassing the unused input to a.c. ground with a capacitor or connect it directly to the VCMO pin. DO NOT
connect either input pin directly to ground.
Ccouple
Signal
Input
To VIN+
1:2 Z-ratio
Balun
To VINCcouple
Figure 53. Single-Ended to Differential signal conversion with a balun
When d.c. coupling to the ADC081000 analog inputs is required, single-ended to differential conversion may be
easily accomplished with the LMH6555, as shown in Figure 54. In such applications, the LMH6555 performs the
task of single-ended to differential conversion while delivering low distortion and noise, as well as output balance,
that supports the operation of the ADC081000. Connecting the ADC081000 VCMO pin to the VCM_REF pin of the
LMH6555, through the appropriate buffer, will ensure that the ADC081000 common mode input voltage is as
needed for optimum performance of the ADC081000. See Figure 54. The LMV321 was chosen as the buffer in
Figure 54 for its low voltage operation and reasonable offset voltage. Be sure to limit output current from the
ADC081000 VCMO pin to 1.0 μA.
LMH6555
RF1
RG1
50:
VIN100:
+
50:
RT1
RG2
VIN+
50:
RF2
50:
VCM_REF
ADC081000
RT2
Signal
Input with
dc-coupled
50:
output
impedance
VCMO
+
LMV321
Figure 54. Example of Servoing the Analog Input with VCMO
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Out Of Range (OR) Indication
When the conversion result is clipped the Out of Range output is activated such that OR+ goes high and ORgoes low. This output is active as long as accurate data on either or both of the buses would be outside the
range of 00h to FFh.
Full-Scale Input Range
As with all A/D Converters, the input range is determined by the value of the ADC's reference voltage. The
reference voltage of the ADC081000 is derived from an internal bandgap reference. The FSR pin controls the
effective reference voltage of the ADC081000 such that the differential full-scale input range at the analog inputs
is 800 mVP-P with the FSR pin high, or is 600 mVP-P with FSR pin low. Best SNR is obtained with FSR high, but
better distortion and SFDR are obtained with the FSR pin low. The LMH6555 is suitable for both settings.
THE CLOCK INPUTS
The ADC081000 has differential LVDS clock inputs, CLK+ and CLK-, which must be driven with an a.c. coupled,
differential clock signal. Although the ADC081000 is tested and its performance is ensured with a differential 1.0GHz clock, it typically will function well with clock frequencies indicated in the Electrical Characteristics Table.
The clock inputs are internally terminated and biased. The clock signal must be capacitive coupled to the clock
pins as indicated in Figure 55.
Operation up to the sample rates indicated in the Electrical Characteristics Table is typically possible if the
conditions of the Operating Ratings are not exceeded. Operating at higher sample rates than indicated for the
given ambient temperature may result in reduced device reliability and product lifetime. This is because of the
higher power consumption and die temperatures at high sample rates. Important also for reliability is proper
thermal management . See Thermal Management.
Ccouple
CLK+
Ccouple
CLK-
ADC081000
Figure 55. Differential (LVDS) Clock Connection
The differential Clock line pair should have a characteristic impedance of 100Ω and be terminated at the clock
source in that (100Ω) characteristic impedance. The clock line should be as short and as direct as possible. The
ADC081000 clock input is internally terminated with an untrimmed 100Ω resistor.
Insufficient clock levels will result in poor dynamic performance. Excessively high clock levels could cause a
change in the analog input offset voltage. To avoid these problems, keep the clock level within the range
specified in the Operating Ratings.
While it is specified and performance is ensured at 1.0 GSPS with a 50% clock duty cycle, ADC081000
performance is essentially independent of clock duty cycle. However, to ensure performance over temperature, it
is recommended that the input clock duty cycle be such that the minimum clock high and low times are
maintained within the range specified in the Electrical Characteristics Table.
High speed, high performance ADCs such as the ADC081000 require very stable clock signals with minimum
phase noise or jitter. ADC jitter requirements are defined by the ADC resolution (number of bits), maximum ADC
input frequency and the input signal amplitude relative to the ADC input full scale range. The maximum jitter (the
total of the jitter from all sources) allowed to prevent a jitter-induced reduction in SNR is found to be
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tJ(MAX) = (VINFSR / VIN(P-P)) x (1/(2(N+1) x π x fIN))
where
•
•
•
•
tJ(MAX) is the rms total of all jitter sources in seconds
VIN(P-P) is the peak-to-peak analog input signal
VINFSR is the full-scale range of the ADC
"N" is the ADC resolution in bits and fIN is the maximum input frequency, in Hertz, to the ADC analog input (3)
Note that the maximum jitter described above is the rms total of the jitter from all sources, including that in the
ADC clock, that added by the system to the ADC clock and input signals and that added by the ADC itself. Since
the effective jitter added by the ADC is beyond user control, the best the user can do is to keep the sum of the
externally added clock jitter and the jitter added by the analog circuitry to the analog signal to a minimum.
CONTROL PINS
Seven control pins provide a wide range of possibilities in the operation of the ADC081000 and facilitate its use.
These control pins provide Full-Scale Input Range setting, Self Calibration, Calibration Delay, Output Edge
Synchronization choice, LVDS Output Level choice and a Power Down feature.
Self Calibration
The ADC081000 self-calibration must be run to achieve rated performance. This procedure is performed upon
power-up and can be run any time on command. The calibration procedure is exactly the same whether there is
a clock present upon power up or if the clock begins some time after application of power. The CalRun output
indicator is high while a calibration is in progress.
Power-on Calibration
Power-on calibration begins after a time delay following the application of power. This time delay is determined
by the setting of CalDly, as described in Self-Calibration.
The calibration process will be not be performed if the CAL pin is high at power up. In this case, the calibration
cycle will not begin until on-command calibration conditions are met. The ADC081000 will function with the CAL
pin held high at power up, but no calibration will be done and performance will be impaired. A manual calibration,
however, may be performed after powering up with the CAL pin high. See On-Command Calibration.
The internal power-on calibration circuitry comes up in a random state. If the clock is not running at power up
and the power on calibration circuitry is active, it will hold the analog circuitry in power down and the power
consumption will typically be less than 200 mW. The power consumption will be normal after the clock starts.
On-Command Calibration
Calibration may be run at any time by bringing the CAL pin high for a minimum of 10 clock cycles after it has
been low for a minimum of 10 clock cycles. Holding the CAL pin high upon power up will prevent execution of
power-on calibration until the CAL pin is low for a minimum of 10 clock clock cycles, then brought high for a
minimum of another 10 clock cycles. The calibration cycle will begin 10 clock cycles after the CAL pin is thus
brought high.
The minimum 10 clock cycle sequences are required to ensure that random noise does not cause a calibration to
begin when it is not desired. As mentioned in Self-Calibration, for best performance, a self calibration should be
performed 20 seconds or more after power up and repeated when the ambient temperature changes more than
30°C since the last self calibration was run. SINAD drops about 1.5 dB for every 30°C change in die temperature
and ENOB drops about 0.25 bit for every 30°C change in die temperature.
Calibration Delay
The CalDly input (pin 127) is used to select one of two delay times after the application of power to the start of
calibration, as described in Self-Calibration. The calibration delay values allow the power supply to come up and
stabilize before calibration takes place. With no delay or insufficient delay, calibration would begin before the
power supply is stabilized at its operating value and result in non-optimal calibration coefficients. If the PD pin is
high upon power-up, the calibration delay counter will be disabled until the PD pin is brought low. Therefore,
holding the PD pin high during power up will further delay the start of the power-up calibration cycle. The best
setting of the CalDly pin depends upon the power-on settling time of the power supply.
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Output Edge Synchronization
DCLK signals are available to help latch the converter output data into external circuitry. The output data can be
synchronized with either edge of these clock signals. That is, the output data transition can be set to occur with
either the rising edge or the falling edge of the DCLK signal, so that either edge of that clock signal can be used
to latch the output data into the receiving circuit.
When the OutEdge pin is high, the output data is synchronized with (changes with) the rising edge of DCLK+.
When OutEdge is low, the output data is synchronized with the falling edge of DCLK+.
At the very high speeds of which the ADC081000 is capable, slight differences in the lengths of the clock and
data lines can mean the difference between successful and erroneous data capture. The OutEdge pin is used to
capture data on the DCLK edge that best suits the application circuit and layout.
Power Down Feature
The Power Down (PD) pin, when high, puts the ADC081000 into a low power mode where power consumption is
greatly reduced.
The digital output pins retain the last conversion output code when the clock is stopped, but are in a high
impedance state when the PD pin is high. However, upon return to normal operation (re-establishment of the
clock and/or lowering of the PD pin), the pipeline will contain meaningless information and must be flushed.
If the PD input is brought high while a calibration is running, the device will not go into power down until the
calibration sequence is complete. However, if power is applied and PD is already high, the device will not begin
the calibration sequence until the PD input goes low. If a manual calibration is requested while the device is
powered down, the calibration will not begin at all. That is, the manual calibration input is completely ignored in
the power down state.
THE DIGITAL OUTPUTS
The ADC081000 demultiplexes its output data onto two LVDS output buses.
The results of successive conversions started on the odd falling edges of the CLK+ pin are available on one of
the two LVDS buses, while the results of conversions started on the even falling edges of the CLK+ pin are
available on the other LVDS bus. This means that the word rate at each LVDS bus is 1/2 the ADC081000 clock
rate and the two buses must be interleaved to obtain the entire 1 GSPS conversion result.
Since the minimum recommended clock rate for this device is 200 MSPS, the effective sample rate can be
reduced to as low as 100 MSPS by using the results available on just one of the the two LVDS buses and a 200
MHz input clock, decimating the 200 MSPS data by two.
There is one LVDS clock pair available for use to latch the LVDS outputs on both buses. Whether the data is
sent at the rising or falling edge of DCLK+ is determined by the sense of the OutEdge pin, as described in
Output Edge Synchronization.
The OutV pin is used to set the LVDS differential output levels. See The LVDS Outputs.
The output format is Offset Binary. Accordingly, a full-scale input level with VIN+ positive with respect to VIN− will
produce an output code of all ones, a full-scale input level with VIN− positive with respect to VIN+ will produce an
output code of all zeros and when VIN+ and VIN− are equal, the output code will vary between 127 and 128.
POWER CONSIDERATIONS
A/D converters draw sufficient transient current to corrupt their own power supplies if not adequately bypassed. A
33 µF capacitor should be placed within an inch (2.5 cm) of the A/D converter power pins. A 0.1 μF capacitor
should be placed as close as possible to each VA pin, preferably within one-half centimeter. Leadless chip
capacitors are preferred because they have low lead inductance. Having power and ground planes in adjacent
layers of the PC Board will provide the best supply bypass capacitance in terms of low ESL.
The VA and VDR supply pins should be isolated from each other to prevent any digital noise from being coupled
into the analog portions of the ADC. A ferrite choke, such as the JW Miller FB20009-3B, is recommended
between these supply lines when a common source is used for them.
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As is the case with all high speed converters, the ADC081000 should be assumed to have little power supply
noise rejection. Any power supply used for digital circuity in a system where a lot of digital power is being
consumed should not be used to supply power to the ADC081000. The ADC supplies should be the same supply
used for other analog circuitry, if not a dedicated supply.
Supply Voltage
The ADC081000 is specified to operate with a supply voltage of 1.9V ±0.1V. It is very important to note that,
while this device will function with slightly higher supply voltages, these higher supply voltages may reduce
product lifetime.
No pin should ever have a voltage on it that is in excess of the supply voltage or below ground by more than 150
mV, not even on a transient basis. This can be a problem upon application of power and power shut-down. Be
sure that the supplies to circuits driving any of the input pins, analog or digital, do not come up any faster than
does the voltage at the ADC081000 power pins.
Linear
Regulator
VIN
1.9V
to ADC
+
10 PF
210
+
33 PF
100
+
10 PF
110
Figure 56. Non-Spiking Power Supply
The Absolute Maximum Ratings should be strictly observed, even during power up and power down. A power
supply that produces a voltage spike at turn-on and/or turn-off of power can destroy the ADC081000. The circuit
of Figure 56 will provide supply overshoot protection.
Many linear regulators will produce output spiking at power-on unless there is a minimum load provided. Active
devices draw very little current until their supply voltages reach a few hundred millivolts. The result can be a turnon spike that can destroy the ADC081000, unless a minimum load is provided for the supply. The 100Ω resistor
at the regulator output in Figure 56 provides a minimum output current during power-up to ensure there is no
turn-on spiking.
In this circuit, an LM317 linear regulator is satisfactory if its input supply voltage is 4V to 5V . If a 3.3V supply is
used, an LM1086 linear regulator is recommended. Also, be sure that the impedance of the power distribution
system is low to minimize resistive losses and minimize noise on the power supply.
The output drivers should have a supply voltage, VDR, that is within the range specified in the Operating Ratings
table. This voltage should not exceed the VA supply voltage and should never spike to a voltage greater than (VA
+ 100mV).
If the power is applied to the device without a clock signal present, the current drawn by the device might be
below 100 mA. This is because the ADC081000 gets reset through clocked logic and its initial state is random. If
the reset logic comes up in the "on" state, it will cause most of the analog circuitry to be powered down, resulting
in less than 100 mA of current draw. This current is greater than the power down current because not all of the
ADC is powered down. The device current will be normal after the clock is established.
Thermal Management
The ADC081000 is capable of impressive speeds and performance at very low power levels for its speed.
However, the power consumption is still high enough to require attention to thermal management. For reliability
reasons, the die temperature should be kept to a maximum of 130°C. That is, tA (ambient temperature) plus ADC
power consumption times θJA (junction to ambient thermal resistance) should not exceed 130°C. This is not a
problem if the ambient temperature is kept to a maximum of +85°C, the device is soldered to a PC Board and the
sample rate is at or below 1 Gsps.
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Note that the following are general recommendations for mounting exposed pad devices onto a PCB. This should
be considered the starting point in PCB and assembly process development. It is recommended that the process
be developed based upon past experience in package mounting.
The package of the ADC081000 has an exposed pad on its back that provides the primary heat removal path as
well as excellent electrical grounding to the printed circuit board. The land pattern design for lead attachment to
the PCB should be the same as for a conventional LQFP, but the exposed pad must be attached to the board to
remove the maximum amount of heat from the package, as well as to ensure best product parametric
performance.
To maximize the removal of heat from the package, a thermal land pattern must be incorporated on the PC
board within the footprint of the package. The exposed pad of the device must be soldered down to ensure
adequate heat conduction out of the package. The land pattern for this exposed pad should be at least as large
as the 5 x 5 mm of the exposed pad of the package and be located such that the exposed pad of the device is
entirely over that thermal land pattern. This thermal land pattern should be electrically connected to ground. A
clearance of at least 0.5 mm should separate this land pattern from the mounting pads for the package pins.
Since a large aperture opening may result in poor release, the aperture opening should be subdivided into an
array of smaller openings, similar to the land pattern of Figure 57.
5.0 mm, min
0.25 mm, typ
0.33 mm, typ
1.2 mm, typ
Figure 57. Recommended Package Land Pattern
To minimize junction temperature, it is recommended that a simple heat sink be built into the PCB. This is done
by including a minimum copper pad of 2 inches by 2 inches (5.1 cm by 5.1 cm) on the opposite side of the PCB.
This copper area may be plated or solder coated to prevent corrosion, but should not have a conformal coating,
which could provide some thermal insulation. Thermal vias should be used to connect these top and bottom
copper areas. These thermal vias act as "heat pipes" to carry the thermal energy from the device side of the
board to the opposite side of the board where it can be more effectively dissipated. The use of 9 to 16 thermal
vias is recommended.
The thermal vias should be placed on a 1.2 mm grid spacing and have a diameter of 0.30 to 0.33 mm. These
vias should be barrel plated to avoid solder wicking into the vias during the soldering process as this wicking
could cause voids in the solder between the package exposed pad and the thermal land on the PCB. Such voids
could increase the thermal resistance between the device and the thermal land on the board, which would cause
the device to run hotter.
On a board of FR-4 material and the built in heat sink described above (4 square inch pad and 9 thermal vias),
the die temperature stabilizes at about 30°C above the ambient temperature in about 20 seconds.
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If it is desired to monitor die temperature, a temperature sensor may be mounted on the heat sink area of the
board near the thermal vias. Allow for a thermal gradient between the temperature sensor and the ADC081000
die of θJC times typical power consumption = 2.8 x 1.43 = 4°C. Allowing for a 5°C (including an extra 1°C)
temperature drop from the die to the temperature sensor, then, would mean that maintaining a maximum pad
temperature reading of 125°C will ensure that the die temperature does not exceed 130°C, assuming that the
exposed pad of the ADC081000 is properly soldered down and the thermal vias are adequate.
LAYOUT AND GROUNDING
Proper grounding and proper routing of all signals are essential to ensure accurate conversion. A single ground
plane should be used, as opposed to splitting the ground plane into analog and digital areas.
Since digital switching transients are composed largely of high frequency components, the skin effect tells us that
total ground plane copper weight will have little effect upon the logic-generated noise. Total surface area is more
important than is total ground plane volume. Coupling between the typically noisy digital circuitry and the
sensitive analog circuitry can lead to poor performance that may seem impossible to isolate and remedy. The
solution is to keep the analog circuitry well separated from the digital circuitry.
High power digital components should not be located on or near any linear component or power supply trace or
plane that services analog or mixed signal components as the resulting common return current path could cause
fluctuation in the analog input “ground” return of the ADC, causing excessive noise in the conversion result.
Generally, we assume that analog and digital lines should cross each other at 90° to avoid getting digital noise
into the analog path. In high frequency systems, however, avoid crossing analog and digital lines altogether.
Clock lines should be isolated from ALL other lines, analog AND digital. The generally accepted 90° crossing
should be avoided as even a little coupling can cause problems at high frequencies. Best performance at high
frequencies is obtained with a straight signal path.
The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input.
This is especially important with the low level drive required of the ADC081000. Any external component (e.g., a
filter capacitor) connected between the converter's input and ground should be connected to a very clean point in
the analog ground plane. All analog circuitry (input amplifiers, filters, etc.) should be separated from any digital
components.
DYNAMIC PERFORMANCE
The ADC081000 is a.c. tested and its dynamic performance is ensured. To meet the published specifications and
avoid jitter-induced noise, the clock source driving the CLK input must exhibit low rms jitter. The allowable jitter is
a function of the input frequency and the input signal level, as described in THE CLOCK INPUTS.
It is good practice to keep the ADC clock line as short as possible, to keep it well away from any other signals
and to treat it as a transmission line. Other signals can introduce jitter into the clock signal. The clock signal can
also introduce noise into the analog path if not isolated from that path.
Best dynamic performance is obtained when the exposed pad at the back of the package has a good connection
to ground. This is because this path from the die to ground is a lower impedance than that offered by the
package pins.
COMMON APPLICATION PITFALLS
Allowing loose power supply voltage tolerance. The ADC081000 is specified for operation between 1.8 Volts
to 2.0 Volts. Using a 1.8 Volt power supply then implies the need for no negative tolerance. The best solution is
to use an adjustable linear regulator such as the LM317 or LM1086 set for 1.9V as discussed in Supply Voltage.
Driving the inputs (analog or digital) beyond the power supply rails. For device reliability, all inputs should
not go more than 150 mV below the ground pins or 150 mV above the supply pins. Exceeding these limits on
even a transient basis may not only cause faulty or erratic operation, but may impair device reliability. It is not
uncommon for high speed digital circuits to exhibit undershoot that goes more than a volt below ground.
Controlling the impedance of high speed lines and terminating these lines in their characteristic impedance
should control overshoot.
Care should be taken not to overdrive the inputs of the ADC081000. Such practice may lead to conversion
inaccuracies and even to device damage.
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Incorrect analog input common mode voltage in the d.c. coupled mode. As discussed in The Analog Inputs
and THE ANALOG INPUT, the Input common mode voltage must remain within 50 mV of the VCMO output and
track that output, which has a variability with temperature that must also be tracked. Distortion performance will
be degraded if the input common mode voltage is more than 50 mV from VCMO.
Using an inadequate amplifier to drive the analog input. Use care when choosing a high frequency amplifier
to drive the ADC081000 as many high speed amplifiers will have higher distortion than will the ADC081000,
resulting in overall system performance degradation.
Driving the VBG pin to change the reference voltage. As mentioned in The Analog Inputs, the reference
voltage is intended to be fixed to provide one of two different full-scale values (600 mVP-P and 800 mVP-P). Over
driving this pin will not change the full scale value, but can otherwise upset operation.
Driving the clock input with an excessively high level signal. The ADC clock level should not exceed the
level described in the Operating Ratings Table or the input offset error could increase.
Inadequate clock levels. As described in THE CLOCK INPUTS, insufficient clock levels can result in poor
performance. Excessive clock levels could result in the introduction of an input offset.
Using an excessively long clock signal trace, or having other signals coupled to the clock signal trace.
This will cause the sampling interval to vary, causing excessive output noise and a reduction in SNR
performance.
Failure to provide adequate heat removal. As described in Thermal Management, it is important to provide an
adequate heat removal to ensure device reliability. This can either be done with adequate air flow or the use of a
simple heat sink built into the board. The backside pad should be grounded for best performance.
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REVISION HISTORY
Changes from Revision F (May 2013) to Revision G
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 36
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PACKAGE OPTION ADDENDUM
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14-Feb-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
ADC081000CIYB/NOPB
NRND
Package Type Package Pins Package
Drawing
Qty
HLQFP
NNB
128
60
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
Op Temp (°C)
Device Marking
(4/5)
-40 to 85
ADC081000
CIYB
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
14-Feb-2015
Addendum-Page 2
MECHANICAL DATA
NNB0128A
VNX128A (Rev B)
www.ti.com
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