Datasheet Analog Sound Processors series Sound Processor for car audio built-in High-Voltage function and 2nd order post filter BD37068FV-M General Description Key Specifications It is built-in input selector of 6 stereo source and output nd to ADC after adjusting signal level. And built-in 2 order post filter to reduce out of band noise and 6ch Volume circuit. It is possible to out until 5.2VRMS at maximum output. (High Voltage function) Moreover, it is simple to design set by built-in TDMA noise reduction systems. 0.003%(Typ) Total Harmonic Distortion： 2.2VRMS(Typ) Maximum Input Voltage： Common Mode Rejection Ratio： 55dB(Min) Maximum Output Voltage： 5.2VRMS(Typ) Output Noise Voltage： 23μVRMS(Typ) Residual Output Noise Voltage： 10.5μVRMS(Typ) Ripple Rejection: -70dB (Typ) Operating Temperature Range: -40˚C to +85˚C Features AEC-Q100 (Grade3) Qualified Built-in differential input selector that can select single-ended / differential input Reduce the pop noise when switching gain due to built-in advanced switch circuit nd Less out-of-band noise of DAC by built-in 2 order post filter. Built-in buffered ground isolation amplifier to realize high CMRR characteristics Built-in TDMA noise reduction circuit reduces the additional components for external filter. It is possible to output 5.2VRMS by High-Voltage function Package is SSOP-B40. Putting same direction input-terminals and output-terminals make PCB layout easier and PCB area smaller. 2 Available to control by 3.3V/5V for I C-bus controller (Note1) (Note1) These specifications are condition of High-Voltage ON. Package W(Typ) x D(Typ) x H(Max) 13.60mm x 7.80mm x 2.00mm SSOP-B40 Applications It is the optimal for the car audio. Besides, it is possible to use for the audio equipment of mini Compo, micro Compo. SSOP-B40 Typical Application Circuit VCCL 10µF OUTC OUTS OUTR1 OUTR2 OUTF1 OUTF2 INF2 10µF 10µF INF1 INR2 INR1 INS INC IG1 VCCH IG2 GND SDA SCL 10µF 10µF 10µF 10µF 10µF 2.2µF 2.2µF 2.2µF 2.2µF 10µF 2.2µF 10µF 2.2µF 10µF VREF 40 39 38 37 35 36 Level Shift Level Shift Level Shift Level Shift Level Shift 34 33 32 31 28 29 30 27 26 100kΩ 100kΩ 100kΩ 100kΩ 100kΩ 24 25 Level Shift 22 23 VREF 100kΩ 21 2 I C-bus LOGIC Front mixing Sub Selector ★ ★ ■Fader : +23dB to -79dB、-∞/1dBstep ■Input Gain : +23dB to -15dB/1dBstep Fader Fader Fader Fader Fader Fader ATT★ ATT★ ATT★ ATT★ ATT★ ATT★ Sub Gain adjust Main Gain adjust ■Front Mixing : on/off ★ Advanced Switch 2nd order LPF Fader Fader Fader Fader Fader Fader Boost★ Boost★ Boost★ Boost★ Boost★ Boost★ ■2nd order LPF: fc=70kHz ■Main/Sub Gain Adjust 0dB/6dB Rear Selector ■Anti-TDMA noise circuit ■High-Voltage Output Front Selector ★ Input Gain Input selector (1 single - end and 5 stereo ISO) 100kΩ 1 100kΩ 250kΩ 2 2.2µF A1 A2 250kΩ 3 2.2µF GND ISO amp GND ISO amp GND ISO amp 250kΩ 250kΩ 4 2.2µF BP1 GND ISO amp 250kΩ 5 2.2µF BP2 6 2.2µF CP1 GND ISO amp 250kΩ 7 10µF CN 8 2.2µF CP2 GND ISO amp 250kΩ 250kΩ 9 2.2µF DP1 DN GND ISO amp 250kΩ 11 10 10µF 2.2µF DP2 250kΩ 12 2.2µF EP1 Differential amp GND ISO amp 250kΩ 250kΩ 13 10µF EN 250kΩ 14 FP1 250kΩ 16 15 2.2µF 2.2µF EP2 Differential amp 250kΩ 10µF FN1 250kΩ 17 10µF FN2 100kΩ 18 2.2µF FP2 19 20 2.2µF 10µF MIN BN HIVOLB Figure 1. Typical Application Circuit ○Product structure：Silicon monolithic integrated circuit www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111・14・001 ○This product is not designed protection against radioactive rays. 1/35 TSZ02201-0C2C0E100130-1-2 14.NOV.2016 Rev.002 BD37068FV-M Contents General Description ........................................................................................................................................................................ 1 Features.......................................................................................................................................................................................... 1 Applications .................................................................................................................................................................................... 1 (Note1) Key Specifications ................................................................................................................................................................... 1 Package W(Typ) x D(Typ) x H(Max) ......................................................................................................................................... 1 Typical Application Circuit ............................................................................................................................................................... 1 Contents ........................................................................................................................................................................................ 2 Pin Configuration ............................................................................................................................................................................ 3 Pin Descriptions .............................................................................................................................................................................. 3 Block Diagram ................................................................................................................................................................................ 4 Absolute Maximum Ratings (Ta=25˚C) ........................................................................................................................................... 4 Operating Range ............................................................................................................................................................................ 4 Electrical Characteristic .................................................................................................................................................................. 5 Typical Performance Curve(s) ........................................................................................................................................................ 7 2 I C-bus Control Signal Specification........................................................................................................................................... 9 1. Electrical specifications and timing for bus lines and I/O stages....................................................................................... 9 2 2. I C-bus Format ............................................................................................................................................................... 10 2 3. I C-bus Interface Protocol............................................................................................................................................... 10 4. Slave Address................................................................................................................................................................. 10 5. Select Address & Data .................................................................................................................................................... 11 6. About power on reset ..................................................................................................................................................... 17 7. About start-up and power off sequence on IC ................................................................................................................ 17 Fader Volume Attenuation of the Detail......................................................................................................................................... 18 About bias voltage of output terminal(27,28,35 to 40pin) vs. VCC ................................................................................................ 19 About Advanced Switch Circuit ..................................................................................................................................................... 20 Application Circuit Diagram........................................................................................................................................................... 26 Thermal Derating Curve ............................................................................................................................................................. 27 I/O Equivalence Circuit ................................................................................................................................................................. 28 Application Information.............................................................................................................................................................. 30 1. Absolute maximum rating voltage................................................................................................................................... 30 2. About a signal input part ................................................................................................................................................. 30 3. About output load characteristics.................................................................................................................................... 30 4. About HIVOLB terminal(20pin) when power supply is off ............................................................................................... 31 5. About signal input terminals ........................................................................................................................................... 31 6. About changing gain of Input Gain and Fader Volume ................................................................................................... 31 7. About inter-pin short to VCCH ........................................................................................................................................ 31 Operational Notes ......................................................................................................................................................................... 32 1. Reverse Connection of Power Supply ............................................................................................................................ 32 2. Power Supply Lines ........................................................................................................................................................ 32 3. Ground Voltage............................................................................................................................................................... 32 4. Ground Wiring Pattern .................................................................................................................................................... 32 5. Thermal Consideration ................................................................................................................................................... 32 6. Recommended Operating Conditions............................................................................................................................. 32 7. Inrush Current................................................................................................................................................................. 32 8. Operation Under Strong Electromagnetic Field .............................................................................................................. 32 9. Testing on Application Boards ........................................................................................................................................ 32 10. Inter-pin Short and Mounting Errors ............................................................................................................................... 33 11. Regarding the Input Pin of the IC ................................................................................................................................... 33 Ordering Name Selection.............................................................................................................................................................. 34 Physical Dimension Tape and Reel Information ............................................................................................................................ 34 Marking Diagram .......................................................................................................................................................................... 34 Revision History ............................................................................................................................................................................ 35 www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 2/35 TSZ02201-0C2C0E100130-1-2 14.NOV.2016 Rev.002 BD37068FV-M Pin Configuration SSOP-B40 (TOP VIEW) A1 1 40 OUTC A2 2 39 OUTS BP1 3 38 OUTR1 BP2 4 37 OUTR2 CP1 5 36 OUTF1 CN 6 35 OUTF2 CP2 7 34 INF2 DP1 8 33 INF1 DN 9 32 INR2 10 31 INR1 EP1 11 30 INS EN 12 29 INC EP2 13 28 IG1 FP1 14 27 IG2 FN1 15 26 VCCL FN2 16 25 VREF FP2 17 24 GND MIN 18 23 SDA BN 19 22 SCL HIVOLB 20 21 VCCH DP2 Figure 2. Pin configuration Pin Descriptions Pin No. 1 Pin Name A1 2 A2 3 Description A input terminal of 1ch Pin No. 21 Pin Name VCCH Description VCCH terminal for power supply A input terminal of 2ch 22 SCL I C Communication clock terminal BP1 B positive input terminal of 1ch 23 SDA I C Communication data terminal 4 BP2 B positive input terminal of 2ch 24 GND GND terminal 5 CP1 C positive input terminal of 1ch 25 VREF BIAS terminal 6 CN C negative input terminal 26 VCCL VCCL terminal for power supply 7 CP2 C positive input terminal of 2ch 27 IG2 Input Gain output terminal of 2ch 8 DP1 D positive input terminal of 1ch 28 IG1 Input Gain output terminal of 1ch 2 2 9 DN D negative input terminal 29 INC Center input terminal 10 DP2 D positive input terminal of 2ch 30 INS Subwoofer input terminal 11 EP1 E positive input terminal of 1ch 31 INR1 Rear input terminal of 1ch 12 EN E negative input terminal 32 INR2 Rear input terminal of 2ch 13 EP2 E positive input terminal of 2ch 33 INF1 Front input terminal of 1ch 14 FP1 F positive input terminal of 1ch 34 INF2 Front input terminal of 2ch 15 FN1 F negative input terminal of 1ch 35 OUTF2 Front output terminal of 2ch 16 FN2 F negative input terminal of 2ch 36 OUTF1 Front output terminal of 1ch 17 FP2 F positive input terminal of 2ch 37 OUTR2 Rear output terminal of 2ch 18 MIN Mixing input terminal 38 OUTR1 Rear output terminal of 1ch 19 BN B negative input terminal 39 OUTS Subwoofer output terminal 20 HIVOLB Output Gain control terminal 40 OUTC Center output terminal www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 3/35 TSZ02201-0C2C0E100130-1-2 14.NOV.2016 Rev.002 BD37068FV-M Block Diagram OUTC OUTS OUTR1 OUTR2 OUTF1 OUTF2 INF2 40 39 38 37 36 Level Shift Level Shift Level Shift Level Shift Level Shift 35 INF1 INR2 INR1 INS INC IG1 IG2 33 32 31 30 29 28 27 34 VCCL VREF GND 26 25 SDA 24 SCL VCCH 22 23 21 Level Shift 100kΩ 100kΩ 100kΩ 100kΩ 100kΩ VREF 100kΩ I2C-bus LOGIC Front Mixing Sub Selector ★ ★ ■Fader : +23dB to -79dB、-∞/1dBstep ■Input Gain : +23dB to -15dB/1dBstep Fader Fader Fader Fader Fader Fader ATT★ ATT★ ATT★ ATT★ ATT★ ATT★ Sub Gain adjust Main Gain adjust ■Front Mixing : on/off ★ Advanced Switch 2nd order LPF Fader Fader Fader Fader Fader Fader Boost★ Boost★ Boost★ Boost★ Boost★ Boost★ ■2nd order LPF: fc=70kHz ■Main/Sub Gain Adjust 0dB/6dB Rear Selector ■Anti-TDMA noise circuit ■High-Voltage Output Front Selector ★ Input Gain Input selector (1 single - end and 5 stereo ISO) GND ISO amp 100kΩ 100kΩ 250kΩ GND ISO amp 250kΩ GND ISO amp GND ISO amp 250kΩ 250kΩ 1 2 3 4 A1 A2 BP1 BP2 5 CP1 250kΩ 6 250kΩ 7 CN GND ISO amp CP2 GND ISO amp 250kΩ 8 DP1 250kΩ 9 DN GND ISO amp 250kΩ 250kΩ 10 11 DP2 EP1 Differential amp GND ISO amp 250kΩ 12 EN 250kΩ 250kΩ 13 14 EP2 FP1 Differential amp 250kΩ 250kΩ 16 15 FN1 FN2 250kΩ 17 FP2 100kΩ 18 19 MIN BN 20 HIVOLB Figure 3. Block diagram and pin assign Absolute Maximum Ratings (Ta=25˚C) Parameter Power Supply Voltage Input Voltage Power Dissipation Storage Temperature Symbol Rating Unit VCCL 10 V VCCH 18 V VIN VCCL+0.3 to GND-0.3 Only SCL, SDA 7 to GND-0.3 V (Note1) Pd TSTG 1.12 -55 to +150 W ˚C (Note1) This value decreases 9mW/˚C for Ta=25˚C or more. ROHM standard board shall be mounted. Thermal resistance θja = 111.1(˚C /W). ROHM Standard board size：70x70x1.6(㎣) material：A FR4 grass epoxy board(3% or less of copper foil area) Operating Range Parameter Power Supply Voltage Temperature www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 Symbol VCCL VCCH Topr Min 7.0 VCCL -40 4/35 Typ 8.5 17 - Max 9.5 17.8 +85 Unit V V ˚C TSZ02201-0C2C0E100130-1-2 14.NOV.2016 Rev.002 BD37068FV-M Electrical Characteristic (Unless specified particularly, Ta=25˚C, VCCL=8.5V, VCCH=17.0V, f=1kHz, VIN=1VRMS, RG=600Ω, RL=10kΩ, A input, Input Gain 0dB, Gain Adjust +6dB, High-Voltage ON, LPF ON, Fader 0dB, Input point=A1/A2, Monitor point=IG1/IG2) Input Selector General Block Limit Parameter Symbol Typ Max Unit Conditions Current upon no signal (VCCL) IQ_VCCL － 30 43 mA No signal Current upon no signal (VCCH) IQ_VCCH - 7 10 mA No signal Input Impedance (A) RIN_S 70 100 130 kΩ Input Impedance (B, C, D, E, F) RIN_D 175 250 325 kΩ Voltage Gain GV -1.5 +0 +1.5 dB GV=20log(VOUT/VIN) Channel Balance CB -1.5 +0 +1.5 dB CB = GV1-GV2 THD+N － 0.003 0.05 % VNO1 － 3.1 8.0 μVRMS VIM 2.0 2.2 － VRMS (Note1) CTC － -100 -90 dB (Note1) CTS － -100 -90 dB Common Mode Rejection Ratio (Note1) (B, C, D, E, F) CMRR 55 65 － dB Minimum Input Gain GIN MIN -17 -15 -13 dB Input gain -15dB GIN=20log(VOUT/VIN) Maximum Input Gain GIN MAX 21 23 25 dB Input gain 23dB VIN=100mVRMS GIN=20log(VOUT/VIN) Gain Set Error GIN ERR -2 +0 +2 dB GAIN=-15 to +23dB Output Impedance ROUT - － 50 Ω VIN=100mVRMS Maximum Output Voltage VOM 2.0 2.2 － VRMS Total Harmonic Distortion (Note1) Output Noise Voltage Maximum Input Voltage Crosstalk Between Channels Crosstalk Between Selectors Input Gain Min VOUT=1VRMS BW=400-30kHz RG = 0Ω BW = IHF-A VIM at THD+N(VOUT)=1% BW=400-30kHz RG = 0Ω CTC=20log(VOUT/VOUT´) BW = IHF-A RG = 0Ω CTS=20log(VOUT/VOUT´) BW = IHF-A XP1 and XN input XP2 and XN input CMRR=20log(VIN/VOUT) BW = IHF-A, [X=B,C,D,E,F] THD+N=1% BW=400-30kHz (Note1) VP-9690A (Average value detection, effective value display) filter by Panasonic is used for measurement. Input and output are in-phase. Output Block (Unless specified particularly, Ta=25˚C, VCCL=8.5V, VCCH=17.0V, f=1kHz, VIN=0.9VRMS, RG=600Ω, RL=10kΩ, A input, Input Gain 0dB, Gain Adjust +6dB, High-Voltage ON, LPF ON, Fader 0dB, Input point=INF1/INF2/INR1/INR2/INC/INS, Monitor point=OUTF1/OUTF2/OUTR1/OUTR2/OUTC/OUTS) Limit Parameter Symbol Min Typ Max Unit Output Impedance ROUT - － 50 Ω Maximum Output Voltage VOM 5.1 5.2 － VRMS Maximum Output Gain GHout 6.3 8.3 10.3 dB www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 5/35 Conditions VIN=100mVRMS VIN=1VRMS THD+N=1% BW=400-30kHz GHout=20log(VOUT/VIN) TSZ02201-0C2C0E100130-1-2 14.NOV.2016 Rev.002 BD37068FV-M (Unless specified particularly, Ta=25˚C, VCCL=8.5V, VCCH=17.0V, f=1kHz, VIN=0.9VRMS, RG=600Ω, RL=10kΩ, A input, Input Gain 0dB, Gain Adjust +6dB, High-Voltage ON, LPF ON, Fader 0dB, Input point=INF1/INF2/INR1/INR2/INC/INS, Monitor point=OUTF1/OUTF2/OUTR1/OUTR2/OUTC/OUTS) Block Limit Parameter Symbol Typ Max Unit GF BST 21 23 25 dB CB -1.5 +0 +1.5 dB CB = GV1-GV2 THD+N － 0.003 0.05 % BW=400-30kHz VNO1 － 23 40 μVRMS VNOR － 10.5 20 μVRMS VIM 2.0 2.1 － VRMS CTC － -100 -90 dB GF MIN － -100 -90 dB Gain Set Error GF ERR -2 +0 +2 dB Gain=+1 to +23dB Attenuation Set Error 1 GF ERR1 -2 +0 +2 dB Attenuation=0 to -15dB Attenuation Set Error 2 GF ERR2 -3 +0 +3 dB Attenuation=-16 to -47dB Attenuation Set Error 3 GF ERR3 -4 +0 +4 dB Attenuation=-48 to -79dB PSRRVCCL － -70 -40 dB PSRRVCCH － -70 -40 dB Input Impedance RIN_M 70 100 130 kΩ Maximum Input voltage VIM_M 2.0 2.2 - VRMS GMX MIN - -100 -85 dB Mixing Gain GMX -2 +0 +2 dB Input Impedance RIN_M 70 100 130 kΩ Boost Gain GF BST 4 6 8 dB Gain=6dB VIN=100mVRMS GF=20log(VOUT/VIN)-GHout CB -1.5 +0 +1.5 dB CB = GV1-GV2 Channel Balance Total Harmonic Distortion (Note1) Output Noise Voltage (Note1) Residual Output Noise Voltage Maximum Input Voltage Crosstalk Between Channels Maximum Attenuation (Note1) (Note1) Mixing Ripple Rejection Gain Adjust Conditions Gain=23dB VIN=100mVRMS GF=20log(VOUT/VIN)-GHout Gain Adjust=0dB Maximum Boost Gain Fader Min Maximum Attenuation (Note1) Channel Balance RG = 0Ω BW = IHF-A Fader = -∞dB RG = 0Ω BW = IHF-A VIM at THD+N(VOUT)=1% BW=400-30kHz Gain Adjust = 0dB RG = 0Ω CTC=20log(VOUT/VOUT´) BW = IHF-A Fader = -∞dB GF=20log(VOUT/VIN) BW = IHF-A f=1kHz VPSRL=100mVRMS PSRRVCCL=20log(VOUT /VCCL) f=1kHz VPSRH=100mVRMS PSRRVCCH=20log(VOUT/VCCH) VIM at THD+N(VOUT)=1% BW=400-30kHz MIN input Front Mixing OFF GMX=20log(VOUT/VIN) BW=IHF-A MIN input Front Mixing ON GMX=20log(VOUT/VIN)-GHout (Note1) VP-9690A (Average value detection, effective value display) filter by Panasonic is used for measurement. Input and output are in-phase. www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 6/35 TSZ02201-0C2C0E100130-1-2 14.NOV.2016 Rev.002 BD37068FV-M 40 30 35 25 30 20 25 IQ_VCCH [mA] IQ_VCCL + IQ_VCCH [mA]aaaaaaaaaaaaaaaaa Typical Performance Curve(s) 20 15 15 10 10 5 (VCC=VCCL=VCCH) (VCC=VCCL=VCCH) 5 0 0 0 1 2 3 4 5 6 7 8 9 10 0 2 4 6 VCC [V] 8 10 12 14 16 18 VCCH [V] Figure 4. IQ_VCCL+IQ_VCCH vs VCC Figure 5. IQ_VCCH vs VCCH (High-Voltage ON) 10 10 10 8 High-Voltage Mode 1 2 THD+N [%] Gain [dB] 4 0 Normal Mode -2 -4 -6 1 f=10kHz f=100,1kHz 0.1 0.1 0.01 0.01 0.001 0.001 -8 -10 10 100 1k 10k 0.001 100k 0.1 1 10 VIN [VRMS] Frequency [Hz] Figure 6. Gain vs Frequency (Normal / High-Voltage mode) www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 0.01 Figure 7. THD+N, VO vs VIN (Gain Adjust=+6dB) 7/35 TSZ02201-0C2C0E100130-1-2 14.NOV.2016 Rev.002 VO [VRMS] 6 BD37068FV-M 0 0 -20 -20 RG=1kΩ CTC [dB] CMRR [dB] -40 RG=470Ω -40 RG=0Ω -60 -60 -80 -80 -100 -100 -120 10 100 1k 10k 10 100k 100 1k 10k 100k Frequency [Hz] Frequency [Hz] Figure 9. CTC vs Frequency Figure 8. CMRR vs Frequency 5 0 -20 0 -40 -5 Gain [dB] PSRR [dB] LPF Pass -60 -80 LPF ON -10 -15 -100 -20 10 100 1k 10k 100k 10 Frequency [Hz] 1k 10k 100k Frequency [Hz] Figure 10. PSRR vs Frequency www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 100 Figure 11. Gain vs Frequency (LPF ON/Pass) 8/35 TSZ02201-0C2C0E100130-1-2 14.NOV.2016 Rev.002 BD37068FV-M 2 I C-bus Control Signal Specification 1. Electrical specifications and timing for bus lines and I/O stages SDA t BUF t t LOW HD;STA T t SP SCL t t HD;STA t HD;DAT t HIGH S P SU;DAT t SU;STA T t Sr SU;STO T P 2 Figure 12. Definition of timing on the I C-bus 2 Table 1 Characteristics of the SDA and SCL bus lines for I C-bus devices 2 Parameter Fast-mode I C-bus Min Max 400 0 Symbol Unit kHz 1 SCL Clock Frequency fSCL 2 Bus Free time between a STOP and START condition tBUF 1.3 － μsec 3 Hold Time (repeated) START condition. After this period, the first clock pulse is generated tHD;STA 0.6 － μsec 4 5 LOW Period of the SCL Clock HIGH Period of the SCL Clock tLOW tHIGH 1.3 0.6 － － μsec μsec 6 Set-up time for a Repeated START Condition tSU;STA 0.6 － μsec 7 Data Hold Time tHD;DAT 0* － μsec 8 Data set-up Time tSU;DAT 100 － nsec 9 Set-up Time for STOP Condition tSU;STO 0.6 － μsec All values referred to VIH min. and VIL max. Levels (see Table 2). 2 Table 2 Characteristics of the SDA and SCL I/O stages for I C-bus devices 2 Parameter Symbol Fast-mode I C-bus Min Max Unit 10 LOW level input voltage: Fixed input levels VIL -0.5 +1 V 11 HIGH level input voltage: Fixed input levels VIH 2.3 - V 12 Pulse width of spikes, which must be suppressed by the input filter. tSP 0 50 nsec 13 LOW level output voltage (open drain or open collector): At 3mA sink current VOL1 0 0.4 V 14 Input current each I/O pin with an input voltage between 0.4V and 0.9 VDD max. Ii -10 +10 μA ｔHD; STA ：2 µsec ｔHD; DAT ：1 µsec ｔSU; DAT ：1 µsec ｔSU; STO ：2 µsec SCL ｔ BUF ：4 µsec ｔ LOW ：3 µsec ｔ HIGH ：1 µsec SDA SCL clock frequency:250kHz 2 Figure 13. I C data transmission timing www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 9/35 TSZ02201-0C2C0E100130-1-2 14.NOV.2016 Rev.002 BD37068FV-M 2. 2 I C-bus Format S 1bit 3. MSB LSB MSB LSB MSB LSB Slave Address A Select Address A Data A P 8bit 1bit 8bit 1bit 8bit 1bit 1bit S = Start condition (Recognition of start bit) Slave Address = Recognition of slave address. 7 bits in upper order are optional. The last bit must be “L” for writing. A = Acknowledge bit (Recognition of acknowledgement) Select Address = Address for each function Data = Data of each function P = Stop condition (Recognition of stop bit) 2 I C-bus Interface Protocol 1) Basic form S Slave Address MSB LSB A Select Address MSB LSB A Data A MSB LSB P 2) Automatic increment(Select Address increases (+1) according to the number of data) S Slave Address A Select Address A Data1 A Data2 A ････ Data N A MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB (Example)①Data 1 shall be set as data of address specified by Select Address. ②Data 2 shall be set as data of address specified by Select Address +1. ③Data N shall be set as data of address specified by Select Address +(N-1). 3) Configuration unavailable for transmission (In this case, only Select Address 1 is set.) S Slave Address A Select Address1 A Data A Select Address 2 A Data A MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB (Note)If any data is transmitted as Select Address 2 next to data, It is recognized as data, not as Select Address 2. 4. P P Slave Address MSB A6 1 A5 0 A4 0 www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 A3 0 A2 0 A1 0 10/35 A0 0 LSB R/W 0 80(hex) TSZ02201-0C2C0E100130-1-2 14.NOV.2016 Rev.002 BD37068FV-M 5. Select Address & Data Items Select Address (hex) MSB Data D7 D6 D5 D4 LSB D3 D2 D1 D0 Initial Setup 1 01 Advanced switch ON/OFF 0 Advanced switch time of Input Gain/Fader 0 0 0 0 Initial Setup 2 02 0 0 Sub Selector 0 0 Rear Selector Front Selector Input Selector 05 0 0 0 Input Gain 06 0 0 Fader 1ch Front 28 Fader Gain / Attenuation Fader 2ch Front 29 Fader Gain / Attenuation Fader 1ch Rear 2A Fader Gain / Attenuation Fader 2ch Rear 2B Fader Gain / Attenuation Fader Center 2C Fader Gain / Attenuation Fader Subwoofer 2D Fader Gain / Attenuation LPF setup Mixing 30 Front Mixing ON/OFF LPF fc 0 0 0 0 Sub Gain Adjust Main Gain Adjust System Reset FE 1 0 0 0 0 0 0 1 0 Input Selector Input Gain Advanced switch Note) Set up bit (It is written with “0” by the above table) which hasn’t been used in “0”. Notes on data format 1. “Advanced switch” function is available for the hatched parts on the above table. 2. In case of transferring data continuously, Select Address (hex) flows by Automatic increment function, as shown below. →01→02→05→06→28→29→2A→2B→2C→2D→30 3. Input selector that is not corresponded for “Advanced switch” function, cannot reduce the noise caused when changing the input selector. Therefore, it is recommended to turn on mute when changing these settings. 4. In case of setting to infinite “-∞” by using Fader when input selector setting is changed, please consider “Advanced switch” time. www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 11/35 TSZ02201-0C2C0E100130-1-2 14.NOV.2016 Rev.002 BD37068FV-M Select Address 01 (hex) Mode MSB D7 D6 Advanced switch ON/OFF 0 D6 OFF MSB D7 0 ON 1 4.7 msec 7.1 msec 11.2 msec 14.4 msec Mode 0 D5 0 0 1 1 Advanced switch time of Input Gain/Fader D4 D3 0 1 0 0 1 LSB D2 D1 D0 0 0 0 D1 LSB D0 0 0 D1 Rear Selector LSB D0 0 1 D1 0 1 LSB D0 Front Selector D2 D1 LSB D0 0 Rear Selector Front Selector Advanced switch ON/OFF D5 D4 D3 D2 Advanced switch time of Input 0 0 Gain/Fader Select Address 02 (hex) Mode MSB D7 D6 FRONT INSIDE THROUGH 0 0 Mode MSB D7 D6 REAR FRONT COPY 0 0 MSB D7 D6 Mode (Note1) OUTC(INS) OUTS(INS) OUTC(INR1) OUTS(INR2) OUTC (INC) OUTS(INS) 0 Prohibition 0 Front Selector D4 D3 D5 Sub Selector Rear Selector D4 D3 D5 Sub Selector 0 Sub Selector D4 D3 D5 0 0 0 1 1 0 1 1 (Note1) xxx(INxx) : “xxx” means “Output terminal”, “(INxx)” means “Output signal” www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 0 12/35 0 D2 0 D2 0 : Initial condition TSZ02201-0C2C0E100130-1-2 14.NOV.2016 Rev.002 BD37068FV-M Select Address 05(hex) Mode A B single C single D single E single F single C diff D diff E diff F full-diff B diff MSB D7 D6 D5 0 0 0 Input Selector D4 D3 0 0 0 0 0 0 0 0 0 1 1 1 Prohibition D2 0 0 0 0 1 1 1 1 0 0 0 LSB D0 0 1 0 1 0 1 0 1 0 1 0 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 1 ： ： ： ： 1 1 1 1 : Initial condition List of active input terminal when set input selector Lch positive Lch negative Mode input terminal input terminal A 1pin(A1) - Rch positive input terminal 2pin(A2) Rch negative input terminal - B single 3pin(BP1) - 4pin(BP2) - C single 5pin(CP1) - 7pin(CP2) - D single 8pin(DP1) - 10pin(DP2) - E single 11pin(EP1) - 13pin(EP2) - F single 14pin(FP1) - 17pin(FP2) - B diff 3pin(BP1) 19pin(BN) 4pin(BP2) 19pin(BN) C diff 5pin(CP1) 6pin(CN) 7pin(CP2) 6pin(CN) D diff 8pin(DP1) 9pin(DN) 10pin(DP2) 9pin(DN) E diff 11pin(EP1) 12pin(EN) 13pin(EP2) 12pin(EN) F full-diff 14pin(FP1) 15pin(FN1) 17pin(FP2) 16pin(FN2) 〔About Ground Isolation Amplifier〕 EP1 1ch Signal Input Ground Isolation Amplifier ：B diff to E diff 11 EN 1ch GND Isolation Amplifier 12 Please select this mode when you use them as a ground isolation amplifier. EP2 2ch Signal Input 13 2ch GND Isolation Amplifier FP1 1ch Signal Input Full Differential Amplifier : F full-diff 14 FN1 15 Please select this mode when you use it as a differential amplifier 1ch Differential Amplifier FN2 16 2ch Signal Input FP2 17 2ch Differential Amplifier Figure 14. About Ground Isolation Amplifier www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 13/35 TSZ02201-0C2C0E100130-1-2 14.NOV.2016 Rev.002 BD37068FV-M Select Address 06 (hex) Mode MSB D7 D6 0 0 Prohibition +23dB +22dB +21dB +20dB +19dB +18dB +17dB +16dB +15dB +14dB +13dB +12dB +11dB +10dB +9dB +8dB +7dB +6dB +5dB +4dB +3dB +2dB +1dB 0dB -1dB -2dB -3dB -4dB -5dB -6dB -7dB -8dB -9dB -10dB -11dB -12dB -13dB -14dB -15dB Prohibition Input Gain D4 D3 0 0 ： ： 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 ： ： 1 1 D5 0 ： 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ： 1 D2 0 ： 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 ： 1 D1 0 ： 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 ： 1 LSB D0 0 ： 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 ： 1 : Initial condition www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 14/35 TSZ02201-0C2C0E100130-1-2 14.NOV.2016 Rev.002 BD37068FV-M Select Address 28, 29, 2A, 2B, 2C, 2D (hex) MSB Gain & ATT D7 D6 Fader Gain / Attenuation D4 D3 D5 D2 D1 LSB D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ： ： ： ： ： ： ： ： 0 1 1 0 1 0 0 0 +23dB 0 1 1 0 1 0 0 1 +22dB 0 1 1 0 1 0 1 0 +21dB ・ ・ ・ +10dB 0 ・ ・ ・ 0 1 ・ ・ ・ 1 1 ・ ・ ・ 1 0 ・ ・ ・ 1 1 ・ ・ ・ 0 0 ・ ・ ・ 1 1 ・ ・ ・ 1 1 ・ ・ ・ 0 +9dB 0 1 1 1 0 1 1 1 +8dB 0 1 1 1 1 0 0 0 +7dB 0 1 1 1 1 0 0 1 +6dB 0 1 1 1 1 0 1 0 +5dB 0 1 1 1 1 0 1 1 +4dB 0 1 1 1 1 1 0 0 +3dB 0 1 1 1 1 1 0 1 +2dB 0 1 1 1 1 1 1 0 +1dB 0 1 1 1 1 1 1 1 0dB 1 0 0 0 0 0 0 0 -1dB 1 0 0 0 0 0 0 1 -2dB 1 0 0 0 0 0 1 0 -3dB 1 0 0 0 0 0 1 1 ・・ ・・ ・・ ・・ ・・ ・・ ・・ ・・ ・・ ・・ ・・ ・・ ・・ ・・ ・・ ・・ ・・ ・・ -78dB 1 1 0 0 1 1 1 0 -79dB 1 1 0 0 1 1 1 1 1 1 0 1 0 0 0 0 ： ： ： ： ： ： ： ： 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 Prohibition Prohibition -∞dB : Initial condition www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 15/35 TSZ02201-0C2C0E100130-1-2 14.NOV.2016 Rev.002 BD37068FV-M Select Address 30(hex) Mode 0dB +6dB Mode 0dB +6dB Mode 70kHz PASS MSB D7 Front Mixing MSB D7 Front Mixing MSB D7 Front Mixing OFF MSB D7 0 ON 1 Mode Main Gain Adjust D4 D3 D6 D5 LPF fc 0 D6 D5 LPF fc 0 0 D6 0 D5 0 0 0 Sub Gain Adjust D4 D3 D2 D1 0 Sub Gain Adjust D2 D1 0 0 0 D4 D3 D2 D1 0 0 0 Sub Gain Adjust D2 D1 0 Sub Gain Adjust 1 LPF fc 1 D6 D5 LPF fc 0 Front Mixing D4 0 ON/OFF D3 0 LSB D0 0 1 LSB D0 Main Gain Adjust LSB D0 Main Gain Adjust LSB D0 Main Gain Adjust : Initial condition www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 16/35 TSZ02201-0C2C0E100130-1-2 14.NOV.2016 Rev.002 BD37068FV-M 6. About power on reset It is possible for the reset circuit inside the IC to initialize when supply voltage is turned on. Please send data to all address as initial data when the supply is turned on, and turn on mute until all initial data are sent. Item Symbol Rise time of VCC VCC voltage of release power on reset 7. Limit Unit tRISE Min 33 Typ － Max － µsec VPOR － 4.1 － V Condition VCC rise time from 0V to 5V About start-up and power off sequence on IC By setting the terminal voltage of HIVOLB, it is possible to change the output gain. At the same time, output DC voltage will also be changed at each mode. HIVOLB terminal voltage High-Voltage GND to 1.0V 2.3V to VCCL ON OFF Please set HIVOLB terminal voltage between the ranges showed by the above tables. If HIVOLB terminal is open, the terminal voltage will be set to 5V due to the pull-up voltage inside the IC. In this case, the IC will be set to “High-Voltage OFF” mode. The relationship between DC Bias and Output Gain to the configuration of HIVOLB terminal shows as the following table. VCCH Supplied Voltage 8.5 V 17 V HIVOLB Terminal Voltage Open (5 V) (High-Voltage OFF) 0V (High-Voltage ON) Output DC Bias Voltage 4.15 V 8.35 V Output Gain 0 dB 8.3 dB If HIVOLB terminal voltage is changed during its operation, Output DC voltage will be also changed shown as above. For reducing these variations, turn the power on after setting the status of the HIVOLB terminal according to the output gain. The start-up and power off sequence is shown next. . VCCL /VCCH VCCH 3.0V ～ ～ OFF Voltage 1.0V ～ ～ VCCL 5.0V ～ ～ 1.0V t2 t1 t2 POR Max ～ ～ 1.0V 2 I C-bus Select Address 01(hex) External MUTE 3.0V POR Min ～ ～ 1.0V Mode = High-Voltage ON HIVOLB 20msec ～ ～ OFF Voltage t1h t2h Mode = High-Voltage OFF HIVOLB I2C-bus Select Address 01(hex) t2-t1≧250µsec t1h-t2≧0µsec t3-t2h≧0µsec ～ ～ VCCL Typ POR Max POR Min t1 ～ ～ 7.0V 5.0V 1.0V 16.7V ～ ～ t2-t1≧250µsec ～ ～ 7.0V ～ ～ VCCH Typ VCC Typ 200msec t3 External MUTE start-up normal term power off start-up normal term power off Normal mode operation (HIVOLB terminal = OPEN) High-Voltage mode operation Figure 15. Power off and start-up sequence in each mode 2 This IC will become active-state by sending data of Select Address 01(hex) on I C-bus. Therefore, this command must always send in start-up sequence. In addition, External MUTE means recommended period that the muting outside IC. In addition, the starting sequence of VCCL and VCCH does not have the limit, but please start VCCL earlier to reduce a pop noise. About HIVOLB terminal, but measures have been made spike removal, please note that the IC may accept when receiving input more than 50nsec. www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 17/35 TSZ02201-0C2C0E100130-1-2 14.NOV.2016 Rev.002 BD37068FV-M Fader Volume Attenuation of the Detail (dB) +23 +22 +21 +20 +19 +18 +17 +16 +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 -16 -17 -18 -19 -20 -21 -22 -23 -24 -25 -26 -27 -28 D7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D4 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 D3 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 D2 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 D1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 D0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 (dB) -29 -30 -31 -32 -33 -34 -35 -36 -37 -38 -39 -40 -41 -42 -43 -44 -45 -46 -47 -48 -49 -50 -51 -52 -53 -54 -55 -56 -57 -58 -59 -60 -61 -62 -63 -64 -65 -66 -67 -68 -69 -70 -71 -72 -73 -74 -75 -76 -77 -78 -79 -∞ D7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D5 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 D4 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 D3 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 D2 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 D1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 D0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 ：Initial condition www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 18/35 TSZ02201-0C2C0E100130-1-2 14.NOV.2016 Rev.002 BD37068FV-M About bias voltage of output terminal(27,28,35 to 40pin) vs. VCC Bias voltage of output terminal (27,28,35 to 40pin) keep fixed voltage in operational range of VCC. OUT(27,28,35 to 40pin)_DC-Bias = 4.15V fixed. (High-Voltage = OFF) Figure 16. OUT(27,28,35 to 40pin)_DC-Bias = 4.15V fixed. (High-Voltage Mode = OFF) OUT(35 to 40pin)_DC-Bias = 8.35V fixed. (High-Voltage = ON,VCCH=17V) Figure 17. OUT(35 to 40pin)_DC-Bias = 8.35V fixed. (High-Voltage Mode = ON, VCCH=17V) OUT(35 to 40pin)_DC-Bias = 8.35V fixed (VCCH=10 to 17.8V). (High-Voltage = ON, VCCL=7 to 9.5V) Figure 18. OUT(35 to 40pin)_DC-Bias = 8.35V fixed(VCCH=10 to 17.8V). (High-Voltage Mode = ON, VCCL=7 to 9.5V) www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 19/35 TSZ02201-0C2C0E100130-1-2 14.NOV.2016 Rev.002 BD37068FV-M About Advanced Switch Circuit 【1】Advanced switch technology 1-1. Advanced switch effects Advanced switch technology is ROHM original technology that can prevent from switching pop noise. If changing the gain setting (for example Fader) immediately, the audible signal will become discontinuously and pop noise will be occurred. This Advanced switch technology will prevent this discontinuous signal by completing the signal waveform and will significantly reduce the noise. select slave I2 C-bus 80 28 data 86 If the gain instantly changes after the data is transmitted, the DC fluctuation will occur as much as before and after the oscillation different. This technology makes this fluctuation changes slow. DC level change Advanced switch waveform Figure 17. The explanation of advanced switch waveform This Advanced switch circuit will start operating when the data is transmitted from microcontroller. Advanced switch waveform is shown as the figure above. For preventing switching noise, this IC will operate optimally by internal processing after the data is transmitted from microcontroller. However, sometimes the switching waveform is not like the intended form depends on the transmission timing. Therefore, below is the example of the relationship between the transmission timing and actual switching time. Please consider this relationship for the setting. 1-2. The kind of the Transferring Data ・Data setting that is not corresponded to Advanced switch (Page11 Select Address & Data Data format without hatching) There is no particular rule about transferring data. ・Data setting that is corresponded to Advanced switch （Page11 Select Address & Data Data format with hatching） There is no particular rule about transferring data, but Advanced switch must follow the switching sequence as mentioned in【2】as follows. www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 20/35 TSZ02201-0C2C0E100130-1-2 14.NOV.2016 Rev.002 BD37068FV-M 【2】Data transmission that is corresponded to Advanced switch 2-1. Switching time of Advanced switch Switching time includes [tWAIT(Wait time)], [tSFT(A→B switching time)] and [tSFT(B→A switching time)]. 25msec is needed per 1 switching. (tSOFT = tWAIT + 2 * tSFT, tWAIT =2.3msec, tSFT =11.2msec) [wait time] =tWAIT Current XdB Send YdB [A→B switching time] =tSFT [B→A switching time] =tSFT A→B B→A Change YdB W Advanced Switch Time (tSOFT) In the figure above, Start/Stop state is expressed as “A” and temporary state is expressed as “B”. The switching sequence of Advanced switch consists of the cycle “A(start)→B(temporary)→A(stop)”. Therefore, switching sequence will not stop at B state. For example, switching is performed from A(Initial gain)→B(set gain)→A(set gain) when switching from initial gain to set gain. And switching time (tSFT) of A→B or B→A are equal. 2-2. About the data transmission’s timing in same block state and switching operation ■ Transmitting example 1 This is an example when transmitting data in same block with “enough interval for data transmission”. (enough interval for data transmission : 1.4 x tSOFT * ”1.4” includes tolerance margin.) Definition of example expression : F1=Fader 1ch Front, F2=Fader 2ch Front, R1=Fader 1ch Rear, R2=Fader 2ch Rear C=Fader Center, S=Fader Subwoofer, MIX=Front Mixing slave I2C-bus select 80 data ack 28 80 (F1 0dB) 80 28 FF (F1 -∞dB) Tsoft * 1.4 msec W Advanced Switch time A→B B→A W A→B B→A F1 output ■ Transmitting example 2 This is an example when the transmission interval is not enough (smaller than “Transmission example 1”). When the data is transmitted during first switching operation, the second data will be reflected after the first switching operation. In this case, there is no wait time (tWAIT) before the second switching operation. slave I2C-bus Advanced Switch time select 80 data 28 80 (F1 0dB) ack 80 28 FF (F1 -∞dB) W A→B B→A A→B B→A F1 output www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 21/35 TSZ02201-0C2C0E100130-1-2 14.NOV.2016 Rev.002 BD37068FV-M ■ Transmitting example 3 This is an example of switching operation when transmission interval is smaller than “Transmission example 2”). When the data is transmitted during the first switching operation, and transmission timing is just during A→B switching operation, the second data will be reflected at B→A switching term. slave I2C-bus select 80 data 28 80 (F1 0dB) ack 80 28 FF (F1 -∞dB) W Advanced Switch time A→B B→A F1 output ■ Transmitting example 4 The below figure shows an example of switching operation that the data are transmitted serially with smaller transmission interval than “Transmission example 3”. IC has internal data-storage buffer and buffer transmitted data as storage data constantly. However, only the latest data is kept so, in this example, +4dB data transmitted secondly is ignored. slave I2C-bus select 80 data ack 28 80 (F1 0dB) 80 28 7C (F1 +4dB) W Advanced Switch time 80 28 FF (F1 -∞dB) B→A A→B A→B B→A F1 output ■ Transmitting example 5 Transmitted data is firstly buffered and written to setting data which set gain. However, when there is no difference between transmitted data and setting data such as refresh data, advanced switch operation doesn’t start. slave I2C-bus select 80 data ack 28 80 (F1 0dB) 80 28 80 (F1 0dB) Refresh Data F1 Advanced Switch Advanced Switch time www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 W A→B B→A 22/35 TSZ02201-0C2C0E100130-1-2 14.NOV.2016 Rev.002 BD37068FV-M 2-3. Mixing ON/OFF switching operation of Front mixing The action of the Mixing switching waveform is different in OFF to ON or ON to OFF. ■ Transmission example 1 This is an example of Mixing OFF to ON state. slave I2C-bus select 80 data ack 30 80 (MIX ON) A→B W Advanced Switch time B→A F1 output This is an example of Mixing ON to OFF state slave I2C-bus select data ack 80 30 00 (MIX OFF) W Advanced Switch time A→B B→A F1 output ■ Transmission example 2 This is an example when transmission ON to OFF in short interval during to Mixing switching operation. This is an example of in case of transmitted data of another status(MIX OFF) in during A→B transmission timing. slave I2C-bus select 80 data 30 80 (MIX ON) W Advanced Switch time ack 80 30 00 (MIX OFF) A→B B→A F1 output This is an example of in case of transmitted data of another status(MIX OFF) in during B→A transmission timing. slave I2C-bus Advanced Switch time select 80 data ack 30 80 (MIX ON) W 80 30 00 (MIX OFF) A→B B→A A→B B→A F1 output www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 23/35 TSZ02201-0C2C0E100130-1-2 14.NOV.2016 Rev.002 BD37068FV-M ■ Transmission example 3 This is an example when transmission OFF to ON in short interval during to Mixing switching operation. This is an example of in case of transmitted data of another status(MIX ON) in during A→B transmission timing. slave I2C-bus select data ack 80 30 00 (MIX OFF) 80 W Advanced Switch time 30 80 (MIX ON) A→B B→A F1 output This is an example of in case of transmitted data of another status(MIX ON) in during B→A transmission timing. slave I2C-bus select data ack 80 30 00 (MIX OFF) Advanced Switch time W 80 A→B 30 80 (MIX ON) B→A A→B B→A F1 output 2-3. About the data transmitting timing and the switching movement in several block state When data are transmitted to several blocks, treatment in the BS (block state) unit is carried out inside the IC. The order of advanced switch movement start is decided in advance dependent on BS. S0 S1 S２ S３ Input Gain Mixing Fader R1 Fader C 06(hex) 30(hex) 2A(hex) 2C(hex) Fader F1 Fader R2 Fader S 28(hex) 2B(hex) 2D(hex) Fader F2 Select address 29(hex) The order of advanced switch start Note) It is possible that blocks in the same BS start switching at the same timing. www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 24/35 TSZ02201-0C2C0E100130-1-2 14.NOV.2016 Rev.002 BD37068FV-M ■ Transmitting example 1 About the transmission to several blocks also, as explained in the previous section, though there is no restriction of the 2 I C- bus data transmitting timing, the start timing of switching follows the figure of previous page, The order of advanced switch start. Therefore, it isn't based on the data transmitting order, and an actual switching order becomes as the figure of previous page, “The order of advanced switch start”. Each block data is being transmitted separately in the transmitting example 5, but it becomes the same result even if data are transmitted by automatic increment. slave I2C-bus select 80 data 28 80 (F1 0dB) ack 80 2A 80 (R1 0dB) 80 2C 80 (C 0dB) F1 Advanced Switch W Advanced Switch time A→B R1 Advanced Switch B→A A→B B→A C Advanced Switch A→B B→A F1 output R1 output C output ■ Transmitting example 2 In the case that data transmission order and actual switching order is different, or data is transmitted to the block in other BS before the advanced switch operation finished, switching of next BS starts after current switching. 80 ① xx ex：①F1 -6dB ②F1 -20dB ③C -6dB ④R1 -6dB ｘｘ ② ③ ④ I2C-bus F1 Advanced Switch Advanced Switch time W A→B B→A R1 Advanced Switch A→B B→A C Advanced Switch A→B B→A A→B B→A Active channel Active channel Output F1 F1 Advanced Switch Initial Initial → ① ① ①→② ② Active channel Output R1 Initial Initial → ④ ④ Active channel Output C Initial www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 Initial → ③ 25/35 ③ TSZ02201-0C2C0E100130-1-2 14.NOV.2016 Rev.002 BD37068FV-M Application Circuit Diagram VCCL 10µF OUTC OUTS OUTR1 OUTR2 OUTF1 OUTF2 INF2 10µF 10µF INF1 INR2 INR1 INS INC IG1 VCCH IG2 GND SDA SCL 10µF 10µF 10µF 10µF 10µF 2.2µF 2.2µF 2.2µF 2.2µF 10µF 2.2µF 10µF 2.2µF 10µF VREF 40 39 38 37 36 35 Level Shift Level Shift Level Shift Level Shift Level Shift 34 33 32 31 28 29 30 27 26 Level Shift 100kΩ 100kΩ 100kΩ 100kΩ 100kΩ 24 25 VREF 100kΩ 22 23 21 I2C-bus LOGIC Front mixing Sub Selector ★ ★ ■Fader : +23dB to -79dB、-∞/1dBstep ■Input Gain : +23dB to -15dB/1dBstep Fader Fader Fader Fader Fader Fader ATT★ ATT★ ATT★ ATT★ ATT★ ATT★ Sub Gain adjust Main Gain adjust ■Front Mixing : on/off ★ Advanced Switch 2nd order LPF Fader Fader Fader Fader Fader Fader Boost★ Boost★ Boost★ Boost★ Boost★ Boost★ ■2nd order LPF: fc=70kHz ■Main/Sub Gain Adjust 0dB/6dB Rear Selector ■Anti-TDMA noise circuit ■High-Voltage Output Front Selector ★ Input Gain Input selector (1 single - end and 5 stereo ISO) 100kΩ 1 100kΩ 250kΩ 2 2.2µF A1 A2 250kΩ 3 2.2µF GND ISO amp GND ISO amp GND ISO amp 250kΩ 250kΩ 4 2.2µF BP1 GND ISO amp 250kΩ 5 2.2µF BP2 6 2.2µF CP1 GND ISO amp 250kΩ 250kΩ 7 10µF CN 8 2.2µF CP2 GND ISO amp 250kΩ 9 2.2µF DP1 DN GND ISO amp 250kΩ 250kΩ 11 10 10µF 2.2µF DP2 250kΩ 12 2.2µF EP1 Differential amp GND ISO amp 250kΩ 13 10µF EN 250kΩ 250kΩ 14 FP1 250kΩ 16 15 2.2µF 2.2µF EP2 Differential amp 10µF FN1 250kΩ 17 10µF FN2 100kΩ 18 2.2µF FP2 19 20 2.2µF 10µF MIN BN HIVOLB Figure 20. Application Circuit Diagram Notes on wiring ①Please connect the decoupling capacitor of a power supply as close as possible to GND. ②Lines of GND shall be one-point connected. ③Wiring pattern of Digital shall be away from that of analog unit and cross-talk shall not be acceptable. ④Lines of SCL and SDA of I2C-bus shall not be parallel if possible. The lines shall be shielded, if they are adjacent to each other. ⑤Lines of analog input shall not be parallel if possible. The lines shall be shielded, if they are adjacent to each other. www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 26/35 TSZ02201-0C2C0E100130-1-2 14.NOV.2016 Rev.002 BD37068FV-M Thermal Derating Curve About the thermal design by the IC Characteristics of an IC have a great deal to do with the temperature at which it is used, and exceeding absolute maximum ratings may degrade and destroy elements. Careful consideration must be given to the heat of the IC from the two standpoints of immediate damage and long-term reliability of operation. Reference data SSOP-B40 1.5 Measurement condition: ROHM Standard board board Size：70mm x 70mm x 1.6mm material：A FR4 grass epoxy board (3% or less of copper foil area) Power Dissipation Pd (W) 1.12W 1.0 θja = 111.1˚C /W 0.5 0.0 0 25 50 75 85 100 125 150 Ambient Temperature Ta（˚C） Figure 21. Temperature Derating Curve Note) Values are actual measurements and are not guaranteed. Note) Power dissipation values vary according to the board on which the IC is mounted. www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 27/35 TSZ02201-0C2C0E100130-1-2 14.NOV.2016 Rev.002 BD37068FV-M I/O Equivalence Circuit Terminal No Terminal Name Terminal Voltage 1 A1 4.15V 2 A2 29 INC 30 INS 31 INR1 32 INR2 33 INF1 34 INF2 18 MIN 3 BP1 4 BP2 5 CP1 6 CN 7 CP2 8 DP1 9 DN 10 DP2 11 EP1 12 EN 13 EP2 14 FP1 15 FN1 16 FN2 17 FP2 19 BN 27 IG2 28 IG1 Equivalent Circuit Terminal Description Terminal for signal input VCCL The input impedance is 100kΩ(Typ). . 100kΩ GND Input terminal 4.15V Single/Differential mode is selectable. The input impedance is 250kΩ(Typ). VCCL 250kΩ GND 4.15V Input Gain output terminal VCCL GND 35 OUTF2 36 OUTF1 37 OUTR2 38 OUTR1 39 OUTS 40 OUTC 8.35/4.15V Fader output terminal High-Voltage OFF : 4.15V High-Voltage ON : 8.35V VCCH GND The figures in the pin explanation and input/output equivalent circuit is designed value, it doesn’t guarantee the value. www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 28/35 TSZ02201-0C2C0E100130-1-2 14.NOV.2016 Rev.002 BD37068FV-M Terminal No Terminal Name Terminal Voltage 20 HIVOLB 5V Equivalent Circuit Terminal Description Output gain control terminal VCCL 5V Low(0V supply) : High-Voltage ON High(terminal open) : High-Voltage OFF 100kΩ 1.65V GND 21 VCCH 17/8.5V 26 VCCL 8.5V 22 SCL － Power supply terminal 2 Terminal for clock input of I C-bus communication VCCL Note: When this pin is shorted to next pin(VCCH), it may result in property degradation and destruction of the device. 1.65V GND 23 SDA － 2 Terminal for data input of I C- bus communication VCCL 1.65V GND 24 GND 25 VREF Ground terminal 0V 4.15V BIAS terminal VCCL 12.5kΩ 4.15V Voltage for reference bias of analog signal system. The simple precharge circuit and simple discharge circuit for an external capacitor are built in. GND The figures in the pin explanation and input/output equivalent circuit is designed value, it doesn’t guarantee the value. www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 29/35 TSZ02201-0C2C0E100130-1-2 14.NOV.2016 Rev.002 BD37068FV-M Application Information 1. Absolute maximum rating voltage When voltage is impressed to VCCL/VCCH exceeding absolute-maximum-rating voltage, circuit current increase rapidly, and it may result in property degradation and destruction of a device. When impressed by a VCCL terminal (26pin) especially by serge examination etc., even if it includes an of operation voltage +serge pulse component, be careful not to impress voltage (about 14V VCCL terminal) greatly more than absolute-maximum-rating voltage. And, be careful that there is no more than 18V VCCH terminal (21pin) also one. 2. About a signal input part In the signal input terminal, the value of the input coupling capacitor C(F) should be sufficient impedance RIN(Ω) inside the IC. The first HPF characteristic of CR is as shown below. to match the value of input G[dB] C [F] 0 A(f) G RIN f A(f)= Frequency[Hz] 2 (2πf・C・RIN) 1+(2πf・C・RIN)2 Figure 22. Input Equivalent Circuit About output load characteristics The usages of load for output are below (reference). Please use the load more than 10 kΩ(Typ). VO,max [VRMS] Output terminal Terminal Terminal No. Name 28 IG1 27 IG2 Terminal No. 36 35 Terminal Name OUTF1 OUTF2 Terminal No. 38 37 3 6 2.5 5 2 4 VO,max [VRMS] 3. 1.5 IG1/IG2 VCCL=8.5V VCCH=17.0V THD+N=1% f=1kHz BW=400 to 30kHz 1 0.5 1k 10k Load Resistance [Ω] Terminal Name OUTC OUTS OUTF1/F2/R1/R2/C/S VCCL=8.5V VCCH=17.0V THD+N=1% f=1kHz BW=400 to 30kHz 1 100k Terminal No. 40 39 3 2 0 100 Terminal Name OUTR1 OUTR2 0 100 1k 10k 100k Load Resistance [Ω] Figure 23. Output load characteristic at VCCL=8.5V, VCCH=17.0V(Reference) www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 30/35 TSZ02201-0C2C0E100130-1-2 14.NOV.2016 Rev.002 BD37068FV-M Application Information - continued 4. About HIVOLB terminal(20pin) when power supply is off Any voltage shall not be supplied to HIVOLB terminal (20pin) when power-supply is off. Please insert a resistor (about 2.2kΩ) to HIVOLB terminal in series, if voltage is supplied to HIVOLB terminal in case. 5. About signal input terminals Because the inner impedance of the terminal becomes 100 kΩ or 250 kΩ when the signal input terminal makes a terminal open, the plunge noise from outside sometimes becomes a problem. When there is an unused signal input terminal, design so it is shorted to ground. 6. About changing gain of Input Gain and Fader Volume In case of the boost of the input gain and fader volume when changing to the high gain which exceeds 20 dB especially, the switching pop noise sometimes becomes big. In this case, we recommend changing every 1 dB step without changing a gain at once. Also, the pop noise sometimes can reduce by making advanced switch time long, too. 7. About inter-pin short to VCCH VCCH terminal(21pin) is assumed that applied high voltage(17.8V MAX) for realization of 5.2VRMS (MAX) output. And so, avoid short between VCCH and SCL, other. When Inter-pin shorts, circuit current increase rapidly, and it may result in property degradation and destruction of a device. www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 31/35 TSZ02201-0C2C0E100130-1-2 14.NOV.2016 Rev.002 BD37068FV-M Operational Notes 1. Reverse Connection of Power Supply Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when connecting the power supply, such as mounting an external diode between the power supply and the IC’s power supply pins. 2. Power Supply Lines Design the PCB layout pattern to provide low impedance supply lines. Separate the ground and supply lines of the digital and analog blocks to prevent noise in the ground and supply lines of the digital block from affecting the analog block. Furthermore, connect a capacitor to ground at all power supply pins. Consider the effect of temperature and aging on the capacitance value when using electrolytic capacitors. 3. Ground Voltage Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition. 4. Ground Wiring Pattern When using both small-signal and large-current ground traces, the two ground traces should be routed separately but connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal ground caused by large currents. Also ensure that the ground traces of external components do not cause variations on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance. 5. Thermal Consideration Should by any chance the maximum junction temperature rating be exceeded the rise in temperature of the chip may result in deterioration of the properties of the chip. In case of exceeding this absolute maximum rating, increase the board size and copper area to prevent exceeding the maximum junction temperature rating. 6. Recommended Operating Conditions These conditions represent a range within which the expected characteristics of the IC can be approximately obtained. The electrical characteristics are guaranteed under the conditions of each parameter. 7. Inrush Current When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may flow instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power supply. Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring, and routing of connections. 8. Operation Under Strong Electromagnetic Field Operating the IC in the presence of a strong electromagnetic field may cause the IC to malfunction. 9. Testing on Application Boards When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may subject the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply should always be turned off completely before connecting or removing it from the test setup during the inspection process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during transport and storage. www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 32/35 TSZ02201-0C2C0E100130-1-2 14.NOV.2016 Rev.002 BD37068FV-M Operational Notes – continued 10. Inter-pin Short and Mounting Errors Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin. Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) and unintentional solder bridge deposited in between pins during assembly to name a few. 11. Regarding the Input Pin of the IC This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a parasitic diode or transistor. For example (refer to figure below): When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode. When GND > Pin B, the P-N junction operates as a parasitic transistor. Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be avoided. Resistor Transistor (NPN) Pin A Pin B C E Pin A N P+ P N N P+ N Parasitic Elements N P+ N P N P+ B N C E Parasitic Elements P Substrate P Substrate Parasitic Elements Pin B B GND Parasitic Elements GND GND N Region close-by GND Figure 24. Example of monolithic IC structure www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 33/35 TSZ02201-0C2C0E100130-1-2 14.NOV.2016 Rev.002 BD37068FV-M Ordering Name Selection B D 3 7 0 6 8 F V Package FV: SSOP-B40 Part Number ‐ ME 2 Product Rank M: for Automotive Packaging and forming specification E2: Embossed tape and reel (SSOP-B40) Physical Dimension Tape and Reel Information Marking Diagram SSOP-B40(TOP VIEW) Part Number Marking BD37068FV LOT Number 1PIN MARK www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 34/35 TSZ02201-0C2C0E100130-1-2 14.NOV.2016 Rev.002 BD37068FV-M Revision History Date Revision 13.MAR.2014 14.NOV.2016 001 002 Changes New Release ・Additional specification about advanced switch operation ・Additional specification of power supply sequence ・Change document style of specification www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 35/35 TSZ02201-0C2C0E100130-1-2 14.NOV.2016 Rev.002 Notice Precaution on using ROHM Products 1. (Note 1) If you intend to use our Products in devices requiring extremely high reliability (such as medical equipment , aircraft/spacecraft, nuclear power controllers, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or serious damage to property (“Specific Applications”), please consult with the ROHM sales representative in advance. Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any ROHM’s Products for Specific Applications. (Note1) Medical Equipment Classification of the Specific Applications JAPAN USA EU CHINA CLASSⅢ CLASSⅡb CLASSⅢ CLASSⅢ CLASSⅣ CLASSⅢ 2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which a failure or malfunction of our Products may cause. The following are examples of safety measures: [a] Installation of protection circuits or other protective devices to improve system safety [b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure 3. Our Products are not designed under any special or extraordinary environments or conditions, as exemplified below. Accordingly, ROHM shall not be in any way responsible or liable for any damages, expenses or losses arising from the use of any ROHM’s Products under any special or extraordinary environments or conditions. If you intend to use our Products under any special or extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of product performance, reliability, etc, prior to use, must be necessary: [a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents [b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust [c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2 [d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves [e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items [f] Sealing or coating our Products with resin or other coating materials [g] Use of our Products without cleaning residue of flux (even if you use no-clean type fluxes, cleaning residue of flux is recommended); or Washing our Products by using water or water-soluble cleaning agents for cleaning residue after soldering [h] Use of the Products in places subject to dew condensation 4. The Products are not subject to radiation-proof design. 5. Please verify and confirm characteristics of the final or mounted products in using the Products. 6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse. is applied, confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect product performance and reliability. 7. De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in the range that does not exceed the maximum junction temperature. 8. Confirm that operation temperature is within the specified range described in the product specification. 9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in this document. Precaution for Mounting / Circuit board design 1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product performance and reliability. 2. In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products, please consult with the ROHM representative in advance. For details, please refer to ROHM Mounting specification Notice-PAA-E © 2015 ROHM Co., Ltd. All rights reserved. Rev.003 Precautions Regarding Application Examples and External Circuits 1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the characteristics of the Products and external components, including transient characteristics, as well as static characteristics. 2. You agree that application notes, reference designs, and associated data and information contained in this document are presented only as guidance for Products use. Therefore, in case you use such information, you are solely responsible for it and you must exercise your own independent verification and judgment in the use of such information contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of such information. Precaution for Electrostatic This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron, isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control). Precaution for Storage / Transportation 1. Product performance and soldered connections may deteriorate if the Products are stored in the places where: [a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2 [b] the temperature or humidity exceeds those recommended by ROHM [c] the Products are exposed to direct sunshine or condensation [d] the Products are exposed to high Electrostatic 2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is exceeding the recommended storage time period. 3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads may occur due to excessive stress applied when dropping of a carton. 4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of which storage time is exceeding the recommended storage time period. Precaution for Product Label A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only. Precaution for Disposition When disposing Products please dispose them properly using an authorized industry waste company. Precaution for Foreign Exchange and Foreign Trade act Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign trade act, please consult with ROHM in case of export. Precaution Regarding Intellectual Property Rights 1. All information and data including but not limited to application example contained in this document is for reference only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any other rights of any third party regarding such information or data. 2. ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the Products with other articles such as components, circuits, systems or external equipment (including software). 3. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to manufacture or sell products containing the Products, subject to the terms and conditions herein. Other Precaution 1. This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM. 2. The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written consent of ROHM. 3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the Products or this document for any military purposes, including but not limited to, the development of mass-destruction weapons. 4. The proper names of companies or products described in this document are trademarks or registered trademarks of ROHM, its affiliated companies or third parties. Notice-PAA-E © 2015 ROHM Co., Ltd. All rights reserved. Rev.003 Datasheet General Precaution 1. Before you use our Pro ducts, you are requested to care fully read this document and fully understand its contents. ROHM shall n ot be in an y way responsible or liabl e for fa ilure, malfunction or acci dent arising from the use of a ny ROHM’s Products against warning, caution or note contained in this document. 2. All information contained in this docume nt is current as of the issuing date and subj ect to change without any prior notice. Before purchasing or using ROHM’s Products, please confirm the la test information with a ROHM sale s representative. 3. The information contained in this doc ument is provi ded on an “as is” basis and ROHM does not warrant that all information contained in this document is accurate an d/or error-free. ROHM shall not be in an y way responsible or liable for an y damages, expenses or losses incurred b y you or third parties resulting from inaccur acy or errors of or concerning such information. Notice – WE © 2015 ROHM Co., Ltd. All rights reserved. Rev.001 Datasheet BD37068FV-M - Web Page Buy Distribution Inventory Part Number Package Unit Quantity Minimum Package Quantity Packing Type Constitution Materials List RoHS BD37068FV-M SSOP-B40 2000 2000 Taping inquiry Yes