Cypress MB95F816KPMC-G-SNE2 New 8fx 8-bit microcontroller Datasheet

MB95810K Series
New 8FX 8-bit Microcontrollers
The MB95810K Series is a series of general-purpose, single-chip microcontrollers. In addition to a compact instruction set, the
microcontrollers of these series contain a variety of peripheral resources.
Features
■
■
❐
F2MC-8FX CPU core
❐ Instruction set optimized for controllers
• Multiplication and division instructions
• 16-bit arithmetic operations
• Bit test branch instructions
• Bit manipulation instructions, etc.
■
■
Low power consumption (standby) modes
There are four standby modes as follows:
• Stop mode
• Sleep mode
• Watch mode
• Time-base timer mode
❐ In standby mode, two further options can be selected: normal
standby mode and deep standby mode.
❐
Clock
Selectable main clock source
• Main oscillation clock (up to 16.25 MHz, maximum machine clock frequency: 8.125 MHz)
• External clock (up to 32.5 MHz, maximum machine clock
frequency: 16.25 MHz)
• Main CR clock (4 MHz 2%)
• Main CR PLL clock
- The main CR PLL clock frequency becomes 8 MHz
2% when the PLL multiplication rate is 2.
- The main CR PLL clock frequency becomes 10 MHz
2% when the PLL multiplication rate is 2.5.
- The main CR PLL clock frequency becomes 12 MHz
2% when the PLL multiplication rate is 3.
- The main CR PLL clock frequency becomes 16 MHz
2% when the PLL multiplication rate is 4.
❐ Selectable subclock source
• Suboscillation clock (32.768 kHz)
• External clock (32.768 kHz)
• Sub-CR clock (Typ: 100 kHz, Min: 50 kHz, Max: 150 kHz)
Timer
8/16-bit composite timer  2 channels
❐ 8/16-bit PPG  2 channels
❐ 16-bit PPG timer  2 channels
❐ 16-bit reload timer  1 channel
❐ Time-base timer  1 channel
❐ Watch prescaler  1 channel
■
■
UART/SIO  1 channel
❐ Full duplex double buffer
❐ Capable of clock asynchronous (UART) serial data transfer
and clock synchronous (SIO) serial data transfer
■
I2C bus interface  1 channel
❐ Built-in wake-up function
■
LIN-UART
❐ Full duplex double buffer
❐ Capable of clock asynchronous serial data transfer and clock
synchronous serial data transfer
■
External interrupt  12 channels
❐ Interrupt by edge detection (rising edge, falling edge, and
both edges can be selected)
I/O port (no. of I/O ports: 58)
General-purpose I/O ports (CMOS I/O): 54
❐ General-purpose I/O ports (N-ch open drain): 4
❐
■
On-chip debug
1-wire serial control
❐ Serial writing supported (asynchronous mode)
❐
■
Hardware/software watchdog timer
Built-in hardware watchdog timer
❐ Built-in software watchdog timer
❐
■
Power-on reset
A power-on reset is generated when the power is switched
on.
❐
■
Low-voltage detection (LVD) reset circuit
The LVD function is enabled by default. For details, see “18.2
Recommended Operating Conditions” in
“Electrical Characteristics”.
❐ The LVD function can be controlled through software.
❐ The LVD reset circuit control register (LVDCC) enables or
disables the LVD reset.
❐ The LVD reset circuit has an internal low-voltage detector.
The combination of detection voltage and release voltage
can be selected from four options.
❐
❐
Cypress Semiconductor Corporation
Document Number: 002-04694 Rev. *A
8/10-bit A/D converter  12 channels
8-bit or 10-bit resolution can be selected.
❐
❐
■
Can be used to wake up the device from different low power
consumption (standby) modes
■
Comparator  2 channels
Built-in dedicated BGR
❐ The comparator reference voltage can be selected between
the BGR voltage and the comparator pin.
❐
■
Clock supervisor counter
Built-in clock supervisor counter
❐
•
■
Dual operation Flash memory
The program/erase operation and the read operation can be
executed in different banks (upper bank/lower bank) simultaneously.
❐
■
198 Champion Court
Flash memory security function
Protects the content of the Flash memory.
❐
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 29, 2016
MB95810K Series
Contents
Features............................................................................. 1
1. Product Line-up ............................................................ 3
2. Packages And Corresponding Products.................... 5
3. Differences Among Products And Notes On
Product Selection ............................................................. 5
4. Pin Assignment ............................................................ 6
5. Pin Functions................................................................ 7
6. I/O Circuit Type ........................................................... 11
7. Handling Precautions.................................................
7.1 Precautions for Product Design...........................
7.2 Precautions for Package Mounting .....................
7.3 Precautions for Use Environment........................
13
13
14
16
8. Notes On Device Handling......................................... 16
9. Pin Connection ........................................................... 17
10. Block Diagram .......................................................... 19
11. CPU Core................................................................... 20
12. Memory Space ..........................................................
12.1 I/O area (addresses: 0x0000 to 0x007F)...........
12.2 Extended I/O area
(addresses: 0x0F80 to 0x0FFF) ................................
12.3 Data area...........................................................
12.4 Program area ....................................................
12.5 Memory space map...........................................
21
21
15. I/O Ports.....................................................................
15.1 Port 0.................................................................
15.2 Port 1.................................................................
15.3 Port 2.................................................................
15.4 Port 3.................................................................
15.5 Port 4.................................................................
15.6 Port 5.................................................................
15.7 Port 6.................................................................
15.8 Port 7.................................................................
15.9 Port 8.................................................................
15.10 Port E ..............................................................
15.11 Port F...............................................................
15.12 Port G ..............................................................
30
31
34
39
42
48
51
55
60
63
66
69
72
16. Interrupt Source Table ............................................. 74
17. Pin States In Each Mode .......................................... 75
18. Electrical Characteristics......................................... 78
18.1 Absolute Maximum Ratings............................... 78
18.2 Recommended Operating Conditions ............... 80
18.3 DC Characteristics ............................................ 81
18.4 AC Characteristics............................................. 84
18.5 A/D Converter................................................. 104
18.6 Flash Memory Program/Erase Characteristics 108
19. Sample Characteristics.......................................... 109
21
21
21
22
13. Areas For Specific Applications ............................. 23
20. Ordering Information.............................................. 116
21. Package Dimension................................................ 117
22. Major Changes In This Edition .............................. 119
Document History Page ............................................... 120
Sales, Solutions, and Legal Information .................... 121
14. I/O Map....................................................................... 24
Document Number: 002-04694 Rev. *A
Page 2 of 121
MB95810K Series
1. Product Line-up
Part number
MB95F814K
MB95F816K
MB95F818K
Parameter
Type
Clock
supervisor
counter
Flash memory product
It supervises the main clock oscillation and the subclock oscillation.
Flash memory
capacity
20 Kbyte
36 Kbyte
60 Kbyte
RAM capacity
512 bytes
1 Kbyte
2 Kbyte
Power-on reset
Yes
Low-voltage
detection reset
Controlled through software
Reset input
Selected through software
•
•
•
CPU functions
•
•
•
Generalpurpose I/O
Number of basic instructions
Instruction bit length
Instruction length
Data bit length
Minimum instruction execution time
Interrupt processing time
• I/O port
• CMOS I/O
• N-ch open drain
: 136
: 8 bits
: 1 to 3 bytes
: 1, 8 and 16 bits
: 61.5 ns (machine clock frequency = 16.25 MHz)
: 0.6 µs (machine clock frequency = 16.25 MHz)
: 58
: 54
:4
Time-base timer Interval time: 0.256 ms to 8.3 s (external clock frequency = 4 MHz)
• Reset generation cycle
Hardware/
Main oscillation clock at 10 MHz: 105 ms (Min)
software
watchdog timer • The sub-CR clock can be used as the source clock of the software watchdog timer.
Wild register
It can be used to replace 3 bytes of data.
LIN-UART
•
•
•
•
8/10-bit
A/D converter
A wide range of communication speed can be selected by a dedicated reload timer.
It has a full duplex double buffer.
Both clock synchronous serial data transfer and clock asynchronous serial data transfer are enabled.
The LIN function can be used as a LIN master or a LIN slave.
12 channels
8-bit or 10-bit resolution can be selected.
2 channels
• The timer can be configured as an “8-bit timer × 2 channels” or a “16-bit timer × 1 channel”.
8/16-bit
• It has the following functions: interval timer function, PWC function, PWM function and input capture
composite timer function.
• Count clock: it can be selected from internal clocks (seven types) and external clocks.
• It can output square wave.
External
interrupt
12 channels
• Interrupt by edge detection (The rising edge, falling edge, and both edges can be selected.)
• It can be used to wake up the device from different standby modes.
Document Number: 002-04694 Rev. *A
Page 3 of 121
MB95810K Series
Part number
MB95F814K
MB95F816K
MB95F818K
Parameter
On-chip debug
• 1-wire serial control
• It supports serial writing (asynchronous mode).
1 channel
UART/SIO
• Data transfer with UART/SIO is enabled.
• It has a full duplex double buffer, variable data length (5/6/7/8 bits), an internal baud rate generator
and an error detection function.
• It uses the NRZ type transfer format.
• LSB-first data transfer and MSB-first data transfer are available to use.
• Both clock asynchronous (UART) serial data transfer and clock synchronous (SIO) serial data transfer
are enabled.
1 channel
I2C bus
interface
• Master/slave transmission and receiving
• It has the following functions: bus error function, arbitration function, transmission direction detection
function, wake-up function, and functions of generating and detecting repeated START conditions.
2 channels
8/16-bit PPG
• Each channel can be used as an “8-bit timer  2 channels” or a “16-bit timer  1 channel”.
• The counter operating clock can be selected from eight clock sources.
2 channels
16-bit PPG
timer
• PWM mode and one-shot mode are available to use.
• The counter operating clock can be selected from eight clock sources.
• It supports external trigger start.
1 channel
16-bit reload
timer
•
•
•
•
Two clock modes and two counter operating modes are available to use.
It can output square wave.
Count clock: it can be selected from internal clocks (seven types) and external clocks.
Two counter operating modes: reload mode and one-shot mode
• Count clock: it can be selected from eight clock sources from the watch prescaler.
Watch counter • The counter value can be selected from 0 to 63. (The watch counter can count for one minute when
the clock source of one second is selected and 60 is selected as the counter value.)
Watch prescaler Eight different time intervals can be selected.
2 channels
Comparator
Flash memory
The reference voltage of each channel can be selected between the BGR voltage and the comparator
pin.
• It supports automatic programming (Embedded Algorithm), and program/erase/erase-suspend/eraseresume commands.
• It has a flag indicating the completion of the operation of Embedded Algorithm.
• Flash security feature for protecting the content of the Flash memory
Number of program/erase cycles
Data retention time
Document Number: 002-04694 Rev. *A
1000
20 years
10000
10 years
100000
5 years
Page 4 of 121
MB95810K Series
Part number
MB95F814K
MB95F816K
MB95F818K
Parameter
There are four standby modes as follows:
• Stop mode
• Sleep mode
Standby mode
• Watch mode
• Time-base timer mode
In standby mode, two further options can be selected: normal standby mode and deep standby mode
FPT-64P-M38
FPT-64P-M39
Package
2. Packages And Corresponding Products
Part number
MB95F814K
MB95F816K
MB95F818K
FPT-64P-M38



FPT-64P-M39



Package
: Available
3. Differences Among Products And Notes On Product Selection
• Current consumption
When using the on-chip debug function, take account of the current consumption of Flash program/erase.
For details of current consumption, see “Electrical Characteristics”.
• Package
For details of information on each package, see “Packages And Corresponding Products” and “Package Dimension”.
• Operating voltage
The operating voltage varies, depending on whether the on-chip debug function is used or not.
For details of operating voltage, see “Electrical Characteristics”.
• On-chip debug function
The on-chip debug function requires that VCC, VSS and one serial wire be connected to an evaluation tool. For details
of the connection method, refer to “CHAPTER 25 EXAMPLE OF SERIAL PROGRAMMING CONNECTION” in “New
8FX MB95810K Series Hardware Manual”.
Document Number: 002-04694 Rev. *A
Page 5 of 121
MB95810K Series
P65/SCK
P66/SOT
P67/SIN
P43/AN11
P42/AN10
P41/AN09
P40/AN08
P37/AN07
P36/AN06
P35/AN05/CMP1_O
P34/AN04/CMP1_P
P33/AN03/CMP1_N
P32/AN02/CMP0_O
P31/AN01/CMP0_P
P30/AN00/CMP0_N
AVss
4. Pin Assignment
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
AVcc
1
48
P64/EC1
AVR
2
47
P63/TO11
PE3/INT13
3
46
P62/TO10
PE2/INT12
4
45
P61/PPG11
PE1/INT11
5
44
P60/PPG10
PE0/INT10
6
43
P53/TRG1
42
P52/PPG1
41
P51/SDA0
40
P50/SCL0
39
P24/EC0
P83/TRG0*/ADTG*
7
P82
8
P81
9
P80
10
(TOP VIEW)
LQFP64
(FPT-64P-M38)
(FPT-64P-M39)
P71/TI0
11
38
P23/TO01
P70/TO0
12
37
P22/TO00
P72
13
36
P21/PPG01
PF0/X0
14
35
P20/PPG00
PF1/X1
15
34
P14/PPG0
Vss
16
33
P13/UCK0/TRG0*/ADTG*
P12/DBG
P10/UI0
P11/UO0
P07/INT07
P06/INT06
P05/INT05
P04/INT04
P02/INT02
P03/INT03
P01/INT01
P00/INT00
PF2/RST
PG1/X0A
C
PG2/X1A
Vcc
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
*: TRG0 and ADTG can be mapped to either P13 or P83 by using the SYSC register.
Document Number: 002-04694 Rev. *A
Page 6 of 121
MB95810K Series
5. Pin Functions
I/O type
Pin no.
Pin name
I/O circuit
type*1
Function
1
AVCC
—
Analog power supply pin for 8/10-bit A/D
converter
—
—
—
—
2
AVR
—
Reference input pin for 8/10-bit A/D
converter
—
—
—
—
Hysteresis CMOS
—

Hysteresis CMOS
—

Hysteresis CMOS
—

Hysteresis CMOS
—

Hysteresis CMOS
—

—
Hysteresis CMOS —
Hysteresis CMOS —

Hysteresis CMOS
—

Hysteresis CMOS
—

Hysteresis CMOS
—

Hysteresis CMOS
—
—
Hysteresis CMOS
—
—
3
4
5
6
PE3
F
INT13
PE2
F
INT12
PE1
F
INT11
PE0
F
INT10
P83
7
TRG0*
General-purpose I/O port
External interrupt input pin
General-purpose I/O port
External interrupt input pin
General-purpose I/O port
External interrupt input pin
General-purpose I/O port
External interrupt input pin
F
4
16-bit PPG timer ch. 0 trigger input pin
8/10-bit A/D converter trigger input pin
8
P82
F
General-purpose I/O port
9
P81
F
General-purpose I/O port
10
P80
F
General-purpose I/O port
12
13
14
15
P71
TI0
P70
TO0
P72
PF0
X0
PF1
X1
Output OD*2 PU*3
General-purpose I/O port
4
ADTG*
11
Input
F
F
F
B
B
General-purpose I/O port
16-bit reload timer ch. 0 input pin
General-purpose I/O port
16-bit reload timer ch. 0 output pin
General-purpose I/O port
General-purpose I/O port
Main clock input oscillation pin
General-purpose I/O port
Main clock I/O oscillation pin
Hysteresis CMOS


16
VSS
—
Power supply pin (GND)
—
—
—
—
17
VCC
—
Power supply pin
—
—
—
—
18
C
—
Decoupling capacitor connection pin
—
—
—
—
Hysteresis CMOS
—

Hysteresis CMOS
—

Hysteresis CMOS

—
19
20
21
PG2
X1A
PG1
X0A
PF2
RST
C
C
A
General-purpose I/O port
Subclock I/O oscillation pin
General-purpose I/O port
Subclock input oscillation pin
General-purpose I/O port
Reset pin
Document Number: 002-04694 Rev. *A
Page 7 of 121
MB95810K Series
Pin no.
22
23
24
25
26
27
28
29
30
31
32
Pin name
P00
I/O circuit
type*1
D
INT00
P01
D
INT01
P02
D
INT02
P03
D
INT03
P04
D
INT04
P05
D
INT05
P06
D
INT06
P07
D
INT07
P10
I
UI0
P11
F
UO0
P12
G
DBG
P13
33
4
F
ADTG*4
34
35
36
37
38
P14
PPG0
P20
PPG00
P21
PPG01
P22
TO00
P23
TO01
General-purpose I/O port
External interrupt input pin
General-purpose I/O port
External interrupt input pin
General-purpose I/O port
External interrupt input pin
General-purpose I/O port
External interrupt input pin
General-purpose I/O port
External interrupt input pin
General-purpose I/O port
External interrupt input pin
General-purpose I/O port
External interrupt input pin
General-purpose I/O port
External interrupt input pin
General-purpose I/O port
UART/SIO ch. 0 data input pin
General-purpose I/O port
UART/SIO ch. 0 data output pin
General-purpose I/O port
DBG input pin
I/O type
Input
Output OD*2 PU*3
Hysteresis CMOS
—

Hysteresis CMOS
—

Hysteresis CMOS
—

Hysteresis CMOS
—

Hysteresis CMOS
—

Hysteresis CMOS
—

Hysteresis CMOS
—

Hysteresis CMOS
—

CMOS
—

Hysteresis CMOS
—

Hysteresis CMOS

—
Hysteresis CMOS
—

Hysteresis CMOS
—

Hysteresis CMOS
—

Hysteresis CMOS
—

Hysteresis CMOS
—

Hysteresis CMOS
—

CMOS
General-purpose I/O port
UCK0
TRG0*
Function
UART/SIO ch. 0 clock I/O pin
16-bit PPG timer ch. 0 trigger input pin
8/10-bit A/D converter trigger input pin
F
F
F
F
F
General-purpose I/O port
16-bit PPG timer ch. 0 output pin
General-purpose I/O port
8/16-bit PPG ch. 0 output pin
General-purpose I/O port
8/16-bit PPG ch. 0 output pin
General-purpose I/O port
8/16-bit composite timer ch. 0 output pin
General-purpose I/O port
8/16-bit composite timer ch. 0 output pin
Document Number: 002-04694 Rev. *A
Page 8 of 121
MB95810K Series
Pin no.
Pin name
I/O circuit
type*1
P24
39
40
41
42
43
44
45
46
47
EC0
P50
SCL
P51
SDA
P52
PPG1
P53
TRG1
P60
PPG10
P61
PPG11
P62
TO10
P63
TO11
49
50
51
52
53
54
55
EC1
P65
SCK
P66
SOT
P67
SIN
P43
AN11
P42
AN10
P41
AN09
P40
AN08
I/O type
Input
Output OD*2 PU*3
General-purpose I/O port
F
H
H
F
F
F
F
F
F
P64
48
Function
8/16-bit composite timer ch. 0 clock input Hysteresis CMOS
pin
General-purpose I/O port
—

CMOS
CMOS

—
CMOS
CMOS

—
Hysteresis CMOS
—

Hysteresis CMOS
—

Hysteresis CMOS
—

Hysteresis CMOS
—

Hysteresis CMOS
—

Hysteresis CMOS
—

8/16-bit composite timer ch. 1 clock input Hysteresis CMOS
pin
—

Hysteresis CMOS
—

Hysteresis CMOS
—

CMOS
—

Hysteresis/
CMOS
analog
—

Hysteresis/
CMOS
analog
—

Hysteresis/
CMOS
analog
—

Hysteresis/
CMOS
analog
—

I2C bus interface ch. 0 clock I/O pin
General-purpose I/O port
I2C bus interface ch. 0 data I/O pin
General-purpose I/O port
16-bit PPG timer ch. 1 output pin
General-purpose I/O port
16-bit PPG timer ch. 1 trigger input pin
General-purpose I/O port
8/16-bit PPG ch. 1 output pin
General-purpose I/O port
8/16-bit PPG ch. 1 output pin
General-purpose I/O port
8/16-bit composite timer ch. 1 output pin
General-purpose I/O port
8/16-bit composite timer ch. 1 output pin
General-purpose I/O port
F
F
F
I
E
E
E
E
General-purpose I/O port
LIN-UART clock I/O pin
General-purpose I/O port
LIN-UART data output pin
General-purpose I/O port
LIN-UART data input pin
General-purpose I/O port
8/10-bit A/D converter analog input pin
General-purpose I/O port
8/10-bit A/D converter analog input pin
General-purpose I/O port
8/10-bit A/D converter analog input pin
General-purpose I/O port
8/10-bit A/D converter analog input pin
Document Number: 002-04694 Rev. *A
CMOS
Page 9 of 121
MB95810K Series
Pin no.
56
57
Pin name
P37
AN07
P36
AN06
I/O circuit
type*1
E
E
P35
58
AN05
E
E
E
P32
AN02
E
E
AVSS
Hysteresis/
CMOS
analog
—

Hysteresis/
CMOS
analog
—

Hysteresis/
CMOS
analog
Comparator ch. 1 inverting analog input
(negative input) pin
—

Hysteresis/
CMOS
analog
—

Hysteresis/
CMOS
analog
—

Hysteresis/
CMOS
analog
Comparator ch. 0 inverting analog input
(negative input) pin
—

—
—
8/10-bit A/D converter analog input pin
8/10-bit A/D converter analog input pin
8/10-bit A/D converter analog input pin
8/10-bit A/D converter analog input pin
8/10-bit A/D converter analog input pin
General-purpose I/O port
E
CMP0_N
64

Comparator ch. 0 non-inverting analog
input (positive input) pin
P30
AN00
—
8/10-bit A/D converter analog input pin
General-purpose I/O port
CMP0_P
63
Hysteresis/
CMOS
analog
General-purpose I/O port
Comparator ch. 0 digital output pin
P31
AN01

General-purpose I/O port
CMP0_O
62
—
8/10-bit A/D converter analog input pin
General-purpose I/O port
CMP1_N
61
Hysteresis/
CMOS
analog
Comparator ch. 1 non-inverting analog
input (positive input) pin
P33
AN03
Output OD*2 PU*3
General-purpose I/O port
CMP1_P
60
Input
Comparator ch. 1 digital output pin
P34
AN04
General-purpose I/O port
I/O type
General-purpose I/O port
CMP1_O
59
Function
—
8/10-bit A/D converter analog input pin
8/10-bit A/D converter power supply pin
(GND)
—
—
(: Available)
*1: For the I/O circuit types, see “I/O Circuit Type”.
*2: N-ch open drain
*3: Pull-up
*4: TRG0 and ADTG can be mapped to either P13 or P83 by using the SYSC register.
Document Number: 002-04694 Rev. *A
Page 10 of 121
MB95810K Series
6. I/O Circuit Type
Type
Circuit
A
Remarks
Reset input / Hysteresis input
Reset output / Digital output
• N-ch open drain output
• Hysteresis input
• Reset output
N-ch
B
P-ch
Port select
Digital output
N-ch
Digital output
Standby control
Hysteresis input
• Oscillation circuit
• High-speed side
Feedback resistance:
approx. 1 M
• CMOS output
• Hysteresis input
Clock input
X1
X0
Standby control / Port select
P-ch
Port select
Digital output
N-ch
Digital output
Standby control
Hysteresis input
C
Port select
R
Pull-up control
P-ch
P-ch
• Oscillation circuit
• Low-speed side
Feedback resistance:
approx. 5 M
Digital output
N-ch
Digital output
Standby control
Hysteresis input
• CMOS output
• Hysteresis input
• Pull-up control
Clock input
X1A
X0A
Standby control / Port select
Port select
R
Pull-up control
Digital output
P-ch
Digital output
N-ch
Digital output
Standby control
Hysteresis input
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MB95810K Series
Type
Circuit
Remarks
D
Pull-up control
R
P-ch
Digital output
P-ch
•
•
•
•
CMOS output
Hysteresis input
Pull-up control
High current output
•
•
•
•
CMOS output
Hysteresis input
Pull-up control
Analog input
Digital output
N-ch
Standby control
Hysteresis input
E
Pull-up control
R
P-ch
Digital output
P-ch
Digital output
N-ch
Analog input
A/D control
Standby control
Hysteresis input
F
Pull-up control
R
P-ch
• CMOS output
• Hysteresis input
• Pull-up control
Digital output
P-ch
Digital output
N-ch
Standby control
Hysteresis input
G
Standby control
• N-ch open drain output
• Hysteresis input
Hysteresis input
Digital output
N-ch
H
Digital output
• N-ch open drain output
• CMOS input
N-ch
Standby control
CMOS input
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MB95810K Series
Type
Circuit
Remarks
I
Pull-up control
R
P-ch
• CMOS output
• CMOS input
• Pull-up control
Digital output
P-ch
Digital output
N-ch
Standby control
CMOS input
7. Handling Precautions
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the
conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions
that must be observed to minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor
devices.
7.1 Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
 Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in
excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings.
 Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's
electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges
may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet.
Users considering application outside the listed conditions are advised to contact their sales representative beforehand.
 Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power supply
and input/output functions.
(1) Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration
within the device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage
or over-current conditions at the design stage.
(2) Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large
current flows. Such conditions if present for extended periods of time can damage the device.
Therefore, avoid this type of connection.
(3) Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins
should be connected through an appropriate resistance to a power supply pin or ground pin.
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 Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected
to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing
large current levels in excess of several hundred mA to flow continuously at the power supply pin. This condition is
called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause
injury or damage from high heat, smoke or flame. To prevent this from happening, do the following:
(1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should
include attention to abnormal noise, surge levels, etc.
(2) Be sure that abnormal current flows do not occur during the power-on sequence.
 Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the design of
products.
 Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss
from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire
protection, and prevention of over-current levels and other abnormal operating conditions.
 Precautions Related to Usage of Devices
Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other
office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation
may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability
are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls,
medical devices for life support, etc.) are requested to consult with sales representatives before such use. The
company will not be responsible for damages arising from such use without prior approval.
7.2 Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during
soldering, you should only mount under Cypress’s recommended conditions. For detailed information about mount
conditions, contact your sales representative.
 Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering
on the board, or mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and
using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually
causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting
processes should conform to Cypress recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to
contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts
and IC leads be verified before mounting.
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MB95810K Series
 Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more
easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased
susceptibility to open connections caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established
a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Cypress
ranking of recommended conditions.
 Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering,
junction strength may be reduced under some conditions of use.
 Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause
absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause
surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following:
(1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store
products in locations where temperature changes are slight.
(2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures
between 5°C and 30°C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
(3) When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags,
with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage.
(4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
 Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended conditions for baking.
Condition: 125°C/24 h
 Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following
precautions:
(1) Maintain relative humidity in the working environment between 40% and 70%.
Use of an apparatus for ion generation may be needed to remove electricity.
(2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
(3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on
the level of 1 M).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock
loads is recommended.
(4) Ground all fixtures and instruments, or protect with anti-static measures.
(5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies.
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7.3 Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described above.
For reliable performance, do the following:
(1) Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity
levels are anticipated, consider anti-humidity processing.
(2) Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In
such cases, use anti-static measures or processing to prevent discharges.
(3) Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect
the device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices.
(4) Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should
provide shielding as appropriate.
(5) Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances.
If devices begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of Cypress products in other special environmental conditions should consult with
sales representatives.
8. Notes On Device Handling
• Preventing latch-ups
When using the device, ensure that the voltage applied does not exceed the maximum voltage rating.
In a CMOS IC, if a voltage higher than VCC or a voltage lower than VSS is applied to an input/output pin that is neither
a medium-withstand voltage pin nor a high-withstand voltage pin, or if a voltage out of the rating range of power supply voltage mentioned in “18.1 Absolute Maximum Ratings” of “Electrical Characteristics” is applied to the VCC pin or
the VSS pin, a latch-up may occur.
When a latch-up occurs, power supply current increases significantly, which may cause a component to be thermally
destroyed.
• Stabilizing supply voltage
Supply voltage must be stabilized.
A malfunction may occur when power supply voltage fluctuates rapidly even though the fluctuation is within the guaranteed operating range of the VCC power supply voltage.
As a rule of voltage stabilization, suppress voltage fluctuation so that the fluctuation in VCC ripple (p-p value) at the
commercial frequency (50 Hz/60 Hz) does not exceed 10% of the standard VCC value, and the transient fluctuation
rate does not exceed 0.1 V/ms at a momentary fluctuation such as switching the power supply.
• Notes on using the external clock
When an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up from subclock mode or stop mode.
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9. Pin Connection
• Treatment of unused pins
If an unused input pin is left unconnected, a component may be permanently damaged due to malfunctions or latchups. Always pull up or pull down an unused input pin through a resistor of at least 2 k. Set an unused input/output
pin to the output state and leave it unconnected, or set it to the input state and treat it the same as an unused input
pin. If there is an unused output pin, leave it unconnected.
• Power supply pins
To reduce unnecessary electro-magnetic emission, prevent malfunctions of strobe signals due to an increase in the
ground level, and conform to the total output current standard, always connect the VCC pin and the VSS pin to the
power supply and ground outside the device. In addition, connect the current supply source to the VCC pin and the
VSS pin with low impedance.
It is also advisable to connect a ceramic capacitor of approximately 0.1 µF as a bypass capacitor between the VCC
pin and the VSS pin at a location close to this device.
• DBG pin
Connect the DBG pin to an external pull-up resistor of 2 k or above.
After power-on, ensure that the DBG pin does not stay at “L” level until the reset output is released.
The DBG pin becomes a communication pin in debug mode. Since the actual pull-up resistance depends on the tool
used and the interconnection length, refer to the tool document when selecting a pull-up resistor.
• RST pin
Connect the RST pin to an external pull-up resistor of 2 k or above.
To prevent the device from unintentionally entering the reset mode due to noise, minimize the interconnection length
between a pull-up resistor and the RST pin and that between a pull-up resistor and the VCC pin when designing the
layout of the printed circuit board.
The PF2/RST pin functions as the reset input/output pin after power-on. In addition, the reset output of the PF2/RST
pin can be enabled by the RSTOE bit in the SYSC register, and the reset input function and the general purpose I/O
function can be selected by the RSTEN bit in the SYSC register.
• Analog power supply
Always set the same potential to the AVCC pin and the VCC pin. When VCC is larger than AVCC, the current may flow
through the AN00 to AN11 pins.
• Treatment of power supply pins on the 8/10-bit A/D converter
Ensure that AVCC is equal to VCC and AVSS equal to VSS even when the 8/10-bit A/D converter is not in use.
Noise riding on the AVCC pin may cause accuracy degradation. Therefore, connect a ceramic capacitor of 0.1 µF (approx.) as a bypass capacitor between the AVCC pin and the AVSS pin in the vicinity of this device.
• C pin
Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The decoupling capacitor for the
VCC pin must have a capacitance equal to or larger than the capacitance of CS. For the connection to a decoupling
capacitor CS, see the diagram below. To prevent the device from unintentionally entering a mode to which the device
is not set to transit due to noise, minimize the distance between the C pin and CS and the distance between CS and
the VSS pin when designing the layout of a printed circuit board.
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MB95810K Series
• DBG/RST/C pins connection diagram
DBG
C
RST
Cs
• Note on serial communication
In serial communication, reception of wrong data may occur due to noise or other causes. Therefore, design a printed
circuit board to prevent noise from occurring. Taking account of the reception of wrong data, take measures such as
adding a checksum to the end of data in order to detect errors. If an error is detected, retransmit the data.
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MB95810K Series
10. Block Diagram
F2MC-8FX CPU
PF2*1/RST*2
Reset with LVD
Dual operation Flash with
security function
(60/36/20 Kbyte)
PF0/X0*2
PF1/X1*2
PG1/X0A*2
Oscillator
circuit
CR oscillator
RAM (2048/1024/512 bytes)
PG2/X1A*2
Interrupt controller
Clock control
C
16-bit PPG timer ch. 1
Watch prescaler
Watch counter
On-chip debug
P62/TO10
8/16-bit composite timer ch. 1
P00 /INT00 to P07 /INT07
P10/UI0
P11/UO0
UART/SIO
P13/UCK0
(P13/TRG0 or P83/TRG0)
P14/PPG0
P63/TO11
P64/EC1
External interrupt
ch. 0 to ch. 7
Internal bus
*3
P23/TO01
P24/EC0
Wild register
*3
P53/TRG1
P22/TO00
8/16-bit composite timer ch. 0
P12*1/DBG
P52/PPG1
P65/SCK
LIN-UART
P66/SOT
P67/SIN
16-bit reload timer ch. 0
16-bit PPG timer ch. 0
P70/TO0
P71/TI0
(P30/CMP0_N)
P20/PPG00
P21/PPG01
P60/PPG10
P61/PPG11
8/16-bit PPG ch. 0
8/16-bit PPG ch. 1
Comparator ch. 0
(P31/CMP0_P)
(P32/CMP0_O)
(P33/CMP1_N)
Comparator ch. 1
(P34/CMP1_P)
(P35/CMP1_O)
(P13/ADTG or P83/ADTG)
(P30/AN00 to P37/AN07)
P40/AN08 to P43/AN11
8/10-bit A/D converter
External interrupt
ch. 8 to ch. 11
AVR
P50*1/SCL
P51*1/SDA
PE0/INT10 to PE3/INT13
P80 to P82
I2C bus interface ch. 0
Port
Port
Vcc
Vss
AVcc
AVss
*1: P12, P50, P51 and PF2 are N-ch open drain pins.
*2: Software select
*3: P00 to P07 are high-current pins.
Note: Pins in parentheses indicate that those pins are shared among different peripheral functions.
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MB95810K Series
11. CPU Core
• Memory space
The memory space of the MB95810K Series is 64 Kbyte in size, and consists of an I/O area, an extended I/O area,
a data area, and a program area. The memory space includes areas intended for specific purposes such as generalpurpose registers and a vector table. The memory maps of the MB95810K Series are shown below.
• Memory maps
MB95F814K
0x0000
0x0080
0x0090
0x0100
0x0200
0x0290
I/O area
Access prohibited
RAM 512 bytes
Registers
MB95F816K
0x0000
0x0080
0x0090
0x0100
0x0200
I/O area
Access prohibited
RAM 1 Kbyte
Registers
MB95F818K
0x0000
0x0080
0x0090
0x0100
0x0200
I/O area
Access prohibited
RAM 2 Kbyte
Registers
0x0490
Access prohibited
Access prohibited
0x0890
Access prohibited
0x0F80
0x0F80
0x0F80
Extended I/O area
Extended I/O area
Extended I/O area
0x1000
0x1000
0x1000
Flash memory 4 Kbyte
Flash memory 4 Kbyte
0x2000
0x2000
Access prohibited
Access prohibited
0x8000
Flash memory 60 Kbyte
Flash memory 32 Kbyte
0xC000
Flash memory 16 Kbyte
0xFFFF
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0xFFFF
0xFFFF
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MB95810K Series
12. Memory Space
The memory space of the MB95810K Series is 64 Kbyte in size, and consists of an I/O area, an extended I/O area,
a data area, and a program area. The memory space includes areas for specific applications such as general-purpose registers and a vector table.
12.1 I/O area (addresses: 0x0000 to 0x007F)
• This area contains the control registers and data registers for built-in peripheral functions.
• As the I/O area forms part of the memory space, it can be accessed in the same way as the memory. It can also
be accessed at high-speed by using direct addressing instructions.
12.2 Extended I/O area (addresses: 0x0F80 to 0x0FFF)
• This area contains the control registers and data registers for built-in peripheral functions.
• As the extended I/O area forms part of the memory space, it can be accessed in the same way as the memory.
12.3
•
•
•
•
Data area
Static RAM is incorporated in the data area as the internal data area.
The internal RAM size varies according to product.
The RAM area from 0x0090 to 0x00FF can be accessed at high-speed by using direct addressing instructions.
In MB95F818K, the area from 0x0090 to 0x047F is an extended direct addressing area. It can be accessed at highspeed by direct addressing instructions with a direct bank pointer set.
• In MB95F816K, the area from 0x0090 to 0x047F is an extended direct addressing area. It can be accessed at highspeed by direct addressing instructions with a direct bank pointer set.
• In MB95F814K, the area from 0x0090 to 0x028F is an extended direct addressing area. It can be accessed at highspeed by direct addressing instructions with a direct bank pointer set.
• The area from 0x0100 to 0x01FF can be used as a general-purpose register area.
12.4
•
•
•
•
Program area
The Flash memory is incorporated in the program area as the internal program area.
The Flash memory size varies according to product.
The area from 0xFFC0 to 0xFFFF is used as the vector table.
The area from 0xFFBB to 0xFFBF is used to store data of the non-volatile register.
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MB95810K Series
12.5 Memory space map
0x0000
0x0080
0x0090
0x0100
I/O area
Direct addressing area
Access prohibited
Registers
(General-purpose register area)
Extended direct addressing area
0x0200
0x047F
Data area
0x088F
0x0890
Access prohibited
0x0F80
0x0FFF
0x1000
Extended I/O area
Program area
0xFFC0
0xFFFF
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Vector table area
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MB95810K Series
13. Areas For Specific Applications
The general-purpose register area and vector table area are used for the specific applications.
• General-purpose register area (Addresses: 0x0100 to 0x01FF)
• This area contains the auxiliary registers used for 8-bit arithmetic operations, transfer, etc.
• As this area forms part of the RAM area, it can also be used as conventional RAM.
• When the area is used as general-purpose registers, general-purpose register addressing enables high-speed access with short instructions.
• Non-volatile register data area (Addresses: 0xFFBB to 0xFFBF)
• The area from 0xFFBB to 0xFFBF is used to store data of the non-volatile register. For details, refer to “CHAPTER
27 NON-VOLATILE REGISTER (NVR) INTERFACE” in “New 8FX MB95810K Series Hardware Manual”.
• Vector table area (Addresses: 0xFFC0 to 0xFFFF)
• This area is used as the vector table for vector call instructions (CALLV), interrupts, and resets.
• The top of the Flash memory area is allocated to the vector table area. The start address of a service routine is set
to an address in the vector table in the form of data.
“Interrupt Source Table” lists the vector table addresses corresponding to vector call instructions, interrupts, and resets.
For details, refer to “CHAPTER 4 RESET”, “CHAPTER 5 INTERRUPTS” and “A.2 Special Instruction ■ Special Instruction ● CALLV #vct” in “APPENDIX” in “New 8FX MB95810K Series Hardware Manual”.
• Direct bank pointer and access area
Direct bank pointer (DP[2:0])
Operand-specified dir
Access area
0bXXX (It does not affect mapping.)
0x0000 to 0x007F
0x0000 to 0x007F
0b000 (initial value)
0x0090 to 0x00FF
0x0090 to 0x00FF
0b001
0x0100 to 0x017F
0b010
0x0180 to 0x01FF
0b011
0x0200 to 0x027F
0b100
0x0080 to 0x00FF
0x0280 to 0x02FF*1
0b101
0x0300 to 0x037F
0b110
0x0380 to 0x03FF
0b111
0x0400 to 0x047F*2
*1: Due to the memory size limit, the available access area is up to “0x028F” in MB95F814K.
*2: Due to the memory size limit, the available access area is up to “0x047F” in MB95F816K/F818K.
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14. I/O Map
Address
Register
abbreviation
0x0000
PDR0
0x0001
Register name
R/W
Initial value
Port 0 data register
R/W
0b00000000
DDR0
Port 0 direction register
R/W
0b00000000
0x0002
PDR1
Port 1 data register
R/W
0b00000000
0x0003
DDR1
Port 1 direction register
R/W
0b00000000
0x0004
—
—
—
0x0005
WATR
Oscillation stabilization wait time setting register
R/W
0b11111111
0x0006
PLLC
PLL control register
R/W
0b000X0000
0x0007
SYCC
System clock control register
R/W
0bXXX11011
0x0008
STBC
Standby control register
R/W
0b00000000
0x0009
RSRR
Reset source register
R/W
0b000XXXXX
0x000A
TBTC
Time-base timer control register
R/W
0b00000000
0x000B
WPCR
Watch prescaler control register
R/W
0b00000000
0x000C
WDTC
Watchdog timer control register
R/W
0b00XX0000
0x000D
SYCC2
System clock control register 2
R/W
0bXXXX0011
0x000E
PDR2
Port 2 data register
R/W
0b00000000
0x000F
DDR2
Port 2 direction register
R/W
0b00000000
0x0010
PDR3
Port 3 data register
R/W
0b00000000
0x0011
DDR3
Port 3 direction register
R/W
0b00000000
0x0012
PDR4
Port 4 data register
R/W
0b00000000
0x0013
DDR4
Port 4 direction register
R/W
0b00000000
0x0014
PDR5
Port 5 data register
R/W
0b00000000
0x0015
DDR5
Port 5 direction register
R/W
0b00000000
0x0016
PDR6
Port 6 data register
R/W
0b00000000
0x0017
DDR6
Port 6 direction register
R/W
0b00000000
0x0018
PDR7
Port 7 data register
R/W
0b00000000
0x0019
DDR7
Port 7 direction register
R/W
0b00000000
0x001A
PDR8
Port 8 data register
R/W
0b00000000
0x001B
DDR8
Port 8 direction register
R/W
0b00000000
0x001C
STBC2
Standby control register 2
R/W
0b00000000
0x001D
to
0x0024
—
—
—
0x0025
PUL8
Port 8 pull-up register
R/W
0b00000000
0x0026
PDRE
Port E data register
R/W
0b00000000
0x0027
DDRE
Port E direction register
R/W
0b00000000
0x0028
PDRF
Port F data register
R/W
0b00000000
(Disabled)
(Disabled)
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MB95810K Series
Address
Register
abbreviation
0x0029
DDRF
0x002A
Register name
R/W
Initial value
Port F direction register
R/W
0b00000000
PDRG
Port G data register
R/W
0b00000000
0x002B
DDRG
Port G direction register
R/W
0b00000000
0x002C
PUL0
Port 0 pull-up register
R/W
0b00000000
0x002D
PUL1
Port 1 pull-up register
R/W
0b00000000
0x002E
PUL2
Port 2 pull-up register
R/W
0b00000000
0x002F
PUL3
Port 3 pull-up register
R/W
0b00000000
0x0030
PUL4
Port 4 pull-up register
R/W
0b00000000
0x0031
PUL5
Port 5 pull-up register
R/W
0b00000000
0x0032
PUL7
Port 7 pull-up register
R/W
0b00000000
0x0033
PUL6
Port 6 pull-up register
R/W
0b00000000
0x0034
PULE
Port E pull-up register
R/W
0b00000000
0x0035
PULG
Port G pull-up register
R/W
0b00000000
0x0036
T01CR1
8/16-bit composite timer 01 status control register 1
R/W
0b00000000
0x0037
T00CR1
8/16-bit composite timer 00 status control register 1
R/W
0b00000000
0x0038
T11CR1
8/16-bit composite timer 11 status control register 1
R/W
0b00000000
0x0039
T10CR1
8/16-bit composite timer 10 status control register 1
R/W
0b00000000
0x003A
PC01
8/16-bit PPG timer 01 control register
R/W
0b00000000
0x003B
PC00
8/16-bit PPG timer 00 control register
R/W
0b00000000
0x003C
PC11
8/16-bit PPG timer 11 control register
R/W
0b00000000
0x003D
PC10
8/16-bit PPG timer 10 control register
R/W
0b00000000
0x003E
TMCSRH0
16-bit reload timer control status register (upper) ch. 0
R/W
0b00000000
0x003F
TMCSRL0
16-bit reload timer control status register (lower) ch. 0
R/W
0b00000000
0x0040,
0x0041
—
—
—
0x0042
PCNTH0
16-bit PPG status control register (upper) ch. 0
R/W
0b00000000
0x0043
PCNTL0
16-bit PPG status control register (lower) ch. 0
R/W
0b00000000
0x0044
PCNTH1
16-bit PPG status control register (upper) ch. 1
R/W
0b00000000
0x0045
PCNTL1
16-bit PPG status control register (lower) ch. 1
R/W
0b00000000
0x0046,
0x0047
—
—
—
0x0048
EIC00
External interrupt circuit control register ch. 0/ch. 1
R/W
0b00000000
0x0049
EIC10
External interrupt circuit control register ch. 2/ch. 3
R/W
0b00000000
0x004A
EIC20
External interrupt circuit control register ch. 4/ch. 5
R/W
0b00000000
0x004B
EIC30
External interrupt circuit control register ch. 6/ch. 7
R/W
0b00000000
0x004C
EIC01
External interrupt circuit control register ch. 10/ch. 11
R/W
0b00000000
0x004D
EIC11
External interrupt circuit control register ch. 12/ch. 13
R/W
0b00000000
0x004E
LVDR
LVD reset voltage selection ID register
R/W
0b00000000
(Disabled)
(Disabled)
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MB95810K Series
Address
Register
abbreviation
0x004F
LVDCC
0x0050
R/W
Initial value
LVD reset circuit control register
R/W
0b00000001
SCR
LIN-UART serial control register
R/W
0b00000000
0x0051
SMR
LIN-UART serial mode register
R/W
0b00000000
0x0052
SSR
LIN-UART serial status register
R/W
0b00001000
RDR
LIN-UART receive data register
TDR
LIN-UART transmit data register
R/W
0b00000000
0x0053
Register name
0x0054
ESCR
LIN-UART extended status control register
R/W
0b00000100
0x0055
ECCR
LIN-UART extended communication control register
R/W
0b000000XX
0x0056
SMC10
UART/SIO serial mode control register 1 ch. 0
R/W
0b00000000
0x0057
SMC20
UART/SIO serial mode control register 2 ch. 0
R/W
0b00100000
0x0058
SSR0
UART/SIO serial status and data register ch. 0
R/W
0b00000001
0x0059
TDR0
UART/SIO serial output data register ch. 0
R/W
0b00000000
0x005A
RDR0
UART/SIO serial input data register ch. 0
R
0b00000000
0x005B
CMR0
Comparator control register ch. 0
R/W
0b11000101
0x005C
CMR1
Comparator control register ch. 1
R/W
0b11000101
0x005D
to
0x005F
—
—
—
0x0060
IBCR00
I2C bus control register 0 ch. 0
R/W
0b00000000
0x0061
IBCR10
I2C bus control register 1 ch. 0
R/W
0b00000000
0x0062
IBSR0
I2C bus status register ch. 0
R/W
0b00000000
0x0063
IDDR0
I2C data register ch. 0
R/W
0b00000000
0x0064
IAAR0
I2C address register ch. 0
R/W
0b00000000
0x0065
ICCR0
I2C clock control register ch. 0
R/W
0b00000000
0x0066
to
0x006B
—
—
—
0x006C
ADC1
8/10-bit A/D converter control register 1
R/W
0b00000000
0x006D
ADC2
8/10-bit A/D converter control register 2
R/W
0b00000000
0x006E
ADDH
8/10-bit A/D converter data register (upper)
R/W
0b00000000
0x006F
ADDL
8/10-bit A/D converter data register (lower)
R/W
0b00000000
0x0070
WCSR
Watch counter control register
R/W
0b00000000
0x0071
FSR2
Flash memory status register 2
R/W
0b00000000
0x0072
FSR
Flash memory status register
R/W
0b000X0000
0x0073
SWRE0
Flash memory sector write control register 0
R/W
0b00000000
0x0074
FSR3
Flash memory status register 3
R
0b000XXXXX
0x0075
FSR4
Flash memory status register 4
R/W
0b00000000
0x0076
WREN
Wild register address compare enable register
R/W
0b00000000
(Disabled)
(Disabled)
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MB95810K Series
Address
Register
abbreviation
0x0077
WROR
0x0078
—
0x0079
ILR0
0x007A
Register name
R/W
Initial value
R/W
0b00000000
—
—
Interrupt level setting register 0
R/W
0b11111111
ILR1
Interrupt level setting register 1
R/W
0b11111111
0x007B
ILR2
Interrupt level setting register 2
R/W
0b11111111
0x007C
ILR3
Interrupt level setting register 3
R/W
0b11111111
0x007D
ILR4
Interrupt level setting register 4
R/W
0b11111111
0x007E
ILR5
Interrupt level setting register 5
R/W
0b11111111
0x007F
—
—
—
0x0F80
WRARH0
Wild register address setting register (upper) ch. 0
R/W
0b00000000
0x0F81
WRARL0
Wild register address setting register (lower) ch. 0
R/W
0b00000000
0x0F82
WRDR0
Wild register data setting register ch. 0
R/W
0b00000000
0x0F83
WRARH1
Wild register address setting register (upper) ch. 1
R/W
0b00000000
0x0F84
WRARL1
Wild register address setting register (lower) ch. 1
R/W
0b00000000
0x0F85
WRDR1
Wild register data setting register ch. 1
R/W
0b00000000
0x0F86
WRARH2
Wild register address setting register (upper) ch. 2
R/W
0b00000000
0x0F87
WRARL2
Wild register address setting register (lower) ch. 2
R/W
0b00000000
0x0F88
WRDR2
Wild register data setting register ch. 2
R/W
0b00000000
0x0F89
to
0x0F91
—
—
—
0x0F92
T01CR0
8/16-bit composite timer 01 status control register 0
R/W
0b00000000
0x0F93
T00CR0
8/16-bit composite timer 00 status control register 0
R/W
0b00000000
0x0F94
T01DR
8/16-bit composite timer 01 data register
R/W
0b00000000
0x0F95
T00DR
8/16-bit composite timer 00 data register
R/W
0b00000000
0x0F96
TMCR0
8/16-bit composite timer 00/01 timer mode control
register
R/W
0b00000000
0x0F97
T11CR0
8/16-bit composite timer 11 status control register 0
R/W
0b00000000
0x0F98
T10CR0
8/16-bit composite timer 10 status control register 0
R/W
0b00000000
0x0F99
T11DR
8/16-bit composite timer 11 data register
R/W
0b00000000
0x0F9A
T10DR
8/16-bit composite timer 10 data register
R/W
0b00000000
0x0F9B
TMCR1
8/16-bit composite timer 10/11 timer mode control
register
R/W
0b00000000
0x0F9C
PPS01
8/16-bit PPG01 cycle setting buffer register
R/W
0b11111111
0x0F9D
PPS00
8/16-bit PPG00 cycle setting buffer register
R/W
0b11111111
0x0F9E
PDS01
8/16-bit PPG01 duty setting buffer register
R/W
0b11111111
0x0F9F
PDS00
8/16-bit PPG00 duty setting buffer register
R/W
0b11111111
Wild register data test setting register
Mirror of register bank pointer (RP) and direct bank
pointer (DP)
(Disabled)
(Disabled)
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MB95810K Series
Address
Register
abbreviation
0x0FA0
PPS11
0x0FA1
R/W
Initial value
8/16-bit PPG11 cycle setting buffer register
R/W
0b11111111
PPS10
8/16-bit PPG10 cycle setting buffer register
R/W
0b11111111
0x0FA2
PDS11
8/16-bit PPG11 duty setting buffer register
R/W
0b11111111
0x0FA3
PDS10
8/16-bit PPG10 duty setting buffer register
R/W
0b11111111
0x0FA4
PPGS
8/16-bit PPG start register
R/W
0b00000000
0x0FA5
REVC
8/16-bit PPG output inversion register
R/W
0b00000000
R/W
0b00000000
R/W
0b00000000
—
—
0x0FA6
0x0FA7
Register name
TMRH0
16-bit reload timer timer register (upper) ch. 0
TMRLRH0
16-bit reload timer reload register (upper) ch. 0
TMRL0
16-bit reload timer timer register (lower) ch. 0
TMRLRL0
16-bit reload timer reload register (lower) ch. 0
0x0FA8,
0x0FA9
—
0x0FAA
PDCRH0
16-bit PPG downcounter register (upper) ch. 0
R
0b00000000
0x0FAB
PDCRL0
16-bit PPG downcounter register (lower) ch. 0
R
0b00000000
0x0FAC
PCSRH0
16-bit PPG cycle setting buffer register (upper) ch. 0
R/W
0b11111111
0x0FAD
PCSRL0
16-bit PPG cycle setting buffer register (lower) ch. 0
R/W
0b11111111
0x0FAE
PDUTH0
16-bit PPG duty setting buffer register (upper) ch. 0
R/W
0b11111111
0x0FAF
PDUTL0
16-bit PPG duty setting buffer register (lower) ch. 0
R/W
0b11111111
0x0FB0
PDCRH1
16-bit PPG downcounter register (upper) ch. 1
R
0b00000000
0x0FB1
PDCRL1
16-bit PPG downcounter register (lower) ch. 1
R
0b00000000
0x0FB2
PCSRH1
16-bit PPG cycle setting buffer register (upper) ch. 1
R/W
0b11111111
0x0FB3
PCSRL1
16-bit PPG cycle setting buffer register (lower) ch. 1
R/W
0b11111111
0x0FB4
PDUTH1
16-bit PPG duty setting buffer register (upper) ch. 1
R/W
0b11111111
0x0FB5
PDUTL1
16-bit PPG duty setting buffer register (lower) ch. 1
R/W
0b11111111
0x0FB6
to
0x0FBB
—
—
—
0x0FBC
BGR1
LIN-UART baud rate generator register 1
R/W
0b00000000
0x0FBD
BGR0
LIN-UART baud rate generator register 0
R/W
0b00000000
0x0FBE
PSSR0
UART/SIO dedicated baud rate generator prescaler
select register ch. 0
R/W
0b00000000
0x0FBF
BRSR0
UART/SIO dedicated baud rate generator baud rate
setting register ch. 0
R/W
0b00000000
0x0FC0,
0x0FC1
—
—
—
0x0FC2
AIDRH
A/D input disable register (upper)
R/W
0b00000000
0x0FC3
AIDRL
A/D input disable register (lower)
R/W
0b00000000
0x0FC4
LVDPW
LVD reset circuit password register
R/W
0b00000000
(Disabled)
(Disabled)
(Disabled)
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MB95810K Series
Address
Register
abbreviation
Register name
R/W
Initial value
0x0FC5
to
0x0FE2
—
(Disabled)
—
—
0x0FE3
WCDR
Watch counter data register
R/W
0b00111111
0x0FE4
CRTH
Main CR clock trimming register (upper)
R/W
0b000XXXXX
0x0FE5
CRTL
Main CR clock trimming register (lower)
R/W
0b000XXXXX
0x0FE6
—
—
—
0x0FE7
CRTDA
Main CR clock temperature dependent adjustment
register
R/W
0b000XXXXX
0x0FE8
SYSC
System configuration register
R/W
0b11000011
0x0FE9
CMCR
Clock monitoring control register
R/W
0b00000000
0x0FEA
CMDR
Clock monitoring data register
R
0b00000000
0x0FEB
WDTH
Watchdog timer selection ID register (upper)
R
0bXXXXXXXX
0x0FEC
WDTL
Watchdog timer selection ID register (lower)
R
0bXXXXXXXX
0x0FED,
0x0FEE
—
—
—
0x0FEF
WICR
R/W
0b01000000
0x0FF0
to
0x0FFF
—
—
—
(Disabled)
(Disabled)
Interrupt pin selection circuit control register
(Disabled)
• R/W access symbols
R/W : Readable/Writable
R
: Read only
• Initial value symbols
0
: The initial value of this bit is “0”.
1
: The initial value of this bit is “1”.
X
: The initial value of this bit is undefined.
Note: Do not write to an address that is “(Disabled)”. If a “(Disabled)” address is read, an indeterminate value is returned.
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MB95810K Series
15. I/O Ports
• List of port registers
Register name
Read/Write
Initial value
Port 0 data register
PDR0
R, RM/W
0b00000000
Port 0 direction register
DDR0
R/W
0b00000000
Port 1 data register
PDR1
R, RM/W
0b00000000
Port 1 direction register
DDR1
R/W
0b00000000
Port 2 data register
PDR2
R, RM/W
0b00000000
Port 2 direction register
DDR2
R/W
0b00000000
Port 3 data register
PDR3
R, RM/W
0b00000000
Port 3 direction register
DDR3
R/W
0b00000000
Port 4 data register
PDR4
R, RM/W
0b00000000
Port 4 direction register
DDR4
R/W
0b00000000
Port 5 data register
PDR5
R, RM/W
0b00000000
Port 5 direction register
DDR5
R/W
0b00000000
Port 6 data register
PDR6
R, RM/W
0b00000000
Port 6 direction register
DDR6
R/W
0b00000000
Port 7 data register
PDR7
R, RM/W
0b00000000
Port 7 direction register
DDR7
R/W
0b00000000
Port 8 data register
PDR8
R, RM/W
0b00000000
Port 8 direction register
DDR8
R/W
0b00000000
Port E data register
PDRE
R, RM/W
0b00000000
Port E direction register
DDRE
R/W
0b00000000
Port F data register
PDRF
R, RM/W
0b00000000
Port F direction register
DDRF
R/W
0b00000000
Port G data register
PDRG
R, RM/W
0b00000000
Port G direction register
DDRG
R/W
0b00000000
Port 0 pull-up register
PUL0
R/W
0b00000000
Port 1 pull-up register
PUL1
R/W
0b00000000
Port 2 pull-up register
PUL2
R/W
0b00000000
Port 3 pull-up register
PUL3
R/W
0b00000000
Port 4 pull-up register
PUL4
R/W
0b00000000
Port 5 pull-up register
PUL5
R/W
0b00000000
Port 6 pull-up register
PUL6
R/W
0b00000000
Port 7 pull-up register
PUL7
R/W
0b00000000
Port 8 pull-up register
PUL8
R/W
0b00000000
Port E pull-up register
PULE
R/W
0b00000000
Port G pull-up register
PULG
R/W
0b00000000
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MB95810K Series
Register name
Read/Write
Initial value
A/D input disable register (upper)
AIDRH
R/W
0b00000000
A/D input disable register (lower)
AIDRL
R/W
0b00000000
R/W
: Readable/writable (The read value is the same as the write value.)
R, RM/W : Readable/writable (The read value is different from the write value. The write value is read by the readmodify-write (RMW) type of instruction.)
15.1 Port 0
Port 0 is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of
peripheral functions, refer to their respective chapters in “New 8FX MB95810K Series Hardware Manual”.
15.1.1 Port 0 configuration
Port 0 is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port 0 data register (PDR0)
• Port 0 direction register (DDR0)
• Port 0 pull-up register (PUL0)
15.1.2 Block diagrams of port 0
• P00/INT00 pin
This pin has the following peripheral function:
• External interrupt input pin (INT00)
• P01/INT01 pin
This pin has the following peripheral function:
• External interrupt input pin (INT01)
• P02/INT02 pin
This pin has the following peripheral function:
External interrupt input pin (INT02)
• P03/INT03 pin
This pin has the following peripheral function:
• External interrupt input pin (INT03)
• P04/INT04 pin
This pin has the following peripheral function:
• External interrupt input pin (INT04)
• P05/INT05 pin
This pin has the following peripheral function:
• External interrupt input pin (INT05)
• P06/INT06 pin
This pin has the following peripheral function:
• External interrupt input pin (INT06)
• P07/INT07 pin
This pin has the following peripheral function:
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MB95810K Series
• External interrupt input pin (INT07)
• Block diagram of P00/INT00, P01/INT01, P02/INT02, P03/INT03, P04/INT04, P05/INT05, P06/INT06 and P07/INT07
Peripheral function input
Peripheral function input enable
(INT00 to INT07)
Hysteresis
0
Pull-up
1
PDR0 read
Pin
PDR0
PDR0 write
Internal bus
Executing bit manipulation instruction
DDR0 read
DDR0
DDR0 write
Stop mode, watch mode (SPL = 1)
PUL0 read
PUL0
PUL0 write
15.1.3 Port 0 registers
• Port 0 register functions
Register
abbreviation
PDR0
DDR0
PUL0
Data
Read
Read by read-modify-write
(RMW) instruction
Write
0
Pin state is “L” level.
PDR0 value is “0”.
As output port, outputs “L” level.
1
Pin state is “H” level.
PDR0 value is “1”.
As output port, outputs “H” level.
0
Port input enabled
1
Port output enabled
0
Pull-up disabled
1
Pull-up enabled
• Correspondence between registers and pins for port 0
Correspondence between related register bits and pins
Pin name
P07
P06
P05
P04
P03
P02
P01
P00
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
PDR0
DDR0
PUL0
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MB95810K Series
15.1.4 Port 0 operations
• Operation as an output port
• A pin becomes an output port if the bit in the DDR0 register corresponding to that pin is set to “1”.
• For a pin shared with other peripheral functions, disable the output of such peripheral functions.
• When a pin is used as an output port, it outputs the value of the PDR0 register to external pins.
• If data is written to the PDR0 register, the value is stored in the output latch and is output to the pin set as an output
port as it is.
• Reading the PDR0 register returns the PDR0 register value.
• Operation as an input port
• A pin becomes an input port if the bit in the DDR0 register corresponding to that pin is set to “0”.
• For a pin shared with other peripheral functions, disable the output of such peripheral functions.
• If data is written to the PDR0 register, the value is stored in the output latch but is not output to the pin set as an
input port.
• Reading the PDR0 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is
used to read the PDR0 register, the PDR0 register value is returned.
• Operation as a peripheral function input pin
• To set a pin as an input port, set the bit in the DDR0 register corresponding to the input pin of a peripheral function
to “0”.
• Reading the PDR0 register returns the pin value, regardless of whether the peripheral function uses that pin as its
input pin. However, if the read-modify-write (RMW) type of instruction is used to read the PDR0 register, the PDR0
register value is returned.
• Operation at reset
If the CPU is reset, all bits in the DDR0 register are initialized to “0” and port input is enabled.
• Operation in stop mode and watch mode
• If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop
mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR0 register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open. However, if the interrupt input is enabled for the external interrupt (INT00 to INT07), the input is enabled and not
blocked.
• If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged
and the output level is maintained.
• Operation as an external interrupt input pin
• Set the bit in the DDR0 register corresponding to the external interrupt input pin to “0”.
• For a pin shared with other peripheral functions, disable the output of such peripheral functions.
• The pin value is always input to the external interrupt circuit. When using a pin for a function other than the interrupt,
disable the external interrupt function corresponding to that pin.
• Operation of the pull-up register
Setting the bit in the PUL0 register to “1” makes the pull-up resistor be internally connected to the pin. When the pin
output is “L” level, the pull-up resistor is disconnected regardless of the value of the PUL0 register.
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MB95810K Series
15.2 Port 1
Port 1 is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of
peripheral functions, refer to their respective chapters in “New 8FX MB95810K Series Hardware Manual”.
15.2.1 Port 1 configuration
Port 1 is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port 1 data register (PDR1)
• Port 1 direction register (DDR1)
• Port 1 pull-up register (PUL1)
15.2.2 Block diagrams of port 1
• P10/UI0 pin
This pin has the following peripheral function:
• UART/SIO ch. 0 data input pin (UI0)
• Block diagram of P10/UI0
Peripheral function input
Peripheral function input enable
CMOS
0
Pull-up
1
PDR1 read
PDR1
Pin
PDR1 write
Internal bus
Executing bit manipulation instruction
DDR1 read
DDR1
DDR1 write
Stop mode, watch mode (SPL = 1)
PUL1 read
PUL1
PUL1 write
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MB95810K Series
• P11/UO0 pin
This pin has the following peripheral function:
• UART/SIO ch. 0 data output pin (UO0)
• Block diagram of P11/UO0
Peripheral function output enable
Peripheral function output
Hysteresis
Pull-up
0
1
PDR1 read
1
PDR1
Pin
0
PDR1 write
Internal bus
Executing bit manipulation instruction
DDR1 read
DDR1
DDR1 write
Stop mode, watch mode (SPL = 1)
PUL1 read
PUL1
PUL1 write
• P12/DBG pin
This pin has the following peripheral function:
• DBG input pin (DBG)
• Block diagram of P12/DBG
Hysteresis
0
1
PDR1 read
Internal bus
PDR1
Pin
OD
PDR1 write
Executing bit manipulation instruction
DDR1 read
DDR1
DDR1 write
Stop mode, watch mode (SPL = 1)
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• P13/UCK0/TRG0/ADTG* pin
This pin has the following peripheral functions:
• UART/SIO ch. 0 clock I/O pin (UCK0)
• 16-bit PPG timer ch. 0 trigger input pin (TRG0)
• 8/10-bit A/D converter trigger input pin (ADTG)
*: TRG0 and ADTG can be mapped to either P13 or P83 by using the SYSC register.
• Block diagram of P13/UCK0/TRG0/ADTG
Peripheral function input
Peripheral function input enable
Peripheral function output enable
Peripheral function output
Hysteresis
Pull-up
0
1
PDR1 read
1
PDR1
0
Pin
PDR1 write
Internal bus
Executing bit manipulation instruction
DDR1 read
DDR1
DDR1 write
Stop mode, watch mode (SPL = 1)
PUL1 read
PUL1
PUL1 write
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• P14/PPG0 pin
This pin has the following peripheral function:
• 16-bit PPG timer ch. 0 output pin (PPG0)
• Block diagram of P14/PPG0
Peripheral function output enable
Peripheral function output
Hysteresis
Pull-up
0
1
PDR1 read
1
PDR1
Pin
0
PDR1 write
Internal bus
Executing bit manipulation instruction
DDR1 read
DDR1
DDR1 write
Stop mode, watch mode (SPL = 1)
PUL1 read
PUL1
PUL1 write
15.2.3 Port 1 registers
• Port 1 register functions
Register
abbreviation
PDR1
DDR1
PUL1
Data
Read
Read by read-modify-write
(RMW) instruction
Write
0
Pin state is “L” level.
PDR1 value is “0”.
As output port, outputs “L” level.
1
Pin state is “H” level.
PDR1 value is “1”.
As output port, outputs “H” level.*
0
Port input enabled
1
Port output enabled
0
Pull-up disabled
1
Pull-up enabled
*: If the pin is an N-ch open drain pin, the pin state becomes Hi-Z.
• Correspondence between registers and pins for port 1
Correspondence between related register bits and pins
Pin name
-
-
-
P14
P13
P12
P11
P10
-
-
-
bit4
bit3
bit2*
bit1
bit0
PDR1
DDR1
PUL1
*: Though P12 has no pull-up function, bit2 in the PUL1 register can still be accessed. The operation of P12 is not affected by the setting of bit2 in the PUL1 register.
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15.2.4 Port 1 operations
• Operation as an output port
• A pin becomes an output port if the bit in the DDR1 register corresponding to that pin is set to “1”.
• For a pin shared with other peripheral functions, disable the output of such peripheral functions.
• When a pin is used as an output port, it outputs the value of the PDR1 register to external pins.
• If data is written to the PDR1 register, the value is stored in the output latch and is output to the pin set as an output
port as it is.
• Reading the PDR1 register returns the PDR1 register value.
• Operation as an input port
• A pin becomes an input port if the bit in the DDR1 register corresponding to that pin is set to “0”.
• For a pin shared with other peripheral functions, disable the output of such peripheral functions.
• If data is written to the PDR1 register, the value is stored in the output latch but is not output to the pin set as an
input port.
• Reading the PDR1 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is
used to read the PDR1 register, the PDR1 register value is returned.
• Operation as a peripheral function output pin
• A pin becomes a peripheral function output pin if the peripheral output function is enabled by setting the output
enable bit of a peripheral function corresponding to that pin.
• The pin value can be read from the PDR1 register even if the peripheral function output is enabled. Therefore, the
output value of a peripheral function can be read by the read operation on the PDR1 register. However, if the readmodify-write (RMW) type of instruction is used to read the PDR1 register, the PDR1 register value is returned.
• Operation as a peripheral function input pin
• To set a pin as an input port, set the bit in the DDR1 register corresponding to the input pin of a peripheral function
to “0”.
• Reading the PDR1 register returns the pin value, regardless of whether the peripheral function uses that pin as its
input pin. However, if the read-modify-write (RMW) type of instruction is used to read the PDR1 register, the PDR1
register value is returned.
• Operation at reset
If the CPU is reset, all bits in the DDR1 register are initialized to “0” and port input is enabled.
• Operation in stop mode and watch mode
• If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop
mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR1 register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open. However, if the interrupt input of P10/UI0 and P13/UCK0/TRG0/ADTG is enabled by the external interrupt control
register ch. 0 (EIC00) of the external interrupt circuit and the interrupt pin selection circuit control register (WICR)
of the interrupt pin selection circuit, the input is enabled and is not blocked.
• If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged
and the output level is maintained.
• Operation of the pull-up register
Setting the bit in the PUL1 register to “1” makes the pull-up resistor be internally connected to the pin. When the pin
output is “L” level, the pull-up resistor is disconnected regardless of the value of the PUL1 register.
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15.3 Port 2
Port 2 is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of
peripheral functions, refer to their respective chapters in “New 8FX MB95810K Series Hardware Manual”.
15.3.1 Port 2 configuration
Port 2 is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port 2 data register (PDR2)
• Port 2 direction register (DDR2)
• Port 2 pull-up register (PUL2)
15.3.2 Block diagrams of port 2
• P20/PPG00 pin
This pin has the following peripheral function:
• 8/16-bit PPG ch. 0 output pin (PPG00)
• P21/PPG01 pin
This pin has the following peripheral function:
• 8/16-bit PPG ch. 0 output pin (PPG01)
• P22/TO00 pin
This pin has the following peripheral function:
• 8/16-bit composite timer ch. 0 output pin (TO00)
• P23/TO01 pin
This pin has the following peripheral function:
• 8/16-bit composite timer ch. 0 output pin (TO01)
• Block diagram of P20/PPG00, P21/PPG01, P22/TO00 and P23/TO01
Peripheral function output enable
Peripheral function output
Hysteresis
Pull-up
0
1
PDR2 read
1
PDR2
0
Pin
PDR2 write
Internal bus
Executing bit manipulation instruction
DDR2 read
DDR2
DDR2 write
Stop mode, watch mode (SPL = 1)
PUL2 read
PUL2
PUL2 write
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• P24/EC0 pin
This pin has the following peripheral function:
• 8/16-bit composite timer ch. 0 clock input pin (EC0)
• Block diagram of P24/EC0
Peripheral function input
Peripheral function input enable
Hysteresis
0
Pull-up
1
PDR2 read
Pin
PDR2
PDR2 write
Internal bus
Executing bit manipulation instruction
DDR2 read
DDR2
DDR2 write
Stop mode, watch mode (SPL = 1)
PUL2 read
PUL2
PUL2 write
15.3.3 Port 2 registers
• Port 2 register functions
Register
abbreviation
PDR2
DDR2
PUL2
Data
Read
Read by read-modify-write
(RMW) instruction
Write
0
Pin state is “L” level.
PDR2 value is “0”.
As output port, outputs “L” level.
1
Pin state is “H” level.
PDR2 value is “1”.
As output port, outputs “H” level.
0
Port input enabled
1
Port output enabled
0
Pull-up disabled
1
Pull-up enabled
• Correspondence between registers and pins for port 2
Correspondence between related register bits and pins
Pin name
-
-
-
P24
P23
P22
P21
P20
-
-
-
bit4
bit3
bit2
bit1
bit0
PDR2
DDR2
PUL2
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15.3.4 Port 2 operations
• Operation as an output port
• A pin becomes an output port if the bit in the DDR2 register corresponding to that pin is set to “1”.
• For a pin shared with other peripheral functions, disable the output of such peripheral functions.
• When a pin is used as an output port, it outputs the value of the PDR2 register to external pins.
• If data is written to the PDR2 register, the value is stored in the output latch and is output to the pin set as an output
port as it is.
• Reading the PDR2 register returns the PDR2 register value.
• Operation as an input port
• A pin becomes an input port if the bit in the DDR2 register corresponding to that pin is set to “0”.
• For a pin shared with other peripheral functions, disable the output of such peripheral functions.
• If data is written to the PDR2 register, the value is stored in the output latch but is not output to the pin set as an
input port.
• Reading the PDR2 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is
used to read the PDR2 register, the PDR2 register value is returned.
• Operation as a peripheral function output pin
• A pin becomes a peripheral function output pin if the peripheral output function is enabled by setting the output
enable bit of a peripheral function corresponding to that pin.
• The pin value can be read from the PDR2 register even if the peripheral function output is enabled. Therefore, the
output value of a peripheral function can be read by the read operation on the PDR2 register. However, if the readmodify-write (RMW) type of instruction is used to read the PDR2 register, the PDR2 register value is returned.
• Operation as a peripheral function input pin
• To set a pin as an input port, set the bit in the DDR2 register corresponding to the input pin of a peripheral function
to “0”.
• Reading the PDR2 register returns the pin value, regardless of whether the peripheral function uses that pin as its
input pin. However, if the read-modify-write (RMW) type of instruction is used to read the PDR2 register, the PDR2
register value is returned.
• Operation at reset
If the CPU is reset, all bits in the DDR2 register are initialized to “0” and port input is enabled.
• Operation in stop mode and watch mode
• If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop
mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR2 register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open. However, if the interrupt input of P24/EC0 is enabled by the external interrupt control register ch. 0 (EIC00) of the
external interrupt circuit and the interrupt pin selection circuit control register (WICR) of the interrupt pin selection
circuit, the input is enabled and is not blocked.
• If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged
and the output level is maintained.
• Operation of the pull-up register
Setting the bit in the PUL2 register to “1” makes the pull-up resistor be internally connected to the pin. When the pin
output is “L” level, the pull-up resistor is disconnected regardless of the value of the PUL2 register.
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15.4 Port 3
Port 3 is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of
peripheral functions, refer to their respective chapters in “New 8FX MB95810K Series Hardware Manual”.
15.4.1 Port 3 configuration
Port 3 is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port 3 data register (PDR3)
• Port 3 direction register (DDR3)
• Port 3 pull-up register (PUL3)
• A/D input disable register (lower) (AIDRL)
15.4.2 Block diagrams of port 3
• P30/AN00/CMP0_N pin
This pin has the following peripheral functions:
• 8/10-bit A/D converter analog input pin (AN00)
• Comparator ch. 0 inverting analog input (negative input) pin (CMP0_N)
• P31/AN01/CMP0_P pin
This pin has the following peripheral functions:
• 8/10-bit A/D converter analog input pin (AN01)
• Comparator ch. 0 non-inverting analog input (positive input) pin (CMP0_P)
• P33/AN03/CMP1_N pin
This pin has the following peripheral functions:
• 8/10-bit A/D converter analog input pin (AN03)
• Comparator ch. 1 inverting analog input (negative input) pin (CMP1_N)
• P34/AN04/CMP1_P pin
This pin has the following peripheral functions:
• 8/10-bit A/D converter analog input pin (AN04)
• Comparator ch. 1 non-inverting analog input (positive input) pin (CMP1_P)
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• Block diagram of P30/AN00/CMP0_N, P31/AN01/CMP0_P, P33/AN03/CMP1_N and P34/AN04/CMP1_P
Comparator analog input
Comparator analog input disable
A/D analog input
Hysteresis
0
Pull-up
1
PDR3 read
PDR3
Pin
PDR3 write
Internal bus
Executing bit manipulation instruction
DDR3 read
DDR3
DDR3 write
Stop mode, watch mode (SPL = 1)
PUL3 read
PUL3
PUL3 write
AIDRL read
AIDRL
AIDRL write
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• P32/AN02/CMP0_O pin
This pin has the following peripheral functions:
• 8/10-bit A/D converter analog input pin (AN02)
• Comparator ch. 0 digital output pin (CMP0_O)
• P35/AN05/CMP1_O pin
This pin has the following peripheral functions:
• 8/10-bit A/D converter analog input pin (AN05)
• Comparator ch. 1 digital output pin (CMP1_O)
• Block diagram of P32/AN02/CMP0_O and P35/AN05/CMP1_O
A/D analog input
Peripheral function output enable
Peripheral function output
Hysteresis
Pull-up
0
1
PDR3 read
1
PDR3
0
Pin
PDR3 write
Internal bus
Executing bit manipulation instruction
DDR3 read
DDR3
DDR3 write
Stop mode, watch mode (SPL = 1)
PUL3 read
PUL3
PUL3 write
AIDRL read
AIDRL
AIDRL write
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• P36/AN06 pin
This pin has the following peripheral function:
• 8/10-bit A/D converter analog input pin (AN06)
• P37/AN07 pin
This pin has the following peripheral function:
• 8/10-bit A/D converter analog input pin (AN07)
• Block diagram of P36/AN06 and P37/AN07
A/D analog input
Hysteresis
0
Pull-up
1
PDR3 read
PDR3
Pin
PDR3 write
Internal bus
Executing bit manipulation instruction
DDR3 read
DDR3
DDR3 write
Stop mode, watch mode (SPL = 1)
PUL3 read
PUL3
PUL3 write
AIDRL read
AIDRL
AIDRL write
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15.4.3 Port 3 registers
• Port 3 register functions
Register
abbreviation
PDR3
DDR3
PUL3
AIDRL
Data
Read
Read by read-modify-write
(RMW) instruction
Write
0
Pin state is “L” level.
PDR3 value is “0”.
As output port, outputs “L” level.
1
Pin state is “H” level.
PDR3 value is “1”.
As output port, outputs “H” level.
0
Port input enabled
1
Port output enabled
0
Pull-up disabled
1
Pull-up enabled
0
Analog input enabled
1
Port input enabled
• Correspondence between registers and pins for port 3
Correspondence between related register bits and pins
Pin name
P37
P36
P35
P34
P33
P32
P31
P30
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
PDR3
DDR3
PUL3
AIDRL
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15.4.4 Port 3 operations
• Operation as an output port
• A pin becomes an output port if the bit in the DDR3 register corresponding to that pin is set to “1”.
• For a pin shared with other peripheral functions, disable the output of such peripheral functions.
• When a pin is used as an output port, it outputs the value of the PDR3 register to external pins.
• If data is written to the PDR3 register, the value is stored in the output latch and is output to the pin set as an output
port as it is.
• Reading the PDR3 register returns the PDR3 register value.
• Operation as an input port
• A pin becomes an input port if the bit in the DDR3 register corresponding to that pin is set to “0”.
• For a pin shared with other peripheral functions, disable the output of such peripheral functions.
• When using a pin shared with the analog input function as an input port, set the corresponding bit in the A/D input
disable register (lower) (AIDRL) to “1”.
• If data is written to the PDR3 register, the value is stored in the output latch but is not output to the pin set as an
input port.
• Reading the PDR3 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is
used to read the PDR3 register, the PDR3 register value is returned.
• Operation as a peripheral function output pin
• A pin becomes a peripheral function output pin if the peripheral output function is enabled by setting the output
enable bit of a peripheral function corresponding to that pin.
• The pin value can be read from the PDR3 register even if the peripheral function output is enabled. Therefore, the
output value of a peripheral function can be read by the read operation on the PDR3 register. However, if the readmodify-write (RMW) type of instruction is used to read the PDR3 register, the PDR3 register value is returned.
• Operation as a peripheral function input pin
• To set a pin as an input port, set the bit in the DDR3 register corresponding to the input pin of a peripheral function
to “0”.
• When using a pin shared with the analog input function as another peripheral function input pin, configure it as an
input port by setting the bit in the AIDRL register corresponding to that pin to “1”.
• Reading the PDR3 register returns the pin value, regardless of whether the peripheral function uses that pin as its
input pin. However, if the read-modify-write (RMW) type of instruction is used to read the PDR3 register, the PDR3
register value is returned.
• Operation at reset
If the CPU is reset, all bits in the DDR3 register are initialized to “0” and port input is enabled. As for a pin shared with
the analog input function, its port input is disabled because the AIDRL register is initialized to “0”.
• Operation in stop mode and watch mode
• If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop
mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR3 register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open.
• If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged
and the output level is maintained.
• Operation as an analog input pin
• Set the bit in the DDR3 register bit corresponding to the analog input pin to “0” and the bit corresponding to that pin
in the AIDRL register to “0”.
• For a pin shared with other peripheral functions, disable the output of such peripheral functions. In addition, set the
corresponding bit in the PUL3 register to “0”.
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• Operation of the pull-up register
Setting the bit in the PUL3 register to “1” makes the pull-up resistor be internally connected to the pin. When the pin
output is “L” level, the pull-up resistor is disconnected regardless of the value of the PUL3 register.
• Operation as a comparator input pin (only for P31 and P34)
• Set the bit in the AIDRL register corresponding to the comparator input pin to “0”.
• Regardless of the value of the PDR3 register and that of the DDR3 register, if the comparator analog input enable
bit in the comparator control register ch. 0/ch. 1 (CMR0/CMR1:VCID) is set to “0”, the comparator input function is
enabled.
• To disable the comparator input function, set the VCID bit to “1”.
• For details of the comparator, refer to “CHAPTER 28 COMPARATOR” in “New 8FX MB95810K Series Hardware
Manual”.
• Operation as a comparator input pin (only for P30 and P33)
• Set the bit in the AIDRL register corresponding to the comparator input pin to “0”.
• Regardless of the value of the PDR3 register and that of the DDR3 register, if the comparator analog input enable
bit (VCID) and the negative analog input voltage source select bit (BGRS) in the comparator control register ch.
0/ch. 1 (CMR0/CMR1) are both set to “0”, the comparator input function is enabled.
• To disable the comparator input function, set the VCID bit or the BGRS bit to “1”.
• For details of the comparator, refer to “CHAPTER 28 COMPARATOR” in “New 8FX MB95810K Series Hardware
Manual”.
15.5 Port 4
Port 4 is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of
peripheral functions, refer to their respective chapters in “New 8FX MB95810K Series Hardware Manual”.
15.5.1 Port 4 configuration
Port 4 is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port 4 data register (PDR4)
• Port 4 direction register (DDR4)
• Port 4 pull-up register (PUL4)
• A/D input disable register (upper) (AIDRH)
15.5.2 Block diagrams of port 4
• P40/AN08 pin
This pin has the following peripheral function:
• 8/10-bit A/D converter analog input pin (AN08)
• P41/AN09 pin
This pin has the following peripheral function:
• 8/10-bit A/D converter analog input pin (AN09)
• P42/AN10 pin
This pin has the following peripheral function:
• 8/10-bit A/D converter analog input pin (AN10)
• P43/AN11 pin
This pin has the following peripheral function:
• 8/10-bit A/D converter analog input pin (AN11)
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• Block diagram of P40/AN08, P41/AN09, P42/AN10 and P43/AN11
A/D analog input
Hysteresis
0
Pull-up
1
PDR4 read
Pin
PDR4
PDR4 write
Internal bus
Executing bit manipulation instruction
DDR4 read
DDR4
DDR4 write
Stop mode, watch mode (SPL = 1)
PUL4 read
PUL4
PUL4 write
AIDRH read
AIDRH
AIDRH write
15.5.3 Port 4 registers
• Port 4 register functions
Register
abbreviation
PDR4
DDR4
PUL4
AIDRH
Data
Read
Read by read-modify-write
(RMW) instruction
Write
0
Pin state is “L” level.
PDR4 value is “0”.
As output port, outputs “L” level.
1
Pin state is “H” level.
PDR4 value is “1”.
As output port, outputs “H” level.
0
Port input enabled
1
Port output enabled
0
Pull-up disabled
1
Pull-up enabled
0
Analog input enabled
1
Port input enabled
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• Correspondence between registers and pins for port 4
Correspondence between related register bits and pins
Pin name
-
-
-
-
P43
P42
P41
P40
-
-
-
-
bit3
bit2
bit1
bit0
PDR4
DDR4
PUL4
AIDRH
15.5.4 Port 4 operations
• Operation as an output port
• A pin becomes an output port if the bit in the DDR4 register corresponding to that pin is set to “1”.
• For a pin shared with other peripheral functions, disable the output of such peripheral functions.
• When a pin is used as an output port, it outputs the value of the PDR4 register to external pins.
• If data is written to the PDR4 register, the value is stored in the output latch and is output to the pin set as an output
port as it is.
• Reading the PDR4 register returns the PDR4 register value.
• Operation as an input port
• A pin becomes an input port if the bit in the DDR4 register corresponding to that pin is set to “0”.
• For a pin shared with other peripheral functions, disable the output of such peripheral functions.
• When using a pin shared with the analog input function as an input port, set the corresponding bit in the A/D input
disable register (upper) (AIDRH) to “1”.
• If data is written to the PDR4 register, the value is stored in the output latch but is not output to the pin set as an
input port.
• Reading the PDR4 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is
used to read the PDR4 register, the PDR4 register value is returned.
• Operation as a peripheral function input pin
• To set a pin as an input port, set the bit in the DDR4 register corresponding to the input pin of a peripheral function
to “0”.
• When using a pin shared with the analog input function as another peripheral function input pin, configure it as an
input port by setting the bit in the AIDRH register corresponding to that pin to “1”.
• Reading the PDR4 register returns the pin value, regardless of whether the peripheral function uses that pin as its
input pin. However, if the read-modify-write (RMW) type of instruction is used to read the PDR4 register, the PDR4
register value is returned.
• Operation at reset
If the CPU is reset, all bits in the DDR4 register are initialized to “0” and port input is enabled. As for a pin shared with
the analog input function, its port input is disabled because the AIDRH register is initialized to “0”.
• Operation in stop mode and watch mode
• If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop
mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR4 register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open.
• If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged
and the output level is maintained.
• Operation as an analog input pin
• Set the bit in the DDR4 register bit corresponding to the analog input pin to “0” and the bit corresponding to that pin
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in the AIDRH register to “0”.
• For a pin shared with other peripheral functions, disable the output of such peripheral functions. In addition, set the
corresponding bit in the PUL4 register to “0”.
• Operation of the pull-up register
Setting the bit in the PUL4 register to “1” makes the pull-up resistor be internally connected to the pin. When the pin
output is “L” level, the pull-up resistor is disconnected regardless of the value of the PUL4 register.
15.6 Port 5
Port 5 is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of
peripheral functions, refer to their respective chapters in “New 8FX MB95810K Series Hardware Manual”.
15.6.1 Port 5 configuration
Port 5 is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port 5 data register (PDR5)
• Port 5 direction register (DDR5)
• Port 5 pull-up register (PUL5)
15.6.2 Block diagrams of port 5
• P50/SCL pin
This pin has the following peripheral function:
• I2C bus interface ch. 0 clock I/O pin (SCL)
• P51/SDA pin
This pin has the following peripheral function:
• I2C bus interface ch. 0 data I/O pin (SDA)
• Block diagram of P50/SCL and P51/SDA
Peripheral function input
Peripheral function input enable
Peripheral function input enable
Peripheral function output
CMOS
0
1
PDR5 read
PDR5
Internal bus
Pin
1
0
OD
PDR5 write
Executing bit manipulation instruction
DDR5 read
DDR5
DDR5 write
Stop mode, watch mode (SPL = 1)
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• P52/PPG1 pin
This pin has the following peripheral function:
• 16-bit PPG timer ch. 1 output pin (PPG1)
• Block diagram of P52/PPG1
Peripheral function output enable
Peripheral function output
Hysteresis
Pull-up
0
1
PDR5 read
1
PDR5
0
Pin
PDR5 write
Internal bus
Executing bit manipulation instruction
DDR5 read
DDR5
DDR5 write
Stop mode, watch mode (SPL = 1)
PUL5 read
PUL5
PUL5 write
• P53/TRG1 pin
This pin has the following peripheral function:
• 16-bit PPG timer ch. 1 trigger input pin (TRG1)
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• Block diagram of P53/TRG1
Peripheral function input
Hysteresis
0
Pull-up
1
PDR5 read
PDR5
Pin
PDR5 write
Internal bus
Executing bit manipulation instruction
DDR5 read
DDR5
DDR5 write
Stop mode, watch mode (SPL = 1)
PUL5 read
PUL5
PUL5 write
15.6.3 Port 5 registers
• Port 5 register functions
Register
abbreviation
PDR5
DDR5
PUL5
Data
Read
Read by read-modify-write
(RMW) instruction
Write
0
Pin state is “L” level.
PDR5 value is “0”.
As output port, outputs “L” level.
1
Pin state is “H” level.
PDR5 value is “1”.
As output port, outputs “H” level.*
0
Port input enabled
1
Port output enabled
0
Pull-up disabled
1
Pull-up enabled
*: If the pin is an N-ch open drain pin, the pin state becomes Hi-Z.
• Correspondence between registers and pins for port 5
Correspondence between related register bits and pins
Pin name
-
-
-
-
P53
P52
P51
P50
-
-
-
-
bit3
bit2
bit1*
bit0*
PDR5
DDR5
PUL5
*: Though P50 and P51 have no pull-up function, bit0 and bit1 in the PUL5 register can still be accessed. The operation
of P50 and P51 is not affected by the settings of bit0 and bit1 in the PUL5 register.
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15.6.4 Port 5 operations
• Operation as an output port
• A pin becomes an output port if the bit in the DDR5 register corresponding to that pin is set to “1”.
• For a pin shared with other peripheral functions, disable the output of such peripheral functions.
• When a pin is used as an output port, it outputs the value of the PDR5 register to external pins.
• If data is written to the PDR5 register, the value is stored in the output latch and is output to the pin set as an output
port as it is.
• Reading the PDR5 register returns the PDR5 register value.
• Operation as an input port
• A pin becomes an input port if the bit in the DDR5 register corresponding to that pin is set to “0”.
• For a pin shared with other peripheral functions, disable the output of such peripheral functions.
• If data is written to the PDR5 register, the value is stored in the output latch but is not output to the pin set as an
input port.
• Reading the PDR5 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is
used to read the PDR5 register, the PDR5 register value is returned.
• Operation as a peripheral function output pin
• A pin becomes a peripheral function output pin if the peripheral output function is enabled by setting the output
enable bit of a peripheral function corresponding to that pin.
• The pin value can be read from the PDR5 register even if the peripheral function output is enabled. Therefore, the
output value of a peripheral function can be read by the read operation on the PDR5 register. However, if the readmodify-write (RMW) type of instruction is used to read the PDR5 register, the PDR5 register value is returned.
• Operation as a peripheral function input pin
• To set a pin as an input port, set the bit in the DDR5 register corresponding to the input pin of a peripheral function
to “0”.
• Reading the PDR5 register returns the pin value, regardless of whether the peripheral function uses that pin as its
input pin. However, if the read-modify-write (RMW) type of instruction is used to read the PDR5 register, the PDR5
register value is returned.
• Operation at reset
If the CPU is reset, all bits in the DDR5 register are initialized to “0” and port input is enabled.
• Operation in stop mode and watch mode
• If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop
mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR5 register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open.
• If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged
and the output level is maintained.
• Operation of the pull-up register
Setting the bit in the PUL5 register to “1” makes the pull-up resistor be internally connected to the pin. When the pin
output is “L” level, the pull-up resistor is disconnected regardless of the value of the PUL5 register.
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15.7 Port 6
Port 6 is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of
peripheral functions, refer to their respective chapters in “New 8FX MB95810K Series Hardware Manual”.
15.7.1 Port 6 configuration
Port 6 is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port 6 data register (PDR6)
• Port 6 direction register (DDR6)
• Port 6 pull-up register (PUL6)
15.7.2 Block diagrams of port 6
• P60/PPG10 pin
This pin has the following peripheral function:
• 8/16-bit PPG ch. 1 output pin (PPG10)
• P61/PPG11 pin
This pin has the following peripheral function:
• 8/16-bit PPG ch. 1 output pin (PPG11)
• P62/TO10 pin
This pin has the following peripheral function:
• 8/16-bit composite timer ch. 1 output pin (TO10)
• P63/TO11 pin
This pin has the following peripheral function:
• 8/16-bit composite timer ch. 1 output pin (TO11)
• P66/SOT pin
This pin has the following peripheral function:
• LIN-UART data output pin (SOT)
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• Block diagram of P60/PPG10, P61/PPG11, P62/TO10, P63/TO11 and P66/SOT
Peripheral function output enable
Peripheral function output
Hysteresis
Pull-up
0
1
PDR6 read
1
PDR6
Pin
0
PDR6 write
Internal bus
Executing bit manipulation instruction
DDR6 read
DDR6
DDR6 write
Stop mode, watch mode (SPL = 1)
PUL6 read
PUL6
PUL6 write
• P64/EC1 pin
This pin has the following peripheral function:
• 8/16-bit composite timer ch. 1 clock input pin (EC1)
• Block diagram of P64/EC1
Peripheral function input
Hysteresis
0
Pull-up
1
PDR6 read
PDR6
Pin
PDR6 write
Internal bus
Executing bit manipulation instruction
DDR6 read
DDR6
DDR6 write
Stop mode, watch mode (SPL = 1)
PUL6 read
PUL6
PUL6 write
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• P65/SCK pin
This pin has the following peripheral function:
• LIN-UART clock I/O pin (SCK)
• Block diagram of P65/SCK
Peripheral function input
Peripheral function input enable
Peripheral function output enable
Peripheral function output
Hysteresis
Pull-up
0
1
PDR6 read
1
PDR6
0
Pin
PDR6 write
Internal bus
Executing bit manipulation instruction
DDR6 read
DDR6
DDR6 write
Stop mode, watch mode (SPL = 1)
PUL6 read
PUL6
PUL6 write
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• P67/SIN pin
This pin has the following peripheral function:
• LIN-UART data input pin (SIN)
• Block diagram of P67/SIN
Peripheral function input
Peripheral function input enable
CMOS
0
Pull-up
1
PDR6 read
Pin
PDR6
PDR6 write
Internal bus
Executing bit manipulation instruction
DDR6 read
DDR6
DDR6 write
Stop mode, watch mode (SPL = 1)
PUL6 read
PUL6
PUL6 write
15.7.3 Port 6 registers
• Port 6 register functions
Register
abbreviation
PDR6
DDR6
PUL6
Data
Read
Read by read-modify-write
(RMW) instruction
Write
0
Pin state is “L” level.
PDR6 value is “0”.
As output port, outputs “L” level.
1
Pin state is “H” level.
PDR6 value is “1”.
As output port, outputs “H” level.
0
Port input enabled
1
Port output enabled
0
Pull-up disabled
1
Pull-up enabled
• Correspondence between registers and pins for port 6
Correspondence between related register bits and pins
Pin name
P67
P66
P65
P64
P63
P62
P61
P60
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
PDR6
DDR6
PUL6
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15.7.4 Port 6 operations
• Operation as an output port
• A pin becomes an output port if the bit in the DDR6 register corresponding to that pin is set to “1”.
• For a pin shared with other peripheral functions, disable the output of such peripheral functions.
• When a pin is used as an output port, it outputs the value of the PDR6 register to external pins.
• If data is written to the PDR6 register, the value is stored in the output latch and is output to the pin set as an output
port as it is.
• Reading the PDR6 register returns the PDR6 register value.
• Operation as an input port
• A pin becomes an input port if the bit in the DDR6 register corresponding to that pin is set to “0”.
• For a pin shared with other peripheral functions, disable the output of such peripheral functions.
• If data is written to the PDR6 register, the value is stored in the output latch but is not output to the pin set as an
input port.
• Reading the PDR6 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is
used to read the PDR6 register, the PDR6 register value is returned.
• Operation as a peripheral function output pin
• A pin becomes a peripheral function output pin if the peripheral output function is enabled by setting the output
enable bit of a peripheral function corresponding to that pin.
• The pin value can be read from the PDR6 register even if the peripheral function output is enabled. Therefore, the
output value of a peripheral function can be read by the read operation on the PDR6 register. However, if the readmodify-write (RMW) type of instruction is used to read the PDR6 register, the PDR6 register value is returned.
• Operation as a peripheral function input pin
• To set a pin as an input port, set the bit in the DDR6 register corresponding to the input pin of a peripheral function
to “0”.
• Reading the PDR6 register returns the pin value, regardless of whether the peripheral function uses that pin as its
input pin. However, if the read-modify-write (RMW) type of instruction is used to read the PDR6 register, the PDR6
register value is returned.
• Operation at reset
If the CPU is reset, all bits in the DDR6 register are initialized to “0” and port input is enabled.
• Operation in stop mode and watch mode
• If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop
mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR6 register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open. However, if the interrupt input of P65/SCK and P67/SIN is enabled by the external interrupt control register ch. 0 (EIC00)
of the external interrupt circuit and the interrupt pin selection circuit control register (WICR) of the interrupt pin selection circuit, the input is enabled and is not blocked.
• If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged
and the output level is maintained.
• Operation of the pull-up register
Setting the bit in the PUL6 register to “1” makes the pull-up resistor be internally connected to the pin. When the pin
output is “L” level, the pull-up resistor is disconnected regardless of the value of the PUL6 register.
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15.8 Port 7
Port 7 is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of
peripheral functions, refer to their respective chapters in “New 8FX MB95810K Series Hardware Manual”.
15.8.1 Port 7 configuration
Port 7 is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port 7 data register (PDR7)
• Port 7 direction register (DDR7)
• Port 7 pull-up register (PUL7)
15.8.2 Block diagrams of port 7
• P70/TO0 pin
This pin has the following peripheral function:
• 16-bit reload timer ch. 0 output pin (TO0)
• Block diagram of P70/TO0
Peripheral function output enable
Peripheral function output
Hysteresis
Pull-up
0
1
PDR7 read
1
PDR7
0
Pin
PDR7 write
Internal bus
Executing bit manipulation instruction
DDR7 read
DDR7
DDR7 write
Stop mode, watch mode (SPL = 1)
PUL7 read
PUL7
PUL7 write
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• P71/TI0 pin
This pin has the following peripheral function:
• 16-bit reload timer ch. 0 input pin (TI0)
• Block diagram of P71/TI0
Peripheral function input
Hysteresis
0
Pull-up
1
PDR7 read
PDR7
Pin
PDR7 write
Internal bus
Executing bit manipulation instruction
DDR7 read
DDR7
DDR7 write
Stop mode, watch mode (SPL = 1)
PUL7 read
PUL7
PUL7 write
• P72 pin
• Block diagram of P72
Hysteresis
0
Pull-up
1
PDR7 read
PDR7
Pin
PDR7 write
Internal bus
Executing bit manipulation instruction
DDR7 read
DDR7
DDR7 write
Stop mode, watch mode (SPL = 1)
PUL7 read
PUL7
PUL7 write
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15.8.3 Port 7 registers
• Port 7 register functions
Register
abbreviation
PDR7
DDR7
PUL7
Data
Read
Read by read-modify-write
(RMW) instruction
Write
0
Pin state is “L” level.
PDR7 value is “0”.
As output port, outputs “L” level.
1
Pin state is “H” level.
PDR7 value is “1”.
As output port, outputs “H” level.
0
Port input enabled
1
Port output enabled
0
Pull-up disabled
1
Pull-up enabled
• Correspondence between registers and pins for port 7
Correspondence between related register bits and pins
Pin name
-
-
-
-
-
P72
P71
P70
-
-
-
-
-
bit2
bit1
bit0
PDR7
DDR7
PUL7
15.8.4 Port 7 operations
• Operation as an output port
• A pin becomes an output port if the bit in the DDR7 register corresponding to that pin is set to “1”.
• For a pin shared with other peripheral functions, disable the output of such peripheral functions.
• When a pin is used as an output port, it outputs the value of the PDR7 register to external pins.
• If data is written to the PDR7 register, the value is stored in the output latch and is output to the pin set as an output
port as it is.
• Reading the PDR7 register returns the PDR7 register value.
• Operation as an input port
• A pin becomes an input port if the bit in the DDR7 register corresponding to that pin is set to “0”.
• For a pin shared with other peripheral functions, disable the output of such peripheral functions.
• If data is written to the PDR7 register, the value is stored in the output latch but is not output to the pin set as an
input port.
• Reading the PDR7 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is
used to read the PDR7 register, the PDR7 register value is returned.
• Operation as a peripheral function output pin
• A pin becomes a peripheral function output pin if the peripheral output function is enabled by setting the output
enable bit of a peripheral function corresponding to that pin.
• The pin value can be read from the PDR7 register even if the peripheral function output is enabled. Therefore, the
output value of a peripheral function can be read by the read operation on the PDR7 register. However, if the readmodify-write (RMW) type of instruction is used to read the PDR7 register, the PDR7 register value is returned.
• Operation as a peripheral function input pin
• To set a pin as an input port, set the bit in the DDR7 register corresponding to the input pin of a peripheral function
to “0”.
• Reading the PDR7 register returns the pin value, regardless of whether the peripheral function uses that pin as its
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input pin. However, if the read-modify-write (RMW) type of instruction is used to read the PDR7 register, the PDR7
register value is returned.
• Operation at reset
If the CPU is reset, all bits in the DDR7 register are initialized to “0” and port input is enabled.
• Operation in stop mode and watch mode
• If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop
mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR7 register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open.
• If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged
and the output level is maintained.
• Operation of the pull-up register
Setting the bit in the PUL7 register to “1” makes the pull-up resistor be internally connected to the pin. When the pin
output is “L” level, the pull-up resistor is disconnected regardless of the value of the PUL7 register.
15.9 Port 8
Port 8 is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of
peripheral functions, refer to their respective chapters in “New 8FX MB95810K Series Hardware Manual”.
15.9.1 Port 8 configuration
Port 8 is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port 8 data register (PDR8)
• Port 8 direction register (DDR8)
• Port 8 pull-up register (PUL8)
15.9.2 Block diagrams of port 8
• P80 pin
• P81 pin
• P82 pin
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• Block diagram of P80, P81 and P82
Hysteresis
0
Pull-up
1
PDR8 read
PDR8
Pin
PDR8 write
Internal bus
Executing bit manipulation instruction
DDR8 read
DDR8
DDR8 write
Stop mode, watch mode (SPL = 1)
PUL8 read
PUL8
PUL8 write
• P83/TRG0/ADTG* pin
This pin has the following peripheral function:
• 16-bit PPG timer ch. 0 trigger input pin (TRG0)
• 8/10-bit A/D converter trigger input pin (ADTG)
*: TRG0 and ADTG can be mapped to either P13 or P83 by using the SYSC register.
• Block diagram of P83/TRG0/ADTG
Peripheral function input
Peripheral function input enable
Hysteresis
0
Pull-up
1
PDR8 read
PDR8
Pin
PDR8 write
Internal bus
Executing bit manipulation instruction
DDR8 read
DDR8
DDR8 write
Stop mode, watch mode (SPL = 1)
PUL8 read
PUL8
PUL8 write
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15.9.3 Port 8 registers
• Port 8 register functions
Register
abbreviation
PDR8
DDR8
PUL8
Data
Read
Read by read-modify-write
(RMW) instruction
Write
0
Pin state is “L” level.
PDR8 value is “0”.
As output port, outputs “L” level.
1
Pin state is “H” level.
PDR8 value is “1”.
As output port, outputs “H” level.
0
Port input enabled
1
Port output enabled
0
Pull-up disabled
1
Pull-up enabled
• Correspondence between registers and pins for port 8
Correspondence between related register bits and pins
Pin name
-
-
-
-
P83
P82
P81
P80
-
-
-
-
bit3
bit2
bit1
bit0
PDR8
DDR8
PUL8
15.9.4 Port 8 operations
• Operation as an output port
• A pin becomes an output port if the bit in the DDR8 register corresponding to that pin is set to “1”.
• For a pin shared with other peripheral functions, disable the output of such peripheral functions.
• When a pin is used as an output port, it outputs the value of the PDR8 register to external pins.
• If data is written to the PDR8 register, the value is stored in the output latch and is output to the pin set as an output
port as it is.
• Reading the PDR8 register returns the PDR8 register value.
• Operation as an input port
• A pin becomes an input port if the bit in the DDR8 register corresponding to that pin is set to “0”.
• For a pin shared with other peripheral functions, disable the output of such peripheral functions.
• If data is written to the PDR8 register, the value is stored in the output latch but is not output to the pin set as an
input port.
• Reading the PDR8 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is
used to read the PDR8 register, the PDR8 register value is returned.
• Operation as a peripheral function input pin
• To set a pin as an input port, set the bit in the DDR8 register corresponding to the input pin of a peripheral function
to “0”.
• Reading the PDR8 register returns the pin value, regardless of whether the peripheral function uses that pin as its
input pin. However, if the read-modify-write (RMW) type of instruction is used to read the PDR8 register, the PDR8
register value is returned.
• Operation at reset
If the CPU is reset, all bits in the DDR8 register are initialized to “0” and port input is enabled.
• Operation in stop mode and watch mode
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• If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop
mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR8 register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open. However, if the interrupt input of P83/TRG0/ADTG is enabled by the external interrupt control register ch. 0 (EIC00) of
the external interrupt circuit and the interrupt pin selection circuit control register (WICR) of the interrupt pin selection circuit, the input is enabled and is not blocked.
• If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged
and the output level is maintained.
• Operation of the pull-up register
Setting the bit in the PUL8 register to “1” makes the pull-up resistor be internally connected to the pin. When the pin
output is “L” level, the pull-up resistor is disconnected regardless of the value of the PUL8 register.
15.10 Port E
Port E is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of
peripheral functions, refer to their respective chapters in “New 8FX MB95810K Series Hardware Manual”.
15.10.1 Port E configuration
Port E is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port E data register (PDRE)
• Port E direction register (DDRE)
• Port E pull-up register (PULE)
15.10.2 Block diagrams of port E
• PE0/INT10 pin
This pin has the following peripheral function:
• External interrupt input pin (INT10)
• PE1/INT11 pin
This pin has the following peripheral function:
• External interrupt input pin (INT11)
• PE2/INT12 pin
This pin has the following peripheral function:
External interrupt input pin (INT12)
• PE3/INT13 pin
This pin has the following peripheral function:
• External interrupt input pin (INT13)
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• Block diagram of PE0/INT10, PE1/INT11, PE2/INT12 and PE3/INT13
Peripheral function input
Peripheral function input enable
(INT10 to INT13)
Hysteresis
0
Pull-up
1
PDRE read
Pin
PDRE
PDRE write
Internal bus
Executing bit manipulation instruction
DDRE read
DDRE
DDRE write
Stop mode, watch mode (SPL = 1)
PULE read
PULE
PULE write
15.10.3 Port E registers
• Port E register functions
Register
abbreviation
PDRE
DDRE
PULE
Data
Read
Read by read-modify-write
(RMW) instruction
Write
0
Pin state is “L” level.
PDRE value is “0”.
As output port, outputs “L” level.
1
Pin state is “H” level.
PDRE value is “1”.
As output port, outputs “H” level.
0
Port input enabled
1
Port output enabled
0
Pull-up disabled
1
Pull-up enabled
• Correspondence between registers and pins for port E
Correspondence between related register bits and pins
Pin name
-
-
-
-
PE3
PE2
PE1
PE0
-
-
-
-
bit3
bit2
bit1
bit0
PDRE
DDRE
PULE
Document Number: 002-04694 Rev. *A
Page 67 of 121
MB95810K Series
15.10.4 Port E operations
• Operation as an output port
• A pin becomes an output port if the bit in the DDRE register corresponding to that pin is set to “1”.
• For a pin shared with other peripheral functions, disable the output of such peripheral functions.
• When a pin is used as an output port, it outputs the value of the PDRE register to external pins.
• If data is written to the PDRE register, the value is stored in the output latch and is output to the pin set as an output
port as it is.
• Reading the PDRE register returns the PDRE register value.
• Operation as an input port
• A pin becomes an input port if the bit in the DDRE register corresponding to that pin is set to “0”.
• For a pin shared with other peripheral functions, disable the output of such peripheral functions.
• If data is written to the PDRE register, the value is stored in the output latch but is not output to the pin set as an
input port.
• Reading the PDRE register returns the pin value. However, if the read-modify-write (RMW) type of instruction is
used to read the PDRE register, the PDRE register value is returned.
• Operation as a peripheral function input pin
• To set a pin as an input port, set the bit in the DDRE register corresponding to the input pin of a peripheral function
to “0”.
• Reading the PDRE register returns the pin value, regardless of whether the peripheral function uses that pin as its
input pin. However, if the read-modify-write (RMW) type of instruction is used to read the PDRE register, the PDRE
register value is returned.
• Operation at reset
If the CPU is reset, all bits in the DDRE register are initialized to “0” and port input is enabled.
• Operation in stop mode and watch mode
• If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop
mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDRE register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open. However, if the interrupt input is enabled for the external interrupt (INT10 to INT13), the input is enabled and not
blocked.
• If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged
and the output level is maintained.
• Operation as an external interrupt input pin
• Set the bit in the DDRE register corresponding to the external interrupt input pin to “0”.
• For a pin shared with other peripheral functions, disable the output of such peripheral functions.
• The pin value is always input to the external interrupt circuit. When using a pin for a function other than the interrupt,
disable the external interrupt function corresponding to that pin.
• Operation of the pull-up register
Setting the bit in the PULE register to “1” makes the pull-up resistor be internally connected to the pin. When the pin
output is “L” level, the pull-up resistor is disconnected regardless of the value of the PULE register.
Document Number: 002-04694 Rev. *A
Page 68 of 121
MB95810K Series
15.11 Port F
Port F is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of
peripheral functions, refer to their respective chapters in “New 8FX MB95810K Series Hardware Manual”.
15.11.1 Port F configuration
Port F is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port F data register (PDRF)
• Port F direction register (DDRF)
15.11.2 Block diagrams of port F
• PF0/X0 pin
This pin has the following peripheral function:
• Main clock input oscillation pin (X0)
• PF1/X1 pin
This pin has the following peripheral function:
• Main clock I/O oscillation pin (X1)
• Block diagram of PF0/X0 and PF1/X1
Hysteresis
0
1
PDRF read
Internal bus
PDRF
Pin
PDRF write
Executing bit manipulation instruction
DDRF read
DDRF
DDRF write
Stop mode, watch mode (SPL = 1)
• PF2/RST pin
This pin has the following peripheral function:
• Reset pin (RST)
Document Number: 002-04694 Rev. *A
Page 69 of 121
MB95810K Series
• Block diagram of PF2/RST
Reset input
Reset input enable
Reset output enable
Reset output
Hysteresis
0
1
PDRF read
Internal bus
Pin
1
PDRF
OD
0
PDRF write
Executing bit manipulation instruction
DDRF read
DDRF
DDRF write
Stop mode, watch mode (SPL = 1)
15.11.3 Port F registers
• Port F register functions
Register
abbreviation
PDRF
DDRF
Data
Read
Read by read-modify-write
(RMW) instruction
Write
0
Pin state is “L” level.
PDRF value is “0”.
As output port, outputs “L” level.
1
Pin state is “H” level.
PDRF value is “1”.
As output port, outputs “H” level.*
0
Port input enabled
1
Port output enabled
*: If the pin is an N-ch open drain pin, the pin state becomes Hi-Z.
• Correspondence between registers and pins for port F
Correspondence between related register bits and pins
Pin name
PDRF
DDRF
-
-
-
-
-
PF2
PF1
PF0
-
-
-
-
-
bit2*
bit1
bit0
*: When the external reset is selected (SYSC:RSTEN = 1), the port function cannot be used.
Document Number: 002-04694 Rev. *A
Page 70 of 121
MB95810K Series
15.11.4 Port F operations
• Operation as an output port
• A pin becomes an output port if the bit in the DDRF register corresponding to that pin is set to “1”.
• For a pin shared with other peripheral functions, disable the output of such peripheral functions.
• When a pin is used as an output port, it outputs the value of the PDRF register to external pins.
• If data is written to the PDRF register, the value is stored in the output latch and is output to the pin set as an output
port as it is.
• Reading the PDRF register returns the PDRF register value.
• Operation as an input port
• A pin becomes an input port if the bit in the DDRF register corresponding to that pin is set to “0”.
• For a pin shared with other peripheral functions, disable the output of such peripheral functions.
• If data is written to the PDRF register, the value is stored in the output latch but is not output to the pin set as an
input port.
• Reading the PDRF register returns the pin value. However, if the read-modify-write (RMW) type of instruction is
used to read the PDRF register, the PDRF register value is returned.
• Operation at reset
If the CPU is reset, all bits in the DDRF register are initialized to “0” and port input is enabled.
• Operation in stop mode and watch mode
• If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop
mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDRF register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open.
• If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged
and the output level is maintained.
Document Number: 002-04694 Rev. *A
Page 71 of 121
MB95810K Series
15.12 Port G
Port G is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of
peripheral functions, refer to their respective chapters in “New 8FX MB95810K Series Hardware Manual”.
15.12.1 Port G configuration
Port G is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port G data register (PDRG)
• Port G direction register (DDRG)
• Port G pull-up register (PULG)
15.12.2 Block diagram of port G
• PG1/X0A pin
This pin has the following peripheral function:
• Subclock input oscillation pin (X0A)
• PG2/X1A pin
This pin has the following peripheral function:
• Subclock I/O oscillation pin (X1A)
• Block diagram of PG1/X0A and PG2/X1A
Hysteresis
0
Pull-up
1
PDRG read
PDRG
Pin
PDRG write
Internal bus
Executing bit manipulation instruction
DDRG read
DDRG
DDRG write
Stop mode, watch mode (SPL = 1)
PULG read
PULG
PULG write
Document Number: 002-04694 Rev. *A
Page 72 of 121
MB95810K Series
15.12.3 Port G registers
• Port G register functions
Register
abbreviation
PDRG
DDRG
PULG
Data
Read
Read by read-modify-write
(RMW) instruction
Write
0
Pin state is “L” level.
PDRG value is “0”.
As output port, outputs “L” level.
1
Pin state is “H” level.
PDRG value is “1”.
As output port, outputs “H” level.
0
Port input enabled
1
Port output enabled
0
Pull-up disabled
1
Pull-up enabled
• Correspondence between registers and pins for port G
Correspondence between related register bits and pins
Pin name
-
-
-
-
-
PG2
PG1
-
-
-
-
-
-
bit2
bit1
-
PDRG
DDRG
PULG
15.12.4 Port G operations
• Operation as an output port
• A pin becomes an output port if the bit in the DDRG register corresponding to that pin is set to “1”.
• For a pin shared with other peripheral functions, disable the output of such peripheral functions.
• When a pin is used as an output port, it outputs the value of the PDRG register to external pins.
• If data is written to the PDRG register, the value is stored in the output latch and is output to the pin set as an output
port as it is.
• Reading the PDRG register returns the PDRG register value.
• Operation as an input port
• A pin becomes an input port if the bit in the DDRG register corresponding to that pin is set to “0”.
• For a pin shared with other peripheral functions, disable the output of such peripheral functions.
• If data is written to the PDRG register, the value is stored in the output latch but is not output to the pin set as an
input port.
• Reading the PDRG register returns the pin value. However, if the read-modify-write (RMW) type of instruction is
used to read the PDRG register, the PDRG register value is returned.
• Operation at reset
If the CPU is reset, all bits in the DDRG register are initialized to “0” and port input is enabled.
• Operation in stop mode and watch mode
• If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop
mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDRG register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open.
• If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged
and the output level is maintained.
• Operation of the pull-up register
Setting the bit in the PULG register to “1” makes the pull-up resistor be internally connected to the pin. When the pin
output is “L” level, the pull-up resistor is disconnected regardless of the value of the PULG register.
Document Number: 002-04694 Rev. *A
Page 73 of 121
MB95810K Series
16. Interrupt Source Table
Interrupt source
External interrupt ch. 0
External interrupt ch. 4
External interrupt ch. 1
External interrupt ch. 5
External interrupt ch. 2
External interrupt ch. 6
External interrupt ch. 3
External interrupt ch. 7
Comparator ch. 1
UART/SIO ch. 0
8/16-bit composite timer ch. 0
(lower)
8/16-bit composite timer ch. 0
(upper)
LIN-UART (reception)
LIN-UART (transmission)
8/16-bit PPG ch. 1 (lower)
8/16-bit PPG ch. 1 (upper)
16-bit reload timer ch. 0
8/16-bit PPG ch. 0 (upper)
8/16-bit PPG ch. 0 (lower)
8/16-bit composite timer ch. 1
(upper)
16-bit PPG timer ch. 0
I2C bus interface ch. 0
16-bit PPG timer ch. 1
8/10-bit A/D converter
Time-base timer
Watch prescaler
Watch counter
External interrupt ch. 10
External interrupt ch. 11
External interrupt ch. 12
External interrupt ch. 13
Comparator ch. 0
8/16-bit composite timer ch. 1
(lower)
Flash memory
Document Number: 002-04694 Rev. *A
Interrupt
request
number
Vector table
address
Upper
Lower
Interrupt level
setting register
Register
Bit
IRQ00
0xFFFA 0xFFFB
ILR0
L00 [1:0]
IRQ01
0xFFF8 0xFFF9
ILR0
L01 [1:0]
IRQ02
0xFFF6 0xFFF7
ILR0
L02 [1:0]
IRQ03
0xFFF4 0xFFF5
ILR0
L03 [1:0]
IRQ04
0xFFF2 0xFFF3
ILR1
L04 [1:0]
IRQ05
0xFFF0 0xFFF1
ILR1
L05 [1:0]
IRQ06
0xFFEE 0xFFEF
ILR1
L06 [1:0]
IRQ07
IRQ08
IRQ09
IRQ10
IRQ11
IRQ12
IRQ13
0xFFEC
0xFFEA
0xFFE8
0xFFE6
0xFFE4
0xFFE2
0xFFE0
0xFFED
0xFFEB
0xFFE9
0xFFE7
0xFFE5
0xFFE3
0xFFE1
ILR1
ILR2
ILR2
ILR2
ILR2
ILR3
ILR3
L07 [1:0]
L08 [1:0]
L09 [1:0]
L10 [1:0]
L11 [1:0]
L12 [1:0]
L13 [1:0]
IRQ14
0xFFDE 0xFFDF
ILR3
L14 [1:0]
IRQ15
IRQ16
IRQ17
IRQ18
IRQ19
0xFFDC
0xFFDA
0xFFD8
0xFFD6
0xFFD4
0xFFDD
0xFFDB
0xFFD9
0xFFD7
0xFFD5
ILR3
ILR4
ILR4
ILR4
ILR4
L15 [1:0]
L16 [1:0]
L17 [1:0]
L18 [1:0]
L19 [1:0]
IRQ20
0xFFD2 0xFFD3
ILR5
L20 [1:0]
IRQ21
0xFFD0 0xFFD1
ILR5
L21 [1:0]
IRQ22
0xFFCE 0xFFCF
ILR5
L22 [1:0]
IRQ23
0xFFCC 0xFFCD
ILR5
L23 [1:0]
Priority order of
interrupt sources
of the same level
(occurring
simultaneously)
High
Low
Page 74 of 121
MB95810K Series
17. Pin States In Each Mode
Pin name
Normal
operation
Sleep mode
Oscillation input Oscillation input
PF0/X0
I/O port*1
I/O port*1
Oscillation input Oscillation input
PF1/X1
I/O port*
1
Reset input*4
PF2/RST
I/O port
I/O port*
1
Reset input*4
I/O port
I/O port*
1
I/O port*
1
Oscillation input Oscillation input
PG2/X1A
P00/INT00
P01/INT01
P02/INT02
P03/INT03
P04/INT04
P05/INT05
P06/INT06
P07/INT07
P10/UI0
P11/UO0
I/O port*1
I/O port/
peripheral
function I/O
I/O port/
peripheral
function I/O
Hi-Z
Hi-Z
- Previous state
- Hi-Z
kept
- Input
- Input
blocked*1*2
1
2
blocked* *
Hi-Z
Hi-Z
- Previous state
- Hi-Z
kept
- Input
- Input
blocked*1*2
blocked*1*2
Reset input
Reset input
- Previous state
- Hi-Z
kept
- Input
- Input
blocked*1*2
1
2
blocked* *
Oscillation input Oscillation input
PG1/X0A
Stop mode
SPL=0
SPL=1
Hi-Z
Hi-Z
- Previous state
- Hi-Z*5
kept
- Input
- Input
blocked*1*2
blocked*1*2
Hi-Z
Hi-Z
Watch mode
SPL=0
SPL=1
Hi-Z
Hi-Z
- Previous state
- Hi-Z
kept
- Input
- Input
blocked*1*2
1
2
blocked* *
Hi-Z
Hi-Z
- Previous state
- Hi-Z
kept
- Input
- Input
blocked*1*2
blocked*1*2
Reset input
Reset input
- Previous state
- Hi-Z
kept
- Input
- Input
blocked*1*2
1
2
blocked* *
Hi-Z
Hi-Z
- Previous state
- Hi-Z*5
kept
- Input
- Input
blocked*1*2
blocked*1*2
Hi-Z
Hi-Z
On reset
—
- Hi-Z
- Input
enabled*3
(However, it
does not
function.)
—
- Hi-Z
- Input
enabled*3
(However, it
does not
function.)
Reset input*4
- Hi-Z
- Input
enabled*3
(However, it
does not
function.)
—
- Hi-Z
- Input
enabled*3
(However, it
does not
function.)
—
- Hi-Z
- Input
enabled*3
(However, it
does not
function.)
- Previous state
- Hi-Z*5
kept
- Input
- Input
blocked*1*2
1
2
blocked* *
- Previous state
- Hi-Z*5
kept
- Input
- Input
blocked*1*2
1
2
blocked* *
I/O port/
peripheral
function I/O
- Previous state
- Hi-Z*5
kept
- Input
- Input
blocked*2*6
2
6
blocked* *
- Previous state
- Hi-Z*5
kept
- Input
- Input
blocked*2*6
2
6
blocked* *
I/O port/
peripheral
function I/O
- Hi-Z
- Input
- Previous state
- Previous state
enabled*3
- Hi-Z*5
- Hi-Z*5
kept
kept
2
2
Input
blocked*
Input
blocked*
(However,
it
- Input blocked*2
- Input blocked*2
does not
function.)
I/O port*1
Document Number: 002-04694 Rev. *A
- Hi-Z
- Input
enabled*3
(However, it
does not
function.)
Page 75 of 121
MB95810K Series
Pin name
Normal
operation
Sleep mode
Stop mode
SPL=0
SPL=1
Watch mode
SPL=0
SPL=1
On reset
- Hi-Z
- Input
enabled*3
(However, it
does not
function.)
- Hi-Z
- Input
- Hi-Z*5
enabled*3
- Input
(However,
it
blocked*2, *6
does not
function.)
- Hi-Z
- Input
enabled*3
- Hi-Z*5
- Input blocked*2 (However, it
does not
function.)
- Hi-Z
- Input
- Hi-Z*5
enabled*3
- Input
(However,
it
blocked*2, *6
does not
function.)
I/O port/
peripheral
function I/O
I/O port/
peripheral
function I/O
- Previous state
- Previous state
- Hi-Z
- Hi-Z
kept
kept
- Input blocked*2
- Input blocked*2
- Input blocked*2
- Input blocked*2
I/O port/
P13/UCK0/
peripheral
TRG0/ADTG
function I/O
I/O port/
peripheral
function I/O
- Previous state
- Hi-Z*5
kept
- Input
- Input
blocked*2, *6
2,
6
blocked* *
P14/PPG0
P20/PPG00
I/O port/
P21/PPG01
peripheral
P22/TO00
function I/O
P23/TO01
I/O port/
peripheral
function I/O
- Previous state
- Previous state
- Hi-Z*5
kept
kept
- Input blocked*2
- Input blocked*2
- Input blocked*2
I/O port/
peripheral
function I/O
I/O port/
peripheral
function I/O
- Previous state
- Hi-Z*5
kept
- Input
- Input
blocked*2, *6
2,
6
blocked* *
I/O port/
peripheral
function I/O/
analog input
I/O port/
peripheral
function I/O/
analog input
- Previous state
- Previous state
- Hi-Z
- Hi-Z*5
- Hi-Z*5
kept*8
kept*8
- Input
2
2
- Input blocked*
- Input blocked*
blocked*2
- Input blocked*2
- Input blocked*2
I/O port/
peripheral
function I/O/
analog input
I/O port/
peripheral
function I/O/
analog input
- Previous state
- Hi-Z*5
kept
- Input
- Input
blocked*2, *7
blocked*2, *7
I/O port/
analog input
I/O port/
analog input
- Previous state
- Previous state
- Hi-Z
- Hi-Z*5
- Hi-Z*5
kept
kept
- Input
- Input blocked*2
- Input blocked*2
- Input blocked*2
- Input blocked*2
blocked*2
I/O port/
peripheral
function I/O
I/O port/
peripheral
function I/O
- Previous state
- Hi-Z
kept
- Input
- Input
blocked*2, *9
2,
9
blocked* *
P12/DBG
P24/EC0
P32/AN02/
CMP0_O
P35/AN05/
CMP1_O
P30/AN00/
CMP0_N
P31/AN01/
CMP0_P
P33/AN03/
CMP1_N
P34/AN04/
CMP1_P
P36/AN06
P37/AN07
P40/AN08
P41/AN09
P42/AN10
P43/AN11
P50/SCL
P51/SDA
Document Number: 002-04694 Rev. *A
- Previous state
kept
- Input
blocked*2, *6
- Previous state
kept
- Input
blocked*2, *6
- Previous state
- Hi-Z*5
kept
- Input
- Input
blocked*2, *7
blocked*2, *7
- Previous state
- Hi-Z
kept
- Input
- Input
blocked*2, *9
2,
9
blocked* *
- Hi-Z
- Input
blocked*2
- Hi-Z
- Input
enabled*3
(However, it
does not
function.)
Page 76 of 121
MB95810K Series
Pin name
Normal
operation
P52/PPG1
P53/TRG1
P60/PPG10
I/O port/
P61/PPG11
peripheral
P62/TO10
function I/O
P63/TO11
P64/EC1
P66/SOT
P65/SCK
P67/SIN
P70/TO0
P71/TI0
I/O port/
peripheral
function I/O
I/O port/
peripheral
function I/O
Sleep mode
Watch mode
SPL=0
SPL=1
On reset
I/O port/
peripheral
function I/O
- Hi-Z
- Input
- Previous state
- Previous state
enabled*3
- Hi-Z*5
- Hi-Z*5
kept
kept
2
2
Input
blocked*
Input
blocked*
(However,
it
- Input blocked*2
- Input blocked*2
does not
function.)
I/O port/
peripheral
function I/O
- Previous state
- Hi-Z*5
kept
- Input
- Input
blocked*2, *6
blocked*2, *6
I/O port/
peripheral
function I/O
- Hi-Z
- Input
- Previous state
- Previous state
enabled*3
- Hi-Z*5
- Hi-Z*5
kept
kept
2
2
Input
blocked*
Input
blocked*
(However,
it
- Input blocked*2
- Input blocked*2
does not
function.)
P72
P80
I/O port
Stop mode
SPL=0
SPL=1
I/O port
P81
P82
- Previous state
- Hi-Z*5
kept
- Input
- Input
blocked*2, *6
blocked*2, *6
- Hi-Z
- Input
enabled*3
(However, it
does not
function.)
- Hi-Z
- Input
- Previous state
- Previous state
enabled*3
- Hi-Z*5
- Hi-Z*5
kept
kept
2
2
Input
blocked*
Input
blocked*
(However,
it
- Input blocked*2
- Input blocked*2
does not
function.)
P83/TRG0/
ADTG
PE0/INT10
PE1/INT11
I/O port/
peripheral
function I/O
I/O port/
peripheral
function I/O
PE2/INT12
- Previous state
- Hi-Z*5
kept
- Input
- Input
blocked*2, *6
blocked*2, *6
- Previous state
- Hi-Z*5
kept
- Input
- Input
blocked*2, *6
blocked*2, *6
- Hi-Z
- Input
enabled*3
(However, it
does not
function.)
PE3/INT13
SPL: Pin state setting bit in the standby control register (STBC:SPL)
Hi-Z: High impedance
*1: The pin stays at the state shown when configured as a general-purpose I/O port.
*2: “Input blocked” means direct input gate operation from the pin is disabled.
*3: “Input enabled” means that the input function is enabled. While the input function is enabled, a pull-up or pull-down
operation has to be performed in order to prevent leaks due to external input. If a pin is used as an output port, its
pin state is the same as that of other ports.
*4: The PF2/RST pin stays at the state shown when configured as a reset pin.
*5: The pull-up control setting is still effective.
*6: Though input is blocked, an external interrupt can be input when the external interrupt request is enabled.
*7: Though input is blocked, an analog signal can also be input to generate a comparator interrupt when the comparator
interrupt is enabled.
*8: The output function of the comparator is still in operation in stop mode and watch mode.
*9: The I2C bus interface can wake up the MCU in stop mode or watch mode when its MCU standby mode wakeup function is enabled. For details of the MCU standby mode wakeup function, refer to “CHAPTER 24 I2C BUS INTERFACE”
in “New 8FX MB95810K Series Hardware Manual”.
Document Number: 002-04694 Rev. *A
Page 77 of 121
MB95810K Series
18. Electrical Characteristics
18.1 Absolute Maximum Ratings
Parameter
Power supply voltage*1
Input voltage*1
Output voltage*1
Maximum clamp current
Total maximum clamp
current
“L” level maximum
output current
Symbol
AVCC,
VCC
AVR
VI
VO
ICLAMP
Rating
Min
Max
Unit
VSS 0.3 VSS  6
V
VSS 0.3 VSS  6
VSS 0.3 VSS  6
VSS 0.3 VSS  6
2
2
—
20
mA Applicable to specific pins*4
IOL
—
15
mA
4
—
“L” level average current
IOLAV2
“L” level total average
output current
“H” level maximum
output current
12
Other than P00 to P07
Average output current =
operating current  operating ratio (1 pin)
mA
P00 to P07
Average output current =
operating current  operating ratio (1 pin)
IOL
—
100
mA
IOLAV
—
37
Total average output current =
mA operating current  operating ratio
(Total number of pins)
IOH
—
15
mA
4
IOHAV1
“H” level average
current
—
8
IOHAV2
“H” level total maximum
output current
*2
V
V *3
V *3
mA Applicable to specific pins*4
|ICLAMP|
IOLAV1
“L” level total maximum
output current
Remarks
IOH
—
100
“H” level total average
output current
IOHAV
—
47
Power consumption
Operating temperature
Storage temperature
Pd
TA
Tstg
—
40
55
320
85
150
Other than P00 to P07
Average output current =
operating current  operating ratio (1 pin)
mA
P00 to P07
Average output current =
operating current  operating ratio (1 pin)
mA
Total average output current =
mA operating current  operating ratio
(Total number of pins)
mW
C
C
*1: These parameters are based on the condition that VSS is 0.0 V.
*2: Apply equal potential to AVCC and VCC. AVR must not exceed AVCC.
*3: V1 and V0 must not exceed VCC  0.3 V. V1 must not exceed the rated voltage. However, if the maximum current
to/from an input is limited by means of an external component, the ICLAMP rating is used instead of the VI rating.
*4: Specific pins: P00 to P07, P10, P11, P13, P14, P20 to P24, P30 to P37, P40 to P43, P52, P53, P60 to P67, P70 to
P72, P80 to P83, PE0 to PE3, PF0, PF1, PG1, PG2
• Use under recommended operating conditions.
• Use with DC voltage (current).
Document Number: 002-04694 Rev. *A
Page 78 of 121
MB95810K Series
• The HV (High Voltage) signal is an input signal exceeding the VCC voltage. Always connect a limiting resistor between
the HV (High Voltage) signal and the microcontroller before applying the HV (High Voltage) signal.
• The value of the limiting resistor should be set to a value at which the current to be input to the microcontroller pin
when the HV (High Voltage) signal is input is below the standard value, irrespective of whether the current is transient
current or stationary current.
• When the microcontroller drive current is low, such as in low power consumption modes, the HV (High Voltage)
input potential may pass through the protective diode to increase the potential of the VCC pin, affecting other devices.
• If the HV (High Voltage) signal is input when the microcontroller power supply is off (not fixed at 0 V), since power
is supplied from the pins, incomplete operations may be executed.
• If the HV (High Voltage) input is input after power-on, since power is supplied from the pins, the voltage of power
supply may not be sufficient to enable a power-on reset.
• Do not leave the HV (High Voltage) input pin unconnected.
• Example of a recommended circuit:
• Input/Output equivalent circuit
Protective diode
VCC
P-ch
Limiting
resistor
HV(High Voltage) input (0 V to 16 V)
N-ch
R
WARNING: Semiconductor devices may be permanently damaged by application of stress (including, without
limitation, voltage, current or temperature) in excess of absolute maximum ratings.
Do not exceed any of these ratings.
Document Number: 002-04694 Rev. *A
Page 79 of 121
MB95810K Series
18.2 Recommended Operating Conditions
(VSS = 0.0 V)
Parameter
Value
Symbol
Min
Max
Unit
Remarks
Power supply voltage
AVCC,
VCC
2.88
5.5
V
A/D converter reference input
voltage
AVR
AVCC 0.1
AVCC
V
Decoupling capacitor
CS
0.022
1
µF
*
Operating temperature
TA
40
85
Other than on-chip debug mode
5
35
C
On-chip debug mode
*: Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The decoupling capacitor for the
VCC pin must have a capacitance equal to or larger than the capacitance of CS. For the connection to a decoupling
capacitor CS, see the diagram below. To prevent the device from unintentionally entering an unknown mode due to
noise, minimize the distance between the C pin and CS and the distance between CS and the VSS pin when designing
the layout of a printed circuit board.
• DBG / RST / C pins connection diagram
*
DBG
C
RST
Cs
*: Connect the DBG pin to an external pull-up resistor of 2 k or above. After power-on, ensure that the
DBG pin does not stay at “L” level until the reset output is released. The DBG pin becomes a communication pin in debug mode. Since the actual pull-up resistance depends on the tool used and the
interconnection length, refer to the tool document when selecting a pull-up resistor.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated under these conditions.
Any use of semiconductor devices will be under their recommended operating condition.
Operation under any conditions other than these conditions may adversely affect reliability of device and
could result in device failure.
No warranty is made with respect to any use, operating conditions or combinations not represented on this
data sheet. If you are considering application under any conditions other than listed herein, please contact
sales representatives beforehand.
Document Number: 002-04694 Rev. *A
Page 80 of 121
MB95810K Series
18.3 DC Characteristics
Parameter Symbol
“H” level
input
voltage
“L” level
input
voltage
Open-drain
output
application
voltage
“H” level
output
voltage
“L” level
output
voltage
Input leak
current (Hi-Z
output leak
current)
Internal
pull-up
resistor
Input
capacitance
(VCC = 5.0 V10%, VSS = 0.0 V, TA = 40 C to 85 °C)
Pin name
Condition
VIHI
P10, P50, P51,
P67
VIHS
Value
Unit
Remarks
VCC  0.3
V
CMOS input level
—
VCC  0.3
V
Hysteresis input
0.8 VCC
—
VCC  0.3
V
Hysteresis input
—
VSS 0.3
—
0.3 VCC
V
CMOS input level
Other than P10,
P50, P51, P67,
PF2
—
VSS 0.3
—
0.2 VCC
V
Hysteresis input
PF2
—
VSS 0.3
—
0.2 VCC
V
Hysteresis input
P12, P50, P51,
PF2
—
VSS 0.3
—
VSS  5.5
V
VOH1
Output pins
other than P00
IOH = 4 mA
to P07, P12,
PF2
VCC 0.5
—
—
V
VOH2
P00 to P07
IOH = 8 mA
VCC 0.5
—
—
V
VOL1
Output pins
other than P00 IOL = 4 mA
to P07
—
—
0.4
V
VOL2
P00 to P07
IOL = 12 mA
—
—
0.4
V
All input pins
0.0 V < VI < VCC
5
—
5
When the internal
µA pull-up resistor is
disabled
Other than P12,
P50, P51,
VI = 0 V
PF0 to PF2
25
50
100
When the internal
k pull-up resistor is
enabled
Other than
AVCC, AVSS,
AVR, VCC and
VSS
—
5
15
pF
Min
Typ
Max
—
0.7 VCC
—
Other than P10,
P50, P51, P67,
PF2
—
0.8 VCC
VIHM
PF2
—
VILI
P10, P50, P51,
P67
VILS
VILM
VD
ILI
RPULL
CIN
Document Number: 002-04694 Rev. *A
f = 1 MHz
Page 81 of 121
MB95810K Series
Parameter
Power
supply
current*3
(VCC = 5.0 V10%, VSS = 0.0 V, TA = 40 C to 85 °C)
Value
Symbol
Pin name
Condition
Unit
Remarks
Min Typ*1 Max*2
Except during
Flash memory
—
4.8
5.8
mA
programming and
FCH = 32 MHz
erasing
FMP = 16 MHz
ICC
During Flash
Main clock mode
memory
(divided by 2)
—
10.1 13.8 mA
programming and
erasing
FCH = 32 MHz
FMP = 16 MHz
ICCS
—
1.9
3
mA
Main sleep mode
(divided by 2)
VCC
FCL = 32 kHz
(External clock
FMPL = 16 kHz
operation)
Subclock mode
ICCL
—
65.9 145
µA
(divided by 2)
TA = 25 °C
FCL = 32 kHz
FMPL = 16 kHz
In deep standby
Subsleep mode
—
11.2
16
µA
ICCLS
mode
(divided by 2)
TA = 25 °C
FCL = 32 kHz
Watch mode
In deep standby
—
8.6
13
µA
ICCT
Main stop mode
mode
TA = 25 °C
FMCRPLL = 16 MHz
FMP = 16 MHz
Main CR PLL clock
ICCMPLL
—
5.1
6.8
mA
mode
(multiplied by 4)
TA = 25 °C
VCC
FCRH = 4 MHz
FMP = 4 MHz
—
1.4
4.6
mA
ICCMCR
Main CR clock
mode
Sub-CR clock mode
(divided by 2)
—
63.1 230
µA
ICCSCR
TA = 25 °C
FCH = 32 MHz
Time-base timer
In deep standby
—
360
455
µA
ICCTS VCC
mode
mode
(External clock
TA = 25 °C
operation)
Substop mode
In deep standby
ICCH
—
8.8
13
µA
TA = 25 °C
mode
Document Number: 002-04694 Rev. *A
Page 82 of 121
MB95810K Series
Parameter
Symbol
Pin name
IV
ILVD
ICRH
VCC
ICRL
Power
supply
current*3
INSTBY
IA
AVCC
IAH
(VCC = 5.0 V10%, VSS = 0.0 V, TA = 40 C to 85 °C)
Value
Condition
Unit
Remarks
Min Typ*1 Max*2
Current consumption
—
60
160
µA
of the comparator
With the LVD reset
Current consumption
already enabled by
of the low-voltage
—
4
7
µA the LVD reset
detection reset circuit
circuit control
register (LVDCC)
Current consumption
of the main CR
—
240
320
µA
oscillator
Current consumption
of the sub-CR
—
7
20
µA
oscillator oscillating at
100 kHz
Current consumption
difference between
normal standby mode
—
22
30
µA
and deep standby
mode
TA = 25 °C
VCC = 5.5 V
FCH = 16 MHz
—
2
3.1
mA
Current consumption
of the A/D converter
FCRH = 4 MHz
FMP = 4 MHz
Current consumption
—
1
5
µA
with the A/D converter
halted
TA = 25 °C
*1: VCC = 5.0 V, TA = 25 °C
*2: VCC = 5.5 V, TA = 85 °C (unless otherwise specified)
*3: • The power supply current is determined by the external clock. When the low-voltage detection reset circuit is selected, the power supply current is the sum of adding the current consumption of the low-voltage detection reset
circuit (ILVD) to one of the values from ICC to ICCH. In addition, when both the low-voltage detection reset circuit and
a CR oscillator are selected, the power supply current is the sum of adding up the current consumption of the lowvoltage detection reset circuit (ILVD), the current consumption of the CR oscillators (ICRH or ICRL) and one of the values from ICC to ICCH. In on-chip debug mode, the main CR oscillator (ICRH) and the low-voltage detection reset circuit
are always in operation, and current consumption therefore increases accordingly.
• See “4. AC Characteristics Clock Timing” for FCH, FCL, FCRH and FMCRPLL.
• See “4. AC Characteristics Source Clock/Machine Clock” for FMP and FMPL.
• The power supply current value in standby mode is measured in deep standby mode. The current consumption in
normal standby mode is higher than that in deep standby mode. The power supply current value in normal standby
mode can be found by adding the current consumption difference between normal standby mode and deep standby
mode (INSTBY) to the power supply current value in deep standby mode. For details of normal standby mode and
deep standby mode, refer to “CHAPTER 3 CLOCK CONTROLLER” in “New 8FX MB95810K Series Hardware
Manual”.
Document Number: 002-04694 Rev. *A
Page 83 of 121
MB95810K Series
18.4 AC Characteristics
18.4.1 Clock Timing
Parameter
Symbol Pin name Condition
X0, X1
FCH
X0
X0, X1
—
X1: open
*
Min
1
1
1
3.92
FCRH
—
—
3.8
7.84
7.6
9.8
Clock
frequency
9.5
FMCRPLL
—
—
11.76
11.4
15.68
15.2
—
FCL
X0A, X1A
—
—
FCRL
—
Document Number: 002-04694 Rev. *A
—
50
(VCC = 2.88 V to 5.5 V, VSS = 0.0 V, TA = 40 °C to 85 °C)
Value
Unit
Remarks
Typ
Max
When the main oscillation
—
16.25 MHz
circuit is used
—
12
MHz When the main external clock
—
32.5 MHz is used
Operating conditions
4
4.08 MHz • The main CR clock is used.
• 0 C TA 70 C
Operating conditions
• The main CR clock is used.
4
4.2 MHz
•  40 C  TA  0 C,
 70 C  TA   85 C
Operating conditions
8
8.16 MHz • PLL multiplication rate: 2
• 0 C TA 70 C
Operating conditions
• PLL multiplication rate: 2
8
8.4 MHz
•  40 C  TA  0 C,
 70 C  TA   85 C
Operating conditions
10
10.2 MHz • PLL multiplication rate: 2.5
• 0 C TA 70 C
Operating conditions
• PLL multiplication rate: 2.5
10
10.5 MHz
•  40 C  TA  0 C,
 70 C  TA   85 C
Operating conditions
12
12.24 MHz • PLL multiplication rate: 3
• 0 C TA 70 C
Operating conditions
• PLL multiplication rate: 3
12
12.6 MHz
•  40 C  TA  0 C,
 70 C  TA   85 C
Operating conditions
16
16.32 MHz • PLL multiplication rate: 4
• 0 C TA 70 C
Operating conditions
• PLL multiplication rate: 4
16
16.8 MHz
•  40 C  TA  0 C,
 70 C  TA   85 C
When the suboscillation
32.768
—
kHz
circuit is used
When the sub-external clock
32.768
—
kHz
is used
When the sub-CR clock is
100
150 kHz
used
Page 84 of 121
MB95810K Series
(VCC = 2.88 V to 5.5 V, VSS = 0.0 V, TA = 40 °C to 85 °C)
Parameter
Symbol Pin name Condition

X0, X1
Clock cycle
time
Input clock
pulse width
Input clock
rising time and
falling time
CR oscillation
start time
tHCYL
X0
tLCYL
X0A, X1A
tWH1,
tWL1
X0
tWH2,
tWL2
X0A
X0, X0A
tCR,
tCF
Remarks
Typ
Max
61.5

1000
ns
83.4
1000
ns
1000
ns
µs When the subclock is used
*
30.8


30.5
33.4



*
12.4



—
15.2

µs
—

5
ns
X1: open
X0, X1
Unit
Min


X1: open
X0, X1
Value
X1: open
When the main oscillation
circuit is used
When an external clock is
used
ns
ns
When an external clock is
used, the duty ratio should
range between 40% and 60%.
When an external clock is
used
X0, X1,
X0A, X1A
*
—
—
5
ns
tCRHWK
—
—
—
—
50
µs
When the main CR clock is
used
tCRLWK
—
—
—
—
30
µs
When the sub-CR clock is
used
—
—
—
—
100
µs
When the main CR PLL clock
is used
PLL oscillation
tMCRPLLWK
start time
*: The external clock signal is input to X0 and the inverted external clock signal to X1.
• Input waveform generated when an external clock (main clock) is used
tHCYL
tWH1
tCR
tWL1
tCF
0.8 VCC 0.8 VCC
X0, X1
0.2 VCC
0.2 VCC
0.2 VCC
• Figure of main clock input port external connection
When a crystal oscillator or
a ceramic oscillator is used
X0
When an external clock is used When an external clock
(X1 is open)
is used
X0
X1
FCH
X1
FCH
Document Number: 002-04694 Rev. *A
X0
X1
Open
FCH
Page 85 of 121
MB95810K Series
• Input waveform generated when an external clock (subclock) is used
tLCYL
tWH2
tCR
tWL2
tCF
0.8 VCC 0.8 VCC
X0A
0.2 VCC
0.2 VCC
0.2 VCC
• Figure of subclock input port external connection
When a crystal oscillator or
a ceramic oscillator is used
X0A
X1A
When an external clock
is used
X0A
X1A
Open
FCL
FCL
• Input waveform generated when an internal clock (main CR clock) is used
tCRHWK
1/FCRH
Main CR clock
Oscillation starts
Oscillation stabilizes
• Input waveform generated when an internal clock (sub-CR clock) is used
tCRLWK
1/FCRL
Sub-CR clock
Oscillation starts
Document Number: 002-04694 Rev. *A
Oscillation stabilizes
Page 86 of 121
MB95810K Series
• Input waveform generated when an internal clock (main CR PLL clock) is used
1/FMCRPLL
tMCRPLLWK
Main CR PLL clock
Oscillation starts
Document Number: 002-04694 Rev. *A
Oscillation stabilizes
Page 87 of 121
MB95810K Series
18.4.2 Source Clock/Machine Clock
Parameter
Symbol
Pin
name
(VCC = 5.0 V10%, VSS = 0.0 V, TA = 40 °C to 85 °C)
Min
Value
Typ
Max
Unit
Remarks
When the main external clock is used
Min: FCH = 32.5 MHz, divided by 2
Max: FCH = 1 MHz, divided by 2
When the main CR clock is used
Source clock
62.5
—
1000
ns Min: FCRH = 4 MHz, multiplied by 4
tSCLK
—
cycle time*1
Max: FCRH = 4 MHz, divided by 4
When the suboscillation clock is used
—
61
—
µs
FCL = 32.768 kHz, divided by 2
When the sub-CR clock is used
—
20
—
µs
FCRL = 100 kHz, divided by 2
0.5
—
16.25 MHz When the main oscillation clock is used
FSP
—
4
12.5 MHz When the main CR clock is used
Source clock
—
—
16.384
—
kHz When the suboscillation clock is used
frequency
FSPL
When the sub-CR clock is used
—
50
—
kHz
FCRL = 100 kHz, divided by 2
When the main oscillation clock is used
61.5
—
32000 ns Min: FSP = 16.25 MHz, no division
Max: FSP = 0.5 MHz, divided by 16
When the main CR clock is used
Machine clock
250
—
4000
ns
Min: FSP = 4 MHz, no division
cycle time*2
Max: FSP = 4 MHz, divided by 16
(minimum
tMCLK
—
When the suboscillation clock is used
instruction
61
—
976.5
µs Min: FSPL = 16.384 kHz, no division
execution time)
Max: FSPL = 16.384 kHz, divided by 16
When the sub-CR clock is used
20
—
320
µs Min: FSPL = 50 kHz, no division
Max: FSPL = 50 kHz, divided by 16
0.031
—
16.25 MHz When the main oscillation clock is used
FMP
0.25
—
16
MHz When the main CR clock is used
Machine clock
—
1.024
—
16.384 kHz When the suboscillation clock is used
frequency
FMPL
When the sub-CR clock is used
3.125
—
50
kHz
FCRL = 100 kHz
*1: This is the clock before it is divided according to the division ratio set by the machine clock division ratio select bits
(SYCC:DIV[1:0]). This source clock is divided to become a machine clock according to the division ratio set by the
machine clock division ratio select bits (SYCC:DIV[1:0]). In addition, a source clock can be selected from the following.
• Main clock divided by 2
• Main CR clock
• PLL multiplication of main CR clock (Select a multiplication rate from 2, 2.5, 3 and 4.)
• Subclock divided by 2
• Sub-CR clock divided by 2
*2: This is the operating clock of the microcontroller. A machine clock can be selected from the following.
• Source clock (no division)
• Source clock divided by 4
• Source clock divided by 8
• Source clock divided by 16
61.5
Document Number: 002-04694 Rev. *A
—
2000
ns
Page 88 of 121
MB95810K Series
• Schematic diagram of the clock generation block
FCH
(Main oscillation clock)
Divided by 2
FMCRPLL
(Main CR PLL clock)
SCLK
(Source clock)
FCRH
(Main CR clock)
FCL
(Suboscillation clock)
Division circuit
×
1
× 1/4
× 1/8
× 1/16
MCLK
(Machine clock)
Divided by 2
Machine clock divide ratio select bits
(SYCC:DIV[1:0])
FCRL
(Sub-CR clock)
Divided by 2
Clock mode select bits
(SYCC:SCS[2:0])
• Operating voltage - Operating Frequency (TA = 40 °C to 85 °C)
5.5
Operating voltage (V)
5.0
A/D converter operation range
4.0
3.5
3.0
2.7
2.4
16 kHz
3 MHz
10 MHz
16.25 MHz
Source clock frequency (FSP/FSPL)
Document Number: 002-04694 Rev. *A
Page 89 of 121
MB95810K Series
18.4.3 External Reset
Parameter
(VCC = 5.0 V10%, VSS = 0.0 V, TA = 40 °C to 85 °C)
Value
Symbol
RST “L” level
pulse width
tRSTL
Min
Max
2 tMCLK*

Unit
Remarks
ns
*: See “Source Clock/Machine Clock” for tMCLK.
tRSTL
RST
0.2 VCC
0.2 VCC
18.4.4 Power-on Reset
(VSS = 0.0 V, TA = 40 °C to 85 °C)
Parameter
Symbol
Condition
Power supply rising time
tR
Power supply cutoff time
tOFF


tR
Value
Unit
Min
Max

50
ms
1

ms
Remarks
Wait time until power-on
tOFF
2.5 V
VCC
0.2 V
0.2 V
0.2 V
Note: A sudden change of power supply voltage may activate the power-on reset function. When changing the power
supply voltage during the operation, set the slope of rising to a value below within 30 mV/ms as shown below.
VCC
2.3 V
Set the slope of rising to
a value below 30 mV/ms.
Hold condition in stop mode
VSS
Document Number: 002-04694 Rev. *A
Page 90 of 121
MB95810K Series
18.4.5 Peripheral Input Timing
(VCC = 5.0 V10%, VSS = 0.0 V, TA = 40 °C to 85 °C)
Parameter
Value
Symbol
Pin name
Peripheral input “H” pulse width
tILIH
Peripheral input “L” pulse width
tIHIL
INT00 to INT07, INT10 to INT13,
EC0, EC1, TI0, TRG0, TRG1
tILIH
INT00 to INT07,
INT10 to INT13,
EC0, EC1, TI0,
TRG0, TRG1
0.8 VCC
Min
Max
2 tMCLK*


2 tMCLK*
Unit
ns
ns
tIHIL
0.8 VCC
0.2 VCC
0.2 VCC
*: See “Source Clock/Machine Clock” for tMCLK.
18.4.6 LIN-UART Timing
Sampling is executed at the rising edge of the sampling clock*1, and serial clock delay is disabled*2.
(ESCR register : SCES bit = 0, ECCR register : SCDE bit = 0)
(VCC = 5.0 V10%, VSS = 0.0 V, TA = 40 °C to 85 °C)
Parameter
Serial clock cycle time
SCK  SOT delay time
Symbol Pin name
tSCYC
SCK
tSLOVI
SCK, SOT Internal clock
operation output pin:
SCK, SIN CL = 80 pF  1 TTL
SCK, SIN
Valid SIN  SCK
tIVSHI
SCK  valid SIN hold time
tSHIXI
Serial clock “L” pulse width
Serial clock “H” pulse width
tSLSH
tSHSL
SCK  SOT delay time
tSLOVE
Valid SIN  SCK
tIVSHE
SCK  valid SIN hold time
tSHIXE
Value
Condition
SCK
SCK
SCK, SOT External clock
SCK, SIN operation output pin:
SCK, SIN CL = 80 pF  1 TTL
t
Max
5 tMCLK*3
—
ns
50
50
ns
MCLK 3
*  80
—
ns
0
—
ns
* tR
—
ns
*  10
—
ns
MCLK 3
3t
t
MCLK 3
—
t
Unit
Min
2t
*  60 ns
MCLK 3
30
—
ns
MCLK 3
*  30
—
ns
SCK fall time
tF
SCK
—
10
ns
SCK rise time
tR
SCK
—
10
ns
*1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling
edge of the serial clock.
*2: The serial clock delay function is a function used to delay the output signal of the serial clock for half the clock.
*3: See “Source Clock/Machine Clock” for tMCLK.
Document Number: 002-04694 Rev. *A
Page 91 of 121
MB95810K Series
• Internal shift clock mode
tSCYC
0.8 VCC
SCK
0.2 VCC
0.2 VCC
tSLOVI
0.8 VCC
SOT
0.2 VCC
tIVSHI
tSHIXI
0.7 VCC 0.7 VCC
SIN
0.3 VCC 0.3 VCC
• External shift clock mode
tSLSH
tSHSL
0.8 VCC
0.8 VCC
0.8 VCC
SCK
0.2 VCC
tF
0.2 VCC
tR
tSLOVE
0.8 VCC
SOT
0.2 VCC
tIVSHE
tSHIXE
0.7 VCC 0.7 VCC
SIN
0.3 VCC 0.3 VCC
Document Number: 002-04694 Rev. *A
Page 92 of 121
MB95810K Series
Sampling is executed at the falling edge of the sampling clock*1, and serial clock delay is disabled*2.
(ESCR register : SCES bit = 1, ECCR register : SCDE bit = 0)
(VCC = 5.0 V10%, VSS = 0.0 V, TA = 40 °C to 85 °C)
Parameter
Serial clock cycle time
SCK  SOT delay time
Symbol Pin name
tSCYC
SCK
tSHOVI
SCK, SOT Internal clock
operation output pin:
SCK, SIN CL = 80 pF  1 TTL
SCK, SIN
Valid SIN  SCK
tIVSLI
SCK valid SIN hold time
tSLIXI
Serial clock “H” pulse width
Serial clock “L” pulse width
tSHSL
tSLSH
SCK  SOT delay time
tSHOVE
Valid SIN  SCK
tIVSLE
SCK valid SIN hold time
tSLIXE
Value
Condition
t
Max
5 tMCLK*3
—
ns
50
50
ns
MCLK 3
*  80
—
ns
0
—
ns
* tR
—
ns
*  10
—
ns
MCLK 3
3t
SCK
SCK
t
SCK, SOT External clock
SCK, SIN operation output pin:
SCK, SIN CL = 80 pF  1 TTL
MCLK 3
—
t
Unit
Min
2t
*  60 ns
MCLK 3
30
—
ns
MCLK 3
*  30
—
ns
SCK fall time
tF
SCK
—
10
ns
SCK rise time
tR
SCK
—
10
ns
*1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling
edge of the serial clock.
*2: The serial clock delay function is a function used to delay the output signal of the serial clock for half the clock.
*3: See “Source Clock/Machine Clock” for tMCLK.
• Internal shift clock mode
tSCYC
0.8 VCC
0.8 VCC
SCK
0.2 VCC
tSHOVI
0.8 VCC
SOT
0.2 VCC
tIVSLI
tSLIXI
0.7 VCC 0.7 VCC
SIN
0.3 VCC 0.3 VCC
Document Number: 002-04694 Rev. *A
Page 93 of 121
MB95810K Series
• External shift clock mode
tSHSL
0.8 VCC
tSLSH
0.8 VCC
SCK
0.2 VCC
tR
tF
0.2 VCC
0.2 VCC
tSHOVE
0.8 VCC
SOT
0.2 VCC
tIVSLE
tSLIXE
0.7 VCC 0.7 VCC
SIN
0.3 VCC 0.3 VCC
Document Number: 002-04694 Rev. *A
Page 94 of 121
MB95810K Series
Sampling is executed at the rising edge of the sampling clock*1, and serial clock delay is enabled*2.
(ESCR register : SCES bit = 0, ECCR register : SCDE bit = 1)
(VCC = 5.0 V10%, VSS = 0.0 V, TA = 40 °C to 85 °C)
Parameter
Symbol Pin name
Value
Condition
Serial clock cycle time
tSCYC
SCK
SCK SOT delay time
tSHOVI
SCK, SOT Internal clock
SCK, SIN operation output pin:
SCK, SIN CL = 80 pF  1 TTL
Valid SIN  SCK
tIVSLI
SCK valid SIN hold time
tSLIXI
SOT  SCKdelay time
tSOVLI
SCK, SOT
t
Unit
Min
Max
5 tMCLK*3
—
ns
50
50
ns
MCLK 3
*  80
—
ns
0
—
ns
* 70
—
ns
3t
MCLK 3
*1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling
edge of the serial clock.
*2: The serial clock delay function is a function used to delay the output signal of the serial clock for half the clock.
*3: See “Source Clock/Machine Clock” for tMCLK.
tSCYC
0.8 VCC
SCK
0.2 VCC
SOT
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
tIVSLI
SIN
0.2 VCC
tSHOVI
tSOVLI
tSLIXI
0.7 VCC
0.7 VCC
0.3 VCC
0.3 VCC
Document Number: 002-04694 Rev. *A
Page 95 of 121
MB95810K Series
Sampling is executed at the falling edge of the sampling clock*1, and serial clock delay is enabled*2.
(ESCR register : SCES bit = 1, ECCR register : SCDE bit = 1)
(VCC = 5.0 V10%, VSS = 0.0 V, TA = 40 °C to 85 °C)
Parameter
Symbol Pin name
Value
Condition
Serial clock cycle time
tSCYC
SCK
SCK  SOT delay time
tSLOVI
SCK, SOT Internal clock
SCK, SIN operation output pin:
SCK, SIN CL = 80 pF  1 TTL
Valid SIN  SCK
tIVSHI
SCK  valid SIN hold time
tSHIXI
SOT  SCKdelay time
tSOVHI
SCK, SOT
t
Unit
Min
Max
5 tMCLK*3
—
ns
50
50
ns
MCLK 3
*  80
—
ns
0
—
ns
* 70
—
ns
3t
MCLK 3
*1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling
edge of the serial clock.
*2: The serial clock delay function is a function used to delay the output signal of the serial clock for half the clock.
*3: See “Source Clock/Machine Clock” for tMCLK.
tSCYC
0.8 VCC
SCK
0.8 VCC
0.2 VCC
tSOVHI
SOT
0.8 VCC
0.2 VCC
0.2 VCC
tIVSHI
SIN
tSLOVI
0.8 VCC
tSHIXI
0.7 VCC
0.7 VCC
0.3 VCC
0.3 VCC
Document Number: 002-04694 Rev. *A
Page 96 of 121
MB95810K Series
18.4.7 Low-voltage Detection
Parameter
(VSS = 0.0 V, TA = 40 °C to 85 °C)
Symbol
Value
Unit
Remarks
Min
Typ
Max
2.52
2.7
2.88
2.61
2.8
2.99
2.89
3.1
3.31
3.08
3.3
3.52
2.43
2.6
2.77
2.52
2.7
2.88
2.80
3
3.20
2.99
3.2
3.41
VHYS
—
—
100
mV
Power supply start
voltage
Voff
—
—
2.3
V
Power supply end
voltage
Von
4.9
—
—
V
Power supply voltage
change time
(at power supply rise)
tr
650
—
—
µs
Slope of power supply that the reset
release signal generates within the
rating (VDL+)
Power supply voltage
change time
(at power supply fall)
tf
650
—
—
µs
Slope of power supply that the reset
release signal generates within the
rating (VDL-)
Reset release delay
time
td1
—
—
30
µs
Reset detection delay
time
td2
—
—
30
µs
LVD reset threshold
voltage transition
stabilization time
tstb
10
—
—
µs
Release voltage*
Detection voltage*
Hysteresis width
VDL
VDL
V
At power supply rise
V
At power supply fall
*: After the LVD reset is enabled by the LVD reset circuit control register (LVDCC), the release voltage and the detection
voltage can be selected by using the LVD reset voltage selection ID register (LVDR) in the low-voltage detection reset
circuit. For details of the LVDCC register and the LVDR register, refer to “CHAPTER 17 LOW-VOLTAGE
DETECTION RESET CIRCUIT” in “New 8FX MB95810K Series Hardware Manual”.
Document Number: 002-04694 Rev. *A
Page 97 of 121
MB95810K Series
VCC
Von
Voff
time
tf
tr
VDL+
VHYS
VDL-
Internal reset signal
time
td2
Document Number: 002-04694 Rev. *A
td1
Page 98 of 121
MB95810K Series
18.4.8 I2C Bus Interface Timing
(VCC = 5.0 V10%, VSS = 0.0 V, TA = 40 °C to 85 °C)
Value
Parameter
Standardmode
Fast-mode
Min
Max
Min
Max
0
100
0
400
kHz
SCL, SDA
4.0
—
0.6
—
µs
Symbol Pin name Condition
SCL clock frequency
fSCL
(Repeated) START condition hold
time
SDA  SCL 
tHD;STA
SCL
Unit
SCL clock “L” width
tLOW
SCL
4.7
—
1.3
—
µs
SCL clock “H” width
tHIGH
SCL
4.0
—
0.6
—
µs
4.7
—
0.6
—
µs
(Repeated) START condition setup
time
SCL  SDA 
tSU;STA
SCL, SDA
Data hold time
SCL  SDA 
tHD;DAT
SCL, SDA
0
3.45*2
0
0.9*3
µs
Data setup time
SDA  SCL 
tSU;DAT
SCL, SDA
0.25
—
0.1
—
µs
STOP condition setup time
SCL   SDA 
tSU;STO
SCL, SDA
4
—
0.6
—
µs
tBUF
SCL, SDA
4.7
—
1.3
—
µs
Bus free time between STOP
condition and START condition
R = 1.7 k,
C = 50 pF*1
*1: R represents the pull-up resistor of the SCL and SDA lines, and C the load capacitor of the SCL and SDA lines.
*2: The maximum tHD;DAT in the Standard-mode is applicable only when the time during which the device is holding the
SCL signal at “L” (tLOW) does not extend.
*3: A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, provided that the condition of tSU;DAT
 250 ns is fulfilled.
tWAKEUP
SDA
tLOW
tHD;DAT
tHIGH
tHD;STA
tBUF
SCL
tHD;STA
tSU;DAT
fSCL
Document Number: 002-04694 Rev. *A
tSU;STA
tSU;STO
Page 99 of 121
MB95810K Series
(VCC = 5.0 V10%, VSS = 0.0 V, TA = 40 °C to 85 °C)
Value*2
Pin
Unit
Remarks
Parameter Symbol
Condition
name
Min
Max
SCL clock
(2  nm/2)tMCLK  20
—
ns Master mode
tLOW SCL
“L” width
SCL clock
(nm/2)tMCLK  20
(nm/2)tMCLK  20
ns Master mode
tHIGH SCL
“H” width
Master mode
Maximum value
is applied when
START
SCL,
(-1  nm/2)tMCLK  20 (-1  nm)tMCLK  20 ns m, n = 1, 8.
condition
tHD;STA
SDA0
Otherwise, the
hold time
minimum value is
applied.
STOP
SCL,
condition
tSU;STO
(1  nm/2)tMCLK  20 (1  nm/2)tMCLK  20 ns Master mode
SDA
setup time
START
SCL,
condition
tSU;STA
(1  nm/2)tMCLK  20 (1  nm/2)tMCLK  20 ns Master mode
SDA
setup time
Bus free time
between
STOP
SCL,
tBUF
(2 nm  4) tMCLK  20
—
ns
condition
SDA
and START
condition
R = 1.7 k,
SCL,
Data hold
C = 50 pF*1
3 tMCLK  20
—
ns Master mode
tHD;DAT
SDA
time
Master mode
It is assumed that
“L” of SCL is not
extended. The
minimum value is
Data setup
SCL,
tSU;DAT
(-2  nm/2) tMCLK  20 (-1  nm/2) tMCLK  20 ns
applied to the first
time
SDA
bit of continuous
data. Otherwise,
the maximum
value is applied.
The minimum
value is applied
Setup time
to the interrupt at
between
the ninth SCL.
clearing
tSU;INT SCL
(nm/2) tMCLK  20 (1  nm/2) tMCLK  20 ns
The maximum
interrupt and
value is applied
SCL rising
to the interrupt at
the eighth SCL.
SCL clock
tLOW SCL
4 tMCLK  20
—
ns At reception
“L” width
SCL clock
tHIGH SCL
4 tMCLK  20
—
ns At reception
“H” width
Document Number: 002-04694 Rev. *A
Page 100 of 121
MB95810K Series
Parameter
Pin
Symbol
Condition
name
START condition
detection
tHD;STA
SCL,
SDA
STOP condition
detection
tSU;STO
SCL,
SDA
RESTART
condition detection
condition
tSU;STA
SCL,
SDA
Bus free time
tBUF
Data hold time
tHD;DAT
Data setup time
tSU;DAT
Data hold time
tHD;DAT
Data setup time
tSU;DAT
SDA  SCL
(with wakeup
function in use)
tWAKEUP
SCL,
SDA
SCL,
SDA
SCL,
SDA
SCL,
SDA
SCL,
SDA
SCL,
SDA
R = 1.7 k,
C = 50 pF*1
(VCC = 5.0 V10%, VSS = 0.0 V, TA = 40 °C to 85 °C)
Value*2
Unit
Remarks
Min
Max
No START
condition is
2 tMCLK  20
—
ns detected when 1
tMCLK is used at
reception.
No STOP condition
is detected when 1
2 tMCLK  20
—
ns
tMCLK is used at
reception.
No RESTART
condition is
2 tMCLK  20
—
ns detected when 1
tMCLK is used at
reception.
2 tMCLK  20
—
ns At reception
2 tMCLK  20
—
ns
tLOW  3 tMCLK  20
—
0
—
ns At reception
tMCLK  20
—
ns At reception
Oscillation
stabilization wait time
2 tMCLK  20
—
ns
At slave
transmission mode
At slave
ns
transmission mode
*1: R represents the pull-up resistor of the SCL and SDA lines, and C the load capacitor of the SCL and SDA0 lines.
*2: • See “Source Clock/Machine Clock” for tMCLK.
• m represents the CS[4:3] bits in the I2C clock control register (ICCR0).
• n represents the CS[2:0] bits in the I2C clock control register (ICCR0).
• The actual timing of the I2C bus interface is determined by the values of m and n set by the machine clock (tMCLK)
and the CS[4:0] bits in the ICCR0 register.
• Standard-mode:
m and n can be set to values in the following range: 0.9 MHz  tMCLK (machine clock)  16.25 MHz.
The usable frequencies of the machine clock are determined by the settings of m and n as shown below.
(m, n) = (1, 8)
: 0.9 MHz < tMCLK  1 MHz
(m, n) = (1, 22), (5, 4), (6, 4), (7, 4), (8, 4)
: 0.9 MHz < tMCLK  2 MHz
(m, n) = (1, 38), (5, 8), (6, 8), (7, 8), (8, 8)
: 0.9 MHz < tMCLK  4 MHz
(m, n) = (1, 98), (5, 22), (6, 22), (7, 22)
: 0.9 MHz < tMCLK  10 MHz
(m, n) = (8, 22)
: 0.9 MHz < tMCLK  16.25 MHz
• Fast-mode:
m and n can be set to values in the following range: 3.3 MHz < tMCLK (machine clock) < 16.25 MHz.
The usable frequencies of the machine clock are determined by the settings of m and n as shown below.
(m, n) = (1, 8)
: 3.3 MHz < tMCLK  4 MHz
(m, n) = (1, 22), (5, 4)
: 3.3 MHz < tMCLK  8 MHz
(m, n) = (1, 38), (6, 4), (7, 4), (8, 4)
: 3.3 MHz < tMCLK  10 MHz
(m, n) = (5, 8)
: 3.3 MHz < tMCLK  16.25 MHz
Document Number: 002-04694 Rev. *A
Page 101 of 121
MB95810K Series
18.4.9 UART/SIO, Serial I/O Timing
Parameter
(VCC = 5.0 V10%, VSS = 0.0 V, TA = 40 °C to 85 °C)
Symbol
Pin name
Value
Condition
Unit
Min
Max
4 tMCLK*
—
ns
190
190
ns
2 tMCLK*
—
ns
Serial clock cycle time
tSCYC
UCK0
UCK  UO time
tSLOV
UCK0, UO0
Valid UI  UCK 
tIVSH
UCK0, UI0
UCK  valid UI hold time
tSHIX
UCK0, UI0
2 tMCLK*
—
ns
Serial clock “H” pulse width
tSHSL
UCK0
4 tMCLK*
—
ns
Serial clock “L” pulse width
tSLSH
UCK0
4 tMCLK*
—
ns
UCK  UO time
tSLOV
UCK0, UO0
—
190
ns
Valid UI  UCK 
tIVSH
UCK0, UI0
2 tMCLK*
—
ns
UCK  valid UI hold time
tSHIX
UCK0, UI0
2 tMCLK*
—
ns
Internal clock operation
External clock operation
*: See “Source Clock/Machine Clock” for tMCLK.
• Internal shift clock mode
tSCYC
0.8 VCC
UCK0
0.2 VCC
0.2 VCC
tSLOV
0.8 VCC
UO0
0.2 VCC
tIVSH
tSHIX
0.7 VCC 0.7 VCC
UI0
0.3 VCC 0.3 VCC
Document Number: 002-04694 Rev. *A
Page 102 of 121
MB95810K Series
• External shift clock mode
tSLSH
tSHSL
0.8 VCC
0.8 VCC
UCK0
0.2 VCC
0.2 VCC
tSLOV
0.8 VCC
UO0
0.2 VCC
tIVSH
tSHIX
0.7 VCC 0.7 VCC
UI0
0.3 VCC 0.3 VCC
18.4.10 Comparator Timing
Parameter
(VCC = 2.88 V to 5.5 V, VSS = 0.0 V, TA = 40 °C to 85 °C)
Pin name
Value
Unit
Remarks
Min
Typ
Max
Voltage range
CMP0_P,
CMP0_N,
CMP1_P,
CMP1_N
0
—
VCC  1.3
V
Offset voltage
CMP0_P,
CMP0_N,
CMP1_P,
CMP1_N
15
—
15
mV
Delay time
CMP0_O,
CMP1_O
—
650
1200
ns
Overdrive 5 mV
—
140
420
ns
Overdrive 50 mV
Power down delay
CMP0_O,
CMP1_O
—
—
1200
ns
Power down recovery
PD: 1  0
Power up
CMP0_O,
stabilization wait time CMP1_O
—
—
1200
ns
Output stabilization time at power
up
18.4.11 BGR for Comparator
(VCC = 2.88 V to 5.5 V, VSS = 0.0 V, TA = 40 °C to 85 °C)
Parameter
Symbol
Power up
stabilization wait time
Output voltage
Value
Unit
Min
Typ
Max
—
—
—
150
µs
VBGR
1.1495
1.21
1.2705
V
Document Number: 002-04694 Rev. *A
Remarks
Load: 10 pF
Page 103 of 121
MB95810K Series
18.5 A/D Converter
18.5.1 A/D Converter Electrical Characteristics
Parameter
(AVCC = VCC = 2.7 V to 5.5 V, AVSS = VSS = 0.0 V, TA = 40 °C to 85 °C)
Value
Symbol
Unit
Min
Typ
Max
Resolution
—
—
10
bit
Total error
3
—
3
LSB
2.5
—
2.5
LSB
1.9
—
1.9
LSB
—
Linearity error
Differential linearity
error
Zero transition
voltage
V0T
AVSS 7.2 LSB AVSS  0.5 LSB AVSS  8.2 LSB
V
Full-scale transition
voltage
VFST
AVR 6.2 LSB AVR 1.5 LSB AVR  9.2 LSB
V
Compare time
—
3
—
10
µs
2.7 V  AVCC  5.5 V
2.7 V  AVCC  5.5 V,
with external
impedance  3.3 k
and external
capacitance = 10 pF
Sampling time
—
0.941
—

µs
Analog input current
IAIN
0.3
—
0.3
µA
Analog input voltage
VAIN
AVSS
—
AVR
V
—
AVCC 0.1
—
AVCC
V
Reference voltage
Remarks
Voltage applied to the
AVR pin
18.5.2 Notes on Using A/D Converter
• External impedance of analog input and its sampling time
The A/D converter of has a sample and hold circuit. If the external impedance is too high to keep sufficient sampling
time, the analog voltage charged to the capacitor of the internal sample and hold circuit is insufficient, adversely affecting A/D conversion precision. Therefore, to satisfy the A/D conversion precision standard, considering the relationship between the external impedance and minimum sampling time, either adjust the register value and operating
frequency or decrease the external impedance so that the sampling time is longer than the minimum value. In addition, if sufficient sampling time cannot be secured, connect a capacitor of about 0.1 µF to the analog input pin.
• Analog input equivalent circuit
Analog input
Comparator
R
C
During sampling: ON
VCC
R
C
4.5 V ≤ AVCC ≤ 5.5 V
1.45 kΩ (Max)
2.7 V ≤ AVCC < 4.5 V
2.7 kΩ (Max)
14.89 pF (Max)
14.89 pF (Max)
Note: The values are reference values.
Document Number: 002-04694 Rev. *A
Page 104 of 121
MB95810K Series
• Relationship between external impedance and minimum sampling time
[External impedance = 0 kΩ to 100 kΩ]
100
External impedance [kΩ]
80
60
40
20
0
0
2
4
6
8
10
12
14
16
18
20
Minimum sampling time [μs]
[External impedance = 0 kΩ to 20 kΩ]
External impedance [kΩ]
20
15
10
5
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
Minimum sampling time [μs]
Note: External capacitance = 10 pF
• A/D conversion error
As |AVR  AVSS| decreases, the A/D conversion error increases proportionately.
Document Number: 002-04694 Rev. *A
Page 105 of 121
MB95810K Series
18.5.3 Definitions of A/D Converter Terms
• Resolution
It indicates the level of analog variation that can be distinguished by the A/D converter.
When the number of bits is 10, analog voltage can be divided into 210 = 1024.
• Linearity error (unit: LSB)
It indicates how much an actual conversion value deviates from the straight line connecting the zero transition point
(“0000000000”   “0000000001”) of a device to the full-scale transition point (“1111111111”   “1111111110”) of
the same device.
• Differential linear error (unit: LSB)
It indicates how much the input voltage required to change the output code by 1 LSB deviates from an ideal value.
• Total error (unit: LSB)
It indicates the difference between an actual value and a theoretical value. The error can be caused by a zero transition error, a full-scale transition errors, a linearity error, a quantum error, or noise.
Ideal I/O characteristics
Total error
VFST
0x3FF
0x3FF
2 LSB
0x3FD
Digital output
Digital output
0x3FD
0x004
0x003
Actual conversion
characteristic
0x3FE
0x3FE
V0T
{1 LSB × (N − 1) + 0.5 LSB}
0x004
VNT
0x003
1 LSB
0x002
0x002
0x001
Actual conversion
characteristic
Ideal characteristic
0x001
0.5 LSB
AVR
Analog input
1 LSB =
AVSS
AVR − AVSS
V
1024
N
AVR
Analog input
Total error of digital output N =
AVSS
VNT − {1 LSB × (N − 1) + 0.5 LSB}
LSB
1 LSB
: A/D converter digital output value
VNT : Voltage at which the digital output transits from 0x(N − 1) to 0xN
Document Number: 002-04694 Rev. *A
Page 106 of 121
MB95810K Series
Zero transition error
Full-scale transition error
0x004
Ideal characteristic
Actual conversion
characteristic
0x3FF
Actual conversion
characteristic
0x002
Ideal
characteristic
Digital output
Digital output
0x003
Actual conversion
characteristic
0x3FE
VFST
(measurement
value)
0x3FD
Actual conversion
characteristic
0x001
0x3FC
V0T (measurement value)
AVR
Analog input
AVSS
AVR
Linearity error
0x3FF
0x3FE
Ideal characteristic
0x(N+1)
Actual conversion
characteristic
{1 LSB × N + V0T}
VFST
Digital output
Digital output
0x3FD
(measurement
value)
VNT
0x004
0x002
AVSS
Differential linearity error
Actual conversion
characteristic
V(N+1)T
0xN
VNT
0x(N−1)
Actual conversion
characteristic
0x003
Analog input
Ideal
characteristic
Actual conversion
characteristic
0x(N−2)
0x001
V0T (measurement value)
AVR
Analog input
AVSS
Linearity error of digital output N =
AVR
AVSS
VNT − {1 LSB × N + V0T}
1 LSB
Differential linearity error of digital output N =
N
Analog input
V(N+1)T − VNT
− 1
1 LSB
: A/D converter digital output value
VNT : Voltage at which the digital output transits from 0x(N − 1) to 0xN
V0T (ideal value) = AVR + 0.5 LSB [V]
VFST (ideal value) = AVSS − 2 LSB [V]
Document Number: 002-04694 Rev. *A
Page 107 of 121
MB95810K Series
18.6 Flash Memory Program/Erase Characteristics
Parameter
Value
Unit
Remarks
1.6*2
s
The time of writing “0x00” prior to erasure is excluded.
0.6*1
3.1*2
s
The time of writing “0x00” prior to erasure is excluded.
17
272
µs
System-level overhead is excluded.
Program/erase cycle 100000
—
—
cycle
Power supply voltage
at program/erase
2.4
—
5.5
V
20*3
—
—
Average TA = 85 °C
Number of program/erase cycles: 1000 or below
10*3
—
—
Average TA = 85 °C
year Number of program/erase cycles: 1001 to 10000
inclusive
5*3
—
—
Min
Typ
Max
Sector erase time
(2 Kbyte sector)
—
0.3*1
Sector erase time
(32 Kbyte sector)
—
Byte writing time
—
Flash memory data
retention time
Average TA = 85 °C
Number of program/erase cycles: 10001 or above
*1: VCC = 5.5 V, TA = 25 °C, 0 cycle
*2: VCC = 2.4 V, TA = 85 °C, 100000 cycles
*3: These values were converted from the result of a technology reliability assessment. (These values were converted
from the result of a high temperature accelerated test using the Arrhenius equation with the average temperature
being 85 °C.)
Document Number: 002-04694 Rev. *A
Page 108 of 121
MB95810K Series
19. Sample Characteristics
• Power supply current temperature characteristics
ICC  VCC
TA  25 C, FMP  2, 4, 8, 10, 16 MHz (divided by 2)
Main clock mode with the external clock operating
ICC  TA
VCC  5.5 V, FMP  2, 4, 8, 10, 16 MHz (divided by 2)
Main clock mode with the external clock operating
20
20
FMP = 16 MHz
FMP = 10 MHz
FMP = 8 MHz
FMP = 4 MHz
FMP = 2 MHz
15
ICC[mA]
ICC[mA]
15
FMP = 16 MHz
FMP = 10 MHz
FMP = 8 MHz
FMP = 4 MHz
FMP = 2 MHz
10
10
5
5
0
0
2
3
4
5
6
−50
7
0
VCC[V]
ICCS  VCC
TA  25 C, FMP  2, 4, 8, 10, 16 MHz (divided by 2)
Main sleep mode with the external clock operating
+150
10
FMP = 16 MHz
FMP = 10 MHz
FMP = 8 MHz
FMP = 4 MHz
FMP = 2 MHz
8
FMP = 16 MHz
FMP = 10 MHz
FMP = 8 MHz
FMP = 4 MHz
FMP = 2 MHz
8
6
ICCS[mA]
ICCS[mA]
+100
ICCS  TA
VCC  5.5 V, FMP  2, 4, 8, 10, 16 MHz (divided by 2)
Main sleep mode with the external clock operating
10
4
2
6
4
2
0
0
2
3
4
5
6
−50
7
0
VCC[V]
+50
+100
+150
TA[°C]
ICCL  VCC
TA  25 C, FMPL  16 kHz (divided by 2)
Subclock mode with the external clock operating
ICCL  TA
VCC  5.5 V, FMPL  16 kHz (divided by 2)
Subclock mode with the external clock operating
100
100
80
80
60
60
ICCL[μA]
ICCL[μA]
+50
TA[°C]
40
40
20
25
0
0
2
3
4
5
VCC[V]
Document Number: 002-04694 Rev. *A
6
7
−50
0
+50
+100
+150
TA[°C]
Page 109 of 121
MB95810K Series
ICCLS  TA
VCC  5.5 V, FMPL  16 kHz (divided by 2)
Subsleep mode with the external clock operating
80
80
70
70
60
60
50
50
ICCLS[μA]
ICCLS[μA]
ICCLS  VCC
TA  25 C, FMPL  16 kHz (divided by 2)
Subsleep mode with the external clock operating
40
30
40
30
20
20
10
10
0
0
2
3
4
5
6
−50
7
0
VCC[V]
+100
+150
ICCT  TA
VCC  5.5 V, FMPL  16 kHz (divided by 2)
Watch mode with the external clock operating
80
80
70
70
60
60
50
50
ICCT[μA]
ICCT[μA]
ICCT  VCC
TA  25 C, FMPL  16 kHz (divided by 2)
Watch mode with the external clock operating
40
40
30
30
20
20
10
10
0
0
2
3
4
5
6
−50
7
0
VCC[V]
+50
+100
+150
TA[°C]
ICCTS  VCC
TA  25 C, FMP  2, 4, 8, 10, 16 MHz (divided by 2)
Time-base timer mode with the external clock
operating
ICCTS  TA
VCC  5.5 V, FMP  2, 4, 8, 10, 16 MHz (divided by 2)
Time-base timer mode with the external clock
operating
1.4
1.4
FMP = 16 MHz
FMP = 10 MHz
FMP = 8 MHz
FMP = 4 MHz
FMP = 2 MHz
1.0
FMP = 16 MHz
FMP = 10 MHz
FMP = 8 MHz
FMP = 4 MHz
FMP = 2 MHz
1.2
1.0
ICCTS[mA]
1.2
ICCTS[mA]
+50
TA[°C]
0.8
0.6
0.8
0.6
0.4
0.4
0.2
0.2
0.0
0.0
2
3
4
5
VCC[V]
Document Number: 002-04694 Rev. *A
6
7
−50
0
+50
+100
+150
TA[°C]
Page 110 of 121
MB95810K Series
ICCH  TA
VCC  5.5 V, FMPL  (stop)
Substop mode with the external clock stopping
20
20
15
15
ICCH[μA]
ICCH[μA]
ICCH  VCC
TA  25 C, FMPL  (stop)
Substop mode with the external clock stopping
10
5
10
5
0
0
1
2
3
4
5
6
−50
7
0
VCC[V]
ICCMCR  VCC
TA  25 C, FMP  4 MHz (no division)
Main CR clock mode
+100
+150
ICCMCR  TA
VCC  5.5 V, FMP  4 MHz (no division)
Main CR clock mode
20
20
15
15
ICCMCR[mA]
ICCMCR[mA]
+50
TA[°C]
10
5
10
5
0
0
2
3
4
5
6
−50
7
0
VCC[V]
+50
+100
+150
TA[°C]
10
10
8
8
6
6
ICCMPLL[mA]
ICCMPLL[mA]
ICCMPLL  VCC
ICCMPLL  TA
TA  25 C, FMP  16 MHz (PLL multiplication rate: 4) VCC  5.5 V, FMP  16 MHz (PLL multiplication rate: 4)
Main CR PLL clock mode
Main CR PLL clock mode
4
2
4
2
0
0
1
2
3
4
VCC[V]
Document Number: 002-04694 Rev. *A
5
6
7
−50
0
+50
+100
+150
TA[°C]
Page 111 of 121
MB95810K Series
ICCSCR  TA
VCC  5.5 V, FMPL  50 kHz (divided by 2)
Sub-CR clock mode
200
200
150
150
ICCSCR[μA]
ICCSCR[μA]
ICCSCR  VCC
TA  25 C, FMPL  50 kHz (divided by 2)
Sub-CR clock mode
100
50
100
50
0
0
2
3
4
5
VCC[V]
Document Number: 002-04694 Rev. *A
6
7
−50
0
+50
+100
+150
TA[°C]
Page 112 of 121
MB95810K Series
• Input voltage characteristics
VIHI  VCC and VILI  VCC
TA  25 C
VIHS  VCC and VILS  VCC
TA  25 C
5
5
VIHI
VILI
VIHS
VILS
4
3
3
VIHI/VILI[V]
VIHS/VILS[V]
4
2
1
2
1
0
0
2
3
4
5
6
7
2
3
4
VCC[V]
5
6
7
VCC[V]
VIHM  VCC and VILM  VCC
TA  25 C
5
VIHM
VILM
VIHM/VILM[V]
4
3
2
1
0
2
3
4
5
6
7
VCC[V]
Document Number: 002-04694 Rev. *A
Page 113 of 121
MB95810K Series
• Output voltage characteristics
(VCC  VOH2)  IOH
TA  25 C
2.0
2.0
1.8
1.8
1.6
1.6
1.4
1.4
VCC − VOH2[V]
VCC − VOH1[V]
(VCC  VOH1)  IOH
TA  25 C
1.2
1.0
0.8
1.2
1.0
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0.0
0
0.0
−1 −2 −3 −4 −5 −6 −7 −8 −9 −10 −11 −12 −13 −14 −15
0
−1 −2 −3 −4 −5 −6 −7 −8 −9 −10 −11 −12 −13 −14 −15
IOH[mA]
IOH[mA]
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.5 V
VCC = 4.0 V
VCC = 4.5 V
VCC = 5.0 V
VCC = 5.5 V
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.5 V
VCC = 4.0 V
VCC = 4.5 V
VCC = 5.0 V
VCC = 5.5 V
VOL1  IOL
TA  25 C
VOL2  IOL
TA  25 C
1.0
2.0
1.8
1.6
0.8
1.4
0.6
VOL2[V]
VOL1[V]
1.2
1.0
0.8
0.4
0.6
0.4
0.2
0.2
0.0
0.0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
IOL[mA]
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.5 V
VCC = 4.0 V
VCC = 4.5 V
VCC = 5.0 V
VCC = 5.5 V
Document Number: 002-04694 Rev. *A
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
IOL[mA]
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.5 V
VCC = 4.0 V
VCC = 4.5 V
VCC = 5.0 V
VCC = 5.5 V
Page 114 of 121
MB95810K Series
• Pull-up characteristics
RPULL  VCC
TA  25 C
200
RPULL[kΩ]
150
100
50
0
2
3
4
5
6
VCC[V]
Document Number: 002-04694 Rev. *A
Page 115 of 121
MB95810K Series
20. Ordering Information
Part number
Package
MB95F814KPMC1-G-SNE2
MB95F816KPMC1-G-SNE2
MB95F818KPMC1-G-SNE2
64-pin plastic LQFP
(FPT-64P-M38)
MB95F814KPMC-G-SNE2
MB95F816KPMC-G-SNE2
MB95F818KPMC-G-SNE2
MB95F818KPMC-G-UNE2
64-pin plastic LQFP
(FPT-64P-M39)
Document Number: 002-04694 Rev. *A
Page 116 of 121
MB95810K Series
21. Package Dimension
64-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
10.00 mm × 10.00 mm
Lead shape
Gullwing
Lead bend
direction
Normal bend
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.32 g
(FPT-64P-M38)
64-pin plastic LQFP
(FPT-64P-M38)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
12.00±0.20(.472±.008)SQ
0.145±0.055
(.006±.002)
*10.00±0.10(.394±.004)SQ
48
33
49
Details of "A" part
32
+0.20
0.08(.003)
1.50 –0.10
(Mounting height)
+.008
.059 –.004
0.25(.010)
0~8°
INDEX
64
17
1
0.22±0.05
(.009±.002)
2010 FUJITSU SEMICONDUCTOR LIMITED F64038S-c-1-2
Document Number: 002-04694 Rev. *A
0.10±0.10
(.004±.004)
(Stand off)
"A"
16
0.50(.020)
C
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.08(.003)
M
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Page 117 of 121
MB95810K Series
64-pin plastic LQFP
Lead pitch
0.65 mm
Package width ×
package length
12.00 mm × 12.00 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.47 g
(FPT-64P-M39)
64-pin plastic LQFP
(FPT-64P-M39)
Note 1) Pins width and pins thickness include plating thickness.
14.00±0.20(.551±.008)SQ
12.00±0.10(.472±.004)SQ
48
0.145±0.055
(.006±.002)
33
Details of "A" part
49
32
+0.20
1.50 –0.10
+.008
.059 –.004
0.10(.004)
INDEX
0.50±0.20
(.020±.008)
64
17
1
C
0.32±0.05
(.013±.002)
0.25(.010)BSC
"A"
0.13(.005)
2010-2011 FUJITSU SEMICONDUCTOR LIMITED HMbF64-39Sc-2-2
Document Number: 002-04694 Rev. *A
0.10±0.10
(.004±.004)
0.60±0.15
(.024±.006)
16
0.65(.026)
0~8˚
M
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Page 118 of 121
MB95810K Series
22. Major Changes In This Edition
Spansion Publication Number: DS702-00015-2v0-E
Page
Section
Details
■ PIN CONNECTION
• DBG pin
Revised details of “• DBG pin”.
• RST pin
Revised details of “• RST pin”.
19
• C pin
Corrected the following statement.
The bypass capacitor for the VCC pin must have a capacitance
larger than CS.

The decoupling capacitor for the VCC pin must have a
capacitance equal to or larger than the capacitance of CS.
79
■ I/O PORTS
11. Port F
(4) Port F operations
• Operation as an input port
Added the following statement.
For a pin shared with other peripheral functions, disable the
output of such peripheral functions.
82
12. Port G
(4) Port G operations
• Operation as an input port
Added the following statement.
For a pin shared with other peripheral functions, disable the
output of such peripheral functions.
89
■ ELECTRICAL CHARACTERISTICS Corrected the following statement in the remark of the
2. Recommended Operating Conditions parameter “Decoupling capacitor”.
The bypass capacitor for the VCC pin must have a capacitance
larger than CS.

The decoupling capacitor for the VCC pin must have a
capacitance equal to or larger than the capacitance of CS.
18
Revised the remark in “• DBG/RST/C pins connection diagram”.
90
3. DC Characteristics
Revised the remark of the parameter “Input leak current (Hi-Z
output leak current)”.
When pull-up resistance is disabled

When the internal pull-up resistor is disabled
Renamed the parameter “Pull-up resistance” to “Internal pull-up
resistor”.
Revised the remark of the parameter “Internal pull-up resistor”.
When pull-up resistance is enabled

When the internal pull-up resistor is enabled
95
4. AC Characteristics
(1) Clock Timing
Corrected the pin names of the parameter “Input clock rising
time and falling time”.
X0  X0, X0A
X0, X1  X0, X1, X0A, X1A
NOTE: Please see “Document History” about later revised information.
Document Number: 002-04694 Rev. *A
Page 119 of 121
MB95810K Series
Document History Page
Document Title: MB95810K Series, New 8FX 8-bit Microcontrollers
Document Number: 002-04694
Revision
ECN
Orig. of
Change
Submission
Date
**
-
AKIH
05/27/2013
Migrated to Cypress and assigned document number 002-08453.
No change to document contents or format.
*A
5193921
AKIH
03/29/2016
Updated to Cypress template
Added MB95F818KPMC-G-UNE2 in "Ordering Information".
Document Number: 002-04694 Rev. *A
Description of Change
Page 120 of 121
MB95810K Series
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
ARM® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
Interface
Lighting & Power Control
Memory
cypress.com/clocks
cypress.com/interface
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Community | Forums | Blogs | Video | Training
cypress.com/powerpsoc
cypress.com/memory
PSoC
cypress.com/psoc
Touch Sensing
Technical Support
cypress.com/support
cypress.com/touch
USB Controllers
Wireless/RF
cypress.com/psoc
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation 2012-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you under its copyright rights in the Software, a personal, non-exclusive, nontransferable license (without the right to sublicense) (a) for Software provided in source code form, to modify
and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either
directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units. Cypress also grants you a personal, non-exclusive, nontransferable, license (without the right
to sublicense) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely to the minimum
extent that is necessary for you to exercise your rights under the copyright license granted in the previous sentence. Any other use, reproduction, modification, translation, or compilation of the Software
is prohibited.
CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes to this document without further notice. Cypress does not
assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or
programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application
made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of
weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or
hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any
component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole
or in part, and Company shall and hereby does release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. Company shall indemnify
and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress
products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United
States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-04694 Rev. *A
Revised March 29, 2016
Page 121 of 121
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