P PI33XX‐X0‐‐LGIZ Cool‐Pow wer® 8V 8 to 36 6Vin Coo ol‐Powerr® ZVS B Buck Reggulator FFamily Descrip ption Feattures The PI33XX X is a family of o high efficien ncy, wide inpu ut range DC C‐DC ZVS‐Bu uck regulatorrs integratin ng controller, power switch hes, and suppo ort componentts all within a high density System‐in‐Pacckage (SiP). The integration n of a high performance e Zero‐Voltagge Switching (ZVS) topologgy, within the PI33XX seriess, increases point p of load performance p providing best in class powe er efficiency. The T PI33XX re equires only an external in nductor and minimal m capaciitors to form a complete DC‐DC D switchin ng mode buck regulator. Device Ou utput Voltage Set Range Iout Max PI3311‐X0‐LGIZ 1.0V 1.00 to 1.4 10A PI3312‐X0‐LGIZ 2.5V 2.0 to 3.1 10A PI3301‐X0‐LGIZ 3.3V 2.3 to 4.1 10A PI3302‐X0‐LGIZ 5.0V 3.3 to 6.5 10A PI3303‐X0‐LGIZ 12V 6.5 to 13.0 8A PI3305‐X0‐LGIZ 15V 10.0 to 16.0 0 8A Table 1 ‐ PI3 33XX Portfolio. Additional A versio ons available forr higher 18A current, c output voltages (Vout) of 1.5 to 1.9V, and Vout >1 15. The Zero Voltage Switcching (ZVS) arrchitecture also enables hiigh frequency operation wh hile minimizing switching losses and maaximizing efficiiency. The high switching frequency f operation reducess the size of the external filtering com mponents, improves powe er density, an nd enables ve ery fast dynam mic response to line and lo oad transientss. The PI33XX series sustain ns high switching frequencyy all the way up u to the rated input voltaage without saacrificing efficiiency and, with its 20ns minimum on‐tim me, supports laarge step down conversion ns up to 36Vin. Picor Corporation • picorpo ower.com 2 I C is a trademark of NXP Semiconductors H High efficiency up to 98% ZZVS‐Buck Topology W Wide input volttage range of 8 8V to 36V V Very‐Fast transsient response H High accuracy p pre‐trimmed output voltage U User adjustablee soft‐start & tracking PPower‐up into pre‐biased load (select versio ons) PParallel capablee with single w wire current shaaring Innput Over/Und der Voltage Lockout (OVLO/U UVLO) O Output Overvoltage Protectio on (OVP) O Over Temperatture Protection n (OTP) FFast and slow ccurrent limits ‐440°C to 125°C operating rangge (TJ) O Optional I2C fun nctionality & p programmabilitty: Vout margiining Fault reporrting Enable and d SYNCI pin polarity Phase delay (for interleavving multiple regulators)) App plications H High efficiency systems CComputing, Com mmunications, Industrial, A Automotive Equipment H High voltage baattery operatio on Packkage Inform mation 110mm x 14mm x 2.6mm LGA SiP PI33XX‐X0‐LGIZZ Family Datasheeet Rev 1.2 August 24, 22012 Page 1 of 39 Contentts Order Info ormation ............................................... 3 EN ABLE (EN) .................................................... 30 PI33XX Efficiency ................................................. 3 Sw witching Frequ uency Synchro onization ........... 30 Pin Descriiption .................................................... 4 Ouutput Voltage Trimming ............................... 30 Package Pin‐Out P .................................................. 4 Sofft‐Start ......................................................... 30 Absolute Maximum Raatings at 25°C C ................... 5 Re mote Sensingg .............................................. 31 PI3311‐X0 0 (1.0 VOUT) Electrical Chaaracteristics . 6 Ouutput Current Limit Protecttion .................... 31 Electriccal Specifications ................................... 6 Inpput Under‐Vo oltage Lockout ........................ 31 PI3311‐‐X0 Typical Ch haracteristicss ................... 8 Inpput Over Voltage Lockout ............................ 31 PI3312‐X0 0 (2.5 Vout) Electrical E Charracteristics . 10 0 Ouutput Over Vo oltage Protecttion .................... 31 Electriccal Specifications ................................. 10 0 Ovver Temperatu ure Protectio on........................ 31 PI3312‐‐X0 Typical Ch haracteristicss ................. 12 Pu lse Skip Modee (PSM) ................................... 31 PI3301‐X0 0 (3.3 Vout) Electrical E Charracteristics . 14 4 on ....................... 32 Va riable Frequeency Operatio Electriccal Specifications ................................. 14 4 Parrallel Operatiion ........................................... 32 PI3301‐‐X0 Typical Ch haracteristic ................... 16 I2C Bus (PI33XX‐‐20 and PI33X XX‐21 only) ........ 32 PI3302‐X0 0 (5.0Vout) Electrical Charaacteristics.. 18 8 Appli cation Descriiption ....................................... 33 Electriccal Specifications ................................. 18 8 Ouutput Voltage Programmin ng ........................ 33 PI3302‐‐X0 Typical Ch haracteristicss ................. 20 0 Sofft‐Start Adjusst and Trackin ng ....................... 34 PI3303‐X0 0 (12Vout) Ele ectrical Charaacteristics... 22 Indductor Pairingg............................................... 34 Electriccal Specifications ................................. 22 Inpput and Output Filter Conssiderations ......... 35 PI3303‐‐X0 Typical Ch haracteristicss ................. 24 4 Layouut Guidelines ................................................ 36 PI3305‐X0 0 (15 Vout) Electrical Charaacteristics .. 26 mmended PC Recom CB Footprint aand Stencil ......... 37 Electriccal Specifications ................................. 26 Packaage Drawingss ............................................... 38 PI3305‐‐X0 Typical Ch haracteristicss ................. 28 8 Warr anty ............................................................. 39 Functionaal Description ...................................... 30 0 Picor Corporation • picorpo ower.com PI33XX‐X0‐LGIZZ Family Datasheeet Rev 1.2 August 24, 22012 Page 2 of 39 Order In nformation Output Range R Set Range Iout Max PI3311‐00‐LGIZ 1.0V 1.00 to 1.4V 10A mm x 14mm 1223‐pin LGA 10m TRAY PI3312‐00‐LGIZ 2.5V 2..0V to 3.1V 10A mm x 14mm 1223‐pin LGA 10m TRAY PI3301‐00‐LGIZ 3.3V 2.3 2 to 4.1V 10A mm x 14mm 1223‐pin LGA 10m TRAY PI3302‐00‐LGIZ 5.0V 3.3 3 to 6.5V 10A mm x 14mm 1223‐pin LGA 10m TRAY PI3303‐00‐LGIZ 12V 6.5 to 13.0V 8A mm x 14mm 1223‐pin LGA 10m TRAY PI3305‐00‐LGIZ 15V 10 0.0 to 16.0V 8A mm x 14mm 1223‐pin LGA 10m TRAY Cool-P Power Packagee TTransport Meedia Higher Current C Versio ons* PI3311‐01‐LGIZ 1.0V 1.0 1 to 1.4V 18A mm x 14mm 1223‐pin LGA 10m TRAY PI3312‐01‐LGIZ 2.5V 2.0 2 to 3.1V 18A mm x 14mm 1223‐pin LGA 10m TRAY PI3301‐01‐LGIZ 3.3V 2.3 2 to 4.1V 18A mm x 14mm 1223‐pin LGA 10m TRAY 2 I C Functionality & Programmabillity* PI3311‐20‐LGIZ 1.0V 1.0 1 to 1.4V 10A mm x 14mm 1223‐pin LGA 10m TRAY PI3312‐20‐LGIZ 2.5V 2.0 2 to 3.1V 10A mm x 14mm 1223‐pin LGA 10m TRAY PI3301‐20‐LGIZ 3.3V 2.3 2 to 4.1V 10A mm x 14mm 1223‐pin LGA 10m TRAY PI3302‐20‐LGIZ 5.0V 3.30 to 6.5V 10A mm x 14mm 1223‐pin LGA 10m TRAY PI3303‐20‐LGIZ 12V 6.5 to 13.0V 8A mm x 14mm 1223‐pin LGA 10m TRAY PI3305‐20‐LGIZ 15V 10 0.0 to 16.0V 8A mm x 14mm 1223‐pin LGA 10m TRAY PI3311‐21‐LGIZ 1.0V 1.0 1 to 1.4V 18A mm x 14mm 1223‐pin LGA 10m TRAY PI3312‐21‐LGIZ 2.5V 2.0 2 to 3.1V 18A mm x 14mm 1223‐pin LGA 10m TRAY PI3301‐21‐LGIZ 3.3V 2.3 2 to 4.1V 18A mm x 14mm 1223‐pin LGA 10m TRAY *Please conntact Picor for avvailability PI33XX Efficiency Picor Corporation • picorpo ower.com PI33XX‐X0‐LGIZZ Family Datasheeet Rev 1.2 August 24, 22012 Page 3 of 39 Pin Desscription Name Number Description SGND Block 1 Signal ground:: Internal logic ground for EA, TR RK, SYNCI, SYNCO O, ADJ and I2C (o options) communication returns. SGND D and PGND are star connected w within the regullator package. PGND Block 2 Power ground: VIN and VOUT power returns VIN Block 3 Input voltage: and sense for UVLO, U OVLO and feed forward raamp VOUT Block 5 Output voltage e: and sense forr power switchess and feed‐forward ramp VS1 Block 4 Switching node: and ZVS sense for power swittches PGD A1 Parallel Good: Used for paralle el timing managgement intendedd for lead regulaator. EAO A2 Error amp output: External co onnection for addditional compennsation and current sharing. EN A3 Enable Input: Regulator enable control. Assertted high or left ffloating – regulaator enabled; Asserted low, regulator r outputt disabled. Polarrity is programm mable via I2C inteerface. REM A5 Remote Sense e: High side conn nection. Connecct to output reguulation point. ADJ B1 TRK C1 NC K3, A4 Adjust input: An A external resisstor may be con nected betweenn ADJ pin and SG GND or VOUT to trim the output volttage up or down n. Soft‐start and track input: An n external capaciitor may be connnected between n TRK pin and SG GND to decrease the rate of rise during soft‐start. No Connect: Leave L pins floating. Synchronizatio on output: Outp puts a low signal for ½ of the minnimum period fo or synchronizatio on of other converte ers. Synchronizatio on input: Synchrronize to the fallling edge of exteernal clock frequ uency. SYNCI is a high impedance diggital input node and a should alwaays be connectedd to SGND when n not in use. SYNCO K4 SYNCI K5 SDA D1 Data Line: Con nnect to SGND for f PI33XX‐10 annd ‐11. For use w with PI33XX‐20 aand ‐21 only. SCL E1 Clock Line: Con nnect to SGND for f PI33XX‐10 annd ‐11. For use w with PI33XX‐20 aand ‐21 only. ADR1 H1 Tri‐state Addre ess : No connectt for PI33XX‐10 aand ‐11. For usee with PI33XX‐200 and ‐21 only. ADR0 G1 Tri‐state Addre ess : No connectt for PI33XX‐10 aand ‐11. For usee with PI33XX‐200 and ‐21 only. e Pin‐Out Package Block 1: B2‐‐4, C2‐4, D2‐3 3, E2‐3, F1‐3, G2‐3, H22‐3, J1‐3, K1‐2 Block 2: A8‐‐10, B8‐10, C8‐‐10, D8‐10, E4‐‐10, F4‐‐10, G4‐10, H4 4‐10, J4‐10, K6‐‐10 4 Block 3: G12‐14, H12‐14, J12‐14, K12‐14 Block 4: A112‐14, B12‐14, C12‐14, D12‐1 14, E12‐14, Block 5: A66‐7, B6‐7, C6‐7,, D6‐7 123‐Lead LGA (10mm x 14mm)) Top view TJmax = 125 °C, θJA = 22 °C/W Picor Corporation • picorpo ower.com PI33XX‐X0‐LGIZZ Family Datasheeet Rev 1.2 August 24, 22012 Page 4 of 39 um Ratingss at 25°C Absolutte Maximu Note: All voltage nodess are referenceed to PGND VIN ‐0.7V to 36V V / 18A DC VS1 ‐0.7 to 36V, ‐‐4V for 5ns VOUT See rrelevant produ uct section SGND 100mA PGD, SYN NCO, SYNCI, EN, EAO, ADJ, TR RK, ADR1, ADR2 2, SCL, SDA ‐0.3V to 5 5.5V / 5mA Storage Temperature T ‐65°C C to 150°C Operatingg Junction Tem mperature ‐40°C C to 140°C Solderingg Temperature for 20 seconds 260°C ESD Ratin ng 2kV HBM VS1 V VIN Q2 Q1 1 Vout VOUT R4 REM Power Control R1 EAO VC CC ZVS Control + R3 ADJ 1V R2 SYNCO SYNCI PGD Mem mory EN I Interface TRK PGND 0Ω Figure 1: Sim mplified Block D Diagram 2 (I C piins SCL, SDA, ADR0, and ADR1 on nly active for PI333XX‐20 and PI333XX‐21 versionss) Picor Corporation • picorpo ower.com PI33XX‐X0‐LGIZZ Family Datasheeet Rev 1.2 August 24, 22012 Page 5 of 39 PI3311‐‐X0 (1.0 VO OUT) Electrical Charaacteristics Electrical Specification ns Unless otherwise specifie ed: ‐40C < TJ < 125C, Vin =2 24V, L1=120nH H Paramete er Symbol Min Efficiency Output Output Vo oltage Output Vo oltage Total Re egulation Output Vo oltage Range VOUT_DC VOUT_DC VOUT_DC 0.987 Typ Max Units 87.7 % 1.0 1.0 1.0 1.013 1.4 V V V Line Regulation ∆VOUT(∆VIN) 0.1 0.15 % Load Regu ulation ∆VOUT(∆IOUT) 0.1 0.15 % Output Vo oltage Ripple VOUT_AC 20 Continuou us Output Currrent Range Current Limit Input Current IOUT_DC IOUT_CL Input Currrent IIN_DC 476 mA Inrush Inp put Current At Soft Start IIN_SS 200 mA 0 10.2 mVp‐p 10 13 A A Input Currrent At Outputt Short (Fault Con ndition) Protection n UVLO Thre eshold UVLO Hyssteresis OVLO Threshold OVLO Hyssteresis VUVLO 7.08 VUVLO_HYS VOVLO VOVLO_HYS 37 UVLO/OVLO Fault Delayy Time tf_DLY 128 Cycles tf 500 20 135 ns % °C UVLO/OVLO Response Time T OVP Over‐Tem mperature Faultt Threshold Over‐Tem mperature Resttart Hysteresiss 300 mA 7.45 0.37 7.82 38.4 0.77 40 V V V V IIN_Short VOVP VOTP 130 140 VOTP_HYS 30 °C fS 380 kHz tFR_DLY 30 ms Co onditions Viin = 24V, TC = 2 25°C, Io out = 10 A 0 °C <TJ <70°C ‐4 40 °C <TJ <125°C @ 25°C, 12 2V<Vin<36V @ 25°C, 0..5A<Iout<10A Iout=5A, Cout=8x100μF, 200MHz BW Seee Iout vs. TA Cu urves Viin = 24V, TC = 2 25°C, Io out=10A Viin=24V, Iout=0 0A Ciin=4x4.7µF MLLCC N Number of thee sswitching frequ uency ccycles ++1% overdrive A Above VOUT Timing Switching Frequency Fault Resttart Delay Picor Corporation • picorpo ower.com PI33XX‐X0‐LGIZZ Family Datasheeet Viin ≥ 18V, Iout ≤ 8A (1)) Rev 1.2 August 24, 22012 Page 6 of 39 PI3311‐‐X0 Electriccal Specificcations (continu ued) Unless otherwise specifie ed: ‐40C < TJ < 125C, Vin =2 24V, Paramete er Input Pow wer Symbol Min Input Volttage VIN_DC 8 Input Volttage Slew Rate VIN_SR Input Quie escent Currentt IQ_VIN Typ p 24 Max 36 V 1 V/μs 2 22.5 Soft Start And Tracking Function TRK Active e Range (Nomiinal) TRK Offset Voltage / Disable Threshold d Charge Cu urrent (Soft – Start) S Discharge Current (Faultt) Soft‐Start Time Enable VTRK VTRK_OV ITRK ITRK_DIS tSS 0 20 ‐70 High Threshold Low Thresshold Threshold d Hysteresis Enable Pull‐Up Voltage Enable Pull‐Down Voltagge Source Cu urrent Sink Curre ent VEN_HI VEN_LO VEN_HYS VEN_PU VEN_PD IEN_SO IEN_SK 0.9 0.7 100 Synchroniization Frequen ncy Range ∆fSYNCI 50 SYNCI Thrreshold SYNCI Pro ogrammable Ph hase Shift Sync Out (SYNCO) VSYNCI ∆φSYNCI 40 ‐‐50 66.8 22.2 1 00.8 2200 2 0 ‐‐50 50 Units mA 1 60 ‐30 2.6 V mV µA mA ms Co onditions Diisabled En nabled CTTRK = 0 1.1 0.9 300 V V mV V V uA uA 110 % 0 ‐270 V ° 4.5 0 10 5.2 0.5 20 V V ns So ource 1mA. SSink 1mA. 2 20pF load 10 20 ns 2 20pF load Sync In (SYNCI) SYNCO Higgh SYNCO Low SYNCO Risse Time VSYNCO_HI VSYNCO_LO tSYNCO_RT SYNCO Fall Time tSYNCO_FT 22.5 W With respect to the seet switching frequency Note 1: Re efer to Switchin ng Frequency vs. v Iout graph Picor Corporation • picorpo ower.com PI33XX‐X0‐LGIZZ Family Datasheeet Rev 1.2 August 24, 22012 Page 7 of 39 PI3311‐‐X0 Typical Characteristics To otal Power Loss (including exxternal components) 100 95 90 85 80 75 70 65 60 55 50 2 1.5 Power Loss oss [W] Efficiency [%] Efficiencyy at 25°C 12Vin 24Vin 36Vin 1 12Vin 0.5 24Vin 0 0 1 2 3 4 5 6 Iout [A] 7 8 9 0 10 1 2 3 4 5 6 7 8 9 10 Iout [[A] 33110 01 ent Curve Ambient Temperature vs. Load Curre 331102 onse: 24V to 1.0V Traansient Respo 12 10 Load Current [A] 8 6 4 8V 24V V 36V V 2 0 75 85 95 9 105 115 Ambientt Temperature [⁰C C] 125 0 LFM, SiP Only 331103 3 Switching Frequency [kHz] Switchingg frequency vss load current 550 500 450 400 350 300 250 200 150 100 50 0 Loaad Step: 2A to 77A at 5A/us Coout = 8X 100 µF C Ceramic 331104 Ou utput ripple: V Vin =24V, Vout = 1.0V at 10A A 12Vin 24Vin 36Vin 1 2 3 4 5 6 LOAD [A] L1 = 120n nH Picor Corporation • picorpo ower.com 7 8 9 10 331105 5 Voout = 50mV/Divv 2.00us/Div Coout = 8X 100 µFF Ceramic PI33XX‐X0‐LGIZZ Family Datasheeet Rev 1.2 August 24, 22012 331106 Page 8 of 39 PI3311 1‐X0 Typica al Characte eristics (contin nued) V, Vout = 1.0V at 5A Output riipple: Vin =24V Vout = 50 0mV/Div 2.0us/Divv Cout = 8X X 100 µF Ceram mic Picor Corporation • picorpo ower.com Sh hort circuit testt 331 1107 Voout = 500mV/D Div =Ch2 Iinn = 500mA/Div = Ch4 ms tddelay_fault = 1m PI33XX‐X0‐LGIZZ Family Datasheeet Rev 1.2 August 24, 22012 331108 Page 9 of 39 PI3312‐‐X0 (2.5 Vo out) Electriical Characcteristics Electrical Specification ns Unless otherwise specifie ed: ‐40C < TJ < 125C, Vin = 24V, 2 L1=200 nH H Paramete er Symbol Min Efficiency Output Output Vo oltage Output Vo oltage Total Re egulation Output Vo oltage Range Line Regulation Load Regu ulation VOUT_DC VOUT_DC VOUT_DC Max Units 991.3 % 22.50 V V V % ∆VOUT(∆VIN) 22.50 22.5 00.1 2.535 3.1 0.15 ∆VOUT(∆IOUT) 00.1 0.15 Output Vo oltage Ripple VOUT_AC 28 Continuou us Output Currrent Range Current Limit Input Current IOUT_DC IOUT_CL Input Currrent IIN_DC 11.14 A Soft‐Start Current IIN_SS 2200 mA Input Currrent At Outputt Short (Fault Condition) Protection n UVLO Thre eshold UVLO Hyssteresis OVLO Threshold OVLO Hyssteresis UVLO/OVLO Fault Delayy Time UVLO/OVLO Response Time T OVP Thresshold Over‐Tem mperature Faullt Threshold Over‐Tem mperature Resttart Hysteresiss 2.465 2.0 TTyp 0 10 12 IIN_Short mA V V V V 7.08 7.82 VUVLO_HYS VOVLO VOVLO_HYS 77.45 00.37 37 338.4 00.77 40 tf_DLY 1128 Cycles tf VOVP VOTP VOTP_HYS 5500 20 1135 30 ns % °C °C fS 5500 kHz tFR_DLY 30 ms 130 140 0 °C <TJ <70°C ‐4 40 °C <TJ <125°C @ 25°C 12V<Vin n<36V @ 25°C, % 0..5A<Iout<10A out=5A, Io mVp‐p Co out=4x100μF, 20 0MHz BW A A 300 VUVLO Co onditions Viin = 24V, TC = 2 25°C, Io out = 10 A Viin = 24V, TC = 2 25°C, Io out=10A Viin=24V, Iout=0 0A Ciin=4x4.7µF MLLCC N Number of thee sswitching frequ uency ccycles ++1% overdrive A Above VOUT Timing Switching Frequency Fault Resttart Delay Picor Corporation • picorpo ower.com PI33XX‐X0‐LGIZZ Family Datasheeet Vin ≥ 18V, Iout ≤ 8A Rev 1.2 August 24, 22012 (1) Page 110 of 39 PI3312‐‐X0 Electriccal Specificcations (continu ued) Unless otherwise specifie ed: ‐40C < TJ < 125C, Vin =2 24V, Paramete er Input Pow wer Symbol Min Input Volttage VIN_DC 8 Input Volttage Slew Rate VIN_SR Input Quie escent Currentt IQ_VIN Typ p 24 Max 36 V 1 V/μs 2 22.5 Soft Start And Tracking Function TRK Active e Range (Nomiinal) TRK Offset Voltage / Disable Threshold d Charge Cu urrent (Soft –Sttart) Discharge Current (Faultt) Soft‐Start Time Enable VTRK VTRK_OV ITRK ITRK_DIS tSS 0 20 ‐70 Enable Higgh Threshold Enable Low Threshold Enable Threshold Hysterresis Enable Pull‐Up Voltage Enable Pull‐Down Voltagge Source Cu urrent Sink Curre ent VEN_HI VEN_LO VEN_HYS VEN_PU VEN_PD IEN_SO IEN_SK 0.9 0.7 100 Synchroniization Frequen ncy Range ∆fSYNCI 50 SYNCI Thrreshold SYNCI Pro ogrammable Ph hase Shift Sync Out (SYNCO) VSYNCI ∆φSYNCI 40 ‐‐50 66.8 22.2 1 00.8 2200 2 0 ‐‐50 50 Units mA 1 60 ‐30 2.6 V mV µA mA ms Co onditions Diisabled En nabled CTTRK = 0, 0A< Iou ut ≤ 8A 1.1 0.9 300 V V mV V V uA uA 110 % 0 270 V ° 4.5 0 10 5.2 0.5 20 V V ns So ource 1mA. SSink 1mA. 2 20pF load 10 20 ns 2 20pF load Sync In (SYNCI) SYNCO Higgh SYNCO Low SYNCO Risse Time VSYNCO_HI VSYNCO_LO tSYNCO_RT SYNCO Fall Time tSYNCO_FT Picor Corporation • picorpo ower.com 22.5 PI33XX‐X0‐LGIZZ Family Datasheeet W With respect to the seet switching frequency Rev 1.2 August 24, 22012 Page 111 of 39 PI3312‐‐X0 Typical Characteristics Efficiency at a 25°C Totaal Power Loss (including external components) 4.00 12V 24V 36V 3.00 Power Loss [W] [ ] Efficiency [%] 95% 90% 85% 80% 75% 70% 65% 60% 55% 50% 12V 24V 36V 0 1 2 3 4 5 6 7 8 9 10 2.00 1.00 0.00 0 1 2 3 4 LOAD [A] L1=200nH 5 6 LOAD [[A] 7 8 9 10 331202 331201 Transsient Responsee: 24V to 2.5V V and 5A to Loaad Step Ambient Temperature vss. Load Curren nt Curve 12 Output Current [A] 10 8 6 8V 24V 36V 4 2 0 75 85 95 105 11 15 Ambient Temperature [°C]] 125 0 LFM, SiP Only 331203 Switching frequency f vs. load current Vouut = 100mV/Divv. = Ch 1 Ioutt = 2A/Div. = Ch 4 2000us/Div. Ceramic Couut = 4 x 100µF C 331204 Outtput ripple: Viin = 24V and V Vout = 2.5V at 1 10A 600 Freq. [KHz] 500 400 300 12V 24V 36V 200 100 0 1 2 3 4 5 6 Load [A] L1 = 200nH Picor Corporation • picorpo ower.com 7 8 9 10 331205 Vouut = 20mV/Div. 2.0uus/Div. Couut = 4 x 100µF C Ceramic PI33XX‐X0‐LGIZZ Family Datasheeet Rev 1.2 August 24, 22012 331206 Page 112 of 39 PI3312‐‐X0 Typicall Characteristics (continu ued) Sho ort circuit test Output ripple: Vin = 24V V and Vout = 2.5V at 5A Vout = 20m mV/Div. 2.0us/Div. Cout = 4 x 100µF Ceramicc Picor Corporation • picorpo ower.com 331207 Vout = 1V/Div. = Ch h4 Iin = 5500mA/Div. = Ch1 tdelaay_fault = 1ms PI33XX‐X0‐LGIZZ Family Datasheeet Rev 1.2 August 24, 22012 331208 Page 113 of 39 PI3301‐‐X0 (3.3 Vo out) Electriical Characcteristics Electrical Specification ns Unless otherwise specifie ed: ‐40C < TJ < 125C, Vin =2 24V, L1=200 nH H Paramete er Symbol Min Efficiency Output Output Vo oltage Output Vo oltage Total Re egulation Output Vo oltage Range Line Regulation Load Regu ulation VOUT_DC VOUT_DC VOUT_DC Max Units 992.2 % 33.30 V V V % ∆VOUT(∆VIN) 33.30 33.3 00.10 3.36 4.1 0.15 ∆VOUT(∆IOUT) 00.10 0.15 Output Vo oltage Ripple VOUT_AC 337.5 Continuou us Output Currrent Range Current Limit Input Current IOUT_DC IOUT_CL Input Currrent IIN_DC 11.49 A Soft‐Start Input Current IIN_SS 2200 mA Input Currrent At Outputt Short (Fault Condition) Protection n UVLO Thre eshold UVLO Hyssteresis OVLO Threshold OVLO Hyssteresis UVLO/OVLO Fault Delayy Time UVLO/OVLO Response Time T OVP Over‐Tem mperature Faullt Threshold Over‐Tem mperature Resttart Hysteresiss 3.25 2.3 TTyp 0 10 12 IIN_Short VUVLO VUVLO_HYS VOVLO VOVLO_HYS mA V V V V 77.45 00.37 7.82 37 338.4 00.77 40.0 tf_DLY 1128 Cycles tf VOTP_HYS 5500 20 1135 30 ns % °C °C fS 6650 kHz tFR_DLY 30 ms VOVP VOTP 130 140 0 °C <TJ <70°C ‐4 40 °C <TJ <125°C @ 25°C 12V<Vin n<36V @ 25°C, % 0..5A<Iout<10A out=5A, Io mVp‐p Co out=4x100μF, 20 0MHz BW A A 300 7.08 Co onditions Viin = 24V, TC = 2 25°C, Io out = 10 A Viin = 24V, TC = 2 25°C, Io out=10A Viin=24V, Iout=0 0A Ciin=4x4.7µF MLLCC N Number of thee sswitching frequ uency ccycles ++1% overdrive A Above VOUT Timing Switching Frequency Fault Resttart Delay Picor Corporation • picorpo ower.com PI33XX‐X0‐LGIZZ Family Datasheeet Viin ≥ 12V, Iout ≤ 10A (1)) Rev 1.2 August 24, 22012 Page 114 of 39 PI3301‐‐X0 Electriccal Specificcations (continu ued) Unless otherwise specifie ed: ‐40C < TJ < 125C, Vin =2 24V, Paramete er Input Pow wer Symbol Min Input Volttage VIN_DC 8 Input Volttage Slew Rate VIN_SR Input Quie escent Currentt IQ_VIN Soft Start And Tracking Function TRK Active e Range (Nomiinal) TRK Offset Voltage / Disable Threshold d Charge Cu urrent (Soft –Sttart) Discharge Current (Faultt) Soft‐Start Time VTRK VTRK_OV ITRK ITRK_DIS Typ p 24 Max 36 V 1 V/μs 2 22.5 0 20 ‐70 Units mA Co onditions Diisabled En nabled 1 60 ‐30 V mV µA mA 22.2 2.6 ms 1 00.8 2200 2 0 ‐‐50 50 1.1 0.9 300 V V mV V V uA uA 110 % 0 270 V ° 4.5 0 10 5.2 0.5 20 V V ns So ource 1mA. SSink 1mA. 2 20pF load 10 20 ns 2 20pF load tSS 40 ‐‐50 66.8 No external CTRKK, 0A< Io out ≤ 8A Enable Enable Higgh Threshold Enable Low Threshold Enable Threshold Hysterresis Enable Pull‐Up Voltage Enable Pull‐Down Voltagge Source Cu urrent Sink Curre ent VEN_HI VEN_LO VEN_HYS VEN_PU VEN_PD IEN_SO IEN_SK 0.9 0.7 100 Synchroniization Frequen ncy Range ∆fSYNCI 50 SYNCI Thrreshold SYNCI Pro ogrammable Ph hase Shift Sync Out (SYNCO) VSYNCI ∆φSYNCI Sync In (SYNCI) SYNCO Higgh SYNCO Low SYNCO Risse Time VSYNCO_HI VSYNCO_LO tSYNCO_RT SYNCO Fall Time tSYNCO_FT Picor Corporation • picorpo ower.com 22.5 PI33XX‐X0‐LGIZZ Family Datasheeet W With respect to the seet switching frequency Rev 1.2 August 24, 22012 Page 115 of 39 PI3301‐‐X0 Typical Characteristic Efficiency at a 25°C Totaal Power Loss (in ncluding external components)) 100% 95% 90% 85% 80% 75% 70% 65% 60% 55% 50% 4.00 12V 24V 36V Power Loss (W) Efficiency [%] 3.00 12V 24 4V 36V 2.00 1.00 0.00 0 1 2 3 4 5 6 LOAD [A] 7 8 9 0 10 L1=200nH 1 2 3 4 5 6 LOAD (A) 7 8 9 10 330102 330101 nse: 24V to 3.3 3V Traansient Respon T vs. v Load Curren nt Curve Ambient Temperature 12 10 Output Current [A] 8 6 8V 24V 36V 4 2 0 75 85 95 105 115 1 C] Ambientt Temperature [°C 125 0 LFM, SiP P Package Only 330103 Loaad Step: 2A to 77A Couut = 4 x 100µF Ceramic 330104 Outtput ripple: Vin = 24V, Vout = 3.3V at 10A Switching frequency vs. load current 700 600 Frequency (KHz) 500 400 300 12V 24V 36V 200 100 0 1 2 3 4 5 6 Load (A) L1 = 200nH Picor Corporation • picorpo ower.com 7 8 9 10 330105 5 Vouut = 50mV/Div 2.0 us/Div Couut = 4 x 100µF Ceramic PI33XX‐X0‐LGIZZ Family Datasheeet Rev 1.2 August 24, 22012 330106 Page 116 of 39 PI3301‐‐X0 Typical Characte eristic (continued) Sho ort circuit test Output rip pple Vin = 24V,, Vout = 3.3V at a 5A Vout = 50m mV/Div 2.0us/Div Cout = 4 x 100µF Ceramic Picor Corporation • picorpo ower.com 330107 tdelaay_fault = 1ms PI33XX‐X0‐LGIZZ Family Datasheeet Rev 1.2 August 24, 22012 330108 Page 117 of 39 PI3302‐‐X0 (5.0Vout) Electriccal Characcteristics Electrical Specification ns Unless otherwise specifie ed: ‐40C < TJ < 125C, Vin =2 24V, L1=200nH H Paramete er Efficiencyy Symbol Min Efficiency Output Output Vo oltage Output Vo oltage Total Re egulation Output Vo oltage Range Line Regulation Load Regu ulation VOUT_DC Max Units 993.9 % 55.00 V V V % ∆VOUT(∆VINN) 5.00 5.0 0.1 5.07 6.5 0.15 ∆VOUT(∆IOUTT) 0.1 0.15 Output Vo oltage Ripple VOUT_AC 30 Continuou us Output Currrent Range Current Limit Input Current IOUT_DC IOUT_CL Input Currrent IIN_DC 22.23 A Inrush Inp put Current At Startup IIN_SS 100 mA Input Currrent At Outputt Short (Fault Condition) Protection n UVLO Thre eshold UVLO Hyssteresis OVLO Threshold OVLO Hyssteresis UVLO/OVLO Fault Delayy Time UVLO/OVLO Response Time T OVP Over‐Tem mperature Faultt Threshold Over‐Tem mperature Restaart Hysteresis 4.93 3.3 TTyp 0 10.2 111.2 IIN_Short 10 12.6 mA V V V V 7.08 7.82 VUVLO_HYS VOVLO VOVLO_HYS 77.45 00.37 37 338.4 00.77 40 tf_DLY 1128 Cycles tf VOTP_HYS 5500 20 1135 30 ns % °C °C fS 1.0 MHz tFR_DLY 30 ms VOVP VOTP 130 140 Viin = 24V, TC = 2 25°C, Io out=10A 0 °C <TJ <70°C ‐4 40 °C <TJ <125°C @ 25°C 12V<Vin n<36V @ 25°C, % 0..5A<Iout<10A out=5A, Io mVp‐p Co out=4x47μF20MHz BW W A A 300 VUVLO Co onditions Viin = 24V, TC = 2 25°C, Io out=10A Viin=24V, Iout=0 0A Ciin=4x4.7µF MLLCC N Number of thee sswitching frequ uency ccycles ++1% overdrive A Above VOUT Timing Switching Frequency Fault Resttart Delay Picor Corporation • picorpo ower.com PI33XX‐X0‐LGIZZ Family Datasheeet Viin ≥ 18V, Iout ≤ 10A (1)) Rev 1.2 August 24, 22012 Page 118 of 39 PI3302‐‐X0 Electriccal Specificcations (continu ued) Unless otherwise specifie ed: ‐40C < TJ < 125C, Vin =2 24V, Paramete er Input Pow wer Symbol Min TTyp Max Units Input Volttage VIN_DC 8 24 36 V Input Volttage Slew Rate VIN_SR 1 V/μs Input Quie escent Currentt IQ_VIN Soft Start And Tracking Function TRK Active e Range (Nomiinal) TRK Offset Voltage / Disable Threshold d Charge Cu urrent (Soft –Sttart) Discharge Current (Faultt) Soft‐Start Time VTRK VTRK_OV ITRK ITRK_DIS 2 22.5 0 20 ‐70 tSS mA 1 60 ‐30 V mV µA mA 22.2 2.6 ms 1 00.8 2200 2 0 ‐‐50 50 1.1 0.9 300 V V mV V V uA uA 110 % 40 ‐‐50 66.8 Conditionss Diisabled En nabled No external CTRKK, 0A< Io out ≤ 8A Enable Enable Higgh Threshold Enable Low Threshold Enable Threshold Hysterresis Enable Pull‐Up Voltage Enable Pull‐Down Voltagge Source Cu urrent Sink Curre ent Sync In (SYNCI) VEN_HI VEN_LO VEN_HYS VEN_PU VEN_PD IEN_SO IEN_SK 0.9 0.7 100 Synchroniization Frequen ncy Range ∆fSYNCI 50 SYNCI Thrreshold SYNCI Pro ogrammable Ph hase Shift Sync Out (SYNCO) VSYNCI ∆φSYNCI 0 270 V ° 4.5 0 10 5.2 0.5 20 V V ns So ource 1mA. SSink 1mA. 2 20pF load 10 20 ns 2 20pF load SYNCO Higgh SYNCO Low SYNCO Risse Time VSYNCO_HI VSYNCO_LO tSYNCO_RT SYNCO Fall Time tSYNCO_FT Picor Corporation • picorpo ower.com 22.5 PI33XX‐X0‐LGIZZ Family Datasheeet W With respect to the seet switching frequency Rev 1.2 August 24, 22012 Page 119 of 39 PI3302‐‐X0 Typical Characteristics Efficiency at a 25°C Totaal Power Loss (inncluding externa al components) 100 4.5 95 4 90 85 Power Loss [W] [ ] 80 Efficiency [%] PL (12V) PL (24V) PL (36V) 3.5 75 70 65 12Vin n 24Vin n 36Vin n 60 55 3 2.5 2 1.5 1 0.5 50 0 1 2 3 4 5 6 7 8 9 0 10 0 Iout [A] L1=200nH 1 2 3 4 5 6 Iout [A A] 7 8 9 10 330202 330201 Trannsient Responsee: 24V to 5V Ambient Temperature T vs. v Load Curren nt Curve 12 Output Current [A] 10 8 6 10V 24V 36V 4 2 0 50 60 70 80 90 100 110 1 Ambient Temperature [°C]] 120 0 LFM, SiP Only 330203 Switching frequency vs. load current Loadd Step: 2A to 7A A Cou t = 4 X 47uF Cerramic 5A/uus 3300204 Outtput ripple: Vin n = 24V, Vout = 5.0V at 10A 1.2 Frequency [MHz] 1 0.8 0.6 12V 24V 36V 0.4 0.2 0 1 2 3 4 5 6 Load [A] L1=200nH 7 8 9 10 330205 Vouut = 50mV/Div 1.0uus/Div Cou t = 4 X 47uF Cerramic Picor Corporation • picorpo ower.com PI33XX‐X0‐LGIZZ Family Datasheeet Rev 1.2 August 24, 22012 330206 Page 220 of 39 PI3302‐‐X0 Typical Characte eristic (continued) Output rip pple Vin = 24V,, Vout = 5.0V at a 5A Vout = 50m mV/Div 1.0us/Div 4 Ceramic Cout = 4 X 47uF Picor Corporation • picorpo ower.com Sho ort circuit test 330207 tdelaay_fault = 1ms PI33XX‐X0‐LGIZZ Family Datasheeet Rev 1.2 August 24, 22012 330208 Page 221 of 39 PI3303‐‐X0 (12Vou ut) Electriccal Charactteristics Electrical Specification ns Unless otherwise specifie ed: ‐40C < TJ < 125C, Vin =2 24V, L1=230nH H Paramete er Symbol Min Efficiency Output Output Vo oltage Output Vo oltage Total Re egulation Output Vo oltage Range Line Regulation Load Regu ulation VOUT_DC VOUT_DC VOUT_DC Max Units 996.5 % 112.0 V V V % ∆VOUT(∆VIN) 112.0 12 00.1 12.18 13.0 0.15 ∆VOUT(∆IOUT) 00.1 0.15 Output Vo oltage Ripple VOUT_AC 60 Continuou us Output Currrent Range Current Limit Input Current IOUT_DC IOUT_CL Input Currrent IIN_DC 44.15 A Inrush Inp put Current At Startup IIN_SS 2200 mA Input Currrent At Outputt Short (Fault Condition) Protection n UVLO Thre eshold UVLO Hyssteresis OVLO Threshold OVLO Hyssteresis UVLO/OVLO Fault Delayy Time UVLO/OVLO Response Time T OVP Over‐Tem mperature Faultt Threshold Over‐Tem mperature Restaart Hysteresis 11.82 6.5 TTyp 0 8.1 8 10 IIN_Short mA V V V V 13.57 15.0 VUVLO_HYS VOVLO VOVLO_HYS 144.29 00.37 37 338.4 00.77 40 tf_DLY 1128 Cycles tf VOVP VOTP VOTP_HYS 5500 20 1135 30 ns % °C °C fS 1.4 MHz tFR_DLY 30 ms 130 140 0 °C <TJ <70°C ‐4 40 °C <TJ <125°C @ 25°C 16V<Vin n<36V @ 25°C, % 0..5A<Iout<8A out=4A, Io mVp‐p Co out=4x22μF, 20MHz BW W A A 300 VUVLO Co onditions Viin = 24V, TC = 2 25°C, Io out=8A Viin = 24V, TC = 2 25°C, Io out=8A Viin=24V, Iout=0 0A Ciin=4x4.7µF MLLCC N Number of thee sswitching frequ uency ccycles ++1% overdrive A Above VOUT Timing Switching Frequency Fault Resttart Delay Picor Corporation • picorpo ower.com PI33XX‐X0‐LGIZZ Family Datasheeet Viin ≥ 18V, Iout ≤ 8A (1)) Rev 1.2 August 24, 22012 Page 222 of 39 PI3303‐‐X0 Electriccal Specificcations (continu ued) Unless otherwise specifie ed: ‐40C < TJ < 125C, Vin =2 24V, Paramete er Input Pow wer Symbol Input Volttage VIN_DC Input Volttage Slew Rate VIN_SR Input Quie escent Currentt IQ_VIN Soft Start And Tracking Function TRK Active e Range (Nomiinal) TRK Offset Voltage / Disable Threshold d Charge Cu urrent (Soft –Sttart) Discharge Current (Faultt) Soft‐Start Time VTRK VTRK_OV ITRK ITRK_DIS Min 15.5 Typ p 24 Max 36 V 1 V/μs 2 22.5 0 20 ‐70 tSS Units mA 1 60 ‐30 V mV µA mA 22.2 2.6 ms 1 00.8 2200 2 0 ‐‐50 50 1.1 0.9 300 V V mV V V uA uA 110 % 40 ‐‐50 66.8 Co onditions Diisabled En nabled No external CTRK, 0A< Io out ≤ 8A Enable Enable Higgh Threshold Enable Low Threshold Enable Threshold Hysterresis Enable Pull‐Up Voltage Enable Pull‐Down Voltagge Source Cu urrent Sink Curre ent VEN_HI VEN_LO VEN_HYS VEN_PU VEN_PD IEN_SO IEN_SK 0.9 0.7 100 Synchroniization Frequen ncy Range ∆fSYNCI 50 SYNCI Thrreshold SYNCI Pro ogrammable Ph hase Shift Sync Out (SYNCO) VSYNCI ∆φSYNCI 0 270 V ° 4.5 0 10 5.2 0.5 20 V V ns So ource 1mA. SSink 1mA. 2 20pF load 10 20 ns 2 20pF load Sync In (SYNCI) SYNCO Higgh SYNCO Low SYNCO Risse Time VSYNCO_HI VSYNCO_LO tSYNCO_RT SYNCO Fall Time tSYNCO_FT Picor Corporation • picorpo ower.com 22.5 PI33XX‐X0‐LGIZZ Family Datasheeet W With respect to the seet switching frequency Rev 1.2 August 24, 22012 Page 223 of 39 PI3303‐‐X0 Typical Characteristics Efficiency at 25° Totaal Power Loss (inncluding externa al components) 100 95 90 Power Loss [W] [ ] 85 Efficiency [%] 80 75 70 18Vin, 12Vo out 24Vin, 12Vo out 36Vin, 12Vo out 65 60 55 50 0 1 2 3 4 Iou ut [A] 5 6 7 8 L1=230nH 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 24Vin 12Vout 36Vin, 12Vout 0 1 2 3 4 Iout [A A] 5 330301 6 7 8 330302 Trannsient Responsee: 24V to 12V T vs. Load Curren nt Curve Ambient Temperature 10 9 8 Load Current [A] 7 6 5 4 16V 24V 36V 3 2 1 0 60 50 70 Loa d Step: 2A to 66A, 5A/us Ceramic Couut = 4 X 22uF C 80 90 100 11 10 120 nt Temperature [°°C] Ambien O LFM SiP P Only 330304 330303 Switching frrequency vs. Loa ad current 8A A Output Ripplle: Vin = 24V, V Vout = 12V at 8 8A 1.6 Frequency [MHz] 1.4 1.2 1 0.8 0.6 16V 24V 36V 0.4 0.2 0 1 2 3 4 5 Load [A] 6 7 8 330305 Picor Corporation • picorpo ower.com Vouut = 50mV/Div 1.0uus/Div Couut = 4 X 22uF C Ceramic PI33XX‐X0‐LGIZZ Family Datasheeet Rev 1.2 August 24, 22012 330306 Page 224 of 39 PI3303‐‐X0 Typical Characteristics (continu ued) 4A Outputt Ripple Vout = 50m mV/Div 1.0us/Div Cout = 4 X 22uF Ceramic Picor Corporation • picorpo ower.com Sho ort circuit test 330307 tdelaay_fault = 1ms PI33XX‐X0‐LGIZZ Family Datasheeet Rev 1.2 August 24, 22012 330308 Page 225 of 39 PI3305‐‐X0 (15 Vout) Electriccal Characcteristics Electrical Specification ns Unless otherwise specifie ed: ‐40C < TJ < 125C, Vin =2 24V, L1=230nH H Paramete er Symbol Min Efficiency Output Output Vo oltage Output Vo oltage Total Re egulation Output Vo oltage Range VOUT_DC 14.78 10.0 TTyp Max Units 997.2 % 115.0 V V V 115.0 15 15.23 16 ∆VOUT(∆VIN) 00.1 0.15 Load Regu ulation ∆VOUT(∆IOUT) 00.1 0.15 Output Vo oltage Ripple VOUT_AC 60 Continuou us Output Currrent Range Current Limit Input Current IOUT_DC IOUT_CL Input Currrent IIN_DC 44.12 A Inrush Inp put Current At Startup IIN_SS 2200 mA Input Currrent At Outputt Short (Fault Condition) Protection n UVLO Thre eshold UVLO Hyssteresis OVLO Threshold OVLO Hyssteresis UVLO/OVLO Fault Delayy Time UVLO/OVLO Response Time T OVP Over‐Tem mperature Faultt Threshold Over‐Tem mperature Restaart Hysteresis 8 10 IIN_Short % 300 mA V V V V VUVLO 16.38 18.1 VUVLO_HYS VOVLO VOVLO_HYS 117.2 00.37 37 338.4 00.77 40 tf_DLY 1128 Cycles tf VOTP_HYS 5500 20 1135 30 ns % °C °C fS 1.5 MHz tFR_DLY 30 ms VOVP VOTP 130 140 10 0 °C <TJ <70°C ‐4 40 °C <TJ <125°C @ 25°C 18 8.5V<Vin<36V @ 25°C, 0.5A<Io out< % 8A A out=4A, Io mVp‐p Co out=4x22μF, 20 0MHz BW A A Line Regulation 0 8.1 Co onditions Viin = 24V, TC = 2 25°C, Io out = 10 A Viin = 24V, TC = 2 25°C, Io out=8A Viin=24V, Iout=0 0A Ciin=4x4.7µF MLLCC N Number of thee sswitching frequ uency ccycles ++1% overdrive A Above Vout Timing Switching Frequency Fault Resttart Delay Picor Corporation • picorpo ower.com PI33XX‐X0‐LGIZZ Family Datasheeet Viin ≥ 18.1V, Iout ≤ 8A (1)) Rev 1.2 August 24, 22012 Page 226 of 39 PI3305‐‐X0 Electriccal Specificcations (continu ued) Unless otherwise specifie ed: ‐40C < TJ < 125C, Vin =2 24V, Paramete Min er Symbol Input Pow wer TTyp Max Units Input Volttage VIN_DC 24 36 V Input Volttage Slew Rate VIN_SR 1 V/μs Input Quie escent Currentt IQ_VIN Soft Start And Tracking Function TRK Active e Range (Nomiinal) TRK Offset Voltage / Disable Threshold d Charge Cu urrent (Soft –Sttart) Discharge Current (Faultt) Soft‐Start Time VTRK VTRK_OV ITRK ITRK_DIS 18.6 2 22.5 0 20 ‐70 mA Conditionss Diisabled En nabled 1 60 ‐30 V mV µA mA 22.2 2.6 ms 1 00.8 2200 2 0 ‐‐50 50 1.1 0.9 300 V V mV V V uA uA 110 % 0 270 V ° 4.5 0 10 5.2 0.5 20 V V ns So ource 1mA. SSink 1mA. 2 20pF load 10 20 ns 2 20pF load tSS 40 ‐‐50 66.8 No external CTRK, 0A< Io out ≤ 8A Enable Enable Higgh Threshold Enable Low Threshold Enable Threshold Hysterresis Enable Pull‐Up Voltage Enable Pull‐Down Voltagge Source Cu urrent Sink Curre ent VEN_HI VEN_LO VEN_HYS VEN_PU VEN_PD IEN_SO IEN_SK 0.9 0.7 100 Synchroniization Frequen ncy Range ∆fSYNCI 50 SYNCI Thrreshold SYNCI Pro ogrammable Ph hase Shift Sync Out (SYNCO) VSYNCI ∆φSYNCI Sync In (SYNCI) SYNCO Higgh SYNCO Low SYNCO Risse Time VSYNCO_HI VSYNCO_LO tSYNCO_RT SYNCO Fall Time tSYNCO_FT Picor Corporation • picorpo ower.com 22.5 PI33XX‐X0‐LGIZZ Family Datasheeet W With respect to the seet switching frequency Rev 1.2 August 24, 22012 Page 227 of 39 PI3305‐‐X0 Typical Characteristics Efficiency at 25°C Totaal Power Loss (inncluding externa al components) 100 5.0 4.0 Power Loss [W] 90 Efficiency [%] 18.6V 24V 36V 80 70 18.6V 24V 36V 60 3.0 2.0 1.0 0.0 50 0 1 2 3 4 5 LOAD [A] 6 7 L1=230nH 0 8 1 2 3 4 LOAD [A] 5 6 7 8 330502 330501 1 Trannsient Responsee: 24 to 15V T vs. Load Curren nt Curve Ambient Temperature 10 9 8 Output Current [A] 7 6 5 4 3 18.6V 2 24V 1 36V 0 50 60 70 80 0 90 100 110 Ambie ent Temperature [°C] [ 120 O LFM, SiP P Only 330503 3 Loadd Step: 2A to 6A A 5A/uus Couut = 4x22µF Ceraamic 330504 n = 24V, Vout = 15V at 8A Outtput ripple: Vin Switching frequency f vs. load current 1.6 Frequency (MHz) 1.4 1.2 1 0.8 0.6 18.6V 24V 36V 0.4 0.2 0 1 2 3 4 5 Load (A) 6 7 8 330505 Picor Corporation • picorpo ower.com Vouut = 100mV/Divv 1uss/Div Couut = 4x22µF Ceramic PI33XX‐X0‐LGIZZ Family Datasheeet Rev 1.2 August 24, 22012 330506 Page 228 of 39 PI3305‐‐X0 Typical Characteristics (continu ued) Sho ort circuit test Output rip pple: Vin = 24V V, Vout = 15V at a 4A Vout = 100 0mV/Div 1us/Div 22µF Ceramic Cout = 4x2 Picor Corporation • picorpo ower.com 330508 330507 PI33XX‐X0‐LGIZZ Family Datasheeet Rev 1.2 August 24, 22012 Page 229 of 39 Functio onal Description The PI33XX X is a family of o highly integrated ZVS‐Bucck regulators. The PI33XX has a set outputt voltage that is i trimmable within a pre escribed range e. Performancce and maxim mum output cu urrent are characterized with a specific external e powerr inductor (see Table 5). Figurre 2 ‐ ZVS‐Buck with required co omponents For basic operation, o Figure 2 shows the e connections and compo onents require ed. No addition nal design or settings are required. ENABLE (EEN) EN is the enable e pin of the converterr. The EN Pin is i referenced d to SGND and d permits the user u to turn the converter on or off. The T EN default polarity is a positive loggic assertion. If the EN pin iss left floating or o asserted high, the converter outpu ut is enabled d. Pulling EN pin below 0.8 Vdc with re espect to SGND will disable e the regulatorr output. The EN inp put polarity can n be programm med (PI33XX‐20 and PI33X XX‐21 versions only) via the e I2C data buss. When the EN pin polarityy is programm med for negativve logic asserrtion; and if th he EN pin is le eft floating, the regulator output o is enab bled. Pulling the EN pin abovve 1.0 Vdc with w respect to SGND, will w disable the regulator output. o Switchingg Frequency Synchronizati S ion The SYNCI input allows the user to synchronize s the controller switching freq quency by an external clocck referenced The external clock can d to SGND. synchronizze the unit bettween 50% an nd 110% of the preset switching freque ency (fS). For PI33XX‐20 and PI33XX‐21 versions only, the phase delay can be b 2 programmed via I C bus with w respect to o the clock Picor Corporation • picorpo ower.com applieed at SYNCI pin. Phase delay allows P PI33XX regulaators to be paralleled and operate in an interleeaving mode. The PPI33XX default for SYNCI is tto sync with reespect to thee falling edge o of the applied clock providing 180° phasee shift from SYNCO. This allows for the parall eling of two PPI33XX devicees without thee need for fuurther user pro ogramming orr external syncc clock circuittry. The user can change th he SYNCI polarity to sync w with the extern nal clock rising edge. Whenn using the in nternal oscillattor, the SYNC CO pin providdes a 5V clockk that can be used to sync other regulaators. Thereforre, one PI33XX X can act as the lead regulaator and havee additional PI33XXs running in parall el and interleaaved. Outp put Voltage Trrimming The PPI33XX output voltage can b be trimmed up p from the p reset output b by connecting a resistor from ADJ pin too SGND and can be trimmed down by conn necting a resisstor from ADJ pin to VOUT. The Table 2 d defines the vooltage ranges ffor the PI33XX family. Device PPI3311‐X0‐LGIZ PPI3312‐X0‐LGIZ PPI3301‐X0‐LGIZ PPI3302‐X0‐LGIZ PPI3303‐X0‐LGIZ PPI3305‐X0‐LGIZ Output Voltage Set 1.0V 2.5V 3.3V 5.0V 12V 15V Range 1.00 to 1.4 2.0 to 3.1 2.3 to 4.1 3.3 to 6.5 6.5 to 13.0 10.0 to 16.0 Table 2 ‐ PI33XX fam mily output volta age ranges. Add ditional versionns available for output voltagess (Vout) of 1.5 tto 1.9V and Voout >15V. Soft‐SStart The P I33XX includess an internal so oft‐start capaccitor to ramp the output voltage in 2m ms from 0V tto full outpuut voltage. Co onnecting an external cap pacitor o SGND will in from the TRK pin to ncrease the sttart‐up ramp period. See, ““Soft Start Adju ustment and TTrack,” in th e Applicationns Description section for more detail s. PI33XX‐X0‐LGIZZ Family Datasheeet Rev 1.2 August 24, 22012 Page 330 of 39 Remote Sensing S Inputt Over Voltagge Lockout An internaal 100Ω resisto or is connected d between REM M pin and VOUT V pin to provide p regulaation when the REM is leftt open. With REM R open, the e converter wiill regulate 100mV above itts set point. Connect C REM to the desired d reference no ode to be regulated. If VIN exceeds the in nput Over Volttage Lockout (OVLO) threshhold (VOVLO), w while the contrroller is runnin ng, the PI33XXX will complete the curreent cycle and d stop switchhing. If VIN recovers within 128 swiitching cycless, the PI33XXX will resume normal operration. Otherrwise, the systtem will enterr a low powerr state and ssets an OVLO fault. The ssystem will reesume operaation when thee input voltagee falls below 9 98% of the O VLO threshold d and after the Fault Restart Delay. The O OVLO fault is sstored in a Fau ult Register an nd can be reead and cleaared (PI33XX‐‐20 and PI33 3XX‐21 versioons only) via I2C data bus. Output Cu urrent Limit Protection P PI33XX haas two metho ods implementted to protecct from outpu ut short or ove er current cond dition. Slow Curre ent Limit prottection: preve ents the outpu ut load from m sourcing current high her than the regulator’ss maximum rated current. If the outpu ut current exceeds the Currrent Limit (IOUTT_CL) for 1024uss, a slow currrent limit faultt is initiated an nd the regulato or is shutdow wn which elim minates outputt current flow w. After Faultt Restart Delayy (tFR_DLY), a so oft‐start cycle is i initiated. This restart cycle will be repeated indefinitelyy until the exce essive load is removed. Fast Curre ent Limit prottection: PI33XX X monitors the regulator inductor i curre ent pulse‐by‐pu ulse to preven nt the outputt from supplyin ng very high current due to a sudden low w impedance short. If the re egulator sense es a high ind ductor current pulse, it will initiate a fault and stop switching until Fault Restart Delay ends and then initiatte a soft‐start cycle. c Both the Fast F and Slow current c limit faaults are stored in a Faultt Register and d can be reaad and cleared (PI33XX‐20 0 and PI33XX‐2 21 versions on nly) via I2C datta bus. Input Und der‐Voltage Lockout L If VIN fallss below the input Under Voltage V Lockou ut (UVLO) thrreshold, but re emains high en nough to powe er the internaal bias supply, the PI33XX wiill complete the current cyycle and stop switching. If VIN recoverrs within 128 8 switching cycles, the PI33XX will resume normal op peration. If this time limit iss exceeded, the system will enter a low w power state e and initiate a fault. The system s will resstart once the input voltage is i reestablish hed and after the Fault Resstart Delay. A UVLO fault is stored in a Fault Registter and can be b read and cleared c (PI33X XX‐20 and PI33 3XX‐21 version ns only) via I2 2C data bus. Picor Corporation • picorpo ower.com Outp put Over Voltaage Protectio on The PPI33XX familyy is equipped with outputt Over Voltagge Protection (OVP) to preveent damage to o input voltagge sensitive devices. If the output vvoltage exceeeds 20% of its set regulated value, the reggulator will coomplete the ccurrent cycle, stop switchin ng and issue an OVP fault. The system w will resume opeeration once the output voltage fallss below the OVP threshhold and afteer Fault Restarrt Delay. Thee OVP fault iis stored in a FFault Register aand can be reaad and cleareed (PI33XX‐20 and PI33XX‐2 21 versions only) via 2 I C daata bus. Over Temperaturee Protection The i nternal packaage temperatu ure is monitorred to preveent system co omponents frrom reaching their therm mal maximum m. If the Over Tempeerature Protecction Thresho old (OTP) is exceeded (VOTPP), the regulaator will comp plete the current switching cycle, enter a low powerr mode, set a fault flag, an nd will soft‐sttart when thee internal temp perature falls below Over‐TTemperature Restart Hysteeresis (VOTP_HYSS). The OTP faault is stored iin a Fault Regisster and can be read and c leared (PI33XXX‐20 and PI33X XX‐21 versionss only) via I2CC data bus. Pulsee Skip Mode ((PSM) PI33XXX features a PPSM to achievve high efficiency at light lloads. The reggulators are setup to skip pu ulses if EAO ffalls below a PSM thresho old. Depending on condittions and com mponent values, this may result in singlee pulses or sevveral consecuttive pulses folllowed PI33XX‐X0‐LGIZZ Family Datasheeet Rev 1.2 August 24, 22012 Page 331 of 39 by skippe ed pulses. Skipping S cycle es significantlly reduces gaate drive pow wer and impro oves light load efficiency. The regulatorr will leave PSM M once the EAO O rises above e the Skip Mod de threshold. Variable Frequency F Op peration Each PI33X XX is preprogrrammed to a base operatin ng frequency,, with respect to the power stage inducto or (see Table 5), to operate e at peak efficie ency across line and load variations. At low line and high load application ns, the base frequency will w stretch to accommod date these exttreme operatin ng ranges. By B stretching the frequen ncy, the ZVSS operation is preserved throughout the t total inpu ut line voltagge range therrefore maintain ning optimum efficiency. Parallel Operation O Paralleling multiple PI33 3XX modules can c be used to increase the t output cu urrent capability of a single power rail and reduce ou utput voltage ripple. r phasee with each otther reducing output ripple (refer to Sw itching Frequeency Synchroniization). To pr ovide synchro onization betw ween regulators over the e ntire operatio onal frequencyy range, the P Parallel Good (PGD) pin m must be conn nected to thee lead regulaator’s SYNCI pin and a 2.5kΩ Ω Resistor, R1,, must be p laced betweeen SYNCO retturn and thee lead regulaator’s SYNCI p pin, as shown in Figure 3. In this configguration, at syystem soft‐starrt, the PGD pin n pulls SYNCII low forcing tthe lead regulaator to initialize the open‐‐loop startup p synchronizaation. Oncee the nd the regulaators reach reggulation, SYNC CI is released an system m is now synchronized in a closed d‐loop configguration which h allows the system to adju ust, on the flyy, when any off the individual regulators beegin to enter variable frequ uency mode in the loop. Multi‐‐phasing threee regulators is possible (PI33 3XX‐20 and PPI33XX‐21 only) with no change to the basic singlee‐phase design n. For more information about how tto program phase delays w within the regu ulator, pleasee refer to Picor applicatio on note PI33 3XX‐2X Multi‐‐Phase Design Procedure. I2C Buus (PI33XX‐220 and PI33XXX‐21 only) PI33XXX‐20 and PI33XX‐21 provvide an I2C digital interfaace that enablles the user to program the EEN pin polariity (from high h to low asserrtion) and swiitching frequeency synchronization phase/delay. Thesse are one tiime programm mable options tto the device. Figure 3 ‐ PI33X XX parallel opera ation By conneccting the EAO pins and SGN ND pins of each module to ogether the units u will share the curren nt equally. When W the TR RK pins of each e unit arre connected together, the e units will traack each othe er during sofft‐start and all unit EN pin ns have to be released to allow the units u to start (See Figure 3). Also, any fault f event in any a regulator will disable the other regu ulators. The tw wo regulators will be out of o Picor Corporation • picorpo ower.com Also, tthe PI33XX‐200 and PI33XX‐2 21 allow for dyynamic during Vout margining vvia I2C that is useful d develoopment (settin ngs stored in vvolatile memorry only and nnot retained by the device). The PI33XX‐2 20 and PI33XXX‐21 also havve the option for extended d fault telem metry: Fault registry list: Over temperature protecction Fast/Slow ccurrent limit Output volttage high Input overvvoltage Input undeervoltage PI33XX‐X0‐LGIZZ Family Datasheeet Rev 1.2 August 24, 22012 Page 332 of 39 For more information about a how to utilize the I2C interface please refer to Picor app plication note e 2 PI33XX‐2X I C Interface Guide. G Application Descrription R1, R R2, R3 and R4 are all internal 1.0 % resisto ors and R_low w and R_high h are external resistors for which the ddesigner can aadd to modifyy VOUT to a d desired outp ut. The in nternal resisto or value for each regullator is listed b below in Table 4. Output Vo oltage Progra amming Device The PI33XX family of Buck Regulatorrs provides sixx common output o voltagess: 1.0V, 2.5V, 3.3V, 3 5.0V, 12V V and 15V. A post‐packagge trim step iss implemented d to offset any resistor divider network errors e ensuringg maximum output accuracy. With a single resistorr connected from the ADJJ pin to SGND or REM, each h device’s output can be varied above or below the e nominal set s voltage (w with the exce eption of the e PI3311‐X0 which can on nly be above the set voltage e of 1V). Device PII3311‐X0‐LGIZ PII3312‐X0‐LGIZ PII3301‐X0‐LGIZ PII3302‐X0‐LGIZ PII3303‐X0‐LGIZ PII3305‐X0‐LGIZ Output Vo oltage Set Range R 1.0V 2.5V 3.3V 5.0V 12V 15V 1.0 00 to 1.4 2.0 to 3.1 2.3 to 4.1 3.3 to 6.5 6.5 5 to 13.0 10.0 to 16.0 PI33311‐X0‐LGIZ PI33312‐X0‐LGIZ PI33301‐X0‐LGIZ PI33302‐X0‐LGIZ PI33303‐X0‐LGIZ PI33305‐X0‐LGIZ R1 R2 R3 R R4 1k 1.5k 2.61k 4.53k 11.0k 14.0k Open n 1.0kk 1.13k 1.13k 1.0kk 1.0kk 0 2.0k 3.0k 3.0k 3.0k 3.0k 1100 1100 1100 1100 1100 1100 Table 4 ‐ PII33XX Internal d divider values By cchoosing an o output voltagee value withiin the rangees stated in Table 3, VO OUT can simp ply be adjussted up or dow wn by selecting the proper R R_high or R R_low value, respectivelyy. The folllowing equaations can be u used to calculatte R_high and R_low valuees: 1 1 1 1 Table e 3 ‐ PI33XX fam mily output voltag ge ranges 2 The remotte pin (REM) should s always be connected d to the VOUT pin, if not used, to prevvent an outputt voltage offfset. Figure 4 shows s the inte ernal feedbackk voltage divvider network. 1 1 1 1 1 3 1 2 2 3. If, foor example, a 6.0V output is needed, thee user shouuld choose thee proper regu ulator from Taable 3. For tthis example, we will selecct the PI3302 (5.0V) and uuse Equation ((1) to calculatee R_high to inccrease the PPI3302’s output. From Taable 4, the reesistor‐ divid er network values for the PI3302 are: R1=44.53Ωk, R2=1.113kΩ, and R3 = 3.0kΩ. Insserting thesee values in to Equation (1), R_high is calculated as fo llows: 1.57 1 6.0 1 4 4.53 1 1.1 13 3.0 . Figure 4 ‐ Internal resistor r divider network n The value calculaated is ideal and may not be availaable for purch hase; therefore, select a staandard Picor Corporation • picorpo ower.com PI33XX‐X0‐LGIZZ Family Datasheeet Rev 1.2 August 24, 22012 Page 333 of 39 1% value close c to the value calculated. A 1.56kΩ,, 1%, resisto or is a standarrd value. Checck your resultss by using th he voltage divid der equation. Master VO OUT Soft‐Startt Adjust and Tracking T The TRK pin offers a means to increase the e regulator’ss soft‐start tim me or to track with w additional regulators. The soft‐staart slope is controlled by an n internal 10 00nF and a fixe ed charge currrent to provide e a minimum m startup tim me of 2ms (typical) for all PI33XX reggulators. By adding an addittional external capacitor to t the TRK pin n, the soft‐starrt time can be e increased further. The following equ uation can be e used to caalculate the proper capacitorr for a desired d soft‐start times: t C t I R1 PII33XX 100xx10 , Where, tTRRK is the soft‐sstart time and ITRK is a 50uA A internal ch harge current (see Electrical Characteristics C s for limits). There is typically eith her proportional or directt tracking implemented within a design. Forr proportion nal tracking be etween several regulators att startup, simply s conne ect all devices TRK pinss together. This type of tracking will force all connected regulators to startup and re each regulation n at the same time (see Figgure 5 (a)). VOU UT 1 VOU UT 2 TRK S Slave R2 SGND Figuure 6 ‐ Voltage ddivider connectio ons for direct tra acking All coonnected regu ulators’ soft‐sttart slopes will track with this metho od. Direct ttracking timing is demoonstrated in Fiigure 5 (b). Alll tracking regu ulators shouuld have their Enable (EN N) pins conn nected togetther to work p properly. Indu uctor Pairing The PI33XX utilizzes an exterrnal inductor.. This inducctor has been optimized for maximum efficiency perfoormance. Tablle 5 details th he specific ind ductor valuee and part n number utilizeed for each P PI33XX devicce and are m manufactured b by Cooper Bussman Coiltrronics. PI3311‐X0‐LGIZ Inductor [nH] 120 Inductor Part Number TBD‐120‐R PI3312‐X0‐LGIZ 200 FPT705‐200‐R R PI3301‐X0‐LGIZ 200 FPT705‐200‐R R PI3302‐X0‐LGIZ 200 FPT705‐200‐R R PI3303‐X0‐LGIZ 230 FPT705‐230‐R R PI3305‐X0‐LGIZ 230 FPT705‐230‐R R Device (a) Maste er VOUT Table 5 ‐ PI33XX Inducto or pairing VOUTT 2 (b) t Figure 5 ‐ PI33X XX tracking meth hods For Direct Tracking, cho oose the regulator with the e highest ou utput voltage as the master and connectt the master to the TRK pin of the other regulatorss through a divider (Figurre 6) with the same ratio ass the slave’ss feedback divid der (see Table 4 for values). Picor Corporation • picorpo ower.com PI33XX‐X0‐LGIZZ Family Datasheeet Rev 1.2 August 24, 22012 Page 334 of 39 Input and d Output Filte er Considerattions The PI33XX X requires inp put bulk storagge capacitance e as well as a low impedance ceramic X5R inputt capacitors to ensure proper p start up and high h frequency decoupling for f the powe er stage. The e PI33XX will draw nearlyy all of the high h frequencyy current fro om the low im mpedance ceramic capacitorss when the main high side MOSFET is conducting. During the e time the high side MOSFET is off, they are e replenished from the bulk b capacitorr. If the inputt impedance e is high at the e switching fre equency of the e converter, the bulk capaacitor must supply all of the e average current c into the convertter, includingg replenishin ng the ceramic capacitors. This T value hass been chose en to be 100µFF so that the PI33XX can Device VINN ILOAD (V V) (A) PI3311 24 4 10 5 PI3312 24 4 10 5 PI3301 10 4 24 5 PI3302 24 4 10 5 PI3303 24 4 8 4 PI3305 24 4 8 4 CINPUUT Bulkk Elecc. 100µ µF 50V V CINPUT Ceramic X5R 4X4.7µF 50V 100µ µF 50V V 4X4.7µF 100µ µF 50V V 4X4.7µF 100µ µF 50V V 4X4.7µF 100µ µF 50V V 4X4.7µF µF 100µ 50V V 4X4.7µF start up into a fu ull resistive lo oad and supply the outp ut capacitive load with the default min nimum soft start capaccitor when the input ssource impeedance is 50 O Ohms at 1MH Hz. The ESR fo or this capa citor should b be approximateely 20mΩ. Thee RMS ripplee current in th his capacitor is small, so it sshould not bbe a concern iff the input reccommended ceeramic capa citors are used. Tablee 6 shows the recom mmended inp put and outpu ut capacitors to be used for the vario ous models aas well as exp pected transsient responsse, RMS rip pple currentss per capa citor, and inp put and outp put ripple volltages. Tablee 7 includes th he recommend ded input and o output ceram mic capacitors. CINPPUT COUTPUT Input Outpu ut Transient Recovery LLoad COUTPUT Ceramic Ripp ple Ripple Ripple Ripple Deviation SStep Time Curre ent Current ((mVpp) (mVpp p) (mVpk) X5R (A) (µs) (IRM (Sleew/µs) (IRMS) MS) 8X100µF 2X1 µF 1X0.1 µF 4X100µF 2X1 µF 1X0.1 µF 4X100µF 2X1 µF 1X0.1 µF 4X100µF 2X1 µF 1X0.1 µF 4X22µF 2X1 µF 1X0.1 µF 4X22µF 2X1 µF 1X0.1 µF 120 5 0.5 1 05 1.0 2 1.2 3 1.3 1.38 20 0.8 100 15 150 50 1.75 100 24 200 40 1.625 125 33 220 50 1.5 140 30 275 100 1.36 150 60 280 150 1.2 160 ‐/+40 40 5 (5A/µs) ‐/+80 25 5 (100A/µs) ‐/+100 20 5 (100A/µs) ‐/+170 30 5 (5A/µs) ‐/+300 30 4 (100A/µs) ‐/+400 30 4 (100A/µs) 75 Table 6 ‐ Recommend ded input and ouutput capacitancce MURATA PAR RT NUMBER DESCRIPTION N MURATA A PART NUMBEER DESCRIP PTION GRM31CCR71H475KA12KK 4.7uF 50V 11206 X7R GRM188R71C C105KA12D 1uF 1 16V 0603 X7R GRM319R71H H104KA01D 0.1uF 0 50V 1206 X7R X GRM31CCR61A476ME15L 47uF 10V 1206 X5R GRM31CR60J107ME39L 100uF 1 6.3V 1206 6 X5R GRM31CCR61E226KE15L 22uF 25V 1206 X5R Table 7 ‐ Capacitorr manufacturer ppart numbers Picor Corporation • picorpo ower.com PI33XX‐X0‐LGIZZ Family Datasheeet Rev 1.2 August 24, 22012 Page 335 of 39 Layout Guideliness To optimizze maximum efficiency and d a low noise e performan nce from a PI33XX de esign, layoutt considerattions are necessary. Re educing trace e resistance and minimizin ng high curren nt loop returnss along with proper compo onent placeme ent will reduce e parasitic re esistance and inductance. A typical buck b converterr circuit is show wn in Figure 9. The potential areas of high parasitic in nductance and d resistance are the circuit return pathss, shown as LR R below. When Q1 is on an nd Q2 is off, th he majority off CIN’s curreent is used to satisfy the staatic output loaad and to reecharge the COUT capacitorrs. When Q1 is off and Q2 is on, thee load currentt is supplied b by the inducctor and the C period COUT capacitor. During this p CIN i s also being reecharged by the VIN. Low CIN N loop inducctance is important to min nimize peak vvoltage whenn Q1 turns off. Also, thee difference in n area betw ween the CIN loop and CO OUT loop is viital to minim mize switchingg and GND noisse. Figure 9 ‐ Typiical Buck Converrter The path between b the COUT and CIN capacitors c is off particular importance since s the AC currents are e flowing thrrough both of them t when Q1 1 is turned on. Figure 10, schematicallyy, shows the reduced trace e length bettween input and a output caapacitors. The e shorter paath lessens the effects thatt copper trace e parasitics can c have on the PI33XX perfo ormance. Figure 111 ‐ Current flow:: Q2 closed The rrecommended d component p placement, sho own in Figurre 11, illustratees the tight paath between CIIN and COUTT (and VIN an nd VOUT) for the high AC return curreent. This optim mized layout is the same tthat is used on the PI33XXX evaluation bo oard. Fig gure 10 ‐ Curren nt flow: Q1 closeed Figure 12 ‐ Recommended d component placem ment and metal routing Picor Corporation • picorpo ower.com PI33XX‐X0‐LGIZZ Family Datasheeet Rev 1.2 August 24, 22012 Page 336 of 39 Recomm mended PC CB Footpriint and Ste encil Figu ure 13 ‐ Recommended Receivingg PCB footprint. Figure 133 3 details the recommended receiving r footp print for PI33XXX 10mm x 14m mm package. A All pads should d have a final cop pper size of 0.5 55mm x 0.55m mm, whether they t are soldeer‐mask defineed or copper d defined, on a 1 1mm x 1mm grid. All stencil ope enings are 0.55 5mm when using a 6mil sten cil. Picor Corporation • picorpo ower.com PI33XX‐X0‐LGIZZ Family Datasheeet Rev 1.2 August 24, 22012 Page 337 of 39 Package e Drawings S YM B OL MIN N OM MAX A 2 2.50 2.56 2.62 A1 -- -- 0.05 A2 -- -- 2.57 b 0 0.50 0.55 0.60 L 0 0.50 0.55 0,60 D 14.00 BSC E 10.00 BSC D1 13.00 BSC E1 9.00 BSC e L1 Picor Corporation • picorpo ower.com PI33XX‐X0‐LGIZZ Family Datasheeet 1.00 BSC 0 0.10 0.15 0.20 aaa 0.10 bbb 0.10 ccc 0.08 ddd 0.10 eee 0.08 Rev 1.2 August 24, 22012 Page 338 of 39 Warran nty Information n furnished by Vicor V is believed to be accurate and reliable. H However, no ressponsibility is asssumed by Vicorr for its use. Vicor makes no reprresentations or warranties with h respect to th e accuracy or ccompleteness o of the contents of this m changes to o any products, specifications, and product deescriptions at an ny time publication.. Vicor reservess the right to make without nottice. Informatio on published by Vicor has been n checked and iss believed to bee accurate at th he time it was p printed; however, Vicor V assumes no responsibility for inaccuracie es. Testing and other quality ccontrols are useed to the extent Vicor deems nece essary to suppo ort Vicor’s produ uct warranty. Except E where m mandated by govvernment requirements, testingg of all parameters of each productt is not necessarrily performed. Specifications S arre subject to chaange without notice. ndard Terms and d Conditions Vicor’s Stan All sales are e subject to Vicor’s Standard Terrms and Conditio ons of Sale, whicch are available on Vicor’s webp page or upon req quest. Product Wa arranty In Vicor’s sttandard terms and conditions of sale, Vicor warrants that its pproducts are freee from non‐confformity to its Standard Specifications (the “Expresss Limited Warran nty”). This warraanty is extendedd only to the origginal Buyer for the period expiring two n transferable e. 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Life Support Policy RODUCTS ARE NOT N AUTHORIZEED FOR USE ASS CRITICAL COM MPONENTS IN LLIFE SUPPORT DEVICES OR SYYSTEMS VICOR’S PR WITHOUT THE T EXPRESS PR RIOR WRITTEN APPROVAL OF THE T CHIEF EXECCUTIVE OFFICER R AND GENERA AL COUNSEL OF VICOR CORPORATION. As used he erein, life support devices or sysstems are devicees which (a) are intended for su urgical implant in nto the body, or (b)) support or susstain life and wh hose failure to perform p when pproperly used inn accordance with instructions ffor use provided in the labeling caan be reasonably expected to result r in a signifficant injury to the user. A crittical componentt is any em whose failurre to perform caan be reasonablly expected to ccause the failuree of the component in a life supporrt device or syste em or to affect itts safety or effe ectiveness. Per Vicor Terms andd Conditions of Sale, the user o of Vicor life support device or syste products an nd components in i life support applications assumes all risks of ssuch use and inddemnifies Vicor against all liabillity and damages. e Intellectual Property Notice wn Intellectual Property P (including issued U.S. aand Foreign Patents and pendin ng patent appliccations) Vicor and its subsidiaries ow t products desscribed in this data sheet. No license, whetherr express, implie d, or arising by estoppel or otheerwise, relating to the to any intellectual propertyy rights is grante ed by this docum ment. Interesteed parties should contact Vicor''s Intellectual Prroperty Departmentt. Vicor Co orporation PPicor Corporation n 25 Frontage Road 551 Industrial Drivve N North Smithfield,, RI 02896 Andover, MA 01810 omer Service: cu ustserv@vicorpo ower.com Tech hnical Support: aapps@vicorpow wer.com Custo Picor Corporation • picorpo ower.com PI33XX‐X0‐LGIZZ Family Datasheeet Tel: 800‐735‐62000 Rev 1.2 August 24, 22012 Page 339 of 39