LODEV LMU112JC50 12 x 12-bit parallel multiplier Datasheet

LMU112
LMU112
DEVICES INCORPORATED
12 x 12-bit Parallel Multiplier
12 x 12-bit Parallel Multiplier
DEVICES INCORPORATED
FEATURES
❑
❑
❑
❑
25 ns Worst-Case Multiply Time
Low Power CMOS Technology
Replaces Fairchild MPY112K
Two’s Complement or Unsigned
Operands
❑ Three-State Outputs
❑ Package Styles Available:
• 48-pin PDIP
• 52-pin PLCC, J-Lead
DESCRIPTION
The LMU112 is a high-speed, low
power 12-bit parallel multiplier built
using advanced CMOS technology.
The LMU112 is pin and functionally
compatible with Fairchilds’s MPY112K.
The A and B input operands are
loaded into their respective registers
on the rising edge of the separate
clock inputs (CLK A and CLK B).
Two’s complement or unsigned
magnitude operands are accommodated via the operand control bit (TC)
LMU112 BLOCK DIAGRAM
TC
A 11-0
12
CLK A
B 11-0
12
A REGISTER
B REGISTER
CLK B
which is loaded along with the B
operands. The operands are specified
to be in two’s complement format
when TC is asserted and unsigned
magnitude when TC is deasserted.
Mixed mode operation is not allowed.
For two’s complement operands, the
17 most significant bits at the output
of the asynchronous multiplier array
are shifted one bit position to the left.
This is done to discard the redundant
copy of the sign-bit, which is in the
most significant bit position, and
extend the bit precision by one bit.
The result is then truncated to the 16
MSB’s and loaded into the output
register on the rising edge of CLK B.
The contents of the output register are
made available via three-state buffers
by asserting OE. When OE is deasserted, the outputs (R23-8) are in the
high impedance state.
24
FORMAT ADJUST
16
RESULT REGISTER
OE
16
R 23-8
Multipliers
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08/16/2000–LDS.112-K
LMU112
DEVICES INCORPORATED
FIGURE 1A.
12 x 12-bit Parallel Multiplier
INPUT FORMATS
BIN
AIN
Fractional Two’s Complement (TC = 1)
11 10 9
–20 2–1 2–2
2 1 0
2–9 2–10 2–11
11 10 9
–20 2–1 2–2
(Sign)
2 1 0
2–9 2–10 2–11
(Sign)
Integer Two’s Complement (TC = 1)
11 10 9
–211 210 29
2 1 0
22 21 20
11 10 9
–211 210 29
(Sign)
2 1 0
22 21 20
(Sign)
Unsigned Fractional (TC = 0)
11 10 9
2–1 2–2 2–3
2 1 0
2–10 2–11 2–12
11 10 9
2–1 2–2 2–3
2 1 0
2–10 2–11 2–12
Unsigned Integer (TC = 0)
11 10 9
211 210 29
FIGURE 1B.
2 1 0
22 21 20
11 10 9
211 210 29
2 1 0
22 21 20
OUTPUT FORMATS
MSP
LSP
Fractional Two’s Complement
23 22 21
–20 2–1 2–2
11 10 9 8
2–12 2–13 2–14 2–15
14 13 12
2–9 2–10 2–11
(Sign)
Integer Two’s Complement
23 22 21
–222 221 220
11 10 9 8
210 29 28 27
14 13 12
213 212 211
(Sign)
Unsigned Fractional
23 22 21
2–1 2–2 2–3
11 10 9 8
2–13 2–14 2–15 2–16
14 13 12
2–10 2–11 2–12
Unsigned Integer
23 22 21
223 222 221
11 10 9 8
211 210 29 28
14 13 12
214 213 212
Multipliers
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08/16/2000–LDS.112-K
LMU112
DEVICES INCORPORATED
12 x 12-bit Parallel Multiplier
MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8)
Storage temperature ........................................................................................................... –65°C to +150°C
Operating ambient temperature ........................................................................................... –55°C to +125°C
VCC supply voltage with respect to ground ............................................................................ –0.5 V to +7.0 V
Input signal with respect to ground ........................................................................................ –3.0 V to +7.0 V
Signal applied to high impedance output ............................................................................... –3.0 V to +7.0 V
Output current into low outputs ............................................................................................................. 25 mA
Latchup current ............................................................................................................................... > 400 mA
OPERATING CONDITIONS To meet specified electrical and switching characteristics
Mode
Temperature Range (Ambient)
Active Operation, Commercial
Active Operation, Military
Supply Voltage
0°C to +70°C
4.75 V ≤ VCC ≤ 5.25 V
–55°C to +125°C
4.50 V ≤ VCC ≤ 5.50 V
ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4)
Symbol
Parameter
Test Condition
Min
VOH
Output High Voltage
VCC = Min., IOH = –2.0 mA
2.4
VOL
Output Low Voltage
VCC = Min., IOL = 8.0 mA
VIH
Input High Voltage
VIL
Input Low Voltage
(Note 3)
IIX
Input Current
IOZ
Typ
Max
Unit
V
0.5
V
2.0
VCC
V
0.0
0.8
V
Ground ≤ VIN ≤ VCC (Note 12)
±20
µA
Output Leakage Current
Ground ≤ VOUT ≤ VCC (Note 12)
±20
µA
ICC1
VCC Current, Dynamic
(Notes 5, 6)
20
mA
ICC2
VCC Current, Quiescent
(Note 7)
1.0
mA
10
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08/16/2000–LDS.112-K
LMU112
DEVICES INCORPORATED
12 x 12-bit Parallel Multiplier
SWITCHING CHARACTERISTICS
COMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns)
Symbol
123456789012
123456789012
123456789012
60*
123456789012
123456789012
123456789012
Min Max
123456789012
123456789012
60
123456789012
123456789012
123456789012
123456789012
15
123456789012
123456789012
123456789012
15
123456789012
123456789012
123456789012
3
123456789012
123456789012
123456789012
25
123456789012
123456789012
123456789012
25
123456789012
123456789012
123456789012
123456789012
25
123456789012
Parameter
tMC
Clocked Multiply Time
tPW
Clock Pulse Width
tS
Input Register Setup Time
tH
Input Register Hold Time
tD
Output Delay
tENA
Three-State Output Enable Delay (Note 11)
tDIS
Three-State Output Disable Delay (Note 11)
LMU112–
50
Min
Max
25
Min
50
Max
25
15
10
15
10
3
1
25
20
25
20
25
20
MILITARY OPERATING RANGE (–55°C to +125°C) Notes 9, 10 (ns)
Symbol
1234567890123456789012345678901212
LMU112–
1234567890123456789012345678901212
1234567890123456789012345678901212
*
65
55*
30*
1234567890123456789012345678901212
1234567890123456789012345678901212
1234567890123456789012345678901212
Min
Max Min Max Min Max
1234567890123456789012345678901212
1234567890123456789012345678901212
1234567890123456789012345678901212
65
55
30
1234567890123456789012345678901212
1234567890123456789012345678901212
1234567890123456789012345678901212
20
20
12
1234567890123456789012345678901212
1234567890123456789012345678901212
1234567890123456789012345678901212
15
15
12
1234567890123456789012345678901212
1234567890123456789012345678901212
1234567890123456789012345678901212
3
3
3
1234567890123456789012345678901212
1234567890123456789012345678901212
1234567890123456789012345678901212
1234567890123456789012345678901212
30
30
25
1234567890123456789012345678901212
1234567890123456789012345678901212
1234567890123456789012345678901212
30
30
25
1234567890123456789012345678901212
1234567890123456789012345678901212
1234567890123456789012345678901212
30
30
25
1234567890123456789012345678901212
Parameter
tMC
Clocked Multiply Time
tPW
Clock Pulse Width
tS
Input Register Setup Time
tH
Input Register Hold Time
tD
Output Delay
tENA
Three-State Output Enable Delay (Note 11)
tDIS
Three-State Output Disable Delay (Note 11)
SWITCHING WAVEFORMS
tS
tH
INPUT
tMC
CLK A
tPW
tPW
CLK B
tD
OE
tDIS
R23-8
tENA
HIGH IMPEDANCE
123456789012345678901234
123456789012345678901234
123456789012345678901234
*DISCONTINUED SPEED GRADE
123456789012345678901234
Multipliers
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08/16/2000–LDS.112-K
LMU112
DEVICES INCORPORATED
12 x 12-bit Parallel Multiplier
NOTES
1. Maximum Ratings indicate stress
specifications only. Functional operation of these products at values beyond
those indicated in the Operating Conditions table is not implied. Exposure to
maximum rating conditions for extended periods may affect reliability.
9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
tDIS test), and input levels of nominally
0 to 3.0 V. Output loading may be a
resistive divider which provides for
specified IOH and IOL at an output
voltage of VOH min and VOL max
2. The products described by this spec- respectively. Alternatively, a diode
ification include internal circuitry de- bridge with upper and lower current
signed to protect the chip from damagsources of I OH and I OL respectively,
ing substrate injection currents and ac- and a balancing voltage of 1.5 V may be
cumulations of static charge. Neverthe- used. Parasitic capacitance is 30 pF
less, conventional precautions should minimum, and may be distributed.
be observed during storage, handling,
and use of these circuits in order to This device has high-speed outputs caavoid exposure to excessive electrical pable of large instantaneous current
stress values.
pulses and fast turn-on/turn-off times.
As a result, care must be exercised in the
3. This device provides hard clamping of testing of this device. The following
transient undershoot and overshoot. In- measures are recommended:
put levels below ground or above VCC
will be clamped beginning at –0.6 V and a. A 0.1 µF ceramic capacitor should be
VCC + 0.6 V. The device can withstand installed between VCC and Ground
indefinite operation with inputs in the leads as close to the Device Under Test
range of –0.5 V to +7.0 V. Device opera- (DUT) as possible. Similar capacitors
tion will not be adversely affected, how- should be installed between device VCC
ever, input current levels will be well in and the tester common, and device
ground and tester common.
excess of 100 mA.
4. Actual test conditions may vary from b. Ground and VCC supply planes
those designated but operation is guar- must be brought directly to the DUT
anteed as specified.
socket or contactor fingers.
5. Supply current for a given applica- c. Input voltages should be adjusted to
tion can be accurately approximated by: compensate for inductive ground and VCC
noise to maintain required DUT input
NCV2 F
levels relative to the DUT ground pin.
4
where
10. Each parameter is shown as a min-
11. For the tENA test, the transition is
measured to the 1.5 V crossing point
with datasheet loads. For the tDIS test,
the transition is measured to the
±200mV level from the measured
steady-state output voltage with
±10mA loads. The balancing voltage, V TH , is set at 3.5 V for Z-to-0
and 0-to-Z tests, and set at 0 V for Zto-1 and 1-to-Z tests.
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.
FIGURE A. OUTPUT LOADING CIRCUIT
S1
DUT
IOL
VTH
CL
IOH
FIGURE B. THRESHOLD LEVELS
tENA
OE
Z
tDIS
1.5 V
1.5 V
3.5V Vth
0
1.5 V
1.5 V
Z
1
VOL*
0.2 V
VOH*
0.2 V
0
Z
1
Z
0V Vth
VOL* Measured VOL with IOH = –10mA and IOL = 10mA
VOH* Measured VOH with IOH = –10mA and IOL = 10mA
imum or maximum value. Input requirements are specified from the point
of view of the external system driving
the chip. Setup time, for example, is
specified as a minimum since the exter6. Tested with all outputs changing ev- nal system must supply at least that
ery cycle and no load, at a 5 MHz clock much time to meet the worst-case requirements of all parts. Responses from
rate.
the internal circuitry are specified from
7. Tested with all inputs within 0.1 V of the point of view of the device. Output
VCC or Ground, no load.
delay, for example, is specified as a
8. These parameters are guaranteed maximum since worst-case operation of
any device always provides data within
but not 100% tested.
that time.
N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency
Multipliers
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08/16/2000–LDS.112-K
LMU112
DEVICES INCORPORATED
12 x 12-bit Parallel Multiplier
ORDERING INFORMATION
48-pin
52-pin
Speed
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
CLK A
GND
GND
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
NC
B3
B2
B1
B0
A11
A10
A9
A8
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
B4
B5
B6
B7
B8
VCC
VCC
B9
B10
B11
TC
CLK B
NC
8
7 6 5 4 3 2 1 52 51 50 49 48 47
46
9
45
10
44
11
43
12
42
13
14
15
41
Top
View
40
39
16
38
17
37
18
36
19
35
20
34
21 22 23 24 25 26 27 28 29 30 31 32 33
NC
A3
A2
A1
A0
CLK A
GND
GND
R8
R9
R10
R11
R12
OE
R23
R22
R21
R20
R19
R18
R17
R16
R15
R14
R13
NC
A10
A11
B0
B1
B2
B3
B4
B5
B6
B7
B8
VCC
VCC
B9
B10
B11
TC
CLK B
OE
R23
R22
R21
R20
R19
Plastic DIP
(P5)
Plastic J-Lead Chip Carrier
(J5)
0°C to +70°C — COMMERCIAL SCREENING
50 ns
25 ns
LMU112JC50
LMU112JC25
LMU112PC50
LMU112PC25
–55°C to +125°C — COMMERCIAL SCREENING
–55°C to +125°C — MIL-STD-883 COMPLIANT
Multipliers
6
08/16/2000–LDS.112-K
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