Cypress CY26049ZXC-22T Failsafeâ ¢ packetclockâ ¢ global communications clock generator Datasheet

CY26049-22
FailSafe™ PacketClock™
Global Communications Clock Generator
Features
Benefits
• Fully integrated phase-locked loop (PLL)
• Integrated high-performance PLL tailored for telecommunications frequency synthesis eliminates the need for external
loop filter components
• FailSafe output
• PLL driven by a crystal oscillator that is phase aligned
with external reference
• When reference is off, DCXO maintains clock outputs and
SAFE pin indicates FailSafe conditions
• 100-MHz output from 10-MHz input
• Low-jitter, high-accuracy outputs
• DCXO maintains continuous operation should the input
reference clock fail
• 3.3V ± 5% operation
• Glitch-free transition simplifies system design
• 16-lead TSSOP
• Works with commonly available, low-cost 10-MHz crystal
• Zero-ppm error for all output frequencies
• Compatible across industry standard design platforms
• Industry standard package with 6.4 × 5.0 mm2 footprint and
a height profile of just 1.1 mm
Logic Block Diagram
e xte rn a l p u lla b le c rysta l
(1 0 M H z )
X IN
XOUT
in p u t re fe re n ce
(1 0 M H z )
IC L K
F A IL S A F E TM
CONTROL
D IG IT A L
C O N TR O LLE D
CRYSTAL
O S C IL L A T O R
PHASE
LO C K E D
LO O P
OUTPUT
D IV ID E R
CLKA
100M H z
SAFE
IC L K d e te cte d
Cypress Semiconductor Corporation
Document #: 38-07730 Rev. **
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised January 12, 2005
CY26049-22
Pin Configuration
16-pin TSSOP
Top View
ICLK 1
NC
2
16 NC
15 CLKA
NC 3
14 NC
NC 4
13 NC
VDD 5
12 VDD
VSS 6
11 VSS
NC
7
10 SAFE
XIN 8
9 XOUT
Pin Description
Pin Number Pin Name
Pin Description
1
ICLK
Reference Input Clock; 10 MHz.
2
NC
No Connect.
3
NC
No Connect.
4
NC
No Connect.
5
VDD
Voltage Supply; 3.3V.
6
VSS
Ground.
7
NC
No Connect
8
XIN
Pullable Crystal Input; 10 MHz.
9
XOUT
10
SAFE
11
VSS
12
VDD
13
NC
No Connect.
14
NC
No Connect.
15
CLKA
16
NC
Pullable Crystal Output; 10 MHz.
High = reference ICLK within range, Low = reference ICLK out of range.
Ground.
Voltage Supply; 3.3V.
Clock Output. 100 MHz
No Connect.
Selector Guide
Part Number
CY26049ZXC-22
Input Frequency Range
Reference Input Clock: 10 MHz
Crystal: 10-MHz pullable Crystal per Cypress Specification
Description
CY26049-22 is a FailSafe frequency synthesizer with a
reference clock input and 100-MHz output. The device
provides an optimum solution for applications where
continuous operation is required in the event of a primary clock
failure. The continuous, glitch-free operation is achieved by
using a DCXO, which serves as a primary clock source. The
FailSafe control circuit synchronizes the DCXO oscillator with
the reference as long as the reference is within the pull range
of the crystal.
Document #: 38-07730 Rev. **
Outputs
Output Frequencies
1
100 MHz
In the event of a reference clock failure the DCXO maintains
the last frequency of the reference clock. The unique feature
of the CY26049-22 is that the DCXO is, in fact, the primary
clocking source. When the reference clock is restored, the
DCXO automatically resynchronizes to the reference. The
status of the reference clock input, as detected by the
CY26049-22, is reported by the SAFE pin.
Page 2 of 6
CY26049-22
Absolute Maximum Conditions
Data Retention @ Tj = 125°C................................ >10 Years
Package Power Dissipation...................................... 350 mW
Supply Voltage (VDD) ........................................–0.5 to +7.0V
ESD (Human Body Model) MIL-STD-883.................... 2000V
DC Input Voltage...................................... –0.5V to VDD + 0.5
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature (Non-Condensing) .... –55°C to +125°C
Junction Temperature ................................ –40°C to +125°C
Recommended Pullable Crystal Specifications
Parameter
Name
FNOM
Nominal crystal frequency
CLNOM
Nominal load capacitance
R1
Equivalent series resistance (ESR)
R3/R1
Ratio of third overtone mode ESR to
fundamental mode ESR
DL
Crystal drive level
Comments
Min.
Typ.
Max.
Unit
Parallel resonance, fundamental mode,
AT cut
–
10
–
MHz
–
14
–
pF
Fundamental mode
–
–
25
Ω
Ratio used because typical R1 values
are much less than the maximum spec
3
–
–
No external series resistor assumed
–
0.5
2
mW
F3SEPLI
Third overtone separation from 3*FNOM High side
400
–
–
ppm
F3SEPLO
Third overtone separation from 3*FNOM Low side
–
–
–200
ppm
pF
C0
Crystal shunt capacitance
–
–
7
C0/C1
Ratio of shunt to motional capacitance
180
–
250
C1
Crystal motional capacitance
14.4
18
21.6
fF
Recommended Operating Conditions
Parameter
Description
VDD
Operating Voltage
Min.
Typ.
Max.
Unit
3.15
3.3
3.45
V
TAC
Ambient Temperature (Commercial Temperature)
0
–
70
°C
CLOAD
Max Output Load Capacitance
–
–
15
pF
tpu
Power-up time for all VDDs to reach minimum specified
voltage (power ramps must be monotonic)
0.05
–
500
ms
Min.
Typ.
Max.
Unit
12
24
–
mA
DC Electrical Specifications (Commercial Temp: 0°to 70°C)
Parameter
Description
IOH
Output High Current
Test Conditions
VOH = VDD – 0.5, VDD = 3.3V (source)
IOL
Output Low Current
VOL = 0.5, VDD = 3.3V (sink)
12
24
–
mA
VIH
Input High Voltage
CMOS Levels
0.7
–
–
VDD
VIL
Input High Voltage
CMOS Levels
–
–
0.3
VDD
IIH
Input High Current
VIH=VDD
–
5
10
µA
IIL
Input Low Current
VIL=0V
–
5
10
µA
CIN
Input Capacitance
–
–
7
pF
IDD
Supply Current
–
–
45
mA
CLOAD = 15 pF, VDD = 3.45V
AC Electrical Specifications (Commercial Temp: 0° to 70°C)
Parameter
fICLK-E
Description
Test Conditions
Frequency, Input Clock
LR
FailSafe Lock Range
DC = t2/t1
Output Duty Cycle
TPJIT1
Clock Jitter
[1]
Input Clock Frequency, External Mode
Range of reference ICLK for Safe = High
Duty Cycle defined in Figure 1, measured at 50% of VDD
Min.
Typ.
–
10
Max. Unit
–
–250
–
45
50
55
MHz
+250 ppm
%
Period Jitter, Peak to Peak, 10,000 periods
–
–
250
ps
RMS Period Jitter
–
–
50
ps
Note:
1. Dependent on crystals chosen and crystal specs.
Document #: 38-07730 Rev. **
Page 3 of 6
CY26049-22
AC Electrical Specifications (Commercial Temp: 0° to 70°C) (continued)
Test Conditions
Min.
Typ.
t6
Parameter
PLL Lock Time
Description
Time for PLL to lock within ± 150 ppm of target frequency
–
–
Max. Unit
3
ms
tfs_lock
FailSafe Lock Time
Time for PLL to lock to ICLK (outputs phase aligned with
ICLK and Safe = High)
–
–
7
s
ferror
Frequency Synthesis Error
Actual mean frequency error vs. target
–
0
–
ppm
ER
Rising Edge Rate
Output Clock Edge Rate, Measured from 20% to 80% of
VDD, CLOAD = 15 pF. See Figure 2.
0.8
1.4
2
V/ns
EF
Falling Edge Rate
Output Clock Edge Rate, Measured from 20% to 80% of
VDD, CLOAD = 15 pF. See Figure 2.
0.8
1.4
2
V/ns
Voltage and Timing Definitions
t1
t2
CLK
50%
50%
Figure 1. Duty Cycle Definition; DC = t2/t1
t4
t3
80%
CLK
20%
Figure 2. Rise and Fall Time Definitions: ER = 0.6 x VDD / t3, EF = 0.6 x VDD / t4
Test Circuit
ICLK
VDD
1
16
2
15
3
14
4
13
5
12
CLKA
CLOAD
0.1uF
VDD
0.1uF
6
11
7
10
8
9
10MHz
Ordering Information
Ordering Code
Package Type
Operating Temperature Range
Lead-Free
CY26049ZXC-22
16-lead TSSOP
Commercial 0° to 70°C
CY26049ZXC-22T
16-lead TSSOP—Tape and Reel
Commercial 0° to 70°C
Document #: 38-07730 Rev. **
Page 4 of 6
CY26049-22
Package Drawing and Dimensions
16-lead TSSOP 4.40 MM Body Z16.173
PIN 1 ID
DIMENSIONS IN MM[INCHES] MIN.
1
MAX.
REFERENCE JEDEC MO-153
6.25[0.246]
6.50[0.256]
PACKAGE WEIGHT 0.05gms
4.30[0.169]
4.50[0.177]
16
0.65[0.025]
BSC.
0.19[0.007]
0.30[0.012]
1.10[0.043] MAX.
0.25[0.010]
BSC
GAUGE
PLANE
0°-8°
0.076[0.003]
0.85[0.033]
0.95[0.037]
4.90[0.193]
5.10[0.200]
0.05[0.002]
0.15[0.006]
SEATING
PLANE
0.50[0.020]
0.70[0.027]
0.09[[0.003]
0.20[0.008]
51-85091-*A
FailSafe and PacketClock are trademarks of Cypress Semiconductor. Corporation. All product and company names mentioned
in this document are the trademarks of their respective holders.
Document #: 38-07730 Rev. **
Page 5 of 6
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY26049-22
Document History Page
Document Title: CY26049-22 FailSafe™ PacketClock™ Global Communications Clock Generator
Document Number: 38-07730
REV.
ECN No.
Issue Date
Orig. of
Change
**
308456
See ECN
RGL
Document #: 38-07730 Rev. **
Description of Change
New Data Sheet
Page 6 of 6
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