Harris CD74HC393M High speed cmos logic dual 4 -stage binary counter Datasheet

CD74HC393,
CD74HCT393
Semiconductor
High Speed CMOS Logic
Dual 4 -Stage Binary Counter
September 1997
Features
Description
• Fully Static Operation
• Negative-Edge Clocking
The Harris CD74HC393 and CD74HCT393 are 4-stage
ripple-carry binary counters. Al counter stages are masterslave flip-flops. The state of the stage advances one count
on the negative transition of each clock pulse; a high voltage
level on the MR line resets all counters to their zero state. All
inputs and outputs are buffered.
• Typical fMAX = 60 MHz at VCC = 5V, CL = 15pF,
TA = 25oC
Ordering Information
• Buffered Inputs
• Common Reset
• Fanout (Over Temperature Range)
PART NUMBER
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
TEMP. RANGE (oC)
PKG.
NO.
PACKAGE
CD74HC393E
-55 to 125
14 Ld PDIP
E14.3
• Wide Operating Temperature Range . . . -55oC to 125oC
CD74HCT393E
-55 to 125
14 Ld PDIP
E14.3
• Balanced Propagation Delay and Transition Times
CD74HC393M
-55 to 125
14 Ld SOIC
M14.15
• Significant Power Reduction Compared to LSTTL
Logic ICs
CD74HCT393M
-55 to 125
14 Ld SOIC
M14.15
NOTES:
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30%of VCC at
VCC = 5V
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer or die for this part number is available which meets all electrical specifications. Please contact your local sales office or
Harris customer service for ordering information.
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
Pinout
CD74HC393, CD74HCT393
(PDIP, SOIC)
TOP VIEW
1CP 1
14 VCC
1MR 2
13 2CP
1Q0 3
12 2MR
1Q1 4
11 2Q0
1Q2 5
10 2Q1
1Q3 6
9 2Q2
GND 7
8 2Q3
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© Harris Corporation 1997
1
File Number
1653.1
CD74HC393, CD74HCT393
Functional Diagram
3
1Q0
1
1CP
2
1MR
4
BINARY
COUNTER
1Q1
5
1Q2
6
1Q3
11
13
2CP
12
2MR
2Q0
10
BINARY
COUNTER
2Q1
9
2Q2
8
2Q3
GND = 7
VCC = 14
TRUTH TABLE
OUTPUTS
CP COUNT
Q0
Q1
Q2
Q3
0
L
L
L
L
1
H
L
L
L
2
L
H
L
L
3
H
H
L
L
4
L
L
H
L
5
H
L
H
L
6
L
H
H
L
7
H
H
H
L
8
L
L
L
H
9
H
L
L
H
10
L
H
L
H
11
H
H
L
H
12
L
L
H
H
13
H
L
H
H
14
L
H
H
H
15
H
H
H
H
CP COUNT
MR
OUTPUT
↑
L
No Change
↓
L
Count
X
H
LLLL
NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care,
↑ = Transition from Low to High Level, ↓ = Transition from High to Low.
2
CD74HC393, CD74HCT393
Logic Diagram
Φ
1(13)
CP
Φ
Q
Φ
Q
Φ
R
Q
Φ
Q
Φ
R
Q
Φ
Q
Φ
R
Q
Q
R
2(12)
MR
3(11)
4(10)
Q1
Q0
3
5(9)
Q2
6(8)
Q3
CD74HC393, CD74HCT393
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA
Thermal Resistance (Typical, Note 3)
θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
175
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θJA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
TEST
CONDITIONS
PARAMETER
25oC
-40oC TO 85oC -55oC TO 125oC
SYMBOL
VI (V)
IO (mA)
VCC
(V)
VIH
-
-
2
1.5
-
-
1.5
4.5
3.15
-
-
3.15
-
3.15
-
V
6
4.2
-
-
4.2
-
4.2
-
V
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
-
1.5
-
V
HC TYPES
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
CMOS Loads
VIL
VOH
-
VIH or VIL
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
VOL
VIH or VIL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
-
2
-
-
0.5
-
0.5
-
0.5
V
4.5
-
-
1.35
-
1.35
-
1.35
V
6
-
-
1.8
-
1.8
-
1.8
V
-0.02
2
1.9
-
-
1.9
-
1.9
-
V
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-0.02
6
5.9
-
-
5.9
-
5.9
-
V
-
-
-
-
-
-
-
-
-
V
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
-5.2
6
5.48
-
-
5.34
-
5.2
-
V
0.02
2
-
-
0.1
-
0.1
-
0.1
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
0.02
6
-
-
0.1
-
0.1
-
0.1
V
-
-
-
-
-
-
-
-
-
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
5.2
6
-
-
0.26
-
0.33
-
0.4
V
II
VCC or
GND
-
6
-
-
±0.1
-
±1
-
±1
µA
ICC
VCC or
GND
0
6
-
-
8
-
80
-
160
µA
4
CD74HC393, CD74HCT393
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
SYMBOL
VI (V)
IO (mA)
High Level Input
Voltage
VIH
-
-
Low Level Input
Voltage
VIL
-
High Level Output
Voltage
CMOS Loads
VOH
VIH or VIL
PARAMETER
VCC
(V)
25oC
-40oC TO 85oC -55oC TO 125oC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
4.5 to
5.5
2
-
-
2
-
2
-
V
-
4.5 to
5.5
-
-
0.8
-
0.8
-
0.8
V
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
HCT TYPES
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
VOL
VIH or VIL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
II
VCC and
GND
0
5.5
-
-
±0.1
-
±1
-
±1
µA
ICC
VCC or
GND
0
5.5
-
-
8
-
80
-
160
µA
∆ICC
VCC
-2.1
-
4.5 to
5.5
-
100
360
-
450
-
490
µA
NOTE: For dual-supply systems theorectical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
HCT Input Loading Table
INPUT
UNIT LOADS
nCP
0.4
nMR
1
NOTE: Unit Load is ∆ICC limit specified in DC Electrical Table, e.g.,
360µA max at 25oC.
Prerequisite for Switching Specifications
25oC
PARAMETER
-40oC TO 85oC
-55oC TO 125oC
SYMBOL
VCC (V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
fMAX
2
6
-
-
5
-
4
-
ns
4.5
30
-
-
24
-
20
-
ns
6
35
-
-
28
-
24
-
ns
2
80
-
-
100
-
120
-
ns
4.5
16
-
-
20
-
24
-
ns
6
14
-
-
17
-
20
-
ns
2
5
-
-
5
-
5
-
ns
4.5
5
-
-
5
-
5
-
ns
6
5
-
-
5
-
5
-
ns
HC TYPES
Maximum Clock
Frequency
Clock Pulse Width
Reset Recovery Time
tW
tREC
5
CD74HC393, CD74HCT393
Prerequisite for Switching Specifications
(Continued)
25oC
PARAMETER
Reset Pulse Width
-40oC TO 85oC
-55oC TO 125oC
SYMBOL
VCC (V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
tW
2
80
-
-
100
-
120
-
ns
4.5
16
-
-
20
-
24
-
ns
6
14
-
-
17
-
20
-
ns
fMAX
4.5
27
-
-
22
-
18
-
MHz
tW
4.5
19
-
-
24
-
29
-
ns
tREC
4.5
5
-
-
5
-
5
-
ns
tW
4.5
16
-
-
20
-
24
-
ns
HCT TYPES
Maximum Clock
Frequency
Clock Pulse Width
Reset Recovery Time
Reset Pulse Width
Switching Specifications Input tr, tf = 6ns
PARAMETER
HC TYPES
Propagation Delay Time
(Figure 1)
TEST
SYMBOL CONDITIONS
tPLH,
tPHL
nCP to nQ1
nCP to nQ2
nCP to nQ3
MR to Qn
Output Transition Time
(Figure 1)
tPLH,
tPHL
tPLH,
tPHL
tPLH,
tPHL
tPLH,
tPHL
-40oC TO 85oC -55oC TO 125oC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
2
-
-
45
-
55
-
70
ns
4.5
-
-
9
-
11
-
14
ns
CL =15pF
5
-
4
-
-
-
-
-
ns
CL = 50pF
6
-
-
8
-
9
-
12
ns
CL = 50pF
2
-
-
150
-
190
-
225
ns
4.5
-
-
30
-
38
-
59
ns
CL =15pF
5
-
12
-
-
-
-
-
ns
CL = 50pF
6
-
-
26
-
33
-
50
ns
CL = 50pF
2
-
-
190
-
245
-
295
ns
4.5
-
-
38
-
49
-
59
ns
6
-
-
33
-
42
-
50
ns
2
-
-
240
-
300
-
360
ns
4.5
-
-
48
-
60
-
72
ns
6
-
-
41
-
51
-
61
ns
2
-
CL = 50pF
Qn to Qn + 1
nCP to nQ0
25oC
VCC
(V)
CL = 50pF
CL = 50pF
4.5
-
285
-
355
-
430
ns
-
57
-
71
-
86
ns
6
-
-
48
-
60
-
73
ns
2
-
-
135
-
170
-
205
ns
4.5
-
-
27
-
34
-
41
ns
CL =15pF
5
-
11
-
-
-
-
-
ns
CL = 50pF
6
-
-
23
-
29
-
35
ns
tTLH, tTHL CL = 50pF
2
-
-
75
-
95
-
110
ns
4.5
-
-
15
-
19
-
22
ns
6
-
-
13
-
16
-
19
ns
tPLH,
tPHL
CL = 50pF
Input Capacitance
CIN
CL = 50pF
-
-
-
10
-
10
-
10
pF
Power Dissipation Capacitance
(Notes 4, 5)
CPD
CL =15pF
5
-
20
-
-
-
-
-
pF
6
CD74HC393, CD74HCT393
Switching Specifications Input tr, tf = 6ns
(Continued)
TEST
SYMBOL CONDITIONS
25oC
-40oC TO 85oC -55oC TO 125oC
VCC
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
CL = 50pF
4.5
-
-
12
-
15
-
18
ns
CL =15pF
5
-
4
-
-
-
-
-
ns
tPLH,
tPHL
CL = 50pF
4.5
-
-
32
-
40
-
48
ns
CL =15pF
5
-
13
-
-
-
-
-
ns
nCP to nQ1
tPLH,
tPHL
CL = 50pF
4.5
-
-
44
-
55
-
66
ns
nCP to nQ2
tPLH,
tPHL
CL = 50pF
4.5
-
-
50
-
63
-
75
ns
nCP to nQ3
tPLH,
tPHL
CL = 50pF
4.5
-
-
62
-
78
-
93
ns
MR to Qn
tPLH,
tPHL
CL = 50pF
4.5
-
-
32
-
40
-
48
ns
CL =15pF
5
-
13
-
-
-
-
-
ns
4.5
-
-
15
-
19
-
22
ns
PARAMETER
HCT TYPES
Propagation Delay Time
(Figure 1)
tPLH,
tPHL
Qn to Qn + 1
nCP to nQ0
Output Transition
tTLH, tTHL CL = 50pF
Input Capacitance
CIN
CL =15pF
-
-
-
10
-
10
-
10
pF
Power Dissipation Capacitance
(Notes 4, 5)
CPD
CL =15pF
5
-
21
-
-
-
-
-
pF
NOTES:
4. CPD is used to determine the dynamic power consumption, per stage.
5. PD = VCC2 fi (CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.
Test Circuits and Waveforms
tr = 6ns
tf = 6ns
90%
50%
10%
INPUT
GND
tTLH
GND
tTHL
90%
50%
10%
INVERTING
OUTPUT
3V
2.7V
1.3V
0.3V
INPUT
tTHL
tPHL
tf = 6ns
tr = 6ns
VCC
tTLH
90%
1.3V
10%
INVERTING
OUTPUT
tPHL
tPLH
FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
tPLH
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
7
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