LINER LTC2402 1-/2-channel 24-bit power no latency adcs in msop-10 Datasheet

LTC2401/LTC2402
1-/2-Channel 24-Bit µPower
No Latency ∆ΣTMADCs in MSOP-10
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FEATURES
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DESCRIPTIO
24-Bit ADCs in Tiny MSOP-10 Packages
4ppm INL, No Missing Codes
4ppm Full-Scale Error
0.5ppm Offset
0.6ppm Noise
Single Conversion Settling Time for
Multiplexed Applications
1- or 2-Channel Inputs
Automatic Channel Selection (Ping-Pong) (LTC2402)
Zero Scale and Full Scale Set for Reference
and Ground Sensing
Internal Oscillator—No External Components Required
110dB Min, 50Hz/60Hz Notch Filter
Reference Input Voltage: 0.1V to VCC
Live Zero—Extended Input Range Accommodates
12.5% Overrange and Underrange
Single Supply 2.7V to 5.5V Operation
Low Supply Current (200µA) and Auto Shutdown
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APPLICATIO S
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Through a single pin, the LTC2401/LTC2402 can be
configured for better than 110dB rejection at 50Hz or
60Hz ±2%, or can be driven by an external oscillator for
a user defined rejection frequency in the range 1Hz to
120Hz. The internal oscillator requires no external frequency setting components.
These converters accept an external reference voltage
from 0.1V to VCC. With an extended input conversion
range of –12.5% VREF to 112.5% VREF (VREF = FSSET –
ZSSET), the LTC2401/LTC2402 smoothly resolve the offset and overrange problems of preceding sensors or
signal conditioning circuits.
The LTC2401/LTC2402 communicate through a 2- or
3-wire digital interface that is compatible with SPI and
MICROWIRETM protocols.
Weight Scales
Direct Temperature Measurement
Gas Analyzers
Strain Gauge Transducers
Instrumentation
Data Acquisition
Industrial Process Control
, LTC and LT are registered trademarks of Linear Technology Corporation.
No Latency ∆Σ is a trademark of Linear Technology Corporation.
MICROWIRE is a trademark of National Semiconductor Corporation.
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The LTC®2401/LTC2402 are 1- and 2-channel 2.7V to 5.5V
micropower 24-bit analog-to-digital converters with an
integrated oscillator, 4ppm INL and 0.6ppm RMS noise.
These ultrasmall devices use delta-sigma technology and
a new digital filter architecture that settles in a single cycle.
This eliminates the latency found in conventional ∆Σ
converters and simplifies multiplexed applications.
TYPICAL APPLICATIO
Pseudo Differential Bridge Digitizer
2.7V TO 5.5V
2.7V TO 5.5V
VCC
1µF
1
VCC
FO
10
LTC2402
REFERENCE VOLTAGE
ZSSET + 0.1V TO VCC
ANALOG INPUT RANGE
ZSSET – 0.12VREF TO
FSSET + 0.12VREF
(VREF = FSSET – ZSSET)
0V TO FSSET – 100mV
2
3
4
5
FSSET
SCK
CH1
SDO
CH0
CS
ZSSET
GND
= INTERNAL OSC/50Hz REJECTION
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/60Hz REJECTION
1
2
9
4
8
3-WIRE
SPI INTERFACE
3
7
5
6
24012 TA01
VCC
LTC2402
FSSET
9
SCK
CH0
SDO
CH1
CS
ZSSET
GND
6
FO
8
3-WIRE
SPI INTERFACE
7
10
INTERNAL OSCILLATOR
60Hz REJECTION
24012TA02
1
LTC2401/LTC2402
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ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
Supply Voltage (VCC) to GND .......................– 0.3V to 7V
Analog Input Voltage to GND ....... – 0.3V to (VCC + 0.3V)
Reference Input Voltage to GND .. – 0.3V to (VCC + 0.3V)
Digital Input Voltage to GND ........ – 0.3V to (VCC + 0.3V)
Digital Output Voltage to GND ..... – 0.3V to (VCC + 0.3V)
Operating Temperature Range
LTC2401/LTC2402C ................................ 0°C to 70°C
LTC2401/LTC2402I ............................ – 40°C to 85°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
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PACKAGE/ORDER INFORMATION
ORDER PART NUMBER
ORDER PART NUMBER
TOP VIEW
TOP VIEW
1
2
3
4
5
VCC
FSSET
VIN
NC
ZSSET
10
9
8
7
6
LTC2401CMS
LTC2401IMS
FO
SCK
SDO
CS
GND
MS10 PART MARKING
MS10 PACKAGE
10-LEAD PLASTIC MSOP
LTMB
LTMC
TJMAX = 125°C, θJA = 130°C/W
VCC
FSSET
CH1
CH0
ZSSET
10
9
8
7
6
1
2
3
4
5
LTC2402CMS
LTC2402IMS
FO
SCK
SDO
CS
GND
MS10 PART MARKING
MS10 PACKAGE
10-LEAD PLASTIC MSOP
LTMD
LTME
TJMAX = 125°C, θJA = 130°C/W
Consult factory for Military grade parts.
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CONVERTER CHARACTERISTICS The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VREF = FSSET – ZSSET. (Notes 3, 4)
PARAMETER
CONDITIONS
Resolution
MIN
●
24
24
No Missing Codes Resolution
0.1V ≤ FSSET ≤ VCC, ZSSET = 0V (Note 5)
●
Integral Nonlinearity
FSSET = 2.5V, ZSSET = 0V (Note 6)
FSSET = 5V, ZSSET = 0V (Note 6)
●
●
Offset Error
2.5V ≤ FSSET ≤ VCC, ZSSET = 0V
●
Offset Error Drift
2.5V ≤ FSSET ≤ VCC, ZSSET = 0V
Full-Scale Error
2.5V ≤ FSSET ≤ VCC, ZSSET = 0V
Full-Scale Error Drift
2.5V ≤ FSSET ≤ VCC, ZSSET = 0V
Total Unadjusted Error
FSSET = 2.5V, ZSSET = 0V
FSSET = 5V, ZSSET = 0V
TYP
MAX
Bits
Bits
2
4
10
15
0.5
2
0.01
4
●
UNITS
0.04
ppm of VREF
ppm of VREF
ppm of VREF
ppm of VREF/°C
10
ppm of VREF
ppm of VREF/°C
5
10
ppm of VREF
ppm of VREF
3
µVRMS
Output Noise
VIN = 0V (Note 13)
Normal Mode Rejection 60Hz ±2%
(Note 7)
●
110
130
dB
Normal Mode Rejection 50Hz ±2%
(Note 8)
●
110
130
dB
Power Supply Rejection, DC
FSSET = 2.5V, ZSSET = 0V, VIN = 0V
100
dB
Power Supply Rejection, 60Hz ±2%
FSSET = 2.5V, ZSSET = 0V, VIN = 0V, (Notes 7, 15)
110
dB
Power Supply Rejection, 50Hz ±2%
FSSET = 2.5V, ZSSET = 0V, VIN = 0V, (Notes 8, 15)
110
dB
2
LTC2401/LTC2402
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A ALOG I PUT A D REFERE CE
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VREF = FSSET – ZSSET. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
VIN
Input Voltage Range
(Note 14)
FSSET
ZSSET
CS(IN)
Input Sampling Capacitance
CS(REF)
Reference Sampling Capacitance
IIN(LEAK)
Input Leakage Current
CS = VCC
●
–10
1
10
nA
IREF(LEAK)
Reference Leakage Current
VREF = 2.5V, CS = VCC
●
– 12
1
12
nA
●
ZSSET – 0.12VREF
Full-Scale Set Range
●
Zero-Scale Set Range
●
TYP
MAX
UNITS
FSSET + 0.12VREF
V
0.1 + ZSSET
VCC
V
0
FSSET – 0.1
V
10
pF
15
pF
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DIGITAL I PUTS A D DIGITAL OUTPUTS
The ● denotes specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
VIH
High Level Input Voltage
CS, FO
2.7V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 3.3V
●
MIN
VIL
Low Level Input Voltage
CS, FO
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
●
VIH
High Level Input Voltage
SCK
2.7V ≤ VCC ≤ 5.5V (Note 9)
2.7V ≤ VCC ≤ 3.3V (Note 9)
●
VIL
Low Level Input Voltage
SCK
4.5V ≤ VCC ≤ 5.5V (Note 9)
2.7V ≤ VCC ≤ 5.5V (Note 9)
●
IIN
Digital Input Current
CS, FO
0V ≤ VIN ≤ VCC
●
IIN
Digital Input Current
SCK
0V ≤ VIN ≤ VCC (Note 9)
●
CIN
Digital Input Capacitance
CS, FO
CIN
Digital Input Capacitance
SCK
(Note 9)
VOH
High Level Output Voltage
SDO
IO = – 800µA
●
VOL
Low Level Output Voltage
SDO
IO = 1.6mA
●
VOH
High Level Output Voltage
SCK
IO = – 800µA (Note 10)
●
VOL
Low Level Output Voltage
SCK
IO = 1.6mA (Note 10)
●
IOZ
High-Z Output Leakage
SDO
●
TYP
MAX
UNITS
2.5
2.0
V
V
0.8
0.6
V
V
2.5
2.0
V
V
0.8
0.6
V
V
–10
10
µA
–10
10
µA
10
pF
10
pF
VCC – 0.5
V
0.4
V
VCC – 0.5
V
–10
0.4
V
10
µA
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POWER REQUIRE E TS
The ● denotes specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
VCC
Supply Voltage
ICC
Supply Current
Conversion Mode
Sleep Mode
CONDITIONS
MIN
●
CS = 0V (Note 12)
CS = VCC (Note 12)
●
●
TYP
2.7
200
20
MAX
UNITS
5.5
V
300
30
µA
µA
3
LTC2401/LTC2402
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TI I G CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
fEOSC
External Oscillator Frequency Range
●
tHEO
External Oscillator High Period
tLEO
External Oscillator Low Period
tCONV
Conversion Time
FO = 0V
FO = VCC
External Oscillator (Note 11)
fISCK
Internal SCK Frequency
Internal Oscillator (Note 10)
External Oscillator (Notes 10, 11)
DISCK
Internal SCK Duty Cycle
(Note 10)
fESCK
External SCK Frequency Range
(Note 9)
●
tLESCK
External SCK Low Period
(Note 9)
●
250
ns
tHESCK
External SCK High Period
(Note 9)
●
250
ns
tDOUT_ISCK
Internal SCK 32-Bit Data Output Time
Internal Oscillator (Notes 10, 12)
External Oscillator (Notes 10, 11)
●
●
1.64
tDOUT_ESCK
External SCK 32-Bit Data Output Time
(Note 9)
●
t1
CS ↓ to SDO Low Z
●
0
150
ns
t2
CS ↑ to SDO High Z
●
0
150
ns
t3
CS ↓ to SCK ↓
(Note 10)
●
0
150
ns
t4
CS ↓ to SCK ↑
(Note 9)
●
50
tKQMAX
SCK ↓ to SDO Valid
tKQMIN
SDO Hold After SCK ↓
●
15
ns
t5
SCK Set-Up Before CS ↓
●
50
ns
t6
SCK Hold After CS ↓
●
MAX
UNITS
2.56
307.2
kHz
●
0.5
390
µs
●
0.5
390
µs
●
●
●
(Note 5)
TYP
130.86
133.53
136.20
157.03
160.23
163.44
20510/fEOSC (in kHz)
19.2
fEOSC/8
45
ms
ms
ms
kHz
kHz
55
%
2000
kHz
1.67
1.70
256/fEOSC (in kHz)
ms
ms
32/fESCK (in kHz)
ms
ns
200
●
Note 1: Absolute Maximum Ratings are those values beyond which the
life of the device may be impaired.
Note 2: All voltage values are with respect to GND.
Note 3: VCC = 2.7 to 5.5V unless otherwise specified. Input source
resistance = 0Ω.
Note 4: Internal Conversion Clock source with the FO pin tied
to GND or to VCC or to external conversion clock source with
fEOSC = 153600Hz unless otherwise specified.
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is defined as the deviation of a code from
a straight line passing through the actual endpoints of the transfer
curve. The deviation is measured from the center of the quantization
band.
Note 7: FO = 0V (internal oscillator) or fEOSC = 153600Hz ±2%
(external oscillator).
Note 8: FO = VCC (internal oscillator) or fEOSC = 128000Hz ±2%
(external oscillator).
4
MIN
50
ns
ns
Note 9: The converter is in external SCK mode of operation such that
the SCK pin is used as digital input. The frequency of the clock signal
driving SCK during the data output is fESCK and is expressed in kHz.
Note 10: The converter is in internal SCK mode of operation such that
the SCK pin is used as digital output. In this mode of operation, the
SCK pin has a total equivalent load capacitance CLOAD = 20pF.
Note 11: The external oscillator is connected to the FO pin. The external
oscillator frequency, fEOSC, is expressed in kHz.
Note 12: The converter uses the internal oscillator.
FO = 0V or FO = VCC.
Note 13: The output noise includes the contribution of the internal
calibration operations.
Note 14: VREF = FSSET – ZSSET. The minimum input voltage is limited
to – 0.3V and the maximum to VCC + 0.3V.
Note 15: VCC (DC) = 4.1V, VCC (AC) = 2.8VP-P.
LTC2401/LTC2402
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TYPICAL PERFOR A CE CHARACTERISTICS
Total Unadjusted Error (3V Supply)
10
Negative Extended Input Range
Total Unadjusted Error (3V Supply)
INL (3V Supply)
10
VCC = 3V
VREF = 2.5V
10
VCC = 3V
VREF = 2.5V
TA = 25°C
TA = 90°C
5
TA = –55°C, –45°C, 25°C, 90°C
0
–5
ERROR (ppm)
5
ERROR (ppm)
ERROR (ppm)
5
0
125°C
–5
TA = 125°C
TA = –45°C
0
TA = –55°C
–5
TA = –55°C, –45°C, 25°C, 90°C
125°C
0.5
0
1.5
2.0
1.0
INPUT VOLTAGE (V)
–10
2.5
0.5
0
1.5
2.0
1.0
INPUT VOLTAGE (V)
2.5
24012 G01
10
10
VCC = 5V
VREF = 5V
–5
2.5
2.55
2.6
2.65
2.7
INPUT VOLTAGE (V)
2.75
–10
2.8
–10
1
0
3
2
INPUT VOLTAGE (V)
–5
10
5
TA = –45°C
TA = –55°C
0
TA = –55°C
TA = –45°C
TA = 125°C
5
Offset Error vs Reference Voltage
VCC = 5V
TA = 25°C
5.0
5.05
5.1
5.15
5.2
INPUT VOLTAGE (V)
30
20
TA = 25°C
–10
24012 G07
4 4.5
10
TA = 90°C
0
1.5 2 2.5 3 3.5
INPUT VOLTAGE (V)
40
VCC = 5V
VREF = 5V
–0.05
0.5 1
24012 G06
VCC = 5V
VREF = 5V
–5
–0.2 –0.15 –0.1
INPUT VOLTAGE (V)
0
50
5
ERROR (ppm)
ERROR (ppm)
TA = 125°C
TA = 25°C
–10
–0.3 –0.25
4
Positive Extended Input Range
Total Unadjusted Error (5V Supply)
10
0
0
24012 G05
Negative Extended Input Range
Total Unadjusted Error (5V Supply)
TA = 90°C
TA = –55°C, –45°C, 25°C, 90°C, 125°C
–5
24012 G04
5
ERROR (ppm)
TA = –55°C, –45°C, 25°C, 90°C, 125°C
–5
–10
VCC = 5V
VREF = 5V
5
0
0
INL (5V Supply)
5
ERROR (ppm)
ERROR (ppm)
5
TA = –55°C, –45°C, 25°C, 90°C, 125°C
–0.05
24012 G03
Total Unadjusted Error (5V Supply)
VCC = 3V
VREF = 2.5V
0
–0.2 –0.15 –0.1
INPUT VOLTAGE (V)
24012 G02
Positive Extended Input Range
Total Unadjusted Error (3V Supply)
10
–10
–0.3 –0.25
3.0
OFFSET ERROR (ppm)
–10
VCC = 3V
VREF = 2.5V
5.25
5.3
24012 G08
0
0
1
3
4
2
REFERENCE VOLTAGE (V)
5
24012 G09
5
LTC2401/LTC2402
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TYPICAL PERFOR A CE CHARACTERISTICS
RMS Noise vs Reference Voltage
VCC = 5V
TA = 25°C
18
16
OFFSET ERROR (ppm)
RMS NOISE (ppm OF VREF)
Offset Error vs VCC
5.0
14
12
10
8
6
RMS Noise vs VCC
5.0
VREF = 2.5V
TA = 25°C
VREF = 2.5V
TA = 25°C
2.5
RMS NOISE (ppm)
20
0
2.5
–2.5
4
2
0
–5.0
1
0
3
4
2
REFERENCE VOLTAGE (V)
2.7
5
3.2
3.7
4.2
4.7
2.7
3.2
3.7
VCC
RMS Noise vs Code Out
1.00
VCC = 5V
VREF = 5V
300 V = 0V
IN
RMS NOISE (ppm)
150
100
5.2
Offset Error vs Temperature
5.0
VCC = 5V
VREF = 5V
VIN = –0.3V TO 5.3V
TA = 25°C
0.75
200
4.7
24012 G12
OFFSET ERROR (ppm)
Noise Histogram
350
250
4.2
VCC
24012 G11
24012 G10
NUMBER OF READINGS
0
5.2
0.50
0.25
VCC = 5V
VREF = 5V
VIN = 0V
2.5
0
–2.5
50
0
–2
–1
0
1
0
–0.3
3
2
2.5
OUTPUT CODE (ppm)
5.3
CODE OUT (HEX)
24012 G13
0
–2.5
5
FULL-SCALE ERROR (ppm)
2.5
40
30
20
0
70
–5
20
45
TEMPERATURE (°C)
95
120
24012 G16
6
VREF = 2.5V
VIN = 2.5V
TA = 25°C
4
3
2
1
10
–5.0
–55 –30
120
Full-Scale Error vs VCC
6
VCC = 5V
VIN = VREF
50
FULL-SCALE ERROR (ppm)
FULL-SCALE ERROR (ppm)
60
95
24012 G15
Full-Scale Error
vs Reference Voltage
VCC = 5V
VREF = 5V
VIN = 5V
70
–5
20
45
TEMPERATURE (°C)
24012 G14
Full-Scale Error vs Temperature
5.0
–5.0
–55 –30
0
1
2
3
4
REFERENCE VOLTAGE (V)
5
24012 G17
0
2.7
3.2
3.7
4.2
VCC
4.7
5.2
24012 G18
LTC2401/LTC2402
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TYPICAL PERFOR A CE CHARACTERISTICS
Conversion Current
vs Temperature
Sleep Current vs Temperature
220
–60
VCC = 4.1V
VIN = 0V
TA = 25°C
FO = 0
VCC = 5.5V
200
VCC = 4.1V
190
180
VCC = 2.7V
170
–75
VCC = 2.7V
20
REJECTION (dB)
210
SUPPLY CURRENT (µA)
SUPPLY CURRENT (µA)
Rejection vs Frequency at VCC
30
230
VCC = 5V
10
–90
–105
160
150
– 55 –30
70
45
20
TEMPERATURE (°C)
–5
95
–120
0
–55 –30
120
–5
20
45
70
TEMPERATURE (°C)
95
Rejection vs Frequency at VCC
–60
VCC = 4.1V
VIN = 0V
TA = 25°C
FO = 0
–75
REJECTION (dB)
REJECTION (dB)
24012 G21
Rejection vs Frequency at VIN
0
VCC = 4.1V
VIN = 0V
TA = 25°C
FO = 0
VCC = 5V
VREF = 5V
VIN = 2.5V
FO = 0
–20
REJECTION (dB)
Rejection vs Frequency at VCC
–40
–80
1M
100
10k
FREQUENCY AT VCC (Hz)
24012 G20
24012 G19
–60
1
120
–90
–40
–60
–80
–105
–100
–100
–120
0
50
150
200
100
FREQUENCY AT VCC (Hz)
250
1
Rejection vs Frequency at VIN
–70
–20
REJECTION (dB)
–80
–110
Rejection vs Frequency at VIN
0
VCC = 5V
VREF = 5V
VIN = 2.5V
FO = 0
–20
–40
–40
REJECTION (dB)
–60
–100
–60
–80
–60
–80
–100
–120
–100
–130
250
100
150
200
FREQUENCY AT VIN (Hz)
24012 G24
Rejection vs Frequency at VIN
0
–90
50
24012 G23
24012 G22
REJECTION (dB)
–120
–120
15200 15250 15300 15350 15400 15450 15500
FREQUENCY AT VCC (Hz)
–120
SAMPLE RATE = 15.36kHz ± 2%
–140
–120
15100
–12
–8
–4
0
4
8
12
INPUT FREQUENCY DEVIATION FROM NOTCH FREQUENCY (%)
24012 G25
15200
15300
15400
FREQUENCY AT VIN (Hz)
15500
–140
0
fS/2
fS
INPUT FREQUENCY
24012 G26
24012 G27
7
LTC2401/LTC2402
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TYPICAL PERFOR A CE CHARACTERISTICS
INL vs Output Rate
Resolution vs Output Rate
24
24
VCC = 5V
VREF = 5V
FO = EXTERNAL
20
16
RESOLUTION (BITS)
INL (BITS)
20
TA = –55°C
TA = 90°C
12
TA = –55°C
TA = 90°C
TA = 25°C
16
12
TA = 25°C
8
0
20
60
40
OUTPUT RATE (Hz)
VCC = 5V
VREF = 5V
FO = EXTERNAL
80
100
24012 G28
8
0
20
60
40
OUTPUT RATE (Hz)
80
100
24012 G29
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PIN FUNCTIONS
VCC (Pin 1): Positive Supply Voltage. Bypass to GND
(Pin␣ 6) with a 10µF tantalum capacitor in parallel with
0.1µF ceramic capacitor as close to the part as possible.
be connected directly to a ground plane through a minimum length trace or it should be the single-point-ground
in a single-point grounding system.
FSSET (Pin 2): Full-Scale Set Input. This pin defines the
full-scale input value. When VIN = FSSET, the ADC outputs
full scale (FFFFFH). The total reference voltage is
FSSET – ZSSET.
CS (Pin 7): Active LOW Digital Input. A LOW on this pin
enables the SDO digital output and wakes up the ADC.
Following each conversion, the ADC automatically enters
the Sleep mode and remains in this low power state as
long as CS is HIGH. A LOW on CS wakes up the ADC. A
LOW-to-HIGH transition on this pin disables the SDO
digital output. A LOW-to-HIGH transition on CS during the
Data Output transfer aborts the data transfer and starts a
new conversion.
CH0, CH1 (Pins 4, 3): Analog Input Channels. The input
voltage range is – 0.125 • VREF to 1.125 • VREF. For
VREF > 2.5V, the input voltage range may be limited by the
absolute maximum rating of – 0.3V to VCC + 0.3V. Conversions are performed alternately between CH0
and CH1 for the LTC2402. Pin 4 is a No Connect (NC) on
the LTC2401.
ZSSET (Pin 5): Zero-Scale Set Input. This pin defines the
zero-scale input value. When VIN = ZSSET, the ADC
outputs zero scale (00000H).
GND (Pin 6): Ground. Shared pin for analog ground,
digital ground, reference ground and signal ground. Should
8
SDO (Pin 8): Three-State Digital Output. During the data
output period, this pin is used for serial data output. When
the chip select CS is HIGH (CS = VCC), the SDO pin is in a
high impedance state. During the Conversion and Sleep
periods, this pin can be used as a conversion status output. The conversion status can be observed by pulling CS
LOW.
LTC2401/LTC2402
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PIN FUNCTIONS
SCK (Pin 9): Bidirectional Digital Clock Pin. In the Internal
Serial Clock Operation mode, SCK is used as digital output
for the internal serial interface clock during the data output
period. In the External Serial Clock Operation mode, SCK
is used as digital input for the external serial interface. An
internal pull-up current source is automatically activated
in Internal Serial Clock Operation mode. The Serial Clock
mode is determined by the level applied to SCK at power
up and the falling edge of CS.
FO (Pin 10): Frequency Control Pin. Digital input that
controls the ADC’s notch frequencies and conversion
time. When the FO pin is connected to VCC (FO = VCC), the
converter uses its internal oscillator and the digital filter’s
first null is located at 50Hz. When the FO pin is connected
to GND (FO = 0V), the converter uses its internal oscillator
and the digital filter’s first null is located at 60Hz. When FO
is driven by an external clock signal with a frequency fEOSC,
the converter uses this signal as its clock and the digital
filter first null is located at a frequency fEOSC/2560.
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FUNCTIONAL BLOCK DIAGRA
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INTERNAL
OSCILLATOR
VCC
GND
VIN
AUTOCALIBRATION
AND CONTROL
∫
∫
FO
(INT/EXT)
∫
∑
SDO
SERIAL
INTERFACE
ADC
SCK
CS
VREF
DECIMATING FIR
DAC
24012 FD
TEST CIRCUITS
VCC
3.4k
SDO
SDO
3.4k
Hi-Z TO VOH
VOL TO VOH
VOH TO Hi-Z
CLOAD = 20pF
24012 TC01
CLOAD = 20pF
Hi-Z TO VOL
VOH TO VOL
VOL TO Hi-Z
24012 TC02
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Converter Operation Cycle
The LTC2401/LTC2402 are low power, delta-sigma analog-to-digital converters with an easy to use 3-wire serial
interface. Their operation is simple and made up of three
states. The converter operating cycle begins with the
conversion, followed by a low power sleep state and
concluded with the data output (see Figure 1). The 3-wire
interface consists of serial data output (SDO), a serial
clock (SCK) and a chip select (CS).
Initially, the LTC2401/LTC2402 perform a conversion.
Once the conversion is complete, the device enters the
sleep state. While in this sleep state, power consumption
is reduced by an order of magnitude. The part remains in
the sleep state as long as CS is logic HIGH. The conversion
result is held indefinitely in a static shift register while the
converter is in the sleep state.
Once CS is pulled low, the device begins outputting the
conversion result. There is no latency in the conversion
result. The data output corresponds to the conversion just
performed. This result is shifted out on the serial data out
pin (SDO) under the control of the serial clock (SCK). Data
is updated on the falling edge of SCK allowing the user to
reliably latch data on the rising edge of SCK, see Figure 3.
The data output state is concluded once 32 bits are read
out of the ADC or when CS is brought HIGH. The device
automatically initiates a new conversion cycle and the
cycle repeats.
Through timing control of the CS and SCK pins, the
LTC2401/LTC2402 offer several flexible modes of operation (internal or external SCK and free-running conversion
modes). These various modes do not require programming configuration registers; moreover, they do not disturb the cyclic operation described above. These modes of
operation are described in detail in the Serial Interface
Timing Modes section.
Conversion Clock
A major advantage delta-sigma converters offer over
conventional type converters is an on-chip digital filter
(commonly known as Sinc or Comb filter). For high
resolution, low frequency applications, this filter is typically designed to reject line frequencies of 50Hz or 60Hz
plus their harmonics. In order to reject these frequencies
in excess of 110dB, a highly accurate conversion clock is
required. The LTC2401/LTC2402 incorporate an on-chip
highly accurate oscillator. This eliminates the need for
external frequency setting components such as crystals or
oscillators. Clocked by the on-chip oscillator, the LTC2401/
LTC2402 reject line frequencies (50Hz or 60Hz ±2%) a
minimum of 110dB.
Ease of Use
The LTC2401/LTC2402 data output has no latency, filter
settling or redundant data associated with the conversion
cycle. There is a one-to-one correspondence between the
conversion and the output data. Therefore, multiplexing
an analog input voltage is easy.
CONVERT
SLEEP
1
CS AND
SCK
The LTC2401/LTC2402 perform offset and full-scale calibrations every conversion cycle. This calibration is transparent to the user and has no effect on the cyclic operation
described above. The advantage of continuous calibration
is extreme stability of offset and full-scale readings with
respect to time, supply voltage change and temperature
drift.
0
DATA OUTPUT
24012 F01
Figure 1. LTC2401/LTC2402 State Transition Diagram
10
Power-Up Sequence
The LTC2401/LTC2402 automatically enter an internal
reset state when the power supply voltage VCC drops
below approximately 2.2V. This feature guarantees the
LTC2401/LTC2402
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integrity of the conversion result and of the serial interface
mode selection which is performed at the initial power-up.
(See the 2-wire I/O sections in the Serial Interface Timing
Modes section.)
When the VCC voltage rises above this critical threshold,
the converter creates an internal power-on-reset (POR)
signal with duration of approximately 0.5ms. The POR
signal clears all internal registers. Following the POR
signal, the LTC2401/LTC2402 start a normal conversion
cycle and follows the normal succession of states described above. The first conversion result following POR
is accurate within the specifications of the device.
VCC + 0.3V
FSSET + 0.12VREF
FSSET
NORMAL
INPUT
RANGE
EXTENDED
INPUT
RANGE
ABSOLUTE
MAXIMUM
INPUT
RANGE
ZSSET
ZSSET – 0.12VREF
–0.3V
(VREF = FSSET – ZSSET)
24012 F02
Figure 2. LTC2401/LTC2402 Input Range
Reference Voltage Range
The LTC2401/LTC2402 can accept a reference voltage
(VREF = FSSET – ZSSET) from 0V to VCC. The converter
output noise is determined by the thermal noise of the
front-end circuits, and as such, its value in microvolts is
nearly constant with reference voltage. A decrease in
reference voltage will not significantly improve the
converter’s effective resolution. On the other hand, a
reduced reference voltage will improve the overall converter INL performance. The recommended range for the
LTC2401/LTC2402 voltage reference is 100mV to VCC.
the parasitic capacitance of the connection between this
series resistance and the VIN pin as low as possible;
therefore, the resistor should be located as close as
practical to the VIN pin. The effect of the series resistance
on the converter accuracy can be evaluated from the
curves presented in the Analog Input/Reference Current
section. In addition, a series resistor will introduce a
temperature dependent offset error due to the input leakage current. A 1nA input leakage current will develop a
1ppm offset error on a 5k resistor if VREF = 5V. This error
has a very strong temperature dependency.
Input Voltage Range
The converter is able to accommodate system level
offset and gain errors as well as system level overrange
situations due to its extended input range, see Figure 2.
The LTC2401/LTC2402 convert input signals within the
extended input range of – 0.125 • VREF to 1.125 • VREF
(VREF = FSSET – ZSSET).
For large values of VREF (VREF = FSSET – ZSSET), this range
is limited by the absolute maximum voltage range of
– 0.3V to (VCC + 0.3V). Beyond this range, the input ESD
protection devices begin to turn on and the errors due to
the input leakage current increase rapidly.
Input signals applied to VIN may extend below ground by
– 300mV and above VCC by 300mV. In order to limit any
fault current, a resistor of up to 5k may be added in series
with the VIN pin without affecting the performance of the
device. In the physical layout, it is important to maintain
Output Data Format
The LTC2401/LTC2402 serial output data stream is 32 bits
long. The first 4 bits represent status information indicating the sign, selected channel, input range and conversion
state. The next 24 bits are the conversion result, MSB first.
The remaining 4 bits are sub LSBs beyond the 24-bit level
that may be included in averaging or discarded without
loss of resolution.
Bit 31 (first output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
This bit is HIGH during the conversion and goes LOW when
the conversion is complete.
Bit 30 (second output bit) for the LTC2402, this bit is LOW
if the last conversion was performed on CH0 and HIGH for
CH1. This bit is always low for the LTC2401.
11
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Bit 29 (third output bit) is the conversion result sign indicator (SIG). If VIN is >0, this bit is HIGH. If VIN is <0, this
bit is LOW. The sign bit changes state during the zero code.
Bit 28 (forth output bit) is the extended input range (EXR)
indicator. If the input is within the normal input range
0␣ ≤␣ VIN ≤ VREF, this bit is LOW. If the input is outside the
normal input range, VIN > VREF or VIN < 0, this bit is HIGH.
The function of these bits is summarized in Table 1.
Table 1. LTC2401/LTC2402 Status Bits
Bit 31
EOC
Bit 30
CH0/CH1
Bit 29
SIG
Bit 28
EXR
VIN > VREF
0
0/1
1
1
0 < VIN ≤ VREF
0
0/1
1
0
VIN = 0+/0 –
0
0/1
1/0
0
VIN < 0
0
0/1
0
1
Input Range
Bit 27 (fifth output bit) is the most significant bit (MSB).
Bits 27-4 are the 24-bit conversion result MSB first.
Bit 4 is the least significant bit (LSB).
Bits 3-0 are sub LSBs below the 24-bit level. Bits 3-0 may
be included in averaging or discarded without loss of
resolution.
Data is shifted out of the SDO pin under control of the serial
clock (SCK), see Figure 3. Whenever CS is HIGH, SDO
remains high impedance and any SCK clock pulses are
ignored by the internal data out shift register.
In order to shift the conversion result out of the device, CS
must first be driven LOW. EOC is seen at the SDO pin of the
device once CS is pulled LOW. EOC changes real time from
HIGH to LOW at the completion of a conversion. This
signal may be used as an interrupt for an external microcontroller. Bit 31 (EOC) can be captured on the first rising
edge of SCK. Bit 30 is shifted out of the device on the first
falling edge of SCK. The final data bit (Bit 0) is shifted out
on the falling edge of the 31st SCK and may be latched on
the rising edge of the 32nd SCK pulse. On the falling edge
of the 32nd SCK pulse, SDO goes HIGH indicating a new
conversion cycle has been initiated. This bit serves as EOC
(Bit 31) for the next conversion cycle. Table 2 summarizes
the output data format.
As long as the voltage on the VIN pin is maintained within
the – 0.3V to (VCC + 0.3V) absolute maximum operating
range, a conversion result is generated for any input value
from – 0.125 • VREF to 1.125 • VREF. For input voltages
greater than 1.125 • VREF, the conversion result is clamped
to the value corresponding to 1.125 • VREF. For input
voltages below – 0.125 • VREF, the conversion result is
clamped to the value corresponding to – 0.125 • VREF.
Frequency Rejection Selection (FO Pin Connection)
The LTC2401/LTC2402 internal oscillator provides better
than 110dB normal mode rejection at the line frequency
and all its harmonics for 50Hz ±2% or 60Hz ±2%. For
60Hz rejection, FO (Pin 10) should be connected to GND
(Pin 6) while for 50Hz rejection the FO pin should be
connected to VCC (Pin␣ 1).
The selection of 50Hz or 60Hz rejection can also be made
by driving FO to an appropriate logic level. A selection
change during the sleep or data output states will not
CS
SDO
BIT 31
BIT 30
BIT 29
BIT 28
BIT 27
BIT 4
EOC
CH0/CH1
SIG
EXT
MSB
LSB24
BIT 0
Hi-Z
SCK
1
SLEEP
2
3
4
5
DATA OUTPUT
27
28
32
CONVERSION
24012 F03
Figure 3. Output Data Timing
12
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Table 2. LTC2401/LTC2402 Output Data Format
Bit 31
EOC
Bit 30
CH SELECT
Bit 29
SIG
Bit 28
EXR
Bit 27
MSB
Bit 26
Bit 25
Bit 24
Bit 23
…
Bit 4
LSB
Bit 3-0
SUB LSBs*
VIN > 9/8 • VREF
0
CH0/CH1
1
1
0
0
0
1
1
...
1
X
9/8 • VREF
0
CH0/CH1
1
1
0
0
0
1
1
...
1
X
VREF + 1LSB
0
CH0/CH1
1
1
0
0
0
0
0
...
0
X
VREF
0
CH0/CH1
1
0
1
1
1
1
1
...
1
X
3/4VREF + 1LSB
0
CH0/CH1
1
0
1
1
0
0
0
...
0
X
3/4VREF
0
CH0/CH1
1
0
1
0
1
1
1
...
1
X
Input Voltage
1/2VREF + 1LSB
0
CH0/CH1
1
0
1
0
0
0
0
...
0
X
1/2VREF
0
CH0/CH1
1
0
0
1
1
1
1
...
1
X
1/4VREF + 1LSB
0
CH0/CH1
1
0
0
1
0
0
0
...
0
X
1/4VREF
0
CH0/CH1
1
0
0
0
1
1
1
...
1
X
0+/0 –
0
CH0/CH1
1/0**
0
0
0
0
0
0
...
0
X
–1LSB
0
CH0/CH1
0
1
1
1
1
1
1
...
1
X
–1/8 • VREF
0
CH0/CH1
0
1
1
1
1
0
0
...
0
X
VIN < –1/8 • VREF
0
CH0/CH1
0
1
1
1
1
0
0
...
0
X
*The sub LSBs are valid conversion results beyond the 24-bit level that may be included in averaging or discarded without loss of resolution.
**The sign bit changes state during the 0 code.
When a fundamental rejection frequency different from
50Hz or 60Hz is required or when the converter must be
synchronized with an outside source, the LTC2401/
LTC2402 can operate with an external conversion clock.
The converter automatically detects the presence of an
external clock signal at the FO pin and turns off the internal
oscillator. The frequency fEOSC of the external signal must
be at least 2560Hz (1Hz notch frequency) to be detected.
The external clock signal duty cycle is not significant as
long as the minimum and maximum specifications for the
high and low periods tHEO and tLEO are observed.
While operating with an external conversion clock of a
frequency fEOSC, the LTC2401/LTC2402 provide better
than 110dB normal mode rejection in a frequency range
fEOSC/2560 ±4% and its harmonics. The normal mode
rejection as a function of the input frequency deviation
from fEOSC/2560 is shown in Figure 4.
Whenever an external clock is not present at the FO pin, the
converter automatically activates its internal oscillator and
enters the Internal Conversion Clock mode. The LTC2401/
LTC2402 operation will not be disturbed if the change of
conversion clock source occurs during the sleep state or
during the data output state while the converter uses an
–60
–70
–80
REJECTION (dB)
disturb the converter operation. If the selection is made
during the conversion state, the result of the conversion in
progress may be outside specifications but the following
conversions will not be affected.
–90
–100
–110
–120
–130
–140
–12
–8
–4
0
4
8
12
INPUT FREQUENCY DEVIATION FROM NOTCH FREQUENCY (%)
24012 F04
Figure 4. LTC2401/LTC2402 Normal Mode Rejection When
Using an External Oscillator of Frequency fEOSC
13
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external serial clock. If the change occurs during the
conversion state, the result of the conversion in progress
may be outside specifications but the following conversions will not be affected. If the change occurs during the
data output state and the converter is in the Internal SCK
mode, the serial clock duty cycle may be affected but the
serial data stream will remain valid.
input. The internal or external SCK mode is selected on
power-up and then reselected every time a HIGH-to-LOW
transition is detected at the CS pin. If SCK is HIGH or floating at power-up or during this transition, the converter
enters the internal SCK mode. If SCK is LOW at power-up
or during this transition, the converter enters the external
SCK mode.
Table 3 summarizes the duration of each state as a
function of FO.
Serial Data Output (SDO)
SERIAL INTERFACE
The LTC2401/LTC2402 transmit the conversion results
and receives the start of conversion command through a
synchronous 3-wire interface. During the conversion and
sleep states, this interface can be used to assess the
converter status and during the data output state it is used
to read the conversion result.
Serial Clock Input/Output (SCK)
The serial clock signal present on SCK (Pin 9) is used to
synchronize the data transfer. Each bit of data is shifted out
the SDO pin on the falling edge of the serial clock.
In the Internal SCK mode of operation, the SCK pin is an
output and the LTC2401/LTC2402 create their own serial
clock by dividing the internal conversion clock by 8. In the
External SCK mode of operation, the SCK pin is used as
The serial data output pin, SDO (Pin 8), drives the serial
data during the data output state. In addition, the SDO pin
is used as an end of conversion indicator during the
conversion and sleep states.
When CS (Pin 7) is HIGH, the SDO driver is switched to a
high impedance state. This allows sharing the serial
interface with other devices. If CS is LOW during the
convert or sleep state, SDO will output EOC. If CS is LOW
during the conversion phase, the EOC bit appears HIGH on
the SDO pin. Once the conversion is complete, EOC goes
LOW. The device remains in the sleep state until the first
rising edge of SCK occurs while CS = 0.
Chip Select Input (CS)
The active LOW chip select, CS (Pin 7), is used to test the
conversion status and to enable the data output transfer as
described in the previous sections.
Table 3. LTC2401/LTC2402 State Duration
State
Operating Mode
CONVERT
Internal Oscillator
External Oscillator
Duration
FO = LOW
(60Hz Rejection)
133ms
FO = HIGH
(50Hz Rejection)
160ms
FO = External Oscillator
with Frequency fEOSC kHz
(fEOSC/2560 Rejection)
20510/fEOSCs
SLEEP
DATA OUTPUT
As Long As CS = HIGH Until CS = 0 and SCK
Internal Serial Clock
External Serial Clock with
Frequency fSCK kHz
14
FO = LOW/HIGH
(Internal Oscillator)
As Long As CS = LOW But Not Longer Than 1.67ms
(32 SCK cycles)
FO = External Oscillator with
Frequency fEOSC kHz
As Long As CS = LOW But Not Longer Than 256/fEOSCms
(32 SCK cycles)
As Long As CS = LOW But Not Longer Than 32/fSCKms
(32 SCK cycles)
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In addition, the CS signal can be used to trigger a new
conversion cycle before the entire serial data transfer has
been completed. The LTC2401/LTC2402 will abort any
serial data transfer in progress and start a new conversion
cycle anytime a LOW-to-HIGH transition is detected at the
CS pin after the converter has entered the data output state
(i.e., after the first rising edge of SCK occurs with CS = 0).
Finally, CS can be used to control the free-running modes
of operation, see Serial Interface Timing Modes section.
Grounding CS will force the ADC to continuously convert
at the maximum output rate selected by FO. Tying a
capacitor to CS will reduce the output rate and power
dissipation by a factor proportional to the capacitor’s
value, see Figures 12 to 14.
SERIAL INTERFACE TIMING MODES
The LTC2401/LTC2402’s 3-wire interface is SPI and
MICROWIRE compatible. This interface offers several
flexible modes of operation. These include internal/external serial clock, 2- or 3-wire I/O, single cycle conversion
and autostart. The following sections describe each of
these serial interface timing modes in detail. In all these
cases, the converter can use the internal oscillator (FO =
LOW or FO = HIGH) or an external oscillator connected to
the FO pin. Refer to Table 4 for a summary.
External Serial Clock, Single Cycle Operation
(SPI/MICROWIRE Compatible)
This timing mode uses an external serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 5.
The serial clock mode is selected on the falling edge of CS.
To select the external serial clock mode, the serial clock pin
(SCK) must be LOW during each CS falling edge.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
While CS is pulled LOW, EOC is output to the SDO pin. EOC
= 1 while a conversion is in progress and EOC = 0 if the
device is in the sleep state. Independent of CS, the device
automatically enters the low power sleep state once the
conversion is complete.
When the device is in the sleep state (EOC = 0), its
conversion result is held in an internal static shift register.
The device remains in the sleep state until the first rising
edge of SCK is seen while CS is LOW. Data is shifted out
the SDO pin on each falling edge of SCK. This enables
external circuitry to latch the output on the rising edge of
SCK. EOC can be latched on the first rising edge of SCK
and the last bit of the conversion result can be latched on
the 32nd rising edge of SCK. On the 32nd falling edge of
SCK, the device begins a new conversion. SDO goes HIGH
(EOC = 1) indicating a conversion is in progress.
At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
Alternatively, CS may be driven HIGH setting SDO to Hi-Z.
As described above, CS may be pulled LOW at any time in
order to monitor the conversion status.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first rising edge and the
32nd falling edge of SCK, see Figure 6. On the rising edge
Table 4. LTC2401/LTC2402 Interface Timing Modes
SCK
Source
Conversion
Cycle
Control
Data
Output
Control
Connection
and
Waveforms
External SCK, Single Cycle Conversion
External
CS and SCK
CS and SCK
Figures 5, 6
External SCK, 2-Wire I/O
External
SCK
SCK
Figure 7
Internal SCK, Single Cycle Conversion
Internal
CS ↓
CS ↓
Figures 8, 9
Internal SCK, 2-Wire I/O, Continuous Conversion
Internal
Continuous
Internal
Figure 10
Internal SCK, Autostart Conversion
Internal
CEXT
Internal
Figure 11
Configuration
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2.7V TO 5.5V
VCC
1µF
1
VCC
FO
= INTERNAL OSC/50Hz REJECTION
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/60Hz REJECTION
10
LTC2402
REFERENCE VOLTAGE
ZSSET + 0.1V TO VCC
2
3
ANALOG INPUT RANGE
ZSSET – 0.12VREF TO
FSSET + 0.12VREF
(VREF = FSSET – ZSSET)
4
0V TO FSSET – 100mV
5
FSSET
SCK
CH1
SDO
CH0
CS
ZSSET
GND
9
8
3-WIRE
SERIAL I/O
7
6
CS
TEST EOC
TEST EOC
BIT 31
BIT 30
EOC
CH0/CH1
SDO
Hi-Z
BIT 29
BIT 28
BIT 27
EXR
MSB
BIT 26
TEST EOC
BIT 4
BIT 0
LSB
SUB LSB
Hi-Z
Hi-Z
SCK
(EXTERNAL)
CONVERSION
SLEEP
DATA OUTPUT
CONVERSION
24012 F05
Figure 5. External Serial Clock, Single Cycle Operation
2.7V TO 5.5V
VCC
1µF
1
VCC
FO
= INTERNAL OSC/50Hz REJECTION
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/60Hz REJECTION
10
LTC2402
REFERENCE VOLTAGE
ZSSET + 0.1V TO VCC
2
3
ANALOG INPUT RANGE
ZSSET – 0.12VREF TO
FSSET + 0.12VREF
(VREF = FSSET – ZSSET)
4
0V TO FSSET – 100mV
5
FSSET
SCK
CH1
SDO
CH0
CS
ZSSET
GND
9
8
3-WIRE
SERIAL I/O
7
6
CS
BIT 0
SDO
TEST EOC
TEST EOC
EOC
Hi-Z
Hi-Z
BIT 31
BIT 30
BIT 29
BIT 28
BIT 27
EOC
CH0/CH1
SIG
EXR
MSB
Hi-Z
BIT 9
TEST EOC
BIT 8
Hi-Z
SCK
(EXTERNAL)
SLEEP
CONVERSION
SLEEP
DATA OUTPUT
DATA OUTPUT
Figure 6. External Serial Clock, Reduced Data Output Length
16
CONVERSION
24012 F06
LTC2401/LTC2402
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of CS, the device aborts the data output state and immediately initiates a new conversion. This is useful for
systems not requiring all 32 bits of output data, aborting
an invalid conversion cycle or synchronizing the start of a
conversion.
progress and EOC = 0 once the conversion enters the low
power sleep state. On the falling edge of EOC, the conversion result is loaded into an internal static shift register.
The device remains in the sleep state until the first rising
edge of SCK. Data is shifted out the SDO pin on each
falling edge of SCK enabling external circuitry to latch
data on the rising edge of SCK. EOC can be latched on the
first rising edge of SCK. On the 32nd falling edge of SCK,
SDO goes HIGH (EOC = 1) indicating a new conversion
has begun.
External Serial Clock, 2-Wire I/O
This timing mode utilizes a 2-wire serial I/O interface. The
conversion result is shifted out of the device by an externally generated serial clock (SCK) signal, see Figure 7. CS
may be permanently tied to ground (Pin 6), simplifying the
user interface or isolation barrier.
Internal Serial Clock, Single Cycle Operation
This timing mode uses an internal serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 8.
The external serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 0.5ms after VCC exceeds 2.2V. The level
applied to SCK at this time determines if SCK is internal or
external. SCK must be driven LOW prior to the end of POR
in order to enter the external serial clock timing mode.
In order to select the internal serial clock timing mode, the
serial clock pin (SCK) must be floating (Hi-Z) or pulled
HIGH prior to the falling edge of CS. The device will not
enter the internal serial clock mode if SCK is driven LOW
on the falling edge of CS. An internal weak pull-up resistor
is active on the SCK pin during the falling edge of CS;
therefore, the internal serial clock timing mode is automatically selected if SCK is not externally driven.
Since CS is tied LOW, the end-of-conversion (EOC) can
be continuously monitored at the SDO pin during the
convert and sleep states. EOC may be used as an interrupt to an external controller indicating the conversion
result is ready. EOC = 1 while the conversion is in
2.7V TO 5.5V
VCC
1µF
1
VCC
FO
= INTERNAL OSC/50Hz REJECTION
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/60Hz REJECTION
10
LTC2402
REFERENCE VOLTAGE
ZSSET + 0.1V TO VCC
ANALOG INPUT RANGE
ZSSET – 0.12VREF TO
FSSET + 0.12VREF
(VREF = FSSET – ZSSET)
0V TO FSSET – 100mV
2
3
4
5
FSSET
SCK
CH1
SDO
CH0
CS
ZSSET
GND
9
2-WIRE SERIAL I/O
8
7
6
CS
SDO
BIT 31
BIT 30
BIT 29
BIT 28
BIT 27
EOC
CH0/CH1
SIG
EXR
MSB
BIT 26
BIT 4
BIT 0
LSB24
SCK
(EXTERNAL)
CONVERSION
SLEEP
DATA OUTPUT
CONVERSION
24012 F07
Figure 7. External Serial Clock, CS = 0 Operation
17
LTC2401/LTC2402
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VCC
2.7V TO 5.5V
VCC
1µF
1
VCC
FO
10
LTC2402
2
REFERENCE VOLTAGE
ZSSET + 0.1V TO VCC
3
ANALOG INPUT RANGE
ZSSET – 0.12VREF TO
FSSET + 0.12VREF
(VREF = FSSET – ZSSET)
4
5
0V TO FSSET – 100mV
FSSET
SCK
CH1
SDO
CH0
CS
ZSSET
GND
= INTERNAL OSC/50Hz REJECTION
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/60Hz REJECTION
10k
9
8
7
6
<tEOCtest
CS
TEST EOC
SDO
Hi-Z
BIT 31
BIT 30
BIT 29
BIT 28
BIT 27
EOC
CH0/CH1
SIG
EXR
MSB
BIT 26
BIT 4
BIT 0
TEST EOC
LSB24
Hi-Z
Hi-Z
Hi-Z
SCK
(INTERNAL)
CONVERSION
SLEEP
DATA OUTPUT
CONVERSION
2400 F08
Figure 8. Internal Serial Clock, Single Cycle Operation
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while a conversion is in progress
and EOC = 0 if the device is in the sleep state.
When testing EOC, if the conversion is complete (EOC = 0),
the device will exit the sleep state and enter the data output
state if CS remains LOW. In order to prevent the device
from exiting the low power sleep state, CS must be pulled
HIGH before the first rising edge of SCK. In the internal
SCK timing mode, SCK goes HIGH and the device begins
outputting data at time tEOCtest after the falling edge of CS
(if EOC = 0) or tEOCtest after EOC goes LOW (if CS is LOW
during the falling edge of EOC). The value of tEOCtest is 23µs
if the device is using its internal oscillator (F0 = logic LOW
or HIGH). If FO is driven by an external oscillator of
frequency fEOSC, then tEOCtest is 3.6/fEOSC. If CS is pulled
HIGH before time tEOCtest, the device remains in the sleep
state. The conversion result is held in the internal static
shift register.
18
If CS remains LOW longer than tEOCtest, the first rising
edge of SCK will occur and the conversion result is serially
shifted out of the SDO pin. The data output cycle begins on
this first rising edge of SCK and concludes after the 32nd
rising edge. Data is shifted out the SDO pin on each falling
edge of SCK. The internally generated serial clock is output
to the SCK pin. This signal may be used to shift the
conversion result into external circuitry. EOC can be
latched on the first rising edge of SCK and the last bit of the
conversion result on the 32nd rising edge of SCK. After the
32nd rising edge, SDO goes HIGH (EOC = 1), SCK stays
HIGH, and a new conversion starts.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first and 32nd rising edge
of SCK, see Figure 9. On the rising edge of CS, the device
aborts the data output state and immediately initiates a
new conversion. This is useful for systems not requiring
all 32 bits of output data, aborting an invalid conversion
cycle, or synchronizing the start of a conversion. If CS is
pulled HIGH while the converter is driving SCK LOW, the
LTC2401/LTC2402
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VCC
2.7V TO 5.5V
VCC
1µF
1
VCC
FO
10
LTC2402
REFERENCE VOLTAGE
ZSSET + 0.1V TO VCC
ANALOG INPUT RANGE
ZSSET – 0.12VREF TO
FSSET + 0.12VREF
(VREF = FSSET – ZSSET)
0V TO FSSET – 100mV
> tEOCtest
2
3
4
5
FSSET
SCK
CH1
SDO
CH0
CS
ZSSET
GND
= INTERNAL OSC/50Hz REJECTION
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/60Hz REJECTION
10k
9
8
7
6
<tEOCtest
CS
TEST EOC
BIT 0
SDO
TEST EOC
EOC
Hi-Z
Hi-Z
Hi-Z
BIT 31
BIT 30
BIT 29
BIT 28
BIT 27
EOC
CH0/CH1
SIG
EXR
MSB
BIT 26
Hi-Z
BIT 8
TEST EOC
Hi-Z
SCK
(INTERNAL)
SLEEP
CONVERSION
SLEEP
DATA OUTPUT
CONVERSION
24012 F09
DATA OUTPUT
Figure 9. Internal Serial Clock, Reduced Data Output Length
internal pull-up is not available to restore SCK to a logic
HIGH state. This will cause the device to exit the internal
serial clock mode on the next falling edge of CS. This can
be avoided by adding an external 10k pull-up resistor to
the SCK pin or by never pulling CS HIGH when SCK is
LOW.
Whenever SCK is LOW, the LTC2401/LTC2402’s internal
pull-up at pin SCK is disabled. Normally, SCK is not
externally driven if the device is in the internal SCK timing
mode. However, certain applications may require an external driver on SCK. If this driver goes Hi-Z after outputting a LOW signal, the LTC2401/LTC2402’s internal pullup remains disabled. Hence, SCK remains LOW. On the
next falling edge of CS, the device is switched to the
external SCK timing mode. By adding an external 10k pullup resistor to SCK, this pin goes HIGH once the external
driver goes Hi-Z. On the next CS falling edge, the device
will remain in the internal SCK timing mode.
A similar situation may occur during the sleep state when
CS is pulsed HIGH-LOW-HIGH in order to test the conversion status. If the device is in the sleep state (EOC = 0), SCK
will go LOW. Once CS goes HIGH (within the time period
defined above as tEOCtest), the internal pull-up is activated.
For a heavy capacitive load on the SCK pin, the internal
pull-up may not be adequate to return SCK to a HIGH level
before CS goes low again. This is not a concern under
normal conditions where CS remains LOW after detecting
EOC = 0. This situation is easily overcome by adding an
external 10k pull-up resistor to the SCK pin.
Internal Serial Clock, 2-Wire I/O,
Continuous Conversion
This timing mode uses a 2-wire, all output (SCK and SDO)
interface. The conversion result is shifted out of the device
by an internally generated serial clock (SCK) signal, see
Figure 10. CS may be permanently tied to ground (Pin 6),
simplifying the user interface or isolation barrier.
19
LTC2401/LTC2402
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VCC
2.7V TO 5.5V
VCC
1µF
1
VCC
FO
10
LTC2402
REFERENCE VOLTAGE
ZSSET + 0.1V TO VCC
ANALOG INPUT RANGE
ZSSET – 0.12VREF TO
FSSET + 0.12VREF
(VREF = FSSET – ZSSET)
0V TO FSSET – 100mV
2
3
4
5
FSSET
SCK
CH1
SDO
CH0
CS
ZSSET
GND
= INTERNAL OSC/50Hz REJECTION
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/60Hz REJECTION
10k
9
8
7
6
CS
SDO
BIT 31
BIT 30
BIT 29
BIT 28
BIT 27
EOC
CH0/CH1
SIG
EXR
MSB
BIT 26
BIT 4
BIT 0
LSB24
SCK
(INTERNAL)
CONVERSION
DATA OUTPUT
CONVERSION
24012 F10
SLEEP
Figure 10. Internal Serial Clock, Continuous Operation
The internal serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 0.5ms after VCC exceeds 2.2V. An internal
weak pull-up is active during the POR cycle; therefore, the
internal serial clock timing mode is automatically selected
if SCK is not externally driven LOW (if SCK is loaded such
that the internal pull-up cannot pull the pin HIGH, the
external SCK mode will be selected).
During the conversion, the SCK and the serial data output
pin (SDO) are HIGH (EOC = 1). Once the conversion is
complete, SCK and SDO go LOW (EOC = 0) indicating the
conversion has finished and the device has entered the
low power sleep state. The part remains in the sleep state
a minimum amount of time (1/2 the internal SCK period)
then immediately begins outputting data. The data output
cycle begins on the first rising edge of SCK and ends after
the 32nd rising edge. Data is shifted out the SDO pin on
each falling edge of SCK. The internally generated serial
clock is output to the SCK pin. This signal may be used
to shift the conversion result into external circuitry. EOC
can be latched on the first rising edge of SCK and the last
bit of the conversion result can be latched on the 32nd
20
rising edge of SCK. After the 32nd rising edge, SDO goes
HIGH (EOC = 1) indicating a new conversion is in progress.
SCK remains HIGH during the conversion.
Internal Serial Clock, Autostart Conversion
This timing mode is identical to the internal serial clock,
2-wire I/O described above with one additional feature.
Instead of grounding CS, an external timing capacitor is
tied to CS.
While the conversion is in progress, the CS pin is held
HIGH by an internal weak pull-up. Once the conversion is
complete, the device enters the low power sleep state and
an internal 25nA current source begins discharging the
capacitor tied to CS, see Figure 11. The time the converter
spends in the sleep state is determined by the value of the
external timing capacitor, see Figures 12 and 13. Once the
voltage at CS falls below an internal threshold (≈1.4V), the
device automatically begins outputting data. The data
output cycle begins on the first rising edge of SCK and
ends on the 32nd rising edge. Data is shifted out the SDO
pin on each falling edge of SCK. The internally generated
serial clock is output to the SCK pin. This signal may be
LTC2401/LTC2402
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VCC
2.7V TO 5.5V
VCC
1µF
1
VCC
FO
= INTERNAL OSC/50Hz REJECTION
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/60Hz REJECTION
10
LTC2402
REFERENCE VOLTAGE
ZSSET + 0.1V TO VCC
ANALOG INPUT RANGE
ZSSET – 0.12VREF TO
FSSET + 0.12VREF
(VREF = FSSET – ZSSET)
0V TO FSSET – 100mV
2
3
4
5
FSSET
SCK
CH1
SDO
CH0
CS
ZSSET
GND
10k
9
8
7
CEXT
6
VCC
CS
GND
SDO
BIT 31
BIT 30
BIT 29
EOC
CH0/CH1
SIG
BIT 0
Hi-Z
Hi-Z
SCK
(INTERNAL)
CONVERSION
SLEEP
DATA OUTPUT
CONVERSION
24012 F11
Figure 11. Internal Serial Clock, Autostart Operation
7
8
6
7
6
SAMPLE RATE (Hz)
tSAMPLE (SEC)
5
4
3
2
VCC = 5V
5
VCC = 3V
4
3
2
VCC = 5V
1
1
VCC = 3V
0
1
10
100
1000
10000
CAPACITANCE ON CS (pF)
100000
24012 F12
Figure 12. CS Capacitance vs tSAMPLE
0
0
10
100
10000 100000
1000
CAPACITANCE ON CS (pF)
24012 F13
Figure 13. CS Capacitance vs Output Rate
21
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used to shift the conversion result into external circuitry.
After the 32nd rising edge, CS is pulled HIGH and a new
conversion is immediately started. This is useful in applications requiring periodic monitoring and ultralow power.
Figure 14 shows the average supply current as a function
of capacitance on CS.
as 100µs. However, some considerations are required to
take advantage of exceptional accuracy and low supply
current.
It should be noticed that the external capacitor discharge
current is kept very small in order to decrease the converter power dissipation in the sleep state. In the autostart
mode the analog voltage on the CS pin cannot be observed
without disturbing the converter operation using a regular
oscilloscope probe. When using this configuration, it is
important to minimize the external leakage current at the
CS pin by using a low leakage external capacitor and
properly cleaning the PCB surface.
In order to preserve the LTC2401/LTC2402’s accuracy, it
is very important to minimize the ground path impedance
which may appear in series with the input and/or reference
signal and to reduce the current which may flow through
this path. The GND pin should be connected to a low
resistance ground plane through a minimum length trace.
The use of multiple via holes is recommended to further
reduce the connection resistance.
The internal serial clock mode is selected every time the
voltage on the CS pin crosses an internal threshold voltage. An internal weak pull-up at the SCK pin is active while
CS is discharging; therefore, the internal serial clock
timing mode is automatically selected if SCK is floating. It
is important to ensure there are no external drivers pulling
SCK LOW while CS is discharging.
SUPPLY CURRENT (µARMS)
VCC = 5V
200
VCC = 3V
150
100
50
0
1
10
100
1000
10000
CAPACITANCE ON CS (pF)
100000
24012 F14
Figure 14. CS Capacitance vs Supply Current
DIGITAL SIGNAL LEVELS
The LTC2401/LTC2402’s digital interface is easy to use.
Its digital inputs (FO, CS and SCK in External SCK mode of
operation) accept standard TTL/CMOS logic levels and the
internal hysteresis receivers can tolerate edge rates as slow
22
In an alternative configuration, the GND pin of the converter
can be the single-point-ground in a single point grounding
system. The input signal ground, the reference signal
ground, the digital drivers ground (usually the digital
ground) and the power supply ground (the analog ground)
should be connected in a star configuration with the common point located as close to the GND pin as possible.
The power supply current during the conversion state
should be kept to a minimum. This is achieved by restricting the number of digital signal transitions occurring
during this period.
300
250
The digital output signals (SDO and SCK in Internal SCK
mode of operation) are less of a concern because they are
not generally active during the conversion state.
While a digital input signal is in the range 0.5V to
(VCC␣ –␣ 0.5V), the CMOS input receiver draws additional
current from the power supply. It should be noted that,
when any one of the digital input signals (FO, CS and SCK
in External SCK mode of operation) is within this range, the
LTC2401/LTC2402 power supply current may increase
even if the signal in question is at a valid logic level. For
micropower operation and in order to minimize the potential errors due to additional ground pin current, it is
recommended to drive all digital input signals to full CMOS
levels [VIL < 0.4V and VOH > (VCC – 0.4V)].
Severe ground pin current disturbances can also occur
due to the undershoot of fast digital input signals. Undershoot and overshoot can occur because of the impedance
mismatch at the converter pin when the transition time of
an external control signal is less than twice the propagation delay from the driver to LTC2401/LTC2402. For
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reference, on a regular FR-4 board, signal propagation
velocity is approximately 183ps/inch for internal traces
and 170ps/inch for surface traces. Thus, a driver generating a control signal with a minimum transition time of
1ns must be connected to the converter pin through a
trace shorter than 2.5 inches. This problem becomes
particularly difficult when shared control lines are used
and multiple reflections may occur. The solution is to
carefully terminate all transmission lines close to their
characteristic impedance.
Parallel termination near the LTC2401/LTC2402 pin will
eliminate this problem but will increase the driver power
dissipation. A series resistor between 27Ω and 56Ω
placed near the driver or near the LTC2401/LTC2402 pin
will also eliminate this problem without additional power
dissipation. The actual resistor value depends upon the
trace impedance and connection topology.
Driving the Input and Reference
The analog input and reference of the typical delta-sigma
analog-to-digital converter are applied to a switched capacitor network. This network consists of capacitors
switching between the analog input (VIN), ZSSET (Pin 5)
and FSSET (Pin 2). The result is small current spikes seen
at both VIN and VREF. A simplified input equivalent circuit
is shown in Figure 15.
The key to understanding the effects of this dynamic
input current is based on a simple first order RC time
constant model. Using the internal oscillator, the
LTC2401/LTC2402’s internal switched capacitor network
is clocked at 153,600Hz corresponding to a 6.5µs sampling period. Fourteen time constants are required each
time a capacitor is switched in order to achieve 1ppm
settling accuracy.
Therefore, the equivalent time constant at VIN and VREF
should be less than 6.5µs/14 = 460ns in order to achieve
1ppm accuracy.
Input Current (VIN)
If complete settling occurs on the input, conversion results
will be uneffected by the dynamic input current. If the
settling is incomplete, it does not degrade the linearity
performance of the device. It simply results in an offset/
full-scale shift, see Figure 16. To simplify the analysis of
input dynamic current, two separate cases are assumed:
large capacitance at VIN (CIN > 0.01µF) and small capacitance at VIN (CIN < 0.01µF).
TUE
ZSSET
FSSET
VIN
VCC
IREF(LEAK)
Figure 16. Offset/Full-Scale Shift
RSW
5k
FSSET
IREF(LEAK)
IIN
VCC
IIN(LEAK) RSW
5k
AVERAGE INPUT CURRENT:
IIN = 0.25(VIN – 0.5 • VREF)fCEQ
CH0/CH1
CEQ
2.5pF (TYP)
IIN(LEAK)
RSW
5k
ZSSET
24012 F16
24012 F15
SWITCHING FREQUENCY
f = 153.6kHz FOR INTERNAL OSCILLATOR (fO = LOGIC LOW OR HIGH)
f = fEOSC FOR EXTERNAL OSCILLATORS
Figure 15. LTC2401/LTC2402 Equivalent Analog Input Circuit
If the total capacitance at VIN (see Figure 17) is small
(< 0.01µF), relatively large external source resistances (up
to 20k for 20pF parasitic capacitance) can be tolerated
without any offset/full-scale error. Figures 18 and 19 show
a family of offset and full-scale error curves for various
small valued input capacitors (CIN < 0.01µF) as a function
of input source resistance.
For large input capacitor values (CIN > 0.01µF), the input
spikes are averaged by the capacitor into a DC current. The
gain shift becomes a linear function of input source
23
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10
RSOURCE
VIN
CIN
CPAR
≅ 20pF
0
LTC2401/
LTC2402
24012 F17
Figure 17. An RC Network at VIN
50
VCC = 5V
VREF = 5V
VIN = 0V
TA = 25°C
OFFSET ERROR (ppm)
40
FULL-SCALE ERROR (ppm)
INTPUT
SIGNAL
SOURCE
–30
–40
CIN = 22µF
CIN = 10µF
CIN = 1µF
CIN = 0.1µF
CIN = 0.01µF
CIN = 0.001µF
–50
–60
–70
0
CIN = 0.01µF
200
30
600
400
RSOURCE (Ω)
800
1000
24012 F20
CIN = 1000pF
20
Figure 20. Full-Scale Error vs RSOURCE (Large C)
CIN = NO CAP
10
10
100
1k
RSOURCE (Ω)
10k
100k
24012 F18
Figure 18. Offset vs RSOURCE (Small C)
CIN = 22µF
CIN = 10µF
CIN = 1µF
CIN = 0.1µF
CIN = 0.01µF
CIN = 0.001µF
60
CIN = 0.01µF
–10
CIN = 1000pF
–50
CIN = 100pF
10
1k
100
RSOURCE (Ω)
10k
100k
Figure 21. Full-Scale Error vs RSOURCE (Small C)
20
200
0
24012 F21
VCC = 5V
40 VREF = 5V
VIN = 0V
TA = 25°C
0
CIN = NO CAP
10
–30
80
0
FULL-SCALE (ppm)
1
VCC = 5V
VREF = 5V
VIN = 5V
TA = 25°C
30
CIN = 100pF
–10
OFFSET ERROR (ppm)
–20
–80
0
600
400
RSOURCE (Ω)
800
1000
24012 F19
Figure 19. Offset vs RSOURCE (Large C)
resistance independent of input capacitance, see Figures
20 and 21. The equivalent input impedance is 6.25MΩ.
This results in ±400µA of input dynamic current at the
extreme values of VIN (VIN = 0V and VIN = VREF, when
VREF = 5V). This corresponds to a 0.8ppm shift in offset
and full-scale readings for every 10Ω of input source
resistance.
24
VCC = 5V
VREF = 5V
VIN = 5V
TA = 25°C
–10
In addition to the input current spikes, the input ESD
protection diodes have a temperature dependent leakage
current. This leakage current, nominally 1nA (±10nA
max), results in a fixed offset shift of 10µV for a 10k source
resistance.
The effect of input leakage current is evident for CIN = 0 in
Figures 18 and 21. A leakage current of 3nA results in a
150µV (30ppm) error for a 50k source resistance. As
RSOURCE gets larger, the switched capacitor input current
begins to dominate.
Reference Current (VREF)
Similar to the analog input, the reference input has a
dynamic input current. This current has negligible effect
LTC2401/LTC2402
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on the offset. However, the reference current at VIN = VREF
is similar to the input current at full-scale. For large values
of reference capacitance (CVREF > 0.01µF), the full-scale
error shift is 0.08ppm/Ω of external reference resistance
independent of the capacitance at VREF, see Figure 22. If
the capacitance tied to VREF is small (CVREF < 0.01µF), an
input resistance of up to 20k (20pF parasitic capacitance
at VREF) may be tolerated, see Figure 23.
Unlike the analog input, the integral nonlinearity of the
device can be degraded with excessive external RC time
constants tied to the reference input. If the capacitance
at node VREF is small (CVREF < 0.01µF), the reference input
can tolerate large external resistances without reduction
in INL, see Figure 24. If the external capacitance is large
(CVREF > 0.01µF), the linearity will be degraded by
0.04ppm/Ω independent of capacitance at VREF, see
Figure 25.
In addition to the dynamic reference current, the VREF ESD
protection diodes have a temperature dependent leakage
current. This leakage current, nominally 1nA (±10nA max),
results in a fixed full-scale shift of 10µV for a 10k source
resistance.
50
VCC = 5V
VREF = 5V
VIN = 5V
120 TA = 25°C
40
INL ERROR (ppm)
FULL-SCALE ERROR (ppm)
160
80
CIN = 0.1µF
CIN = 1µF
40
CIN = 0.01µF
200
600
800
400
RESISTANCE AT VREF (Ω)
0
CIN = 1000pF
30
CIN = 0.01µF
CIN = 100pF
20
CIN = 20pF
CIN = 10µF
0
VCC = 5V
VREF = 5V
TA = 25°C
10
0
100
1000
1k
10k
RESISTANCE AT VREF (Ω)
24012 F24
24012 F22
Figure 24. INL Error vs RVREF (Small C)
Figure 22. Full-Scale Error vs RVREF (Large C)
25
40
VCC = 5V
VREF = 5V
VIN = 5V
TA = 25°C
VCC = 5V
VREF = 5V
TA = 25°C
30
CIN = 10µF
0
CIN = 1000pF
CIN = 20pF
CIN = 100pF
–25
INL ERROR (ppm)
FULL-SCALE ERROR (ppm)
50
100k
CVREF = 10µF
CVREF = 1µF
CVREF = 0.1µF
20
10
CVREF = 0.01µF
–50
100
1k
10k
RESISTANCE AT VREF (Ω)
100k
24012 F23
Figure 23. Full-Scale Error vs RVFEF (Small C)
0
0
200
600
800
400
RESISTANCE AT VREF (Ω)
1000
24012 F25
Figure 25. INL Error vs RVREF (Large C)
25
LTC2401/LTC2402
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APPLICATIO S I FOR ATIO
ANTIALIASING
One of the advantages delta-sigma ADCs offer over conventional ADCs is on-chip digital filtering. Combined with
a large oversampling ratio, the LTC2401/LTC2402 significantly simplify antialiasing filter requirements.
The digital filter provides very high rejection except at
integer multiples of the modulator sampling frequency
(fS), see Figure 26. The modulator sampling frequency is
256 • FO, where FO is the notch frequency (typically 50Hz
or 60Hz). The bandwidth of signals not rejected by the
digital filter is narrow (≈ 0.2%) compared to the bandwidth
of the frequencies rejected.
As a result of the oversampling ratio (256) and the digital
filter, minimal (if any) antialias filtering is required in front
of the LTC2401/LTC2402. If passive RC components are
placed in front of the LTC2401/LTC2402, the input dynamic current should be considered (see Input Current
section). In cases where large effective RC time constants
are used, an external buffer amplifier may be required to
minimize the effects of input dynamic current.
The modulator contained within the LTC2401/LTC2402
can handle large-signal level perturbations without saturating. Signal levels up to 40% of VREF do not saturate the
analog modulator. These signals are limited by the input
ESD protection to 300mV below ground and 300mV above
VCC.
Single Ended Half-Bridge Digitizer
with Reference and Ground Sensing
Sensors convert real world phenomena (temperature,
pressure, gas levels, etc.) into a voltage. Typically, this
voltage is generated by passing an excitation current
through the sensor. The wires connecting the sensor to
the ADC form parasitic resistors RP1 and RP2. The excitation current also flows through parasitic resistors RP1 and
RP2, as shown in Figure 27. The voltage drop across these
parasitic resistors leads to systematic offset and full-scale
errors.
In order to eliminate the errors associated with these
parasitic resistors, the LTC2401/LTC2402 include a fullscale set input (FSSET) and a zero-scale set input
(ZSSET). As shown in Figure 28, the FSSET pin acts as a zero
current full-scale sense input. Errors due to parasitic
resistance RP1 in series with the half-bridge sensor are
removed by the FSSET input to the ADC. The absolute fullscale output of the ADC (data out = FFFFFFHEX ) will occur
RP1
+
V
– FULL-SCALE ERROR
+
SENSOR OUTPUT
–
SENSOR
IEXCITATION
RP2
+
V
– OFFSET ERROR
24012 F27
Figure 27. Errors Due to Excitation Currents
0
–20
1
VCC
REJECTION (dB)
–40
RP1
–60
IDC = 0
VB
RP3
IDC = 0
–80
IEXCITATION
–100
RP4
IDC = 0
–120
VA
RP2
–140
0
fS/2
fS
RP5
2
3
LTC2401
FSSET
SCK
VIN
SDO
CS
5
6
9
8
7
3-WIRE
SPI INTERFACE
ZSSET
GND
FO
10
24012 F03
INPUT FREQUENCY
24012 F26
Figure 26. Sinc4 Filter Rejection
26
Figure 28. Half-Bridge Digitizer with
Zero-Scale and Full-Scale Sense
LTC2401/LTC2402
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APPLICATIO S I FOR ATIO
at VIN = VB = FSSET, see Figure 29. Similarly, the offset
errors due to RP2 are removed by the ground sense input
ZSSET. The absolute zero output of the ADC (data out =
000000HEX) occurs at VIN = VA = ZSSET. Parasitic resistors
RP3 to RP5 have negligible errors due to the 1nA (typ)
leakage current at pins FSSET, ZSSET and VIN. The wide
dynamic input range (– 300mV to 5.3V) and low noise
(0.6ppm RMS) enable the LTC2401 or the LTC2402 to
directly digitize the output of the bridge sensor.
temperature probe and a cold junction temperature sensor. Absolute temperature measurements can be
performed with a variety of thermocouples using digital
cold junction compensation.
The selection between CH0 and CH1 is automatic. Initially,
after power-up, a conversion is performed on CH0. For
each subsequent conversion, the input channel selection
is alternated. Embedded within the serial data output is a
status bit indicating which channel corresponds to the
conversion result. If the conversion was performed on
CH0, this bit (Bit 30) is LOW and is HIGH if the conversion
was performed on CH1 (see Figure 31).
The LTC2402 is ideal for applications requiring continuous monitoring of two input sensors. As shown in
Figure 30, the LTC2402 can monitor both a thermocouple
12.5%
EXTENDED
RANGE
ADC DATA OUT
FFFFFH
00000H
12.5%
UNDER
RANGE
ZSSET
FSSET
VIN
24012 F29
Figure 29. Transfer Curve with Zero-Scale and Full-Scale Set
2.7V TO 5.5V
LTC2402
1
2
12k
COLD JUNCTION
THERMISTOR
100Ω
3
4
5
+
VCC
FO
FSSET
SCK
CH1
SDO
CH0
CS
ZSSET
GND
10
9
PROCESSOR
8
7
24012 F30
6
–
THERMOCOUPLE
ISOLATION
BARRIER
Figure 30. Isolated Temperature Measurement
27
LTC2401/LTC2402
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APPLICATIO S I FOR ATIO
• • •
SCK
SDO
• • •
CH1 DATA OUT
CH0 DATA OUT
24012 F31
EOC
EOC
CH1
CH0
Figure 31. Embedded Selected Channel Indicator
IEXCITATION
5V
1
IDC = 0
2
350Ω
350Ω
3
4
350Ω
VCC
FSSET
LTC2402
9
SCK
CH1
SDO
CH0
CS
350Ω
IDC = 0
5
FO
8
3-WIRE
SPI INTERFACE
7
10
ZSSET
GND
24012 F32
Figure 32. Pseudo Differential Strain Guage Application
There are no extra control or status pins required to
perform the alternating 2-channel measurements. The
LTC2402 only requires two digital signals (SCK and SDO).
This simplification is ideal for isolated temperature measurements or systems where minimal control signals are
available.
Pseudo Differential Applications
Generally, designers choose fully differential topologies
for several reasons. First, the interface to a 4- or 6-wire
bridge is simple (it is a differential output). Second, they
require good rejection of line frequency noise. Third, they
typically look at a small differential signal sitting on a
large common mode voltage; they need accurate
measurements of the differential signal independent of
28
the common mode input voltage. Many applications
currently using fully differential analog-to-digital converters for any of the above reasons may migrate to a
pseudo differential conversion using the LTC2402.
Direct Connection to a Full Bridge
The LTC2402 interfaces directly to a 4- or 6-wire bridge, as
shown in Figure 32. The LTC2402 includes a FSSET and a
ZSSET for sensing the excitation voltage directly across the
bridge. This eliminates errors due to excitation currents
flowing through parasitic resistors. The LTC2402 also
includes two single ended input channels which can tie
directly to the differential output of the bridge. The two
conversion results may be digitally subtracted yielding the
differential result.
LTC2401/LTC2402
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APPLICATIO S I FOR ATIO
The LTC2402’s single ended rejection of line frequencies
(±2%) and harmonics is better than 110dB. Since the
device performs two independent single ended conversions each with > 110dB rejection, the overall common
mode and differential rejection is much better than the
80dB rejection typically found in other differential input
delta-sigma converters.
In addition to excellent rejection of line frequency noise,
the LTC2402 also exhibits excellent single ended noise
rejection over a wide range of frequencies due to its 4th
order sinc filter. Each single ended conversion independently rejects high frequency noise (> 60Hz). Care must be
taken to insure noise at frequencies below 15Hz and at
multiples of the ADC sample rate (15,360Hz) are not
present. For this application, it is recommended the
LTC2402 is placed in close proximity to the bridge sensor
in order to reduce the noise injected into the ADC input. By
performing three successive conversions (CH0-CH1-CH0),
the drift and low frequency noise can be measured and
compensated for digitally.
The absolute accuracy (less than 10 ppm total error) of the
LTC2402 enables extremely accurate measurement of
small signals sitting on large voltages. Each of the two
pseudo differential measurements performed by the
LTC2402 is absolutely accurate independent of the common mode voltage output from the bridge. The pseudo
differential result obtained from digitally subtracting the
two single ended conversion results is accurate to within
the noise level of the device (3µVRMS) times the square
root of 2, independent of the common mode input voltage.
Typically, a bridge sensor outputs 2mV/V full scale. With
a 5V excitation, this translates to a full-scale output of
10mV. Divided by the RMS noise of 4.2µV(= 3µV • 1.414),
this circuit yields 2,300 counts with no averaging or
amplification. If more counts are required, several conversions may be averaged (the number of effective counts is
increased by a factor of square root of 2 for each doubling
of averages).
An RTD Temperature Digitizer
RTDs used in remote temperature measurements often
have long lead lengths between the ADC and RTD sensor.
These long lead lengths lead to voltage drops due to
excitation current in the interconnect to the RTD. This
voltage drop can be measured and digitally removed using
the LTC2402 (see Figure 33).
The excitation current (typically 200µA) flows from the
ADC through a long lead length to the remote temperature
sensor (RTD). This current is applied to the RTD, whose
resistance changes as a function of temperature (100Ω to
400Ω for 0°C to 800°C). The same excitation current flows
back to the ADC ground and generates another voltage
drop across the return leads. In order to get an accurate
measurement of the temperature, these voltage drops
must be measured and removed from the conversion
result. Assuming the resistance is approximately the same
5V
1
2
VCC
FSSET
LTC2402
IEXCITATION = 200µA
+
Pt
VRTD
100Ω
–
25Ω
R1
R2
4
SCK
CH0
SDO
1000pF
IEXCITATION = 200µA
IDC = 0
5k
3
25Ω
5k
0.1µF
5
CS
9
8
7
3-WIRE
SPI INTERFACE
CH1
FO
10
ZSSET
GND
24012 F33
Figure 33. RTD Remote Temperature Measurement
29
LTC2401/LTC2402
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for the forward and return paths (R1 = R2), the auxiliary
channel on the LTC2402 can measure this drop. These
errors are then removed with simple digital correction.
During power-up, the LTC2402 becomes active at VCC =
2.3V, while the isolated side of the LTC1535 must wait for
VCC2 to reach its undervoltage lockout threshold of 4.2V.
Below 4.2V, the LTC1535’s driver outputs Y and Z are in a
high impedance state, allowing the 1kΩ pull-down to
define the logic state at SCK. When the LTC2402 first
becomes active, it samples SCK; a logic “0” provided by
the 1kΩ pull-down invokes the external serial clock mode.
In this mode, the LTC2402 is controlled by a single clock
line from the nonisolated side of the barrier, through the
LTC1535’s driver output Y. The entire power-up sequence,
from the time power is applied to VCC1 until the LT1761’s
output has reached 5V, is approximately 1ms.
The result of the first conversion on CH0 corresponds to
an input voltage of VRTD + R1 • IEXCITATION. The result of the
second conversion (CH1) is – R1 • IEXCITATION. Note, the
LTC2402’s input range is not limited to the supply rails, it
has underrange capabilities. The device’s input range is
– 300mV to VREF + 300mV. Adding the two conversion
results together, the voltage drop across the RTD’s leads
are cancelled and the final result is VRTD.
An Isolated, 24-Bit Data Acquisition System
Data returns to the nonisolated side through the LTC1535’s
receiver at RO. An internal divider on receiver input B sets
a logic threshold of approximately 3.4V at input A, facilitating communications with the LTC2402’s SDO output
without the need for any external components.
The LTC1535 is useful for signal isolation. Figure 34
shows a fully isolated, 24-bit differential input A/D converter implemented with the LTC1535 and LTC2402. Power
on the isolated side is regulated by an LT1761-5.0 low
noise, low dropout micropower regulator. Its output is
suitable for driving bridge circuits and for ratiometric
applications.
1/2 BAT54C
LT1761-5
+
T1
10µF
16V
TANT
IN
OUT
SHDN
BYP
10µF
+
GND
1µF
10µF
10V
TANT
2
+
1/2 BAT54C
2
RO ST1
RE
DE
DI VCC1
“SDO”
“SCK”
LOGIC 5V
1
10µF
10V
TANT
+
ST2
LTC1535
G1
1
1
VCC2
G2
2
ISOLATION
BARRIER
1
A
B
Y
Z
= LOGIC COMMON
10µF
CERAMIC
10µF
10V
TANT
2
LTC2402
FO
SCK
SDO
CS
GND
1k
2
VCC
FSSET
CH1
CH0
ZSSET
24012 F09
= FLOATING COMMON
2
2
T1 = COILTRONICS CTX02-14659
OR SIEMENS B78304-A1477-A3
Figure 34. Complete, Isolated 24-Bit Data Acquisition System
30
LTC2401/LTC2402
W
PACKAGE I FOR ATIO
Dimensions in inches (millimeters) unless otherwise noted.
U
U
MS10 Package
10-Lead Plastic MSOP
(LTC DWG # 05-08-1661)
0.118 ± 0.004*
(3.00 ± 0.102)
10 9 8 7 6
0.118 ± 0.004**
(3.00 ± 0.102)
0.193 ± 0.006
(4.90 ± 0.15)
1 2 3 4 5
0.040 ± 0.006
(1.02 ± 0.15)
0.007
(0.18)
0.034 ± 0.004
(0.86 ± 0.102)
0° – 6° TYP
0.021 ± 0.006
(0.53 ± 0.015)
SEATING
PLANE 0.009
(0.228)
REF
0.0197
(0.50)
BSC
0.006 ± 0.004
(0.15 ± 0.102)
MSOP (MS10) 1098
* DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
31
LTC2401/LTC2402
U
TYPICAL APPLICATIO
convert either the thermal couple output or the thermistor
cold juntion output. After each conversion, the devices
enter their sleep state and wait for the SCK signal before
clocking out data and beginning the next conversion.
Figure 35 shows the block diagram of a demo circuit
(contact LTC for a demonstration) of a multichannel
isolated temperature measurement system. This circuit
decodes an address to select which LTC2402 receives a
32-bit burst of SCK signal. All devices independently
D1
LTC1535 A
SDO
Y
SCK
LTC2402
RE
R0
SCK
ZSSET
CH1
CH0
HC138
D1
LTC1535 A
SDO
Y
SCK
R0
ZSSET
D1
HC138
LTC1535 A
SDO
Y
SCK
R0
HC595
ADDRESS
LATCH
+
–
CH1
CH0
2500V
VCC
FSSET
LTC2402
RE
SD0
VCC
FSSET
LTC2402
RE
DIN
(ADDRESS
OR COUNTER)
VCC
FSSET
ZSSET
CH1
CH0
SEE FIGURE 34 FOR
THE COMPLETE CIRCUIT
24012 F35
Figure 35. Mulitchannel Isolated Temperature Measurement System
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1019
Precision Bandgap Reference, 2.5V, 5V
3ppm/°C Drift, 0.05% Max
LTC1050
Precision Chopper Stabilized Op Amp
No External Components 5µV Offset, 1.6µVP-P Noise
LT1236A-5
Precision Bandgap Reference, 5V
0.05% Max, 5ppm/°C Drift
LTC1391
8-Channel Multiplexer
Low RON: 45Ω, Low Charge Injection Serial Interface
LT1460
Micropower Series Reference
0.075% Max, 10ppm/°C Max Drift, 2.5V, 5V and 10V Versions
LT1461-2.5
Precision Micropower Voltage Reference
50µA Supply Current, 3ppm/°C Drift
LTC1535
Isolated RS485 Transceiver
2500VRMS Isolation
LTC2400
24-Bit, No Latency ∆Σ ADC in SO-8
4ppm INL, 10ppm Total Unadjusted Error, 200µA
LTC2404/LTC2408
4-/8-Channel, 24-Bit, No Latency ∆Σ ADC
4ppm INL, 10ppm Total Unadjusted Error, 200µA
LTC2410
24-Bit, Fully Differential, No Latency ∆Σ ADC in SSOP-16
0.16ppm Noise, 2ppm INL, 10ppm Total Unadjusted Error, 200µA
LTC2411
24-Bit, Fully Differential, No Latency ∆Σ ADC in MS10
0.29ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA
LTC2413
24-Bit, No Latency ∆Σ ADC
Simultaneous 50Hz and 60Hz Rejection, 0.16ppm Noise
LTC2420
20-Bit, No Latency ∆Σ ADC in SO-8
1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2400
LTC2424/LTC2428
4-/8-Channel, 20-Bit, No Latency ∆Σ ADC
1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2404/LTC2408
32
Linear Technology Corporation
24012f LT/LCG 1000 4K • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
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