IRF IRF7555PBF Hexfetâ® power mosfet Datasheet

PD -95993
IRF7555PbF
HEXFET® Power MOSFET
Trench Technology
l Ultra Low On-Resistance
l Dual P-Channel MOSFET
l Very Small SOIC Package
l Low Profile (<1.1mm)
l Available in Tape & Reel
l Lead-Free
l
S1
G1
S2
G2
1
8
D1
2
7
D1
3
6
4
5
VDSS = -20V
D2
D2
RDS(on) = 0.055Ω
Top View
Description
New trench HEXFET® power MOSFETs from International
Rectifier utilize advanced processing techniques to achieve
extremely low on-resistance per silicon area. This benefit,
combined with the ruggedized device design that HEXFET
Power MOSFETs are well known for, provides the designer
with an extremely efficient and reliable device for use in a wide
variety of applications.
The new Micro8™ package has half the footprint area of the
standard SO-8. This makes the Micro8 an ideal package for
applications where printed circuit board space is at a premium.
The low profile (<1.1mm) of the Micro8 will allow it to fit easily
into extremely thin application environments such as portable
electronics and PCMCIA cards.
Micro8™
Absolute Maximum Ratings
Parameter
VDS
ID @ TA = 25°C
ID @ TA = 70°C
IDM
PD @TA = 25°C
PD @TA = 70°C
VGS
EAS
dv/dt
TJ , TSTG
Max.
Drain-Source Voltage
Continuous Drain Current, VGS @ -4.5V
Continuous Drain Current, VGS @ -4.5V
Pulsed Drain Current
Maximum Power Dissipation
Maximum Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy
Peak Diode Recovery dv/dt
Junction and Storage Temperature Range
Soldering Temperature, for 10 seconds
-20
-4.3
-3.4
-34
1.25
0.8
10
± 12
36
1.1
-55 to + 150
240 (1.6mm from case)
Units
V
A
W
W
mW/°C
V
mJ
V/ns
°C
Thermal Resistance
Parameter
RθJA
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Max.
Maximum Junction-to-Ambient
Units
100
°C/W
1
2/22/05
IRF7555PbF
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
∆V(BR)DSS/∆TJ
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
RDS(on)
Static Drain-to-Source On-Resistance
VGS(th)
gfs
Gate Threshold Voltage
Forward Transconductance
IDSS
Drain-to-Source Leakage Current
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
V(BR)DSS
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Ciss
Coss
Crss
Min.
-20
–––
–––

-0.60
2.5
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Typ. Max. Units
Conditions
––– –––
V
VGS = 0V, ID = -250µA
-0.005 ––– V/°C Reference to 25°C, ID = -1mA
––– 0.055
VGS = -4.5V, ID = -4.3A
Ω
––– 0.105
VGS = -2.5V, ID = -3.4A
––– -1.2
V
VDS = VGS, ID = -250µA
––– –––
S
VDS = -10V, ID = -0.8A
––– -1.0
VDS = -16V, VGS = 0V
µA
––– -25
VDS = -16V, VGS = 0V, TJ = 125°C
––– -100
VGS = -12V
nA
––– 100
VGS = 12V
10
15
ID = -3.0A
2.1 3.1
nC
VDS = -10V
2.5 3.7
VGS = -5.0V
10 –––
VDD = -10V
46 –––
ID = -2.0A
ns
60 –––
RG = 6.0Ω
64 –––
RD = 5.0Ω
1066 –––
VGS = 0V
402 –––
pF
VDS = -10V
126 –––
ƒ = 1.0MHz
Source-Drain Ratings and Characteristics
IS
ISM
VSD
trr
Qrr
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Min. Typ. Max. Units

-1.3

-34
–––
–––
–––
–––
54
41
-1.2
82
61
A
V
ns
nC
Conditions
MOSFET symbol
showing the
G
integral reverse
p-n junction diode.
TJ = 25°C, IS = -1.6A, VGS = 0V
TJ = 25°C, IF = -2.5A
di/dt = -100A/µs
D
S
Notes:
Repetitive rating; pulse width limited by
Surface mounted on FR-4 board, t ≤ 10sec.
max. junction temperature.
ISD ≤ -2.0A, di/dt ≤ -140A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 150°C
Starting TJ = 25°C, L = 8.0mH
RG = 25Ω, I AS = -3.0A.
Pulse width ≤ 300µs; duty cycle ≤ 2%.
2
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IRF7555PbF
100
100
VGS
-7.50V
-5.00V
-4.00V
-3.50V
-3.00V
-2.50V
-2.00V
BOTTOM -1.50V
VGS
-7.50V
-5.00V
-4.00V
-3.50V
-3.00V
-2.50V
-2.00V
BOTTOM -1.50V
TOP
-I D , Drain-to-Source Current (A)
-I D , Drain-to-Source Current (A)
TOP
10
1
-1.50V
20µs PULSE WIDTH
TJ = 25 °C
0.1
0.1
1
10
100
10
-1.50V
1
0.1
0.1
-VDS , Drain-to-Source Voltage (V)
RDS(on) , Drain-to-Source On Resistance
(Normalized)
-I D , Drain-to-Source Current (A)
2.0
TJ = 25 ° C
TJ = 150 ° C
10
V DS = -15V
20µs PULSE WIDTH
3.0
4.0
-VGS , Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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10
100
Fig 2. Typical Output Characteristics
100
2.0
1
-VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
1
1.0
20µs PULSE WIDTH
TJ = 150 ° C
5.0
ID = -4.3A
1.5
1.0
0.5
0.0
-60 -40 -20
VGS = -4.5V
0
20
40
60
80 100 120 140 160
TJ , Junction Temperature ( °C)
Fig 4. Normalized On-Resistance
Vs. Temperature
3
IRF7555PbF
VGS
Ciss
Crss
Coss
= 0V,
f = 1MHz
= Cgs + Cgd , Cds SHORTED
= Cgd
= Cds + Cgd
C, Capacitance (pF)
1200
Ciss
800
400
Coss
Crss
15
-VGS , Gate-to-Source Voltage (V)
1600
12
VDS =-10V
9
6
3
0
0
1
10
ID = -4.3A
-4.5A
100
0
4
16
20
24
100
100
OPERATION IN THIS AREA LIMITED
BY RDS(on)
10us
-II D , Drain Current (A)
-ISD , Reverse Drain Current (A)
12
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
10
TJ = 150 ° C
TJ = 25 ° C
1
0.1
0.0
V GS = 0 V
0.4
0.8
1.2
1.6
2.0
-VSD ,Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
8
Q G , Total Gate Charge (nC)
-VDS, Drain-to-Source Voltage (V)
2.4
10
100us
1ms
1
10ms
TC = 25 °C
TJ = 150 °C
Single Pulse
0.1
0.1
1
10
100
-VDS , Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRF7555PbF
5.0
EAS , Single Pulse Avalanche Energy (mJ)
100
-ID , Drain Current (A)
4.0
3.0
2.0
1.0
0.0
25
50
75
100
125
150
TC , Case Temperature ( ° C)
ID
-1.3A
-2.4A
BOTTOM -3.0A
TOP
80
60
40
20
0
25
50
75
100
125
150
Starting TJ , Junction Temperature ( °C)
Fig 9. Maximum Drain Current Vs.
Case Temperature
Fig 10. Maximum Avalanche Energy
Vs. Drain Current
Thermal Response (Z thJA )
1000
100
D = 0.50
0.20
0.10
10
0.05
PDM
0.02
0.01
t1
SINGLE PULSE
(THERMAL RESPONSE)
1
0.1
0.0001
t2
Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJA + TA
0.001
0.01
0.1
1
10
100
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
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5
IRF7555PbF
Current Regulator
Same Type as D.U.T.
50KΩ
QG
QGS
.2µF
12V
.3µF
D.U.T.
QGD
+VDS
VGS
VG
-3mA
IG
ID
Current Sampling Resistors
Charge
Fig 12a. Basic Gate Charge Waveform
Fig 12b. Gate Charge Test Circuit
+
Fig 13a. Switching Time Test Circuit
td(on)
tr
t d(off)
tf
VGS
10%
90%
VDS
Fig 13b. Switching Time Waveforms
6
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IRF7555PbF
Peak Diode Recovery dv/dt Test Circuit
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
+
-
-
+
• dv/dt controlled by RG
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
+
-
*
Reverse Polarity for P-Channel
** Use P-Channel Driver for P-Channel Measurements
Driver Gate Drive
P.W.
D=
Period
P.W.
Period
VGS=10V
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
ISD
*** VGS = 5.0V for Logic Level and 3V Drive Devices
Fig -14 For P Channel HEXFETS
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7
IRF7555PbF
Micro8 Package Outline
Dimensions are shown in milimeters (inches)
LEAD ASSIGNMENTS
INCHES
DIM
D
3
-B-
D D D D
D1 D1 D2 D2
8 7 6 5
8 7 6 5
SINGLE
DUAL
A
MILLIMETERS
MIN
MAX
MIN
MAX
.036
.044
0.91
1.11
A1
.004
.008
0.10
0.20
B
.010
.014
0.25
0.36
C
.005
.007
0.13
0.18
D
.116
.120
2.95
3.05
e
.0256 BASIC
0.65 BASIC
e1
.0128 BASIC
0.33 BASIC
E
.116
.120
2.95
3.05
H
.188
.198
4.78
5.03
e
L
.016
.026
0.41
0.66
6X
θ
0°
6°
8 7 6 5
3
H
E
0.25 (.010)
-A-
M
A
M
1 2 3 4
1 2 3 4
S S S G
S1 G1 S2 G2
1 2 3 4
0°
6°
e1
RECOMMENDED FOOTPRINT
θ
-CB
0.10 (.004)
A1
8X
0.08 (.003)
M
C A S
0.38
8X
( .015 )
1.04
( .041 )
8X
A
L
8X
C
8X
B S
3.20
( .126 )
4.24
5.28
( .167 ) ( .208 )
NOTES:
1 DIMENSIONING AND TOLERANCING PER ANSI Y14.5M-1982.
2 CONTROLLING DIMENSION : INCH.
0.65 6X
( .0256 )
3 DIMENSIONS DO NOT INCLUDE MOLD FLASH.
Micro8 Part Marking Information
EXAMPLE: T HIS IS AN IRF7501
LOT CODE (XX)
DAT E CODE (YW) - S ee table below
Y = YEAR
W = WEEK
P = DES IGNAT ES LEAD - FREE
PRODUCT (OPTIONAL)
PART NUMBER
WW = (1-26) IF PRECEDED BY LAS T DIGIT OF CALENDAR YEAR
8
YEAR
Y
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
1
2
3
4
5
6
7
8
9
0
WORK
WEEK
WW = (27-52) IF PRECEDED BY A LETT ER
W
YEAR
Y
01
02
03
04
A
B
C
D
24
25
26
X
Y
Z
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
A
B
C
D
E
F
G
H
J
K
WORK
WEEK
W
27
28
29
30
A
B
C
D
50
51
52
X
Y
Z
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IRF7555PbF
Micro8 Tape & Reel Information
Dimensions are shown in millimeters (inches)
TERMINAL NUMBER 1
12.3 ( .484 )
11.7 ( .461 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIRECTION
NOTES:
1. OUTLINE CONFORMS TO EIA-481 & EIA-541.
2. CONTROLLING DIMENSION : MILLIMETER.
330.00
(12.992)
MAX.
14.40 ( .566 )
12.40 ( .488 )
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. OUTLINE CONFORMS TO EIA-481 & EIA-541.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Consumer market.
Qualifications Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 02/05
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9

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