ETC1 A6155SO8A High efficiency linear power supply Datasheet

EM MICROELECTRONIC-MARIN SA
A6155
High Efficiency Linear Power Supply with
Extremely Accurate Power Surveillance, Software
Monitoring and Sleep Mode Detection
Features
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Can-bus sleep mode detector
Highly accurate 5 V, 100 mA guaranteed output
Low dropout voltage, typically 380 mV at 100 mA
Low quiescent current, typically 155 µA
Standby mode, maximum current 350 µA (with
100 µA load on OUTPUT)
Unregulated DC input can withstand –20 V reverse
battery and + 60 V power transients
Fully operational for unregulated DC input voltage
up to 26 V and regulated output voltage down to 3.0 V
Reset output guaranteed for regulated output voltage
down to 1.2 V
No reverse output current
Very low temperature coefficient for the regulated output
Current limiting
Comparator for voltage monitoring,voltage reference
1.275 V
±2.0% voltage reference accuracy at +25 °C (3 to 5.5 V)
±2.7% voltage reference accuracy from –40 to
+85 °C (3 to 5.5 V)
Programmable reset voltage monitoring
Programmable power-on reset (POR ) delay
Watchdog with programmable time windows guarantees a minimum time and a maximum time between
software clearing of the watchdog
Time base accuracy ± 10%
System enable output offers added security
TTL/CMOS compatible
-40 to +85 °C temperature range
DIP8 and SO8 packages
state for a regulated output voltage as low as 1.2 V.
The watchdog function monitors software cycle time
and execution. If software clears the watchdog too
quickly (incorrect cycle time) or too slowly (incorrect
execution) it will cause the system to be reset. The
system enable output prevents critical control
functions being activated until software has
successfully cleared the watchdog three times. Such a
security could be used to prevent motor controls
being energized on repeated resets of a faulty system.
If the microcontroller does not work that means no
signal on the TCL input the A6155 goes in a standby
mode (CAN-bus sleep detector).
Applications
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Automotive systems
Cellular telephones
Security systems
Battery powered products
High efficiency linear power supplies
Industrial electronics
Typical Operating Configuration
Unregulated voltage
A6155
Description
The A6155 offers a high level of integration by combining
voltage regulation, voltage monitoring and software
monitoring in an 8 lead package. The voltage regulator
has a low dropout voltage (typ. 380 mV at 100 mA) and a
low quiescent current (155 µA). The quiescent current
increases only slightly in dropout prolonging battery life.
Built-in protection includes a positive transient absorber for
up to 60 V (load dump) and the ability to survive an
unregulated input voltage of –20 V (reverse battery). The
input may be connected to ground or a reverse voltage
without reverse current flow from the output to the input. A
comparator monitors the voltage applied at the VIN input
comparing it with an internal 1.275 V reference. The
power-on reset function is initialized after VIN reaches
1.275 V and takes the reset output inactive after TPOR
depending of external resistance. The reset output
goes active low when the VIN voltage is less than 1.275 V.
The RES and EN outputs are guaranteed to be in a correct
5V
INPUT OUTPUT
R
VSS
VIN
TCL
RES
EN
GND
Fig. 1
Pin Assignment
DIP8/ SO8
EN
RES
TCL
VSS
V IN
A6155
R
OUTPUT
INPUT
Fig. 2
1
A6155
Absolute Maximum Ratings
Parameter
Continuous voltage at INPUT
to VSS
Transients on INPUT for
t < 100 ms and duty cycle 1%
Reverse supply voltage on INPUT
Max. voltage at any signal pin
Min. voltage at any signal pin
Storage temperature
Electrostatic discharge max. to
MIL-STD-883C method 3015
Max. soldering conditions
Symbol
Operating Conditions
Conditions
VINPUT
-0.3 to + 30 V
VTRANS
VREV
VMAX
VMIN
TSTO
up to + 60 V
- 20 V
OUTPUT + 0.3 V
VSS – 0.3 V
-65 to + 150 °C
VSmax
TSmax
1000 V
250 °C x 10 s
Parameter
Operating junction
temperature 1)
INPUT voltage 2)
OUTPUT voltage 2)3)
RES & EN guaranteed 4)
OUTPUT current 5)
Comparator input
voltage
RC-oscillator
programming
Thermal resistance from
junction to ambient 6)
-DIP8
-SO8
Table 1
Stresses above these listed maximum ratings may
cause permanent damage to the device. Exposure beyond specified operating conditions may affect device
reliability or cause malfunction.
1)
Handling Procedures
2)
This device has built-in protection against high static
voltages or electric fields; however, anti-static precautions should be taken as for any other CMOS component. Unless otherwise specified, proper operation can
only occur when all terminal voltages are kept within the
supply voltage range. At any time, all inputs must be tied
to a defined logic voltage level.
Min.
TJ
VINPUT
VOUTPUT
VOUTPUT
IOUTPUT
-40
2.3
1.2
1.2
Typ. Max.
+85
26
Units
100
°C
V
V
V
mA
VIN
0
VOUTPUT
V
R
10
1000
kΩ
105
160
°C/W
°C/W
Rth(j-a)
Rth(j-a)
Table 2
3)
4)
5)
6)
2
Symbol
The maximum operating temperature is confimed by
sampling at initial device qualification. In production, all
devices are tested at +85 °C.
Full operation quaranteed. To achieve the load regulation
specified in Table 3 a 22 µF capacitor or greater is required
on the INPUT, see Fig. 8. The 22 µF must have an effective
resistance ≤ 5 Ω and a resonant frequency above 500 kHz.
A 10 µF load capacitor and a 100 nF decoupling capacitor
are required on the regulator OUTPUT for stability. The
10 µF must have an effective series resistance of ≤ 5 Ω and
a resonant frequency above 500 kHz.
RES must be pulled up externally to VOUTPUT even if it is
unused. (Note: RES and EN are used as inputs by EM
test).
The OUTPUT current will not apply for all possible
combinations of input voltage and output current.
Combinations that would require the A6155 to work above
the maximum junction temperature (+85 °C) must be
avoided.
The thermal resistance specified assumes the package is
soldered to a PCB.
A6155
Electrical Characteristics
VINPUT = 6.0 V, CL = 10 µF + 100 nF, CINPUT = 22 µF, TJ = -40 to +85 °C, unless otherwise specified
Parameter
Symbol
Supply current in standby mode ISS
(switched to RINT)
Supply current 1)
ISS
Supply current 1)
ISS
Output voltage
Output voltage
VOUTPUT
VOUTPUT
Output voltage temperature
Coefficient 2)
Line regulation 3)
Vth(coeff)
VLINE
Load regulation 3)
Dropout voltage 4)
Dropout voltage 4)
Dropout voltage 4)
Dropout supply current
VL
VDROPOUT
VDROPOUT
VDROPOUT
ISS
Thermal regulation 5)
Vthr
Current limit
ILmax
OUTPUT noise, 10Hz to 100kHz VNOISE
Test Conditions
Min. Typ.
REXT = don’t care, TCL = VOUTPUT,
VIN = VOUTPUT, IL = 100 µA
O/PS 1 MΩ to VOUTPUT
REXT = 100 kΩ, I/PS at VOUTPUT,
O/PS 1 MΩ to VOUTPUT, IL = 100 µA
155
REXT = 100 kΩ, I/PS at VOUTPUT, VINPUT =
8.0 V, O/PS 1 MΩ to VOUTPUT, IL = 100 mA
1.7
IL = 100 µA
4.88
100 µA ≤ IL ≤ 100 mA,
-40 °C ≤ TJ ≤+85 °C
4.85
6 V ≤ VINPUT ≤26 V, IL = 1 mA,
TJ = +85 °C
100 µA ≤ IL ≤ 100 mA
IL = 100 µA
IL = 100 mA
IL = 100 mA, -40 °C ≤ TJ ≤+85 °C
VINPUT = 4.5 V, IL = 100 µA,
REXT = 100 kΩ, O/PS 1 MΩ to
VOUTPUT, I/PS at VOUTPUT
TJ = +25 °C, IL = 50 mA,
VINPUT = 26 V, T = 10 ms
OUTPUT tied to VSS
Max.
Unit
350
µA
400
µA
4.2
5.12
mA
V
5.15
V
50
180
ppm/°C
0.2
0.2
40
380
0.5
0.6
170
650
%
%
mV
mV
mV
1.2
1.6
mA
0.05
450
200
0.25
%/W
mA
µVrms
3.0 ≤ VOUTPUT ≤ 5.5 V, IL = 100 µA, CL = 10 µF + 100 nF, CINPUT = 22 µF, TJ = -40 to +85 °C, unless otherwise specified
RES and EN
Output Low Voltage
EN
Output High Voltage
TCL and VIN
TCL Input Low Level
TCL Input High Level
Leakage current TCL input
VIN input resistance
Comparator reference 6)7)
Comparator hysteresis 7)
VOL
VOL
VOL
VOL
VOUTPUT = 4.5 V, IOL= 20 mA
VOUTPUT = 4.5 V, IOL = 8 mA
VOUTPUT = 2.0 V, IOL = 4 mA
VOUTPUT = 1.2 V, IOL = 0.5 mA
VOH
VOH
VOH
VOUTPUT = 4.5 V, IOH= -1 mA
VOUTPUT = 2.0 V, IOH= -100 µA
VOUTPUT = 1.2 V, IOH= -30 µA
VIL
VIH
ILI
RVIN
VREF
VREF
VHY
VSS ≤ VTCL ≤ VOUTPUT
TJ = +25 °C
0.4
0.2
0.2
0.06
3.5
1.8
1.0
0.4
0.4
0.2
4.1
1.9
1.1
VSS
2.0
0.8
VOUTPUT
0.05
1
100
1.25 1.275 1.30
1.24
1.31
2
V
V
V
V
V
V
V
V
V
µA
MΩ
V
V
mV
Table 3
If INPUT is connected to VSS, no reverse current will flow from the OUTPUT to the INPUT, however the supply
current specified will be sank by the OUTPUT to supply the A6155.
2)
The OUTPUT voltage temperature coefficient is defined as the worst case voltage change divided by the total temperature range.
3)
Regulation is measured at constant junction temperature using pulse testing with a low duty cycle. Changes in OUTPUT voltage
due to heating effects are covered in the specification for thermal regulation.
4)
The dropout voltage is defined as the INPUT to OUTPUT differential, measured with the input voltage equal to 5.0 V.
5)
Thermal regulation is defined as the change in OUTPUT voltage at a time T after a change in power dissipation is applied,
excluding load or line regulation effects.
6)
The comparator and the voltage regulator have separate voltage references (see “ Block Diagram” Fig. 8).
7)
The comparator reference is the power-down reset threshold. The power-on reset threshold equals the comparator reference
voltage plus the comparator hysteresis (see Fig. 5).
1)
3
A6155
Timing Characteristics
V INPUT = 6.0 V, IL = 100 µA, CL = 10 µF + 100 nF, CINPUT = 22 µF, TJ = -40 to + 85 °C, unless otherwise specified
Parameter
Symbol Test Conditions
Propagation delays:
TCL to Output Pins
VIN sensitivity
Logic Transition Times on all Output Pins
Power-on Reset delay
Watchdog Time
Open Window Percentage
Closed Window Time
TDIDO
TSEN
TTR
TPOR
TWD
OWP
TCW
TCW
Open Window Time
TOW
TOW
Watchdog Reset Pulse
TWDR
TWDR
TCL Input Pulse Width
TTCL
Reset Pulse when switched to R internal TRI
Watchdog Reset Pulse with R internal (RI) TRIR
Min.
1
Load 10 kΩ, 50 pF
REXT = 110 kΩ, ±1%
REXT = 110 kΩ, ±1%
90
90
REXT = 110 kΩ, ±1%
72
REXT = 110 kΩ, ±1%
36
REXT = 110 kΩ, ±1%
150
0.3
Typ.
Max.
Units
250
5
30
100
100
±0.2 TWD
0.8 TWD
80
0.4 TWD
40
TWD/40
2.5
500
20
100
110
110
ns
µs
ns
ms
ms
88
ms
44
ms
0.9
TRI/320
2.3
ms
ns
s
s
Table 4
TRI versus Temperature at VOUTPUT = 5 V
2.5
TRI [s]
2.0
1.5
1.0
0.5
0
-40
+85
+25
+125
TJ [°C]
Fig.3
Timing Waveforms
Watchdog Timeout Period
TWD = TPOR
Watchdog
timer reset
TCW – closed window
TOW – open window
t [ms]
80
4
Condition:
REXT = 110 kΩ
+ OWP
+ 20%
− OWP
− 20%
100
120
Fig. 4
A6155
Voltage Monitoring
VHY
VIN
Conditions:
VOUTPUT ≥ 3 V
No timeout
VREF
TSEN
TSEN
TSEN
TSEN
TPOR
TPOR
RES
Fig. 5
Timer Reaction
TCW
TOW
TCW +TOW
TCW
TCL
TCW + TOW
TCW + TOW
TTCL
TRI
RES
EN
Conditions: VIN > VREF after power-up sequence
TCW + TOW
2
TWDR
TRIR
TWDR
1
TCW + TOW
3
3 correct TCL services
→EN goes active low
After 3 reset pulse
periods
→ switch to R internal
Timeout
- Watchdog timer reset
After one edge (falling or rising)
on TCL input
→ switch to R input
Fig. 6
Combined Voltage and Timer Reaction
VIN
VREF
TPOR=TWD
TCL
TOW
Condition:
VOUTPUT ≥ 3 V
TCW
TRI
TCW+TOW
TRIR
RES
EN
1
- Watchdog timer reset
TCL
too early
2
3
3 correct TCL services
→EN goes active low
After 3 reset pulse periods
→ switch to R internal
Fig. 7
5
A6155
Block Diagram
Voltage
Regulator
INPUT
Voltage
Reference
OUTPUT
VREF
Comparator
Voltage
Reference
Enable
Logic
EN
Reset
Control
RES
VIN
Current
Controlled
Oscillator
R
R1∼ 1 MΩ
Switch
Timer
Controller
Open drain
output RES
TCL
Fig. 8
Pin Description
Pin Name
1 EN
2 RES
3
4
5
6
7
8
Function
Push-pull active low enable output
Open drain active low reset output.
RES must be pulled up to VOUTPUT
even if unused
TCL
Watchdog timer clear input signal
VSS
GND terminal
INPUT
Voltage regulator input
OUTPUT Voltage regulator output
R
REXT input for RC oscillator tuning
VIN
Voltage comparator input
Table 5
Functional Description
Voltage Regulator
The A6155 has a 5 V ± 2%, 100 mA, low dropout voltage regulator. The low supply current (typ.155 µA) makes the A6155 particularly suited to automotive systems then
remain energized 24 hours a day. The input voltage range is
2.3 V to 26 V for operation and the input protection includes
both reverse battery (20 V below ground) and load dump
(positive transients up to 60 V). There is no reverse current
flow from the OUTPUT to the INPUT when the INPUT equals
VSS. This feature is important for systems which need to
implement (with capacitance) a minimum power supply
hold-up time in the event of power failure. To achieve good
load regulation a 22 µF capacitor (or greater ) is needed on
the INPUT (see Fig.9). Tantalum or aluminium electrolytics
are adequate for the 22 µF capacitor; film types will work but
are relatively expensive. Many aluminium electrolytics have
electrolytes that freeze at about –30 °C, so tantalums are
recommended for operation below –25 °C. The important
parameters of the 22 µF capacitor are an effective series
6
resistance of ≤ 5 Ω and a resonant frequency above
500 kHz..
A 10 µF capacitor (or greater) and a 100 nF capacitor
are required on the OUTPUT to prevent oscillations due
to instability. The specification of the 10 µF capacitor is
as per the 22 µF capacitor on the INPUT (see previous
paragraph).
The A6155 will remain stable and in regulation with no
external load and the dropout voltage is typically constant as the input voltage fall to below its minimum level
(see Table 2). These features are especially important in
CMOS RAM keep-alive applications.
Care must be taken not to exceed the maximum junction
temperature (+ 85 °C). The power dissipation within the
A6155 is given by the formula:
PTOTAL = (VINPUT – VOUTPUT) * IOUTPUT + (VINPUT) * ISS
The maximum continuous power dissipation at a given
temperature can be calculated using the formula:
PMAX = ( 85 °C – TA) / Rth(j-a)
where Rth(j-a) is the termal resistance from the junction to
the ambient and is specified in Table 2. Note the Rth(j-a)
given in Table 2 assumes that the package is soldered
to a PCB. The above formula for maximum power dissipation assumes a constant load (ie. ≥100 s). The
transient thermal resistance for a single pulse is much
lower than the continuous value. For example the A6155
in DIP8 package will have an effective thermal resistance
from the junction to the ambient of about 10°C/W for a
single 100 ms pulse.
VIN Monitoring
The power-on reset and the power-down reset are
generated as a response to the external voltage level
applied on the VIN input. The VDD voltage at which reset is
asserted or released is determined by the external
voltage divider between VDD and VSS, as shown on Fig. 9.
A part of VDD is compared to the internal voltage
reference. To determine the values of the divider, the
leakage current at VIN must be taken into account, as
A6155
well as the current consumption of the divider itself. Low
resistor values will need more current, but high resistor
values will make the reset threshold less accurate at
high temperature, due to a possible leakage current at
the VIN input. The sum of the two resistors should stay
below 300 kΩ. The formula is: VRESET = VREF *(1 + R1/R2).
Example: choosing R1 = 100 kΩ and R2 = 39 kΩ will
result in a VDD reset threshold of 4.54 V (typ.).
At power-up the reset output (RES) is held low (see
Fig. 5). After INPUT reaches 3.36 V (and so OUTPUT
reach-es at least 3 V) and VIN becomes greater than VREF,
the RES output is held low for an additional power-onreset (POR) delay which is equal to the watchdog time
TWD (typically 100 ms with an external resistor of 110 kΩ
con-nected at R pin). The POR delay prevents repeated
togging of RES even if VIN and the INPUT voltage drops
out and recovers. The POR delay allows the microprocessor’s crystal oscillator time to start and stabilize and
ensures correct recognition of the reset signal to the
microprocessor.
The RES output goes active low generating the powerdown reset whenever VIN falls below VREF. The sensitivity
or reaction time of the internal comparator to the voltage level on VIN is typically 5 µs.
Timer Programming
The on-chip oscillator with an external resistor REXT connected between the R pin and VSS (see Fig. 9) allows the
user to adjust the power-on reset (POR) delay,
watchdog time TWD and with this also the closed and
open time windows as well as the watchdog reset pulse
width (TWD/40).
With REXT = 110 kΩ typical values are:
-Power-on reset delay: TPOR is 100 ms
-Watchdog time:
TWD is 100 ms
-Closed window:
TCW is 80 ms
-Open window:
TOW is 40 ms
-Watchdog reset:
TWDRis 2.25 ms
Note the current consumption increases as the frequency increases.
Watchdog Timeout Period Description
The watchdog timeout period is divided into two parts, a
“closed” window and an “open” window (see Fig. 4) and
is defined by two parameters, TWD and the Open Window
Percentage (OWP).
The closed window starts just after the watchdog timer
resets and is defined by TCW = TWD – OWP(TWD).
The open window starts after the closed time window
finishes and lasts till TWD + OWP(TWD).The open window
time is defined by TOW = 2 x OWP (TWD)
For example if TWD = 100 ms (actual value) and OWP =
± 20% this means the closed window lasts during first
the 80 ms (TCW = 80 ms = 100 ms – 0.2 (100 ms)) and
the open window the next 40 ms (TOW = 2 x 0.2 (100 ms)
= 40 ms). The watchdog can be serviced between
80 ms and 120 ms after the timer reset. However as the
time base is ± 10% accurate, software must use the
following calculation for servicing signal TCL during the
open window:
Related to curves (Fig. 10 to Fig. 21), especially Fig. 20
and Fig. 21, the relation between TWD and REXT could
easely be defined. Let us take an example describing
the variations due to production and temperature:
1. Choice, TWD = 26 ms.
2. Related to Fig. 21, the coefficient (TWD to REXT) is
1.025 where REXT is in kΩ and TWD in ms.
3. REXT (typ.) = 26 x 1.025 =26.7 kΩ.
4.
26 ms at +25 °C
a)
b)
(26 − 10% = 23.4 ms) (26 + 10% = 28.6 ms)a)
(23.4 − 5% = 22.2 ms)
(28.6 + 5% = 30.0 ms)b)
min.: (30.0 − 20% = 24.0 ms) max.: (22.2 + 20% = 26.7 ms)
Typical TCL period of
(24.0 + 26.7) / 2 = 25.4 ms
The ratio between TWD = 26 ms and the (TCL period)
= 25.4 ms is 0.975.
Then the relation over the production and the full
temperature range is, TCL period = 0.975 x TWD or
0.975 x REXT
TCL period =
, as typical value.
1.025
a)While PRODUCTION value unknown for the customer when REXT ≠ 110 kΩ.
b)While operating TEMPERATURE range
-40 °C ≤ TJ ≤ +85 °C.
5. If you fixed a TCL period = 26 ms
26 x 1.025
⇒ REXT =
= 27.3 kΩ.
0.975
If during your production the TWD time can be measured at TJ = + 25 °C and the µC can adjust the TCL
period, then the TCL period range will be much larger
for the full operating temperature.
Timer Clearing and RES Action
The watchdog circuit monitors the activity of the processor. If the user’s software does not send a pulse to the
TCL input within the programmed open window timeout
period a short watchdog RES pulse is generated which
is equal to TWD /40 = 2.5 ms typically (see Fig. 6).
With the open window constraint new security is added
to conventional watchdogs by monitoring both software
cycle time and execution. Should software clear the
watchdog too quickly (incorrect cycle time) or too slowly
(incorrect execution) it will cause the system to be reset.
If software is stuck in a loop which includes the routine
to clear the watchdog then a conventional watchdog
would not make a system reset even though software is
malfunctioning; the A6155 would make a system reset
because the watchdog would be cleared too quickly.
If no TCL signal is applied before the closed and open
windows expire, RES will start to generate square waves
of period (TCW + TOW + TWDR). The watchdog will remain
in this state until the next TCL falling edge appears
7
A6155
during an open window,or until a fresh power-up sequence. The system enable output, EN , can be used to
prevent critical control functions being activated in the
event of the system going into this failure mode (see
section “Enable-EN Output”).
The RES output must be pulled up to VOUTPUT even if that
output is not used by the system (see Fig 9).
Combined Voltage and Timer Action
The combination of voltage and timer actions is illustrated by the sequence of events shown in Fig. 7. On power-up, when the voltage at VIN reaches VREF, the poweron-reset, POR, delay is initialized and holds RES active
for the time of the POR delay. A TCL pulse will have
no effect until this power-on-reset delay is completed.
When the risk exists that TCL temporarily floats, e.g.
during TPOR, a pull-up to VDD is required on that pin. After
the POR delay has elapsed, RES goes inactive and the
watchdog timer starts acting. If no TCL pulse occurs,
RES goes active low for a short time TWDR after each
closed and open window period. A TCL pulse coming
during the open window clears the watchdog timer.
When the TCL pulse occurs too early (during the closed
window), RES goes active and a new timeout sequence
starts. A voltage drop below the VREF level for longer than
typically 5 µs overrides the timer and immediately forces
RES active and EN inactive. Any further TCL pulse has
no effect until the next power-up sequence has
completed.
Enable - EN Output
The system enable output, EN , is inactive always when
RES is active and remains inactive after a RES pulse
until the watchdog is serviced correctly 3 consecutive
8
times (ie. the TCL pulse must come in the open
window). After three consecutive services of the
watchdog with TCL during the open window, the EN
goes active low.
A malfunctioning system would be repeatedly reset by
the watchdog. In a conventional system critical motor
controls could be energized each time reset goes inactive (time allowed for the system to restart) and in this
way the electrical motors driven by the system could
function out of control. The A6155 prevents the above
failure mode by using the EN output to disable the motor
controls until software has successfully cleared the
watchdog three times (ie. the system has correctly restarted after a reset condition).
CAN -Bus Sleep Mode Detector
If the microcontroller is in standby mode that means it
does not have any pulses on the TCL input. After 3 reset
pulse periods (TCW + T OW + TWDR) on the RES output, the
A6155 switches on an internal resistor of 1 MΩ, and it
will have a reset pulse of typically 3 ms every 1 second
on the RES output. When a TCL edge (rising or falling)
appears on the TCL input or the power supply goes
down and up, the A6155 switches to the R input.
A6155
Typical Application
Regulated voltage
Unregulated voltage
INPUT
22 µF
+
100 kΩ
OUTPUT
A6155
R
100 nF
+ 10 µF
R1
Address
Decoder
VIN
TCL
RES
EN
VSS
RES
R2
EN
µP
Motor
Controls
GND
Fig.9
OUTPUT Current versus INPUT Voltage
SO8 package
soldered to
PC board
TJmax = + 125 °C
100
OUTPUT current [mA]
80
60
TA=+50 °C
TA=+25 °C
40
TA=+85 °C
20
0
0
5
10
15
20
25
30
INPUT voltage [V]
Fig.10
9
A6155
VREF versus VOUTPUT at TJ = -40 °C, +25 °C, +85 °C
VREF versus VOUTPUT at TJ = -40 °C, +25 °C, +85 °C
2.0
1.290
1.8
1.285
1.6
1.4
1.280
1.2
TJ = +25 °C
VREF [V]
VREF [V]
TJ = -40 °C
TJ = -40 °C
1.0
TJ = +25 °C
1.275
0.8
TJ = +85 °C
1.270
0.6
TJ = +85 °C
0.4
1.265
0.2
1.260
0.0
1.5
2.5
3.5
4.5
5.5
VOUTPUT [V]
6.5
1
7.5
3
4
5
6
VOUTPUT [V]
Fig. 11
VREF versus Temperature at VOUTPUT =3 V,5 V and 8 V
7
8
Fig. 12
VREF versus Temperature at VOUTPUT =3 V,5 V and 8 V
1.280
1.50
1.45
VOUTPUT = 5 V
1.275
VOUTPUT = 3 V
1.40
1.270
1.35
VOUTPUT = 8 V
1.25
VREF [V]
1.30
VREF [V]
2
VOUTPUT = 5 V and 3 V
1.265
1.260
1.20
VOUTPUT = 8 V
1.15
1.255
1.10
1.250
1.05
1.245
1.00
-50
-25
0
+25
+50 +75 +100 +125
TJ [°C]
10
Fig. 13
-50
-25
0
+25
+50
TJ [°C]
+75 +100 +125
Fig. 14
A6155
TWD versus Supply Voltage at TJ ≤ +85 °C
TWD versus VOUTPUT at TJ = 125 °C
100000
100000
R = 10 MΩ
R = 10 MΩ
10000
10000
R = 1 MΩ
TWD [ms]
TWD [ms]
R = 100 kΩ
100
5
4
3
6
R = 100 kΩ
100
R = 10 kΩ
10
R = 1 MΩ
1000
1000
R = 10 kΩ
10
7
VOUTPUT[V]
3
8
4
7
VOUTPUT[V]
Fig. 15
TWD versus Temperature at VOUTPUT = 5 V
6
5
8
Fig. 16
TWD versus R at VOUTPUT = 5 V
10000
100000
TJ =+125 °C
R = 10 MΩ
1000
10000
R = 1 MΩ
100
TWD [ms]
TWD [ms]
1000
R = 100 kΩ
100
10
TJ ≤ +85 °C
R = 10 kΩ
10
-40
-15
+35 +60
TJ[°C]
+10
1
+85 +110
Fig. 17
1
10
100
R [kΩ]
1000
10000
Fig. 18
11
A6155
TWD versus R at VOUTPUT = 5 V
10 000
TJ = +125 °C
TJ ≤ +85 °C
TWD [ms]
1 000
100
10
1
1
10
100
R [kΩ]
12
1000
10000
Fig. 19
A6155
TWD Coefficient versus REXT at TJ = + 25 °C
1.10
1.08
1.06
1.04
TWD Coefficient
1.02
1.00
0.98
0.96
0.94
0.92
0.90
0.88
0.86
10
100
REXT [kΩ]
1000
Fig. 20
REXT Coefficient versus TWD at TJ = + 25 °C
1.16
1.14
1.12
REXT Coefficient
1.10
1.08
1.06
1.04
1.02
1.00
0.98
0.96
0.94
0.92
0.90
10
100
TWD [ms]
1000
Fig. 21
13
A6155
Package Information
Dimensions of 8-Pin SOIC Package
E
D
e
4
3
2
5
6
7
C
A
A1
0 - 8°
L
B
H
Dimensions in mm
Min Nom Max
A 1.35 1.63 1.75
A1 0.10 0.15 0.25
B 0.33 0.41 0.51
C 0.19 0.20 0.25
D 4.80 4.94 5.00
E 3.80 3.94 4.00
e
1.27
H 5.80 5.99 6.20
L 0.40 0.64 1.27
8
Fig. 22
Dimensions of 8-Pin Plastic DIP Package
A1
A2
A
C
L
b3
eA
eB
e
b2
Dimensions in mm
b
4
3
2
1
E1
5
6
7
8
E
A
A1
A2
b
b2
b3
C
Min. Nom. Max.
5.33
0.38
2.92 3.30 4.95
0.35 0.45 0.56
1.14 1.52 1.78
0.76 0.99 1.14
0.20 0.25 0.35
D
E
E1
e
eA
eB
L
Min. Nom. Max.
9.01 9.27 10.16
7.62 7.87 8.25
6.09 6.35 7.11
2.54
7.62
10.92
2.92 3.30 3.81
Fig. 23
14
A6155
Ordering Information
When ordering please specify complete Part Number.
Part Number
Package
Delivery Form
A6155DL8A
A6155SO8A
A6155SO8B
8-pin plastic DIP
8-pin SOIC
8-pin SOIC
Stick
Stick
Tape & Reel
Package Marking
(first line)
A6155 I
6155A
6155A
EM Microelectronic-Marin SA cannot assume any responsibility for use of any circuitry described other than entirely
embodied in an EM Microelectronic-Marin SA product. EM Microelectronic-Marin SA reserves the right to change the
circuitry and specifications without notice at any time. You are strongly urged to ensure that the information given
has not been superseded by a more up-to-date version.
© 2002 EM Microelectronic-Marin SA, 03/02, Rev. E/346
15
EM Microelectronic-Marin SA, CH - 2074 Marin, Switzerland, Tel. +41 – (0)32 75 55 111, Fax +41 – (0)32 75 55 403
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