NSC DAC1054CIN Quad 10-bit voltage-output serial d/a converter with readback Datasheet

DAC1054 Quad 10-Bit Voltage-Output
Serial D/A Converter with Readback
General Description
Features
The DAC1054 is a complete quad 10-bit voltage-output digital-to-analog converter that can operate on a single 5V supply. It includes on-chip output amplifiers, internal voltage reference, and serial microprocessor interface. By combining
in one package the reference, amplifiers, and conversion
circuitry for four D/A converters, the DAC1054 minimizes
wiring and parts count and is hence ideally suited for applications where cost and board space are of prime concern.
The DAC1054 also has a data readback function, which can
be used by the microprocessor to verify that the desired
input word has been properly latched into the DAC1054’s
data registers. The data readback function simplifies the design and reduces the cost of systems which need to verify
data integrity.
The logic comprises a MICROWIRETM -compatible serial interface and control circuitry. The interface allows the user to
write to any one of the input registers or to all four at once.
The latching registers are double-buffered, consisting of 4
separate input registers and 4 DAC registers. Each DAC
register may be written to individually. Double buffering allows all 4 DAC outputs to be updated simultaneously or
individually.
The four reference inputs allow the user to configure the
system to have a separate output voltage range for each
DAC. The output voltage of each DAC can range between
0.3V and 2.8V and is a function of VBIAS, VREF, and the
input word.
Y
Y
Y
Y
Y
Y
Y
Y
Key Specifications
Y
Y
Y
Y
Y
Y
Y
Y
Y
Guaranteed monotonic over temperature
g */4 LSB max
Integral linearity error
Output settling time
3.7 ms max
Analog output voltage range
0.3V to 2.8V
Supply voltage range
4.5V to 5.5V
Clock frequency for write
10 MHz max
Clock frequency for read back
5 MHz max
Power dissipation (fCLK e 10 MHz)
100 mW max
On-board reference
2.65V g 2% max
Applications
Y
Y
Y
Y
Connection Diagram
Single a 5V supply operation
MICROWIRE serial interface allows easy interface to
many popular microcontrollers including the COPSTM
and HPCTM families of microcontrollers
Data readback capability
Output data can be formatted to read back MSB or
LSB first
Versatile logic allows selective or global update of the
DACs
Power fail flag
Output amplifiers can drive 2 kX load
Synchronous/asynchronous update of the DAC outputs
Automatic test equipment
Industrial process controls
Automotive controls and diagnostics
Instrumentation
Ordering Information
Industrial (b40§ C k TA k a 85§ C)
Package
DAC1054CIN
N24A Molded DIP
DAC1054CIWM
M24B Small Outline
Military (b55§ C k TA k a 125§ C)
DAC1054CMJ/883 or
5962-9466201MJA
J24A Ceramic DIP
TL/H/11437 – 1
Top View
COPSTM , HPCTM and MICROWIRETM are trademarks of National Semiconductor Corporation.
C1995 National Semiconductor Corporation
TL/H/11437
RRD-B30M75/Printed in U. S. A.
DAC1054 Quad 10-Bit Voltage-Output Serial D/A Converter with Readback
January 1995
Absolute Maximum Ratings
(Notes 1 & 2)
Soldering Information
N Package (10 sec.)
SO Package
Vapor Phase (60 sec.)
Infrared (15 sec.) (Note 7)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (AVCC, DVCC)
7V
g 5.5V
Supply Voltage Difference (AVCC – DVCC)
Voltage at Any Pin (Note 3)
GND b0.3V to
AVCC/DVCC a 0.3V
Input Current at Any Pin (Note 3)
Package Input Current (Note 4)
Power Dissipation (Note 5)
ESD Susceptibility (Note 6)
Human Body Model
Machine Model
260§ C
215§ C
220§ C
b 65§ C to a 150§ C
Storage Temperature
Operating Ratings (Notes 1 & 2)
Supply Voltage
4.5V to 5.5V
g 1V
Supply Voltage Difference (AVCC b DVCC)
Temperature Range
TMIN k TA k TMAX
b 40§ C k TA k 85§ C
DAC1054CIN, DAC1054CIWM
b 55§ C k TA k 125§ C
DAC1054CMJ/883
5 mA
30 mA
950 mW
2000V
200V
Converter Electrical Characteristics
The following specifications apply for AVCC e DVCC e 5V, VREF e 2.65V, VBIAS e 1.4V, RL e 2 kX (RL is the load resistor on
the analog outputs – pins 2, 13, 17, and 23) and fCLK e 10 MHz unless otherwise specified. Boldface limits apply for TA
e TJ from TMIN to TMAX. All other limits apply for TA e 25§ C.
Symbol
Parameter
Conditions
Typical
(Note 8)
Limit
(Note 9)
Units
(Limits)
10
10
bits
10
10
bits
STATIC CHARACTERISTICS
n
Resolution
Monotonicity
(Note 10)
Integral Linearity Error
DAC1054CIN, DAC1054CIWM
(Note 11)
Differential Linearity Error
Fullscale Error
(Note 12)
Fullscale Error Tempco
(Note 13)
Zero Error
(Note 14)
Zero Error Tempco
(Note 13)
Power Supply Sensitivity
(Note 15)
g 0.75
LSB (max)
g 1.0
LSB (max)
g 30
b 38
mV
ppm/§ C
g 25
b 38
mV
ppm/§ C
b 34
dB (max)
DYNAMIC CHARACTERISTICS
ts a
Positive Voltage Output
Settling Time
(Note 16)
CL e 200 pF
1.8
3.2
ms
tsb
Negative Voltage Output
Settling Time
(Note 16)
CL e 200 pF
2.3
3.7
ms
Digital Crosstalk
(Note 17)
15
mVp-p
Digital Feedthrough
(Note 18)
15
mVp-p
Clock Feedthrough
(Note 19)
20
mVp-p
Channel-to-Channel Isolation
(Note 20)
b 71
dB
Glitch Energy
(Note 21)
7
nVbs
38
mV
(Note 22)
b 49
dB
Peak Value of Largest Glitch
PSRR
Power Supply Rejection Ratio
2
Converter Electrical Characteristics (Continued)
The following specifications apply for AVCC e DVCC e 5V, VREF e 2.65V, VBIAS e 1.4V, RL e 2 kX (RL is the load resistor on
the analog outputs – pins 2, 13, 17, and 23) and fCLK e 10 MHz unless otherwise specified. Boldface limits apply for TA
e TJ from TMIN to TMAX. All other limits apply for TA e 25§ C.
Symbol
Parameter
Conditions
Typical
(Note 3)
Limit
(Note 4)
Units
(Limits)
DIGITAL AND DC ELECTRICAL CHARACTERISTICS
VIN(1)
Logical ‘‘1’’ Input Voltage
AVCC e DVCC e 5.5V
2.0
V (min)
VIN(0)
Logical ‘‘0’’ Input Voltage
AVCC e DVCC e 4.5V
0.8
V (max)
IIL
Digital Input Leakage Current
1
mA (max)
CIN
Input Capacitance
4
COUT
Output Capacitance
5
VOUT(1)
Logical ‘‘1’’ Output Voltage
ISOURCE e 0.8 mA
2.4
V (min)
VOUT(0)
Logical ‘‘0’’ Output Voltage
ISINK e 3.2 mA
0.4
V (max)
VINT
Interrupt Pin Output Voltage
10 kX Pullup
0.4
V (max)
IS
Supply Current
Outputs Unloaded
20
mA
4
9
kX (min)
kX (max)
14
pF
pF
REFERENCE INPUT CHARACTERISTICS
VREF
Input Voltage Range
RREF
Input Resistance
CREF
Input Capacitance
0 – 2.75
7
Full-Scale Data Input
V
25
pF
VBIAS INPUT CHARACTERISTICS
VBIAS
CBIAS
VBIAS Input Voltage Range
0.3 – 1.4
V
Input Leakage
1
mA
Input Capacitance
9
pF
BANDGAP REFERENCE CHARACTERISTICS (CL e 220mF)
VREFOUT
Output Voltage
DVREF/DT
Tempco
(Note 23)
Line Regulation
4.5V k VCC k 5.5V, IL e 4 mA
Load Regulation
0 k IL k 4 mA
b 1 k IL k 0 mA
VREFOUT e 0V
DVREF/DIL
ISC
Short Circuit Current
2.65 g 2%
29
V
ppm/§ C
5
mV
10
2.5
mV
mV
12
mA
AC ELECTRICAL CHARACTERISTICS
tDS
Data Setup Time
15
ns (min)
tDH
Data Hold Time
0
ns (min)
tCS
Control Setup Time
15
ns (min)
tCH
Control Hold Time
0
ns (min)
fWMAX
Clock Frequency Write
10
MHz (max)
fRMAX
Clock Frequency Readback
5
MHz (max)
tH
Minimum Clock High Time
20
ns (min)
tL
Minimum Clock Low Time
20
ns (min)
3
Converter Electrical Characteristics (Continued)
The following specifications apply for AVCC e DVCC e 5V, VREF e 2.65V, VBIAS e 1.4V, RL e 2 kX (RL is the load resistor on
the analog outputs – pins 2, 13, 17, and 23) and fCLK e 10 MHz unless otherwise specified. Boldface limits apply for TA
e TJ from TMIN to TMAX. All other limits apply for TA e 25§ C.
Symbol
Parameter
Typical
(Note 3)
Conditions
Limit
(Note 4)
Units
(Limits)
AC ELECTRICAL CHARACTERISTICS (Continued)
tCZ1
Output Hi-Z to Valid 1
fCLK e 5 MHz
70
ns (max)
tCZ0
Output Hi-Z to Valid 0
fCLK e 5 MHz
70
ns (max)
t1H
CS to Output Hi-Z
10 kX with 60 pF, fCLK e 5 MHz
150
ns (max)
t0H
CS to Output Hi-Z
10 kX with 60 pF, fCLK e 5 MHz
130
ns (max)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional. These ratings do not guarantee specific performance limits, however. For guaranteed specifications and test conditions, see the Converter Electrical
Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not
operated under the listed test conditions.
Note 2: All voltages are measured with respect to ground, unless otherwise specified.
Note 3: When the input voltage (VIN) at any pin exceeds the power supply rails (VIN k GND or VIN l V a ) the absolute value of current at that pin should be limited
to 5 mA or less.
Note 4: The sum of the currents at all pins that are driven beyond the power supply voltages should not exceed 30 mA.
Note 5: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature), HJA
(package junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature is
PDmax e (TJmax b TA)/HJA or the number given in the Absolute Maximum Ratings, whichever is lower. The table below details TJmax and HJA for the various
packages and versions of the DAC1054.
Part Number
TJmax (§ C)
HJA (§ C/W)
DAC1054CIN
DAC1054CIWM
125
125
42
57
Note 6: Human body model, 100 pF discharged through a 1.5 kX resistor.
Note 7: See AN450 ‘‘Surface Mounting Methods and Their Effect on Production Reliability’’ of the section titled ‘‘Surface Mount’’ found in any current Linear
Databook for other methods of soldering surface mount devices.
Note 8: Typicals are at TJ e 25§ C and represent most likely parametric norm.
Note 9: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 10: A monotonicity of 10 bits for the DAC1054 means that the output voltage changes in the same direction (or remains constant) for each increase in the
input code.
Note 11: Integral linearity error is the maximum deviation of the output from the line drawn between zero and full-scale (excluding the effects of zero error and fullscale error).
Note 12: Full-scale error is measured as the deviation from the ideal 2.800V full-scale output when VREF e 2.650V and VBIAS e 1.400V.
Note 13: Full-scale error tempco and zero error tempco are defined by the following equation:
Error tempco e
Ð
Error (TMAX) b Error (TMIN)
VSPAN
( ÐT
106
MAX b TMIN
(
where Error (TMAX) is the zero error or full-scale error at TMAX (in volts), and Error (TMIN) is the zero error or full-scale error at TMIN (in volts); VSPAN is the output
voltage span of the DAC1054, which depends on VBIAS and VREF.
Note 14: Zero error is measured as the deviation from the ideal 0.302V output when VREF e 2.650V, VBIAS e 1.400V, and the digital input word is all zeros.
Note 15: Power Supply Sensitivity is the maximum change in the offset error or the full-scale error when the power supply differs from its optimum 5V by up to
0.50V (10%). The load resistor RL e 2 kX.
Note 16: Positive or negative settling time is defined as the time taken for the output of the DAC to settle to its final full-scale or zero output to within g 0.5 LSB.
This time shall be referenced to the 50% point of the positive edge of CS, which initiates the update of the analog outputs.
Note 17: Digital crosstalk is the glitch measured on the output of one DAC while applying an all 0s to all 1s transition at the input of the other DACs.
Note 18: All DACs have full-scale outputs latched and DI is clocked with no update of the DAC outputs. The glitch is then measured on the DAC outputs.
Note 19: Clock feedthrough is measured for each DAC with its output at full-scale. The serial clock is then applied to the DAC at a frequency of 10 MHz and the
glitch on each DAC full-scale output is measured.
Note 20: Channel-to-channel isolation is a measure of the effect of a change in one DAC’s output on the output of another DAC. The VREF of the first DAC is varied
between 1.4V and 2.65V at a frequency of 15 kHz while the change in full-scale output of the second DAC is measured. The first DAC is loaded with all 0s.
Note 21: Glitch energy is the difference between the positive and negative glitch areas at the output of the DAC when a 1 LSB digital input code change is applied
to the input. The glitch energy will have its largest value at one of the three major transitions. The peak value of the maximum glitch is separately specified.
Note 22: Power Supply Rejection Ratio is measured by varying AVCC e DVCC between 4.50V and 5.50V with a frequency of 10 kHz and measuring the proportion
of this signal imposed on a full-scale output of the DAC under consideration.
Note 23: The bandgap reference tempco is defined by the largest value from the following equations:
Tempco (TMAX) e
Ð
VREF (TMAX) b VREF (TROOM)
VREF (TROOM)
( ÐT
106
MAX b TROOM
( or Tempco (T
MIN) e
Ð
VREF (TMIN) b VREF (TROOM)
VREF (TROOM)
where TROOM e 25§ C, VREF (TMAX) is the reference output at TMAX, and similarly for VREF (TMIN) and VREF (TROOM).
Note 24: A Military RETS specification is available upon request.
4
( ÐT
106
ROOM b TMIN
(
Typical Converter Performance Characteristics
Zero Error vs
Temperature
Full-Scale Error
vs Temperature
Supply Current
vs Temperature
Zero Error PSRR
vs Temperature
Full-Scale Error PSRR
vs Temperature
Supply Current vs
Clock Frequency
Integral Non-Linearity
Error vs Temperature
TL/H/11437 – 2
Typical Reference Performance Characteristics
Bandgap Voltage
vs Temperature
Line Regulation
vs Temperature
TL/H/11437 – 3
TL/H/11437 – 4
5
TRI-STATE Test Circuits and Waveforms
TL/H/11437 – 6
TL/H/11437–5
TL/H/11437 – 8
TL/H/11437–7
Timing Waveforms
Data Input Timing
Data Output Timing
TL/H/11437 – 10
TL/H/11437–9
Timing Diagrams
TL/H/11437 – 11
FIGURE 1. Write to One DAC with Update of Output (AU e 1), 10 MHz Maximum CLK Rate
6
Timing Diagrams (Continued)
TL/H/11437 – 12
* DACs are written to MSB first.
DAC1 is written to first, then DACs 2, 3, and 4.
FIGURE 2. Write to All DACs with Update of Outputs (AU e 1), 10 MHz Maximum CLK Rate
TL/H/11437 – 13
FIGURE 3. Read One DAC, DO LSB First, DO Changes on Falling Edge of CLK (AU e 1), 5 MHz Maximum CLK Rate
TL/H/11437 – 14
*DAC1 is read first, then DACs 2, 3, and 4.
FIGURE 4. Read All DACs, DO LSB First, DO Changes on Falling Edge of CLK (AU e 1), 5 MHz Maximum CLK Rate
7
Block Diagram
TL/H/11437 – 15
Pin Description
VOUT1(2),
VOUT2(23),
VOUT3(17),
VOUT4(13)
The voltage output connections of the
four DACS. These provide output
voltages in the range 0.3V–2.8V.
AU(11)
When this pin is taken low, all DAC outputs
will be asynchronously updated. CS must
be held high during the update. AU must be
held high during Read back.
VREFOUT(21)
The internal voltage reference output.
The output of the reference is 2.65V
g 2%.
The voltage reference inputs for the four
DACs. The allowed range is 0V – 2.75V.
VBIAS1(3),
VBIAS2(24),
VBIAS3(16),
VBIAS4(15)
The non-inverting inputs of the 4 output
amplifiers. These pins set the virtual
ground voltage for the respective DACs.
The allowed range is 0.3V–1.4V.
VREF1(1),
VREF2(22),
VREF3(18),
VREF4(14)
CS(9)
The Chip Select control input. This input is
active low.
The external clock input pin.
AGND(20),
DGND(5)
The analog and digital ground pins.
DVCC(4, 6),
AVCC(19)
The digital and analog power supply
pins. The power supply range of the
DAC1054 is 4.5V–5.5V. To guarantee
accuracy, it is required that the AVCC
and DVCC pins be bypassed separately
with bypass capacitors of 10 mF
tantalum in parallel with 0.1 mF ceramic.
CLK(8)
8
DI(10)
The serial data input. The data is clocked in
MSB first. Preceding the data byte are 4 or
6 bits of instructions. The read back
command requires 7 bits of instructions.
DO(7)
The serial data output. The data can be
clocked out either MSB or LSB first, and on
either the positive or negative edge of the
clock.
INT(12)
The power interrupt output. On an
interruption of the digital power supply, this
pin goes low. Since this pin has an open
drain output, a 10 kX pull-up resistor must
be connected to the supply.
Applications Information
The current output IOUT2, summed with the correction current IEEPROM, is applied to the internal output amplifier and
converted to a voltage. The output voltage of each DAC is a
function of VBIAS, VREF, and the digital input word, and is
given by
FUNCTIONAL DESCRIPTION
The DAC1054 is a monolithic quad 10-bit digital-to-analog
converter that is designed to operate on a single 5V supply.
Each of the four units is comprised of an input register, a
DAC register, a shift register, a current output DAC, and an
output amplifier. In addition, the DAC1054 has an onboard
bandgap reference and a logic unit which controls the internal operation of the DAC1054 and interfaces it to microprocessors.
Each of the four internal 10-bit DACs uses a modified R-2R
ladder to effect the digital-to-analog conversion (Figure 5).
The resistances corresponding to the 2 most significant bits
are segmented to reduce glitch energy and to improve
matching. The bottom of the ladder has been modified so
that the voltage across the LSB resistor is much larger than
the input offset voltage of the buffer amplifier. The input
digital code determines the state of the switches in the ladder network. An internal EEPROM, which is programmed at
the factory, is used to correct for linearity errors in the resistor ladder of each of the four internal DACs. The codes
stored in the EEPROM’s memory locations are converted to
a current, IEEPROM, with a small trim DAC. The sum of currents IOUT1 and IOUT2 is fixed and is given by
IOUT1 a IOUT2 e
#
VREF b VBIAS
R
VOUT e 2 (VREFbVBIAS)
DATA 2047
1023
a
VBIASb
VREF
1024
512
512
The output voltage range for each DAC is 0.3V – 2.8V. This
range can be achieved by using the internal 2.65V reference
and a voltage divider network which provides a VBIAS of
1.40V (Figure 6). In this case the DAC transfer function is
VOUT e 2.5
(DATA)
a 0.30244
1024
The output impedance of any external reference that is
used will affect the accuracy of the conversion. In order that
this error be less than (/2 LSB, the output impedance of the
external reference must be less than 2X.
J 1024
1023
TL/H/11437 – 16
FIGURE 5. Equivalent Circuit of R-2R Ladder and Output Amplifier
TL/H/11437 – 17
FIGURE 6. Generating a VBIAS e 1.40V from the Internal Reference, Typical Application
9
Digital Interface
high; DAC 1 is written to first, then DACs 2, 3 and 4 (in that
order). For a global write bits A0 and A1 of the instruction
byte are not required (see Figure 2 timing diagram). If the
update bit (U) is high, then the DAC output(s) will be updated on the rising edge of CS; otherwise, the new data byte
will be placed only in the input register. Chip Select (CS)
must remain low for at least one clock cycle after the last
data bit has been entered. (See Figures 1 and 2 )
When the U bit is set low an asynchronous update of all the
DAC outputs can be achieved by taking AU low. The contents of the input registers are loaded into the DAC registers, with the update occurring on the falling edge of AU. CS
must be held high during an asynchronous update.
All DAC registers will have their contents reset to all zeros
on power up.
The DAC1054 has two interface modes: a WRITE mode
and a READ mode. The WRITE mode is used to convert a
10-bit digital input word into a voltage. The READ mode is
used to read back the digital data that was sent to one or all
of the DACs. The WRITE mode maximum clock rate is
10 MHz. READ mode is limited to a 5 MHz maximum clock
rate. These modes are selected by the appropriate setting
of the RD/WR bit, which is part of the instruction byte. The
instruction byte precedes the data byte at the DI pin. In both
modes, a high level on the Start Bit (SB) alerts the DAC to
respond to the remainder of the input stream.
Table I lists the instruction set for the WRITE mode when
writing to only a single DAC, and Table II lists the instruction
set for a global write. Bits A0 and A1 select the DAC to be
written to. The DACs are always written to MSB first. All
DACs will be written to sequentially if the global bit (G) is
TABLE I. WRITE Mode Instruction Set (Writing to a Single DAC)
SB
RD/WR
G
U
A1
A0
Bit Ý1
Bit Ý2
1
0
0
0
0
0
Write DAC 1, no update of DAC outputs
1
0
0
0
0
1
Write DAC 2, no update of DAC outputs
1
0
0
0
1
0
Write DAC 3, no update of DAC outputs
1
0
0
0
1
1
Write DAC 4, no update of DAC outputs
1
0
0
1
0
0
Write DAC 1, update DAC 1 on CS rising edge
1
0
0
1
0
1
Write DAC 2, update DAC 2 on CS rising edge
1
0
0
1
1
0
Write DAC 3, update DAC 3 on CS rising edge
1
0
0
1
1
1
Write DAC 4, update DAC 4 on CS rising edge
SB
RD/WR
G
U
Bit Ý 1
Bit Ý2
Bit Ý3
Bit Ý4
1
0
1
0
Write all DACs, no update of outputs
1
0
1
1
Write all DACs, update all outputs on CS rising edge
Description
Bit Ý3 Bit Ý4 Bit Ý5 Bit Ý6
TABLE II. WRITE Mode Instruction Set (Writing to all DACs)
Description
10
Digital Interface (Continued)
following rising clock edges. With the R/F bit low, DO goes
out of TRI-STATE on the falling edge that occurs 1 clock
cycle after the end of the instruction byte; the data will continue to be sequentially clocked by the next falling clock
edges. The rising edge of CS returns DO to TRI-STATE.
Read back with the R/F bit set high is not MICROWIRE
compatible. One can choose to read the data back MSB
first or LSB first by setting the M/L bit. (See Figures 3 and
4)
Table III lists the instruction set for the READ mode. By the
appropriate setting of the global (G) and address (A1 and
A0) bits, one can select a specific DAC to be read, or one
can read all the DACs in succession, starting with DAC 1.
The R/F bit determines whether the data changes on the
rising or the falling edge of the system clock. With the R/F
bit high, DO goes out of TRI-STATE on the rising edge that
occurs 1(/2 clock cycles after the end of the instruction byte;
the data will continue to be sequentially clocked out by the
TABLE III. READ MODE Instruction Set
SB
RD/WR
G
R/F
M/L
A1
A0
Bit Ý1
Bit Ý2
Bit Ý3
Bit Ý4
Bit Ý5
Bit Ý6
Bit Ý7
1
1
0
0
0
0
0
Read DAC 1, LSB first, data changes on the falling edge
1
1
0
0
0
0
1
Read DAC 2, LSB first, data changes on the falling edge
1
1
0
0
0
1
0
Read DAC 3, LSB first, data changes on the falling edge
1
1
0
0
0
1
1
Read DAC 4, LSB first, data changes on the falling edge
1
1
0
0
1
0
0
Read DAC 1, MSB first, data changes on the falling edge
1
1
0
0
1
0
1
Read DAC 2, MSB first, data changes on the falling edge
1
1
0
0
1
1
0
Read DAC 3, MSB first, data changes on the falling edge
1
1
0
0
1
1
1
Read DAC 4, MSB first, data changes on the falling edge
1
1
0
1
0
0
0
Read DAC 1, LSB first, data changes on the rising edge
1
1
0
1
0
0
1
Read DAC 2, LSB first, data changes on the rising edge
1
1
0
1
0
1
0
Read DAC 3, LSB first, data changes on the rising edge
1
1
0
1
0
1
1
Read DAC 4, LSB first, data changes on the rising edge
1
1
0
1
1
0
0
Read DAC 1, MSB first, data changes on the rising edge
1
1
0
1
1
0
1
Read DAC 2, MSB first, data changes on the rising edge
1
1
0
1
1
1
0
Read DAC 3, MSB first, data changes on the rising edge
1
1
0
1
1
1
1
Read DAC 4, MSB first, data changes on the rising edge
1
1
1
0
0
1
0
Read all DACs, LSB first, data changes on the falling edge
1
1
1
0
1
1
0
Read all DACs, MSB first, data changes on the falling edge
1
1
1
1
0
1
0
Read all DACs, LSB first, data changes on the rising edge
1
1
1
1
1
1
0
Read all DACs, MSB first, data changes on the rising edge
Description
Power Fail Function
Power Supplies
The DAC1054 powers up with the INT pin in a Low state. To
force this output high and reset this flag, the CS pin will have
to be brought low. When this is done the INT output will be
pulled high again via an external 10 kX pull-up resistor. Anytime a power failure occurs on the DVCC line, the INT will be
set low when power is reapplied. This feature may be used
by the microprocessor to discard data whose integrity is in
question.
The DAC1054 is designed to operate from a a 5V (nominal)
supply. There are two supply lines, AVCC and DVCC. These
pins allow separate external bypass capacitors for the analog and digital portions of the circuit. To guarantee accurate
conversions, the two supply lines should each be bypassed
with a 0.1 mF ceramic capacitor in parallel with a 10 mF
tantalum capacitor.
11
Typical Applications
TL/H/11437 – 18
FIGURE 7. Trimming the Offset of a 5V Op Amp Whose Output is Biased at 2.5V
TL/H/11437 – 19
FIGURE 8. Trimming the Offset of a Dual Supply Op Amp (VIN is Ground Referenced)
TL/H/11437 – 20
FIGURE 9. Bringing the Output Range Down to Ground
12
Physical Dimensions inches (millimeters)
Order Number DAC1054CMJ/883 or 5962-9466201MJA
NS Package Number J24A
Order Number DAC1054CIWM
NS Package Number M24B
13
DAC1054 Quad 10-Bit Voltage-Output Serial D/A Converter with Readback
Physical Dimensions inches (millimeters) (Continued)
Lit. Ý 02236
Order Number DAC1054CIN
NS Package Number N24A
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