MC74VHC1G09 2-Input AND Gate with Open Drain Output Features • • • • • • • http://onsemi.com MARKING DIAGRAMS 5 M The MC74VHC1G09 is an advanced high speed CMOS 2−input AND gate with open drain output fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The internal circuit is composed of three stages, including an open drain output which provides the capability to set output switching level. This allows the MC74VHC1G09 to be used to interface 5 V circuits to circuits of any voltage between VCC and 7 V using an external resistor and power supply. The MC74VHC1G09 input structure provides protection when voltages up to 7 V are applied, regardless of the supply voltage. SC−88A / SOT−353 / SC−70 DF SUFFIX CASE 419A VX M G G 1 High Speed: tPD = 4.3 ns (Typ) at VCC = 5 V Low Internal Power Dissipation: ICC = 1 mA (Max) at TA = 25°C Power Down Protection Provided on Inputs Pin and Function Compatible with Other Standard Logic Families Chip Complexity: FETs = 62; Equivalent Gates = 16 NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable These Devices are Pb−Free and are RoHS Compliant VX M G G TSOP−5 / SOT−23 / SC−59 DT SUFFIX CASE 483 VX M G = Device Code = Date Code* = Pb−Free Package (Note: Microdot may be in either location) *Date Code orientation and/or position may vary depending upon manufacturing location. IN B 1 5 VCC PIN ASSIGNMENT OVT IN A GND 2 3 4 OUT Y 1 IN B 2 IN A 3 GND 4 OUT Y 5 VCC FUNCTION TABLE Inputs Figure 1. Pinout (Top View) IN A IN B & OUT Y Output A B Y L L H H L H L H L L L Z Figure 2. Logic Symbol ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. © Semiconductor Components Industries, LLC, 2013 October, 2013 − Rev. 18 1 Publication Order Number: MC74VHC1G09/D MC74VHC1G09 MAXIMUM RATINGS Symbol Characteristics Value Unit VCC DC Supply Voltage −0.5 to +7.0 V VIN DC Input Voltage −0.5 to +7.0 V VOUT DC Output Voltage −0.5 to 7.0 V IIK Input Diode Current −20 mA IOK Output Diode Current +20 mA IOUT DC Output Current, per Pin +25 mA ICC DC Supply Current, VCC and GND +50 mA PD Power dissipation in still air SC−88A, TSOP−5 200 mW qJA Thermal resistance SC−88A, TSOP−5 333 °C/W TL Lead temperature, 1 mm from case for 10 s 260 °C TJ Junction temperature under bias +150 °C Tstg Storage temperature −65 to +150 °C MSL Moisture Sensitivity Level 1 FR Flammability Rating VESD Oxygen Index: 28 to 34 ESD Withstand Voltage ILatchup UL 94 V−0 @ 0.125 in Human Body Model (Note 1) Machine Model (Note 2) Charged Device Model (Note 3) Latchup Performance Above VCC and Below GND at 125°C (Note 4) > 2000 > 200 N/A V ±500 mA Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Tested to EIA/JESD22−A114−A 2. Tested to EIA/JESD22−A115−A 3. Tested to JESD22−C101−A 4. Tested to EIA/JESD78 RECOMMENDED OPERATING CONDITIONS Symbol Characteristics Min Max Unit VCC DC Supply Voltage 2.0 5.5 V VIN DC Input Voltage 0.0 5.5 V DC Output Voltage 0.0 7.0 V TA Operating Temperature Range −55 +125 °C tr, tf Input Rise and Fall Time 0 0 100 20 ns/V VOUT VCC = 3.3 V ± 0.3 V VCC = 5.0 V ± 0.5 V 90 419,300 47.9 100 178,700 20.4 110 79,600 9.4 120 37,000 4.2 130 17,800 2.0 140 8,900 TJ = 80 ° C 117.8 TJ = 90 ° C 1,032,200 TJ = 100 ° C 80 FAILURE RATE OF PLASTIC = CERAMIC UNTIL INTERMETALLICS OCCUR TJ = 110° C Time, Years TJ = 120° C Time, Hours TJ = 130 ° C Junction Temperature °C NORMALIZED FAILURE RATE Device Junction Temperature versus Time to 0.1% Bond Failures 1 1 10 100 TIME, YEARS 1.0 Figure 3. Failure Rate vs. Time Junction Temperature http://onsemi.com 2 1000 MC74VHC1G09 DC ELECTRICAL CHARACTERISTICS Test Conditions TA = 25°C VCC (V) Min 1.5 2.1 3.15 3.85 Symbol Parameter VIH Minimum High−Level Input Voltage 2.0 3.0 4.5 5.5 VIL Maximum Low−Level Input Voltage 2.0 3.0 4.5 5.5 VOL Maximum Low−Level Output Voltage VIN = VIH or VIL Typ TA ≤ 85°C Max Min −55 ≤ TA ≤ 125°C Max Min 1.5 2.1 3.15 3.85 0.0 0.0 0.0 Max 1.5 2.1 3.15 3.85 Unit V 0.5 0.9 1.35 1.65 0.5 0.9 1.35 1.65 0.5 0.9 1.35 1.65 V 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 V VIN = VIH or VIL IOL = 50 mA 2.0 3.0 4.5 VIN = VIH or VIL IOL = 4 mA IOL = 8 mA 3.0 4.5 0.36 0.36 0.44 0.44 0.52 0.52 V IIN Maximum Input Leakage Current VIN = 5.5 V or GND 0 to 5.5 ±0.1 ±1.0 ±1.0 mA ICC Maximum Quiescent Supply Current VIN = VCC or GND 5.5 1.0 20 40 mA IOFF Power Off−Output Leakage Current VOUT = 5.5 V VIN = 5.5 V 0 0.25 2.5 5 mA ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ AC ELECTRICAL CHARACTERISTICS Cload = 50 pF, Input tr = tf = 3.0 ns TA = 25°C Symbol tPZL tPLZ CIN Parameter Min Test Conditions TA ≤ 85°C Typ Max Min −55 ≤ TA ≤ 125°C Max Min Max Unit ns Maximum Output Enable Time, Input A or B to Y VCC = 3.3 ± 0.3 V CL = 15 pF RL = RI = 500 W CL = 50 pF 6.2 8.7 8.8 12.3 10.5 14.0 12.5 16.5 VCC = 5.0 ± 0.5 V CL = 15 pF RL = RI = 500 W CL = 50 pF 4.3 5.8 5.9 7.9 7.0 9.0 9.0 11.0 Maximum Output Disable Time VCC = 3.3 ± 0.3 V CL = 50 pF RL = RI = 500 W 8.7 12.3 14.0 16.5 VCC = 5.0 ± 0.5 V CL = 50 pF RL = RI = 500 W 5.8 7.9 9.0 11.0 6.0 10 10 10 Maximum Input Capacitance ns pF Typical @ 25°C, VCC = 5.0 V CPD 18 Power Dissipation Capacitance (Note 5) pF 5. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no−load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC. http://onsemi.com 3 MC74VHC1G09 A VCC VCC − 7 V OVT RL VCC A or B 50% B 50% VCC Y Figure 4. Output Voltage Mismatch Application GND tPLZ tPZL HIGH IMPEDANCE VOL +0.3 V Figure 5. Switching Waveforms VCC PULSE GENERATOR R1 DUT RT CL VCC x 2 RL CL = 50 pF equivalent (Includes jig and probe capacitance) RL = R1 = 500 W or equivalent RT = ZOUT of pulse generator (typically 50 W) Figure 6. Test Circuit VCC VCC MC74VHC1G09 A 2.2 kW B B A MC74VHC1G03 1 5 2 4 220 W A GTL B E = (A • B) + (C+D) Figure 7. Complex Boolean Functions MC74VHC1G09 3.3 V 1.5 V RLED 3 C D VCC Figure 8. LED Driver Figure 9. GTL Driver ORDERING INFORMATION Device Package Shipping† MC74VHC1G09DFT1G NLVVHC1G09DFT1G* MC74VHC1G09DFT2G SC70−5 / SC−88A / SOT−353 (Pb−Free) 3000/Tape & Reel NLVVHC1G09DFT2G* MC74VHC1G09DTT1G NLV74VHC1G09DTT1G* SOT23−5 / TSOP−5 / SC59−5 (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable. http://onsemi.com 4 MC74VHC1G09 PACKAGE DIMENSIONS SC−88A (SC−70−5/SOT−353) CASE 419A−02 ISSUE L A NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. 419A−01 OBSOLETE. NEW STANDARD 419A−02. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. G 5 4 −B− S 1 2 DIM A B C D G H J K N S 3 D 5 PL 0.2 (0.008) M B M N J C K H SOLDERING FOOTPRINT* 0.50 0.0197 0.65 0.025 0.65 0.025 0.40 0.0157 1.9 0.0748 SCALE 20:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 5 INCHES MIN MAX 0.071 0.087 0.045 0.053 0.031 0.043 0.004 0.012 0.026 BSC --0.004 0.004 0.010 0.004 0.012 0.008 REF 0.079 0.087 MILLIMETERS MIN MAX 1.80 2.20 1.15 1.35 0.80 1.10 0.10 0.30 0.65 BSC --0.10 0.10 0.25 0.10 0.30 0.20 REF 2.00 2.20 MC74VHC1G09 PACKAGE DIMENSIONS TSOP−5 CASE 483−02 ISSUE K D 5X NOTE 5 2X NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSION A. 5. OPTIONAL CONSTRUCTION: AN ADDITIONAL TRIMMED LEAD IS ALLOWED IN THIS LOCATION. TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2 FROM BODY. 0.20 C A B 0.10 T M 2X 0.20 T B 5 1 4 2 B S 3 K DETAIL Z G A A TOP VIEW DIM A B C D G H J K M S DETAIL Z J C 0.05 H SIDE VIEW C SEATING PLANE END VIEW MILLIMETERS MIN MAX 3.00 BSC 1.50 BSC 0.90 1.10 0.25 0.50 0.95 BSC 0.01 0.10 0.10 0.26 0.20 0.60 0_ 10 _ 2.50 3.00 SOLDERING FOOTPRINT* 0.95 0.037 1.9 0.074 2.4 0.094 1.0 0.039 0.7 0.028 SCALE 10:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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