AD AD9803 Ccd signal processor for electronic camera Datasheet

a
CCD Signal Processor
for Electronic Cameras
AD9803
PRODUCT DESCRIPTION
FEATURES
3-Wire Serial I/F for Digital Control
18 MHz Correlated Double Sampler
Low Noise PGA with 0 dB–30 dB Range
Analog Pre-Blanking Function
AUX Input with Input Clamp and PGA
10-Bit 18 MSPS A/D Converter
Direct ADC Input with Input Clamp
Internal Voltage Reference
Two Auxiliary 8-Bit DACs
+3 V Single Supply Operation
Low Power: 150 mW at 2.7 V Supply
48-Lead LQFP Package
The AD9803 is a complete CCD and video signal processor
developed for electronic cameras. It is well suited for video
camera and still-camera applications.
The 18 MHz CCD signal processing chain consists of a CDS,
low noise PGA, and 10-bit ADC. Required clamping circuitry
and a voltage reference are also provided. The AUX input
features a wideband PGA and input clamp, and can be used to
sample analog video signals.
The AD9803 nominally operates from a single 3 V power supply, typically dissipating 170 mW. The AD9803 is packaged in a
space-saving 48-lead LQFP and is specified over an operating
temperature range of –20°C to +70°C.
FUNCTIONAL BLOCK DIAGRAM
PBLK
PGACONT1-2
CLPOB
0–30dB
AD9803
PGA
CDS
CCDIN
CLAMP
10
MUX
S/H
ADC
DOUT
CLAMP
0–10dB
CLPDM
DAC1
8-BIT
DAC
DAC2
8-BIT
DAC
AUXCONT
PGA
10-BIT
DAC
REF
CLAMP
VRT
VRB
INTF
TIMING
GENERATOR
3
3-W INTF
ADCIN AUXIN ACLP SHP SHD ADCCLK
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
AD9803–SPECIFICATIONS
GENERAL SPECIFICATIONS (T
MIN
to TMAX, ACVDD = ADVDD = DVDD = +2.8 V, fADCCLK = 18 MHz unless otherwise noted)
Parameter
Min
TEMPERATURE RANGE
Operating
Storage
–20
–65
POWER SUPPLY VOLTAGE
(For Functional Operation)
Analog
Digital
Digital Driver
2.7
2.7
2.7
POWER CONSUMPTION
(Power-Down Modes Selected Through Serial I/F)
Normal Operation (D-Reg 00)
High Speed AUX-MODE (D-Reg 01)
Reference Standby (D-Reg 10 or STBY Pin Hi)
Shutdown Mode (D-Reg 11)
(Specified Under Each Mode of Operation)
(Specified Under AUX-MODE)
10
10
MAXIMUM CLOCK RATE
Typ
3.0
3.0
3.0
Max
Units
70
150
°C
°C
3.6
3.6
3.6
V
V
V
mW
mW
(Specified Under Each Mode of Operation)
S/H AMPLIFIER
Gain
Clock Rate
0
27
A/D CONVERTER
Resolution
Differential Nonlinearity
0–255 Code
256–1023 Code
No Missing Codes
Full-Scale Input Range
Clock Rate
10
dB
MHz
Bits
± 0.5
± 0.5
GUARANTEED
1.0
0.01
REFERENCE
Reference Top Voltage
Reference Bottom Voltage
± 0.8
± 1.0
LSBs
LSBs
18
V p-p
MHz
1.75
1.25
V
V
Specifications subject to change without notice.
DIGITAL SPECIFICATIONS (T
MIN
to TMAX, DRVDD = +2.7 V, CL = 20 pF unless otherwise noted)
Parameter
Symbol
Min
LOGIC INPUTS
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
VIH
VIL
IIH
IIL
CIN
2.1
LOGIC OUTPUTS
High Level Output Voltage
Low Level Output Voltage
High Level Output Current
Low Level Output Current
VOH
VOL
IOH
IOL
2.1
SERIAL INTERFACE TIMING (Figure 35)
Maximum SCLK Frequency
SDATA to SCLK Setup
tDS
10
10
MHz
ns
tDH
tLS
tLH
10
10
10
ns
ns
ns
SCLK to SDATA Hold
SLOAD to SCLK Setup
SCLK to SLOAD Hold
Typ
Max
0.6
10
10
10
0.6
50
50
Units
V
V
µA
µA
pF
V
V
µA
µA
Specifications subject to change without notice.
–2–
REV. 0
AD9803
CCD-MODE SPECIFICATIONS
(TMIN to TMAX, ACVDD = ADVDD = DVDD = +2.8 V, fSHP = fSHD = fADCCLK = 18 MHz unless otherwise
noted)
Parameter
Min
POWER CONSUMPTION
VDD = 2.7
VDD = 2.8
VDD = 3.0
Typ
Max
150
170
185
MAXIMUM CLOCK RATE
mW
mW
mW
18
CDS
Gain
Allowable CCD Reset Transient 1
Max Input Range Before Saturation 1
MHz
0
500
PGA
Max Input Range
Max Output Range
Digital Gain Control (See Figure 26)
Gain Control Resolution
Minimum Gain (Code 0)
Low Gain (Code 207)
Medium Gain (Code 437)
High Gain (Code 688)
Max Gain (Code 1023)
Analog Gain Control (See Figure 25)
PGACONT1 = 0.7 V, PGACONT2 = 1.5 V
PGACONT1 = 1.8 V, PGACONT2 = 1.5 V
Units
1000
dB
mV
mV p-p
1000
1000
mV p-p
mV p-p
–3.5
0
22
32
10 (Fixed)
–1.5
4
15
26
0
8
30
Bits
dB
dB
dB
dB
dB
4.5
26
dB
dB
BLACK-LEVEL CLAMP
Clamp Level (Selected by the Serial I/F)
CLP(0) (E-Reg 00)
CLP(1) (E-Reg 01)
CLP(2) (E-Reg 10)
CLP(3) (E-Reg 11)
Even-Odd Offset2
34
50
66
18
± 0.5
LSB
LSB
LSB
LSB
LSB
SIGNAL-TO-NOISE RATIO 3 (@ Minimum PGA Gain)
61
dB
5
7
3
Cycles
Cycles
ns
ns
ns
ns
ns
ns
ns
TIMING SPECIFICATIONS 4
Pipeline Delay
Even-Odd Offset Correction Disabled
Even-Odd Offset Correction Enabled
Internal Clock Delay5 (tID)
Inhibited Clock Period (tINHIBIT)
Output Delay (tOD)
Output Hold Time (tHOLD)
ADCCLK, SHP, SHD, Clock Period
ADCCLK Hi-Level, Or Low Level
SHP, SHD Minimum Pulsewidth 6
SHP Rising Edge to SHD Rising Edge
15
20
2
47
20
10
20
55.6
28
14
28
NOTES
1
Input Signal Characteristics defined as shown:
500mV TYP
RESET TRANSIENT
650mV MAX
OPTICAL BLACK PIXEL
1V MAX
INPUT SIGNAL
RANGE
2V MAX
INPUT SIGNAL
W/PBLK
ENABLED
2
Even-Odd Offset is described under the Theory of Operation section. The Even-Odd Offset is measured with the Even-Off Offset correction enabled.
SNR = 20 log10 (Full-Scale Voltage/RMS Output Noise).
20 pF loading; timing shown in Figure 1.
5
Internal aperture delay for actual sampling edge.
6
Active Low Clock Pulse Mode (C-Reg 00).
3
4
Specifications subject to change without notice.
REV. 0
–3–
ns
AD9803–SPECIFICATIONS
AUX-MODE SPECIFICATIONS
(TMIN to TMAX, ACVDD = ADVDD = DVDD = +2.8 V, fADCCLK = 18 MHz unless otherwise noted)
Parameter
Min
POWER CONSUMPTION
Normal (D-Reg 00)
High Speed (D-Reg 01)
Typ
Max
80
110
MAXIMUM CLOCK RATE
PGA
Max Input Range
Max Output Range
Digital Gain Control
Gain Control Resolution
Gain (Selected by the Serial I/F)
Gain(0)
Gain(255)
mW
mW
18
MHz
700
1000
mV p-p
mV p-p
ACTIVE CLAMP (CLAMP ON)
Clamp Level (Selectable by the Serial I/F)
CLP(0) (E-Reg 00)
CLP(1) (E-Reg 01)
CLP(2) (E-Reg 10)
CLP(3) (E-Reg 11)
TIMING SPECIFICATIONS 1
Pipeline Delay
Internal Clock Delay (tID)
Output Delay (tOD)
Output Hold Time (tHOLD)
Units
8 (Fixed)
Bits
–3.5
10.5
dB
dB
34
50
66
18
LSB
LSB
LSB
LSB
4 (Fixed)
5
20
2
Cycles
ns
ns
ns
NOTES
1
20 pF loading; timing shown in Figure 2.
Specifications subject to change without notice.
ADC-MODE SPECIFICATIONS (T
MIN
to TMAX, ACVDD = ADVDD = DVDD = +2.8 V, fADCCLK = 18 MHz unless otherwise noted)
Parameter
Min
POWER CONSUMPTION (Normal D-Reg 00)
Typ
Max
65
MAXIMUM CLOCK RATE
Units
mW
18
MHz
ACTIVE CLAMP (Same as AUX-MODE)
TIMING SPECIFICATIONS (Same as AUX-MODE)
Specifications subject to change without notice.
DAC SPECIFICATIONS (DAC1 and DAC2)
Parameter
Min
Typ
Max
Units
RESOLUTION
8 (Fixed)
Bits
MIN OUTPUT
0.1
V
MAX OUTPUT
VDD – 0.1
V
MAX CURRENT LOAD
1
mA
MAX CAPACITIVE LOAD
500
pF
Specifications subject to change without notice.
–4–
REV. 0
AD9803
TIMING SPECIFICATIONS
CCD
N
N+1
N+2
N+3
N+4
tID
SHP
tINHIBIT
tID
SHD
ADCCLK
tHOLD
tOD
ADCCLK RISING EDGE PLACEMENT
D0–D9
N–8
N–7
N–6
N–5
N–4
N–3
NOTES:
1. SHP AND SHD SHOULD BE OPTIMALLY ALIGNED WITH THE CCD SIGNAL. SAMPLES ARE TAKEN AT THE RISING EDGES.
2. ADCCLK RISING EDGE MUST OCCUR AT LEAST 15ns AFTER THE RISING EDGE OF SHP (tINHIBIT).
3. RECOMMENDED PLACEMENT FOR ADCCLK RISING EDGE IS BETWEEN THE RISING EDGE OF SHD AND FALLING EDGE OF SHP.
4. OUTPUT LATENCY (7 CYCLES) SHOWN WITH EVEN-ODD OFFSET CORRECTION ENABLED.
5. ACTIVE LOW CLOCK PULSE MODE IS SHOWN.
Figure 1. CCD-MODE Timing
N+1
N
VIDEO
INPUT
N+5
N+4
N+2
N+3
tOD
tID
ADCCLK
tHOLD
N–4
D0–D9
N–3
N–2
N–1
N
NOTE:
EXAMPLE OF OUTPUT DATA LATCHED BY ADCCLK RISING EDGE.
Figure 2. AUX-MODE and ADC-MODE Timing
EFFECTIVE
PIXELS
OPTICAL BLACK
BLANKING
INTERVAL
DUMMY BLACK
EFFECTIVE
PIXELS
CCD
SIGNAL
CLPOB
CLPDM
PBLK
NOTES:
1. CLPOB PULSEWIDTH SHOULD BE A MINIMUM OF 10 OB PIXELS WIDE, 20 OB PIXELS ARE RECOMMENDED.
2. CLPDM PULSEWIDTH SHOULD BE AT LEAST 1 ms WIDE.
3. PBLK IS NOT REQUIRED, BUT RECOMMENDED IF THE CCD SIGNAL AMPLITUDE EXCEEDS 1V p-p.
4. CLPDM OVERWRITES PBLK.
5. ACTIVE LOW CLAMP PULSE MODE IS SHOWN.
Figure 3. CCD-MODE Clamp Timing
REV. 0
–5–
AD9803
TIMING SPECIFICATIONS (CONTINUED)
VIDEO
SIGNAL
H
SYNC
MANUAL CLAMPING
ACLP
AUTOMATIC CLAMPING
Figure 4. AUX-MODE Clamp Timing
NOTE: ACLP can be used two different ways. To control the
exact time of the clamp, an active low pulse is used to specify
the clamp interval. Alternatively, ACLP may be tied to ground.
In this configuration, the clamp circuitry will sense the most
negative portion of the signal and use this level to set the clamp
voltage. For the video waveform in Figure 4, the SYNC level
will be clamped to the black level specified in the E-Register.
Active low clamp pulse mode is shown.
ABSOLUTE MAXIMUM RATINGS*
Parameter
With Respect To
Min
Max
Units
ADVDD
ACVDD
DVDD
DRVDD
CLOCK INPUTS
PGACONT1, PGACONT2
PIN, DIN
DOUT
VRT, VRB
CCDBYP1, CCDBYP2
DAC1, DAC2
DRVSS, DVSS, ACVSS, ADVSS
Junction Temperature
Storage Temperature
Lead Temperature (10 sec)
ADVSS, SUBST
ACVSS, SUBST
DVSS
DRVSS
DVSS
SUBST
SUBST
DRVSS
SUBST
SUBST
SUBST
SUBST
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
6.5
6.5
6.5
6.5
DVDD + 0.3
ACVDD + 0.3
ACVDD + 0.3
DRVDD + 0.3
ADVDD + 0.3
ACVDD + 0.3
ACVDD + 0.3
+0.3
+150
+150
+300
V
V
V
V
V
V
V
V
V
V
V
V
°C
°C
°C
–65
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device
at these or other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods
may affect device reliability.
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
AD9803JST
0°C to +70°C
48-Lead Plastic Thin Quad Flatpack
ST-48
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9803 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
–6–
WARNING!
ESD SENSITIVE DEVICE
REV. 0
AD9803
VTRBYP
CMLEVEL
DAC1
SL
DAC2
ADVDD
SCK
SDATA
SUBST
ADVSS
VRT
VRB
PIN CONFIGURATION
48 47 46 45 44 43 42 41 40 39 38 37
NC 1
36 ADCIN
PIN 1
IDENTIFIER
(LSB) D0 2
35 AUXCONT
D1 3
34 AUXIN
D2 4
33 ACVDD
D3 5
D4 6
AD9803
D5 7
TOP VIEW
(Not to Scale)
D6 8
32 CLPBYP
31 ACVSS
30 PGACONT2
29 PGACONT1
D7 9
28 CCDBYP1
D8 10
27 PIN
(MSB) D9 11
26 DIN
DRVDD 12
25 CCDBYP2
NC
SHD
CLPDM
SHP
CLPOB
PBLK
STBY
DVDD
ACLP
ADCCLK
DVSS
NC = NO CONNECT
DRVSS
13 14 15 16 17 18 19 20 21 22 23 24
PIN FUNCTION DESCRIPTIONS
Pin #
Pin Name
Type
Description (See Figures 37 and 38 for Circuit Configurations)
1, 24
2–11
12
13
14
15
16
17
18
19
20
21
22
23
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
NC
D0–D9
DRVDD
DRVSS
DVSS
ACLP
ADCCLK
DVDD
STBY
PBLK
CLPOB
SHP
SHD
CLPDM
CCDBYP2
DIN
PIN
CCDBYP1
PGACONT1
PGACONT2
ACVSS
CLPBYP
ACVDD
AUXIN
AUXCONT
ADCIN
CMLEVEL
VTRBYP
DAC1
DAC2
SL
SCK
ADVDD
SDATA
ADVSS
SUBST
VRB
VRT
DO
P
P
P
P
DI
P
DI
DI
DI
DI
DI
DI
AO
AI
AI
AO
AI
AI
P
AO
P
AI
AI
AI
AO
AO
AO
AO
DI
DI
P
DI
P
P
AO
AO
No Connect (Should be Left Floating or Tied to Ground)
Digital Data Outputs
Digital Driver Supply (3 V)
Digital Driver Ground
Digital Ground
AUX-MODE/ADC-MODE Clamp
ADC Sample Clock Input
Digital Supply (3 V)
Power-Down Mode (Active Hi/Internal Pull-Down). Enables Reference Stand-By Mode.
Pixel Blanking
Black Level Restore Clamp
CCD Reference Sample Clock Input
CCD Data Sample Clock Input
Input Clamp
CDS Ground Bypass (0.1 µF to Ground)
CDS Negative Input (Tie to Pin 27 and AC-Couple to CCD Input Signal)
CDS Positive Input (See Above)
CDS Ground Bypass (0.1 µF to Ground)
PGA Coarse Gain Analog Control
PGA Fine Gain Analog Control
Analog Ground
Bias Bypass (0.1 µF to Ground)
Analog Supply (3 V)
AUX-MODE Input
AUX-MODE PGA Gain Analog Control
ADC-MODE Input
Common-Mode Level (0.1 µF to Ground)
Bias Bypass (0.1 µF to Ground)
DAC1 Output
DAC2 Output
Serial I/F Load Signal
Serial I/F Clock
Analog Supply (3 V)
Serial I/F Input Data
Analog Ground
Analog Ground
Bottom Reference (0.1 µF to Ground and 1 µF to VRT)
Top Reference (0.1 µF to Ground)
NOTE
Type: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power.
REV. 0
–7–
AD9803
EQUIVALENT INPUT CIRCUITS
DVDD
DRVDD
ACVDD
50V
10pF
SUBST
DVSS
ACVSS
DRVSS
Figure 5. Pins 2–11 (D0–D9)
Figure 8. Pin 26 (DIN) and Pin 27 (PIN)
ACVDD
DVDD
10kV
PGACONT1
OPEN – ANALOG CONTROL
CLOSED – DIGITAL CONTROL
1kV
200V
PGACONT2
8kV
DVSS
8kV
CMLEVEL
SUBST
DVSS
Figure 6. Pin 16, 21, 22 (ADCCLK, SHP, SHD)
Figure 9. Pin 29 (PGACONT1) and Pin 30 (PGACONT2)
ACVDD
ACVDD
10kV
50V
200V
30kV
SUBST
ACVSS
SUBST
ACVSS
Figure 10. Pin 32 (CLPBYP)
Figure 7. Pins 25, 28 (CCDBYP)
–8–
REV. 0
AD9803
ACVDD
ADVDD
50V
1.4pF
INTERNAL
DAC OUT
50V
70V
DAC1, DAC2
OUTPUT
39kV
SUBST
39kV
ADVSS
ACVSS
Figure 11. Pin 34 (AUXIN) and Pin 36 (ADCIN)
Figure 14. Pin 39 (DAC1) and 40 (DAC2)
DVDD
DRVDD
DATA
OUT
ACVDD
SDATA
RNW
5.5kV
OPEN – ANALOG CONTROL
CLOSED – DIGITAL CONTROL
SUBST
DATA
IN
CMLEVEL
DVSS
Figure 12. Pin 35 (AUXCONT)
DRVSS
Figure 15. Pin 44 (SDATA)
3kV
1.1kV
ADVDD
ADVDD
200V
9.3kV
ADVSS
SUBST
Figure 13. Pin 37 (CMLEVEL)
REV. 0
ADVSS
Figure 16. Pin 47 (VRB) and Pin 48 (VRT)
–9–
AD9803–Typical Performance Characteristics
240
800000
s = 0.8 LSB
700000
VDD = 3.3V
600000
NUMBER OF HITS
POWER DISSIPATION – mV
220
200
VDD = 3.0V
180
VDD = 2.8V
160
500000
400000
300000
200000
140
100000
120
4
6
8
10
12
14
SAMPLE RATE – MHz
16
0
18
29
Figure 17. CCD-MODE Power vs. Clock Rate
30
31
32 33
34
35
36
37
DIGITAL OUTPUT CODE – Decimal
38
39
Figure 20. CCD-MODE Grounded-Input Noise
(PGA Gain = MIN)
60
0.6
FUND
50
THD = –38.7dB
40
0.4
30
20
0.2
2ND
dB
0
3RD
–10
–20
–0.2
–30
5TH
4TH
–40
–0.4
–50
–0.6
0
150
300
450
600
TITLE
750
900
–60
DC
1023
Figure 18. CCD-MODE DNL at 18 MHz
1
2
3
4
5
6
FREQUENCY – MHz
7
8
9
Figure 21. AUX-MODE THD at 18 MHz
(fIN = 3.54 MHz at –3 dB)
4
60
FUND
50
2
THD = –54.1dB
40
30
0
20
10
dB
TITLE
10
0.0
–2
0
2ND
–10
–4
–20
–30
–6
3RD
4TH
5TH
–40
–50
–8
0
150
300
450
600
750
900
–60
DC
1023
Figure 19. CCD-MODE INL at 18 MHz
1
2
3
4
5
6
FREQUENCY – MHz
7
8
9
Figure 22. ADC-MODE at 18 MHz
(fIN = 3.54 MHz at –3 dB)
–10–
REV. 0
AD9803
Programmable Gain Amplifier (PGA)
THEORY OF OPERATION
Introduction
The on-chip PGA provides a gain range of 0 dB–30 dB, which
is “linear in dB.” Typical gain characteristics are shown in
Figures 25 and 26.
40
35
30
25
GAIN – dB
The AD9803 is a 10-bit analog-to-digital interface for CCD
cameras. The block level diagram of the system is shown in
Figure 23. The device includes a correlated double sampler
(CDS), 0 dB–30 dB programmable gain amplifier (PGA), black
level correction loop, input clamp and voltage reference. The
only external analog circuitry required at the system level is an
emitter follower buffer between the CCD output and AD9803
inputs.
CLPDM
INPUT CLAMP
20
15
DIFFERENTIAL SIGNAL PATH
10
PIN
CDS
PGA
5
SHA
ADC
DIN
0
–5
0
0.5
INTEG
1.0
1.5
2.0
2.5
3.0
PGACONT1 – Volts
BLACK LEVEL CLAMP
Figure 25. PGA Gain Curve—Analog Control
CLPOB
40
Figure 23. CCD Mode Signal Path
35
Correlated Double Sampling (CDS)
CDS is important in high performance CCD systems as a
method for removing several types of noise. Basically, two
samples of the CCD output are taken: one with the signal
present (“data”) and one without (“reference”). Subtracting
these two samples removes any noise which is common—or
correlated—to both.
30
GAIN – dB
25
20
15
10
Figure 24 shows the block diagram of the AD9803’s CDS. The
S/H blocks are directly driven by the input and the sampling
function is performed passively, without the use of amplifiers.
This implementation relies on the off-chip emitter follower
buffer to drive the two 10 pF sampling capacitors. Only one
capacitor at a time is seen at the input pin.
5
0
–5
0
171
341
511
682
PGA GAIN REGISTER
852
1023
Figure 26. PGA Gain Curve—Digital Control
S/H
FROM
CCD
Q1
S
OUT
S/H
Q2
10pF
Figure 24. CDS Block Diagram
As shown in Figure 27, analog PGA control is provided through
the PGACONT1 and PGACONT2 inputs. PGACONT1 provides coarse and PGACONT2 fine (1/16) gain control. The
PGA gain can also be controlled using the internal 10-bit DAC
through the serial digital interface. The gain characteristic
shown in Figure 26, with the internal DAC providing the same
control range as PGACONT1. See the Serial Interface Specifications for more details.
The AD9803 actually uses two CDS circuits in a “ping pong”
fashion to allow the system more acquisition time. In this way,
the output from one of the two CDS blocks will be valid for an
entire clock cycle. Thus, the bandwidth requirement of the
subsequent gain stage is reduced as compared to that for a singlechannel CDS system. This lower bandwidth translates to lower
power and noise.
PGACONT1
PGACONT2
A
PGACONT1 = COARSE CONTROL
PGACONT2 = FINE (1/16) CONTROL
Figure 27. Analog PGA Control
REV. 0
–11–
AD9803
Black Level Clamping
CLPDM
For correct signal processing, the CCD signal must be referenced to a well established “black level.” The AD9803 uses the
CCD’s optical black (OB) pixels as a calibration signal, which is
used to establish the black level. Two sources of offset are
addressed during the calibration—the CCD’s own “black level”
offset, and the AD9803’s internal offsets in the CDS and PGA
circuitry.
The feedback loop shown in Figure 28 is closed around the
PGA during the calibration interval (CLPOB = LOW) to set
the black level. As the black pixels are being processed, an integrator block measures the difference between the input level
and the desired reference level. This difference, or error, signal
is amplified and passed to the CDS block where it is added to
the incoming pixel data. As a result of this process, the black
pixels are digitized at one end of the ADC range, taking maximum advantage of the available linear range of the system.
Using the AD9803’s serial digital interface, the black level
reference may programmed to 16 LSB, 32 LSB, 48 LSB, or
64 LSB.
IN
CDS
PGA
ADC
CLPOB
INTEGRATOR
NEG REF
Figure 28. Black Level Correction Loop (Simplified)
The actual implementation of this loop is slightly more complicated as shown in Figure 29. Because there are two separate
CDS blocks, two black level feedback loops are required and
two offset voltages are developed. Figure 29 also shows an
additional PGA block in the feedback loop labeled “RPGA.”
The RPGA uses the same control inputs as the PGA, but has
the inverse gain. The RPGA functions to attenuate by the same
factor as the PGA amplifies, keeping the gain and bandwidth of
the loop constant.
There exists an unavoidable mismatch in the two offset voltages
used to correct both CDS blocks. This mismatch causes a
slight difference in the offset level for odd and even pixels, often
called “pixel-to-pixel offset” or “even-odd offset.” To compensate for this mismatch, the AD9803 uses a digital correction
circuit after the ADC which removes the even-odd offset between the channels.
INPUT
CLAMP
CCD
Figure 30. Input Clamp
Input Blanking
In some applications, the AD9803’s input may be exposed to
large signals from the CCD, either during blanking intervals or
“high speed” modes. If the signals are larger than the AD9803’s
1 V p-p input signal range, then the on-chip input circuitry
may saturate. Recovery time from a saturated state could be
substantial.
To avoid problems associated with processing these large transients, the AD9803 includes an input blanking function. When
active (PBLK = LOW) this function stops the CDS operation
and allows the user to disconnect the CDS inputs from the
CCD buffer. Additionally, the AD9803’s digital outputs will all
go to zero while PBLK is low.
If the input voltage exceeds the supply rail by more than
0.3 volts, then protection diodes will be turned on, increasing
current flow into the AD9803 (see Equivalent Input Circuits).
Such voltage levels should be externally clamped to prevent
possible device damage.
10-Bit Analog-to-Digital Converter (ADC)
The ADC employs a multibit pipelined architecture which is
well-suited for high throughput rates while being both area and
power efficient. The multistep pipeline presents a low input
capacitance resulting in lower on-chip drive requirements. A
fully differential implementation was used to overcome headroom constraints of the single +3 V power supply.
Differential Reference
The AD9803 includes a 0.5 V reference based on a differential,
continuous-time bandgap cell. Use of an external bypass capacitor reduces the reference drive requirements, thus lowering the
power dissipation. The differential architecture was chosen for
its ability to reject supply and substrate noise. Required decoupling is shown in Figure 31.
0.1mF
VRT
PGA
TO ADC
BLACK
LEVEL CLP
CDS1
IN
PGA
CDS
ADC
REF
CDS2
VRB
1mF
CLPOB
RPGA2
INT2
RPGA1
INT1
0.1mF
Figure 31. Reference Decoupling
NEG REF
Internal Timing
CONTROL
Figure 29. Black Level Correction Loop (Detailed)
Input Bias Level Clamping
The AD9803’s on-chip timing circuitry generates all clocks
necessary for operation of the CDS and ADC blocks. The user
needs only to synchronize the SHP and SHD clocks with the
CCD waveform, as all other timing is handled internally. The
ADCCLK signal is used to strobe the output data, and can be
adjusted to accommodate desired timing. Figure 1 shows the
recommended placement of ADCCLK relative to SHP and
SHD.
The buffered CCD output is connected to the AD9803 through
an external coupling capacitor. The dc bias point for this coupling capacitor is established during the clamping (CLPDM =
LOW) period using the “dummy clamp” loop shown in Figure
30. When closed around the CDS, this loop establishes the
desired dc bias point on the coupling capacitor.
–12–
REV. 0
AD9803
Even-Odd Pixel Offset Correction
The AD9803 includes digital correction circuitry following the
10-bit ADC. The purpose of the digital correction is remove
the residual offset between the even and odd pixel channels,
which results from the “ping-pong” CDS architecture of the
AD9803. The digital offset correction tracks the black level of
the even and odd channels, applying the necessary digital correction value to keep them balanced. There is an additional two
cycle delay when using the offset correction, resulting in pipeline delay of 7 ADCCLK cycles (see Figure 1).
ADCCLK
A/D
CONVERTER
The recommended method of controlling the input clamp is
to simply ground the ACLP input (Pin 15) to activate the
“automatic” clamping capability of the AD9803. The clamp
may also be controlled with a separate clock signal. See the
clamp timing in Figure 4 for more details.
The THD performance for fS = 18 MHz is shown in Figure 21.
When operating at fS = 18 MHz, the linearity performance is
comparable to the CCD-Mode linearity, shown in Figure 18.
The AUX-MODE can be operated at a sampling rate of up to
28.6 MHz. If the sample rate exceeds 18 MHz, then the High
Speed AUX-MODE should be programmed through the serial
interface (D-Register 01).
EVEN
2:1
MUX
+
10
AD9803
DOUT
VIDEO
SIGNAL
ODD
CLPOB
0~10 dB
AUXIN
34
PGA
2mA
DIGITAL
OFFSET
CORRECTION
–
CLP
+
LPF
CLAMP LEVEL (E-REG)
Figure 32. Digital Offset Correction
AUX
CONT
Auxiliary DACs
The AD9803 includes two 8-bit DACs for controlling any offchip system functions. These are voltage output DACs with
near rail-to-rail output capability. Output voltage levels are
programmed through the serial interface. DAC specifications
are shown on page 4, and the DAC equivalent output circuit is
shown in Figure 14.
35
ACLP
0.1mF
15
16
ADCCLK
GND
Figure 33. AUX-MODE Circuit Configuration
ADC-MODE Operation
AUX-MODE Operation
In addition to the CCD signal-processing path, the AD9803
includes an analog video-processing path. The AUXIN (Pin 34)
input consists of an input clamp, PGA, and ADC. Figure 33
shows the Input Configuration of this mode. The recommended
value of the external ac-coupling capacitor is 0.1 µF. The voltage droop with this capacitor value is 20 µV/µs.
REV. 0
ADC
SHA
0.1mF
The ADC-MODE of operation is the same as the AUX-MODE,
except there is no PGA in the signal path, only the input clamp
and ADC. Input specifications and timing for ADC-MODE are
the same as those for AUX-MODE. The THD performance is
shown in Figure 22.
–13–
AD9803
SERIAL INTERFACE SPECIFICATIONS
SDATA
A0
A1
A2
MODES
1
0
0
PGA
0
1
0
D0
D1
D2
D3
D4
d0
d1
c0
D5
D6
c1
b0
D7
D8
D9
b1
a0
a1
SELECT
e0
e1
CLAMP
LEVEL
POWER DOWN
MODES
f0
f1
f2
f3
g0
g1
g2
g3
CLOCK
MODES
f4
OUTPUT
MODES
f5
f6
OPERATION
MODES
f7
f8
f9
PGA GAIN LEVEL SELECTION
DAC1
1
1
g4
g5
g6
g7
h5
h6
h7
0
DAC1 INPUT
h0
DAC2
0
0
h1
h2
h3
h4
1
DAC2 INPUT
m0
MODES21
1
1
0
1
k0
j0
OPERATION AND
POWER DOWN MODES
SELECT
a0–a1
b0–b1
NOTE
1MODES2 REGISTER BIT D1 MUST
BE SET TO ZERO.
SHIFT REGISTER
c0–c1
d0–d1
e0–e1
f0–f9
A-REG
B-REG
C-REG
D-REG
E-REG
F-REG
(a) OPERATION MODES
(b) OUTPUT MODES
(c) CLOCK MODES
(d) POWER DOWN MODES
(e) CLAMP LEVEL
(f) PGA GAIN
g0–g7
h0–h7
G-REG
H-REG
(g) DAC1 INPUT
(h) DAC2 INPUT
j0
k0
J-REG
K-REG
M-REG
(k) EXTERNAL PGA
GAIN CONTROL
(m) DAC1 AND DAC2
POWER DOWN
(j) EVEN-ODD OFFSET
CORRECTION
m0
Figure 34. Internal Register Map
SDATA
RNW
A0
A1
A2
RISING EDGE
TRIGGERED
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
tDS
tDH
SCK
tLS
tLH
REGISTER LOADED ON
RISING EDGE
SL
Figure 35. Serial WRITE Operation
DUMMY BITS
IGNORED
SDATA
RNW
A0
A1
A2
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
XX
XX
SCK
SL
Figure 36. 16-Bit Serial WRITE Operation
–14–
REV. 0
AD9803
REGISTER DESCRIPTION
(a) A-REGISTER: Modes of Operation (Power-On Default
Value = 11)
a1
a0
Modes
0
0
1
1
0
1
0
1
ADC-MODE
AUX-MODE
CCD-MODE
CCD-MODE
(f) F-REGISTER: PGA Gain Selection (Default = 00 . . . 0)
f 9 f8 f 7 f 6 f5 f 4 f 3 f 2
Gain (0)
0 0 0 0 0 0 0 0
Gain (255) 1 1 1 1 1 1 1 1
AUX-Gain
Minimum
Maximum
(g) G-REGISTER: DAC1 Input (Default = 00 . . . 0)
g7 g6 g5 g4 g3 g2 g1 g0
(b) B-REGISTER: Output Modes (Default = 00)
DAC1 Output
b1
b0
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Code (0)
0 0 0 0 0 0 0 0
Code (255) 1 1 1 1 1 1 1 1
0
0
1
1
0
1
0
1
Normal
0 1 0 1
1 0 1 0
High Impedance
(h) H-REGISTER: DAC2 Input (Default = 00 . . . 0)
0
1
1
0
0
1
1
0
0
1
1
0
h7 h6 h5 h4 h3 h2 h1 h0
Code (0)
0 0 0 0 0 0 0 0
Code (255) 1 1 1 1 1 1 1 1
(c) C-REGISTER: Clock Modes (Default = 00)
c1 c0
SHP-SHD Clock Pulses
Clamp Active Pulses
0
0
1
1
Active Low
Active Low
Active High
Active High
Active Low
Active High
Active Low
Active High
0
1
0
1
Minimum
Maximum
DAC2 Output
Minimum
Maximum
(j) J-REGISTER: Even-Odd Offset Correction (Default = 0)
j0
Even-Odd Offset Correction
0
1
Offset Correction In Use
Offset Correction Not Used
(d) D-REGISTER: Power-Down Modes (Default = 00)
Modes
d1
d0 Description
Normal
High Speed
Power-Down 1
0
0
1
0
1
0
Power-Down 2
1
1
(k) K-REGISTER: External PGA Gain Control (Default = 0)
Normal Operation
High Speed AUX-MODE
Reference Stand-By (Same Mode
as STBY Pin 18)
Total Shut-Down
k0
PGA Gain Control
0
External Voltage Control Through AUXCONT or
PGACONT1 and PGACONT2
Internal 10-Bit DAC Control of PGA Gain
1
(m) M-REGISTER: DAC1 & DAC2 pdn (Default = 0)
(e) E-REGISTER: Clamp Level Selection (Default = 00)
CLP (0)
CLP (1)
CLP (2)
CLP (3)
e1
e0
Clamp Level
0
0
1
1
0
1
0
1
32 LSBs
48 LSBs
64 LSBs
16 LSBs
m0
Power-Down of 8-Bit DACs
0
1
8-Bit DACs Powered-Down
8-Bit DACs Operational
(f) F-REGISTER: PGA Gain Selection (Default = 00 . . . 0)
f 9 f 8 f 7 f6 f 5 f 4 f 3 f 2 f 1 f 0
Gain (0)
0 0 0 0 0 0 0 0 0 0
Gain (1023) 1 1 1 1 1 1 1 1 1 1
REV. 0
CCD-Gain
Minimum
Maximum
–15–
AD9803
NOTE: With the exception of a write to the PGA register during AUX-mode, all data writes must be 10 bits. During an
AUX-mode write to the PGA register, only 8 bits of data are
required. If more than 14 SCK rising edges are applied during a
write operation, additional SCK pulses will be ignored (see
Figure 35). All reads must be 10 bits to receive valid register
contents. All registers default to 0s on power-up, except for the
A-register which defaults to 11. Thus, on power-up, the AD9803
defaults to CCD mode. During the power-up phase, it is recommended that SL be HIGH and SCK be LOW to prevent accidental register write operations. SDATA may be unknown. The
RNW bit (“Read/Not Write”) must be LOW for all write operations to the serial interface, and HIGH when reading back from
the serial interface registers.
APPLICATIONS INFORMATION
Power and Grounding Recommendations
The AD9803 should be treated as an analog component when
used in a system. The same power supply and ground plane
should be used for all of the pins. In a two-ground system, this
requires that the digital supply pins be decoupled to the analog
ground plane and the digital ground pins be connected to analog ground for best noise performance. Separate digital supplies
can be used, particularly if slightly different driver supplies are
needed, but the digital power pins should still be decoupled to
the same point as the digital ground pins (the analog ground
plane). If the AD9803 digital outputs need to drive a bus or
substantial load, then a buffer should be used at the AD9803’s
outputs, with the buffer referenced to system digital ground. In
some cases, when system digital noise is not substantial, it is
acceptable to split the ground pins on the AD9803 to separate
analog and digital ground planes. If this is done, be sure to
connect the two ground planes together at the AD9803.
To further improve performance, isolating the driver supply
DRVDD from DVDD with a ferrite bead can help reduce kickback effects during major code transitions. Alternatively, the
use of damping resistors on the digital outputs will reduce the
output rise times, also reducing the kickback effect.
Application Circuit Utilizing the AD9803’s Digital Gain Control
Figure 37 shows the recommended circuit configuration for
CCD-Mode operation when using the 3-wire serial interface.
The analog PGA control pins, PGACONT1 and PGACONT2,
should be shorted together and decoupled to ground. If the two
auxiliary DACs are not used, then Pins 39 and 40 (DAC1 and
DAC2) may be grounded.
Using the AD9803 in AD9801 Sockets
The AD9803 may be easily used in existing AD9801 designs
without any circuit modifications. Most of the pin assignments
are the same for both ICs. Table I outlines the differences. The
circuit of Figure 38 shows the necessary connections for the
AD9803 when used in an existing AD9801 socket. The poweron reset in the AD9803 assures that the device will power-up in
CCD-mode, with analog PGA gain control.
Table I. AD9801/AD9803 Pin Differences
Pin
No.
AD9801
AD9803
AD9801 Connection
1
14
15
24
32
ADVSS
DSUBST
DVSS
DVSS
CLAMP_BIAS
NC
DVSS
ACLP
NC
CLPBYP
34
35
36
ACVDD
ACVDD
INT_BIAS1
AUXIN
AUXCONT
ADCIN
38
INT_BIAS2
VTRBYP
39
40
41
42
44
MODE2
MODE1
ADVSS
ADVDD
ADVSS
DAC1
DAC2
SL
SCK
SDATA
Ground
Ground
Ground
Ground
Decoupled with 0.1 µF
to Ground
+3 Volt Supply
+3 Volt Supply
Decoupled with 0.1 µF
to Ground
Decoupled with 0.1 µF
to Ground
Ground
Ground
Ground
+3 Volt Supply
Ground
–16–
REV. 0
AD9803
SDATA
SCK
SL
VDD
0.1mF
VOUT2
VOUT1
0.1mF
0.1mF
1.0mF
0.1mF
0.1mF
CMLEVEL
DAC1
VTRBYP
SL
DAC2
SCK
SDATA
ADVDD
SUBST
VRT
ADVSS
VDD
1
NC
2
D0 (LSB)
3
D1
AUXIN 34
4
D2
ACVDD 33
5
D3
CLPBYP 32
6
D4
7
D5
8
D6
PGACONT1 29
9
D7
CCDBYP1 28
10
D8
PIN 27
11
D9 (MSB)
DIN 26
0.1mF
0.1mF
ACVSS 31
PGACONT2 30
NC
SHD
CLPDM
SHP
CLPOB
PBLK
STBY
CCDBYP2 25
DVDD
ACLP
DRVDD
ADCCLK
AD9803
DVSS
12
ADCIN 36
AUXCONT 35
DRVSS
DIGITAL
OUTPUT
DATA
VRB
48 47 46 45 44 43 42 41 40 39 38 37
0.1mF
0.1mF
0.1mF
CCD
SIGNAL
INPUT
0.1mF
13 14 15 16 17 18 19 20 21 22 23 24
VDD
0.1mF
CLPDM
SHD
SHP
CLPOB
PBLK
ADCCLK
VDD
0.1mF
NC = NO CONNECT
Figure 37. CCD-Mode Circuit Configuration—Digital PGA Control
REV. 0
–17–
AD9803
VDD
0.1mF
0.1mF
0.1mF
1.0mF
0.1mF
0.1mF
0.1mF
CMLEVEL
DAC1
VTRBYP
SL
DAC2
SCK
SDATA
ADVDD
SUBST
ADVSS
VRT
0.1mF
ADCIN 36
1
NC
2
D0 (LSB)
3
D1
4
D2
ACVDD 33
5
D3
CLPBYP 32
6
D4
7
D5
8
AUXCONT 35
0.1mF
AUXIN 34
0.1mF
VDD
0.1mF
ACVSS 31
AD9803
PGACONT1
9
D7
CCDBYP1 28
10
D8
PIN 27
11
D9 (MSB)
DIN 26
12
DRVDD
NC
CLPDM
SHD
SHP
CLPOB
PBLK
DVDD
CCDBYP2 25
STBY
ACLP
PGACONT1 29
ADCCLK
PGACONT2
D6
DVSS
PGACONT2 30
DRVSS
DIGITAL
OUTPUT
DATA
VRB
48 47 46 45 44 43 42 41 40 39 38 37
0.1mF
CCD SIGNAL INPUT
0.1mF
0.1mF
13 14 15 16 17 18 19 20 21 22 23 24
VDD
0.1mF
CLPDM
SHD
SHP
CLPOB
PBLK
STBY
ADCCLK
VDD
0.1mF
NC = NO CONNECT
Figure 38. Recommended Circuit for AD9801 Sockets
–18–
REV. 0
AD9803
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
48-Lead Plastic Thin Quad Flatpack (LQFP)
(ST-48)
0.063 (1.60) MAX
0.276 (7.0) BSC
0.276 (7.0) BSC
37
36
48
1
SEATING
PLANE
TOP VIEW
(PINS DOWN)
0.076 MAX
NO MIN
0° – 7°
REV. 0
0° MIN
0.007 (0.18)
0.004 (0.09)
12
13
0.019 (0.5)
BSC
–19–
25
24
0.009 (0.225)
0.006 (0.17)
0.354 (9.00) BSC
0.030 (0.75)
0.018 (0.45)
0.354 (9.00) BSC
0.030 (1.45)
(0.75)
0.057
0.018 (1.35)
(0.45)
0.053
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