ISSI IS25C128A-3ZLI 128k-bit spi serial electrically erasable prom Datasheet

IS25C128A
128K-bit SPI SERIAL
ELECTRICALLY ERASABLE PROM
Advanced Information
DECEMBER 2008
FEATURES
DESCRIPTION
• Serial Peripheral Interface (SPI) Compatible
— Supports SPI Modes 0 (0,0) and 3 (1,1)
• Low power CMOS
— Active current less than 3.0 mA (1.8V)
— Standby current less than 15 µA (1.8V)
• Low-voltage Operation
— Vcc = 1.8V to 5.5V
• Block Write Protection
— Protect 1/4, 1/2, or Entire Array
• 64-byte page write mode
— Partial page writes allowed
• 10 MHz Clock Rate (5V)
• Self timed write cycles
— 5ms max @ 2.5V
• High-reliability
— Endurance: 1,000,000 cycles
— Data retention: 40 years
• Packages: SOIC/SOP, TSSOP and PDIP
• Industrial temperature range
• Lead free
The IS25C128A is electrically erasable PROM devices
that use the Serial Peripheral Interface (SPI) for
communications. The IS25C128A is 128Kbit
(16K x 8). The IS25C128A EEPROMs is offered in a
wide operating voltage range of 1.8V to 5.5V for
compatibility with most application voltages. ISSI
designed the IS25C128A to be an efficient SPI EEPROM
solution. The device is offered in lead-free, RoHS,
halogen free or Green. The available package types are
8-pin SOIC, TSSOP and PDIP.
The functional features of the IS25C128A allow them to
be among the most advanced serial non-volatile memories available. Each device has a Chip-Select (CS) pin,
and a 3-wire interface of Serial Data In (SI), Serial Data
Out (SO), and Serial Clock (SCK). While the 3-wire
interface of the IS25C128A provides for high-speed
access, a HOLD pin allows the memories to ignore the
interface in a suspended state; later the HOLD pin reactivates communication without re-initializing the serial
sequence. A Status Register facilitates a flexible write
protection mechanism, and a device-ready bit (RDY).
Copyright © 2008 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for critical medical or surgical equipment,
aerospace systems, or for other applications planned to support or sustain life. It is the customer's obligation to optimize the design in their own products for the best
performance and optimization on the functionality and etc. ISSI assumes no liability arising out of the application or use of any information, products or services described
herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and prior placing orders for products.
Integrated Silicon Solution, Inc.
Advanced Information Rev. 00E
11/25/08
1
IS25C128A
PIN CONFIGURATION
8-Pin DIP, TSSOP and SOIC
CS
1
8
VCC
SO
2
7
HOLD
WP
3
6
SCK
GND
4
5
SI
PIN DESCRIPTIONS
CS
Chip Select
SCK
SI
SO
GND
VCC
WP
HOLD
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
Power
Write Protect
Suspends Serial Input
PIN DESCRIPTIONS
Serial Clock (SCK): This timing signal provides synchronization between the microcontroller and
IS25C128A. Op-Codes, byte addresses, and data are
latched on SI with a rising edge of the SCK. Data on SO
is refreshed on the falling edge of SCK for SPI modes
(0,0) and (1,1).
Serial Data Input (SI): This is the input pin for all data
that the IS25C128A is required to receive.
Serial Data Output (SO): This is the output pin for all
data transmitted from the IS25C128A.
2
CS
Chip Select (CS
CS): The CS pin activates the device.
Upon power-up, CS should follow Vcc. When the device
is to be enabled for instruction input, the signal requires
a High-to-Low transition. While CS is stable Low, the
master and slave will communicate via SCK, SI, and SO
signals. Upon completion of communication, CS must
be driven High. At this moment, the slave device may
start its internal write cycle. When CS is high, the
device enters a power-saving standby mode, unless an
internal write operation is underway. During this mode,
the SO pin becomes high impedance.
WP
Write Protect (WP
WP): The purpose of this input signal is
to initiate Hardware Write Protection mode. This mode
prevents the Block Protection bits and the WPEN bit in
the Status Register from being altered. To cause
Hardware Write Protection, WP must be Low at the same
time WPEN is 1. WP may be hardwired to Vcc or GND.
HOLD
HOLD (HOLD
HOLD): This input signal is used to suspend the
device in the middle of a serial sequence and temporarily
ignore further communication on the bus (SI, SO, SCK).
Together with Chip Select, the HOLD signal allows
multiple slaves to share the bus. The HOLD signal
transitions must occur only when SCK is Low, and be
held stable during SCK transitions. (See Figure 8 for
Hold timing) To disable this feature, HOLD may be
hardwired to Vcc.
Integrated Silicon Solution, Inc.
Advanced Information Rev. 00E
11/25/08
IS25C128A
SERIAL INTERFACE DESCRIPTION
MASTER: The device that provides a clock signal.
SLAVE: The IS25C128A is a slave because the clock
signal is an input.
TRANSMITTER/RECEIVER: The IS25C128A has both
data input (SI) and data output (SO).
MSB: The most significant bit. It is always the first bit
transmitted or received.
OP-CODE: The first byte transmitted to the slave
following CS transition to LOW. If the OP-CODE is a
valid member of the IS25C128A instruction set (Table 3),
then it is decoded appropriately. If the OP-CODE is not
valid, and the SO pin remains in high impedance.
BLOCK DIAGRAM
VCC
STATUS
REGISTER
GND
16K x 8
MEMORY ARRAY
DATA
REGISTER
ADDRESS
DECODER
SI
CS
WP
SCK
OUTPUT
BUFFER
MODE
DECODE
LOGIC
CLOCK
SO
HOLD
Integrated Silicon Solution, Inc.
Advanced Information Rev. 00E
11/25/08
3
IS25C128A
STATUS REGISTER
The status register contains 8-bits for write protection
control and write status. (See Table 1). It is the only
region of memory other than the main array that is
accessible by the user.
Table 1. Status Register Format
Bit 7
WPEN
Bit 6 Bit 5 Bit 4
X
X
X
Bit 3 Bit 2
Bit1 Bit 0
BP1 BP0 WEN RDY
Notes:
1. X = Don't care bit.
2. During internal write cycles, bits 0 to 7 are temporarily 1's.
The Status Register is Read-Only if either: a) Hardware
Write Protection is enabled or b) WEN is set to 0. If
neither is true, it can be modified by a valid instruction.
RDY
Ready (RDY
RDY), Bit 0: When RDY = 1, it indicates that
the device is busy with a write cycle. RDY = 0 indicates that the device is ready for an instruction. If RDY
= 1, the only command that will be handled by the
device is Read Status Register.
Write Enable (WEN), Bit 1: This bit represents the
status of device write protection. If WEN = 0, the Status
Register and the entire array is protected from modification, regardless of the setting of WPEN, WP pin, or block
protection. The only way to set WEN to 1 is via the
Write Enable command (WREN). WEN is reset to 0
upon power-up.
4
Block Protect (BP1, BP0), Bits 2-3: Together, these
bits represent one of four block protection configurations
implemented for the memory array. (See Table 2 for
details.)
BP0 and BP1 are non-volatile cells similar to regular
array cells, and factory programmed to 0. The block of
memory defined by these bits is always protected,
regardless of the setting of WPEN, WP , or WEN.
Table 2. Block Protection
Status
Register
Bits
Array Addresses Protected
Level
BP1
BP0
IS25C128A
0
1(1/4)
0
0
0
1
2(1/2)
1
0
3(All)
1
1
None
3000h
-3FFFh
2000h
-3FFFh
0000h
-3FFFh
Don’t Care, Bits 4-6: Each of these bits can receive
either 0 or 1, but values will not be retained. When
these bits are read from the register, they are always 0.
Write Protect Enable (WPEN), Bit 7: This bit can be
used in conjunction with WP pin to enable Hardware
Write Protection, which causes the Status Register to
be read-only. The memory array is not protected by this
mode. Hardware Write Protection requires that WP = 0
and WPEN = 1; it is disabled otherwise. Note: WPEN
cannot be changed from 1 to 0 if the WP pin is already
set to Low. (See Table 4 for data protection relationship)
Integrated Silicon Solution, Inc.
Advanced Information Rev. 00E
11/25/08
IS25C128A
DEVICE OPERATION
The operations of the IS25C128A are controlled by a set of instructions that are clocked-in serially SI pin. (See Table
3). To begin an instruction, the chip select (CS) should be dropped Low. Subsequently, each Low-to-High transition of
the clock (SK) will latch a stable value on the SI pin. After the 8-bit op-code, it may be appropriate to continue to input
an address or data to SI, or to output data from SO. During data output, values appear on the falling edge of SK. All
bits are transferred with MSB first. Upon the last bit of communication, but prior to any following Low-to-High transition
of SK, CS should be raised High to end the transaction. The device then would enter Standby Mode if no internal
programming were underway.
Table 3. Instruction Set
Name
Op-code
WREN
0000 X110
WRDI
0000 X100
Operation
Address
Data(SI)
Data (SO)
Set Write Enable Latch
-
-
-
Reset Write Enable Latch
-
-
-
RDSR
0000 X101
Read Status Register
-
-
D7-D0,...
WRSR
0000 X001
Write Status Register
-
D7-D0
-
READ
0000 X011
Read Data from Array
A15-A0
-
D7-D0,...
WRITE
0000 X010
Write Data to Array
A15-A0
D7-D0,...
-
Notes:
1. X = Don’t care bit. For consistency, it is best to use “0”.
2. Some address bits are don’t care. See Table 5.
3. If the bits clocked-in for an op-code are invalid, SO remains high impedance, and upon CS going High there is no affect. A
valid op-code with an invalid number of bits clocked-in for address or data will cause an attempt to modify the array or
Status Register to be ignored.
WRITE ENABLE (WREN)
When Vcc is initially applied, the device powers up with
both status register and entire array in a write-disabled
state. Upon completion of Write Disable (WRDI), Write
Status Register (WRSR), or Write Data to Array
(WRITE), the device resets the WEN bit in the Status
Register to 0. Prior to any data modification, a WREN
instruction is necessary to set WEN to 1. (See Figure 2
for timing).
READ STATUS REGISTER (RDSR)
The Read Status instruction tells the user the status of
Write Protect Enable, the Block Protection setting (see
Table 2), the Write Enable state, and the RDY status.
RDSR is the only instruction accepted when a write
cycle is underway. It is recommended that the status of
Write Enable and RDY be checked, especially prior to
an attempted modification of data. The 8 bits of the
Status Register can be repeatedly output on SO after
the initial Op-code. (See Figure 4 for timing).
WRITE DISABLE (WRDI)
The device can be completely protected from modification by resetting WEN to 0 through the WRDI instruction. (See Figure 3 for timing).
Integrated Silicon Solution, Inc.
Advanced Information Rev. 00E
11/25/08
5
IS25C128A
WRITE STATUS REGISTER (WRSR)
This instruction lets the user choose a Block Protection
setting, and set or reset the WPEN bit. The values of
the other data bits incorporated into WRSR can be 0 or
1, and are not stored in the Status Register. WRSR will
be ignored unless both the following are true: a) WEN =
1, due to a prior WREN instruction; and b) Hardware
Write Protection is not enabled. (See Table 4 for details). Except for the RDY status, the values in the
Status Register remain unchanged until the moment
when the write cycle is complete and the register is
updated. Note: WPEN can be changed from 1 to 0 only
if WP is already set High. Once completed, WEN is
reset for complete chip write protection. (See Figure 5
for timing).
READ DATA (READ)
This instruction begins with the op-code and the 16-bit
address, and causes the selected data byte to be
shifted out on SO. Following this first data byte, additional sequential bytes are output. If the data byte in the
highest address is output, the address rolls-over to the
lowest address in the array, and the output could loop
indefinitely. At any time, a rising CS signal completes
the operation. (See Figure 6 for timing).
WRITE DATA (WRITE)
The WRITE instruction begins with the op-code, the 16bit address of the first byte to be modified, and the first
data byte. Additional data bytes may be written sequentially to the array after the first byte. Each WRITE
instruction can affect the contents of a 64 byte page, but
no more. The page begins at address XXXXXXXX
XX000000, and ends with XXXXXXXX XX111111. If the last
byte of the page is input, the address rolls over to the
beginning of the same page. More than 64 data bytes
can be input during the same instruction, but upon a
completed write cycle, a page would only contain the
last 64 bytes.
The region of the array defined within Block Protection
cannot be modified as long as that block configuration is
selected. The region of the array outside the Block
Protection can only be modified if Write Enable (WEN) is
set to 1. Therefore, it may be necessary that a WREN
instruction occur prior to WRITE. Hardware Write
Protection has no affect on the memory array. Once
Write is completed, WEN is reset for complete chip
write protection. (See Figure 7 for timing).
Table 5. Address Key
Name
IS25C128A
AN
Don't
Care Bits
A13-A0
A15-A14
Table 4. Write Protection
WPEN
0
0
1
1
X
X
WP
Hardware Write
Protection
WEN
Inside Block
Outside Block
Status Register
(WPEN, BP1, BP0)
X
X
0
0
1
1
Not Enabled
Not Enabled
Enabled
Enabled
Not Enabled
Not Enabled
0
1
0
1
0
1
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Unprotected
Read-only
Unprotected
Read-only
Unprotected
Read-only
Unprotected
Read-only
Read-only
Read-only
Unprotected
Note: X = Don't care bit.
6
Integrated Silicon Solution, Inc.
Advanced Information Rev. 00E
11/25/08
IS25C128A
ABSOLUTE MAXIMUM RATINGS (1)
Symbol
VS
VP
TBIAS
TSTG
IOUT
Parameter
Supply Voltage
Voltage on Any Pin
Temperature Under Bias
Storage Temperature
Output Current
Value
-0.5 to + 6.5
–0.5 to Vcc + 0.5
–55 to +125
–65 to +150
5
Unit
V
V
°C
°C
mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions outside those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
POWER SUPPLY CHARACTERISTICS
TA = –40°C to +85°C
Symbol Parameter
Test Conditions
Min.
Max.
Unit
ICC1
Operating Current
Read/Write at 10 MHz (Vcc = 5V)
—
10.0
mA
ICC2
Operating Current
Read/Write at 5 MHz (Vcc = 2.5V)
—
4.0
mA
ICC3
Operating Current
Read/Write at 5 MHz (Vcc = 1.8V)
—
3.0
mA
ISB1
Standby Current
Vcc = 5.0V, VIN = VCC or GND, CS = Vcc
—
25
µA
ISB2
Standby Current
Vcc = 2.5V, VIN = VCC or GND, CS = Vcc
—
20
µA
ISB3
Standby Current
Vcc = 1.8V, VIN = VCC or GND, CS = Vcc
—
15
µA
CAPACITANCE(1,2)
Symbol
Parameter
CIN
Input Capacitance
COUT
Output Capacitance
Conditions
Max.
Unit
VIN = 0V
6
pF
VOUT = 0V
8
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters and not 100%
tested.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 5.0V.
Integrated Silicon Solution, Inc.
Advanced Information Rev. 00E
11/25/08
7
IS25C128A
DC ELECTRICAL CHARACTERISTICS
TA = –40°C to +85°C
8
Symbol Parameter
Test Conditions
Min.
Max.
Unit
VOL1
Output LOW Voltage
VCC = 5V, IOL = 3 mA
—
0.4
V
VOL2
Output LOW Voltage
VCC = 2.5V, IOL = 1.5 mA
—
0.4
V
VOL3
Output LOW Voltage
VCC = 1.8V, IOL = 0.15 mA
—
0.2
V
VOH1
Output HIGH Voltage
VCC = 5V, IOH = -3 mA
0.8 X VCC
—
V
VOH2
Output HIGH Voltage
VCC = 2.5V, IOH = -0.4mA
0.8 X VCC
—
V
VOH3
Output HIGH Voltage
VCC = 1.8V, IOH = -0.1mA
0.8 X VCC
—
V
VIH
Input HIGH Voltage
0.7X VCC
VCC + 1
V
VIL
Input LOW Voltage
-1.0
0.3 X VCC
V
ILI
Input Leakage Current
VIN = 0V TO VCC
-3
3
µA
ILO
Output Leakage Current
VOUT = 0V TO VCC, CS = VCC
-3
3
µA
Integrated Silicon Solution, Inc.
Advanced Information Rev. 00E
11/25/08
IS25C128A
AC Characteristics
TA = –40°C to +85°C
1.8V ≤ Vcc < 4.5V
Symbol
Parameter
fSCK
4.5V ≤ Vcc ≤ 5.5V
Min
Max
Min
Max
Units
SCK Clock Frequency
0
5
0
10
MHz
tRI
Input Rise Time
—
2
—
2
µs
tFI
Input Fall Time
—
2
—
2
µs
tWH
SCK High Time
90
—
40
—
ns
tWL
SCK Low Time
90
—
40
—
ns
tCS
CS High Time
100
—
40
—
ns
tCSS
CS Setup Time
90
—
40
—
ns
tCSH
CS Hold Time
90
—
25
—
ns
tSU
Data In Setup Time
20
—
15
—
ns
tH
Data In Hold Time
30
—
15
—
ns
tHD
Hold Setup Time
50
—
25
—
ns
tCD
Hold Hold Time
50
—
25
—
ns
tV
Output Valid
0
60
0
25
ns
tHO
Output Hold Time
0
—
0
—
ns
tLZ
Hold to Output Low Z
0
50
0
25
ns
tHZ
Hold to Output High Z
—
100
—
25
ns
tDIS
Output Disable Time
—
100
—
25
ns
tWC
Write Cycle Time
—
5
—
5
ms
CL = 100pF
Integrated Silicon Solution, Inc.
Advanced Information Rev. 00E
11/25/08
9
IS25C128A
TIMING DIAGRAMS
Figure 1. Synchronous Data Timing
CS
tCS
VIH
VIL
tCSH
tCSS
SK
VIH
VIL
DIN
VIH
VIL
DOUT
VOH
VOL
tWH
tSU
tWL
tH
VALID IN
tV
HIGH-Z
tHO
tDIS
HIGH-Z
Figure 2. WREN Timing
CS
SK
DIN
DOUT
WREN OP-CODE
HIGH-Z
Figure 3. WRDI Timing
CS
SK
DIN
DOUT
10
WRDI OP-CODE
HIGH-Z
Integrated Silicon Solution, Inc.
Advanced Information Rev. 00E
11/25/08
IS25C128A
Figure 4. RDSR Timing
CS
SK
Din
Instruction
DATA OUT
7 6 5 4 3 2 1 0
Dout
Note: The "Don't Care" bit of the op-code is set to 0 in the above instruction for consistency.
Figure 5. WRSR Timing
CS
SK
Din
Instruction
DATA IN
7 6 5
4
3
2
1
0
Dout
Note: The "Don't Care" bit of the op-code is set to 0 in the above instruction for consistency.
Figure 6. READ Timing
CS
SK
Instruction
Din
Dout
BYTE Address
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA OUT
7 6 5 4 3 2 1 0
Note: The "Don't Care" bit of the op-code is set to 0 in the above instruction for consistency.
Integrated Silicon Solution, Inc.
Advanced Information Rev. 00E
11/25/08
11
IS25C128A
Figure 7. WRITE Timing
CS
SK
Instruction
BYTE Address
Din
DATA IN
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Dout
Note: The "Don't Care" bit of the op-code is set to 0 in the above instruction for consistency.
Figure 8. HOLD Timing
CS
tCD
tCD
SCK
tHD
tHD
HOLD
tHZ
DOUT
tLZ
12
Integrated Silicon Solution, Inc.
Advanced Information Rev. 00E
11/25/08
IS25C128A
Figure 9. Entry into Deep Sleep Timing
CS
3 μs (max)
SK
Instruction
Din
Dout
Figure 10. Release from Deep Sleep Timing
30 μs (max)
CS
SK
Instruction
Din
Dout
Integrated Silicon Solution, Inc.
Advanced Information Rev. 00E
11/25/08
13
IS25C128A
ORDERING INFORMATION
Industrial Range: –40°C to +85°C
Voltage
Range
Part Number*
Package*
2.5V
to 5.5V
IS25C128A-3GLI
IS25C128A-3ZLI
150-mil SOIC (JEDEC)
3 x 4.4mm TSSOP
1.8V
to 5.5V
IS25C128A-2GLI
IS25C128A-2ZLI
IS25C128A-2PLI
150-mil SOIC (JEDEC)
3 x 4.4mm TSSOP
300-mil PDIP
*
1. Contact ISSI Sales Representatives for availability and other information.
2. Most listed part numbers are packed in tube.
3. For tape and reel, add “-TR” at the end of the P/N.
4. Refer to ISSI website for related declaration document on lead free, RoHS, halogen free, or Green, whichever is applicable.
5. ISSI offers Industrial grade for Commercial applications (0oC to +70oC).
14
Integrated Silicon Solution, Inc.
Advanced Information Rev. 00E
11/25/08
IS25C128A
Integrated Silicon Solution, Inc.
Advanced Information Rev. 00E
11/25/08
15
IS25C128A
Thin Shrink Small Outline TSSOP
Package Code: Z (8 pin, 14 pin)
N
E1
1
E
α
N/2
A1
D
A2
A
L
C
e
B
TSSOP (Z)
Ref. Std.
JEDEC MO-153
No. Leads
8
Millimeters
Inches
Symbol Min Max
Min Max
A
—
1.20
— 0.047
A1
0.05 0.15
0.002 0.006
A2
0.80 1.05
0.032 0.041
B
0.19 0.30
0.007 0.012
C
0.09 0.20
0.004 0.008
D
2.90 3.10
0.114 0.122
E1
4.30 4.50
0.169 0.177
E
6.40 BSC
0.252 BSC
e
0.65 BSC
0.026 BSC
L
0.45 0.75
0.018 0.030
α
—
8°
—
8°
TSSOP (Z)
Ref. Std.
JEDEC MO-153
No. Leads
14
Millimeters
Inches
Symbol Min Max
Min Max
A
—
1.20
—
0.047
A1
0.05 0.15
0.002 0.006
A2
0.80 1.05
0.031 0.041
B
0.19 0.30
0.007 0.012
C
0.09 0.20
0.0035 0.008
D
4.90 5.10
0.193 0.201
E1
4.30 4.50
0.170 0.177
E
6.40 BSC
0.252 BSC
e
0.65 BSC
0.026 BSC
L
0.45 0.75
0.0177 0.0295
α
—
8°
—
8°
SSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may
appear in this publication. © Copyright 2002, Integrated Silicon Solution, Inc.
16
Integrated Silicon Solution, Inc.
Advanced Information Rev. 00E
11/25/08
IS25C128A
300-mil Plastic DIP
Package Code: N,P
N
E1
1
D
S
S
SEATING PLANE
B1
E
A
L
C
A1
FOR
32-PIN ONLY
e
MILLIMETERS
Sym.
Min.
B
INCHES
Max.
Min.
Max.
4.57
9.53
8.26
0.145
0.015
0.014
0.045
0.032
0.008
0.359
0.300
0.180
E
3.68
0.38
0.36
1.14
0.81
0.20
9.12
7.62
E1
6.20
6.60
0.244
0.260
eA
e
8.13
9.65
0.320
0.380
L
3.18
—
0.125
—
S
0.64
0.762
0.025
0.030
N0.
Leads
A
A1
B
B1
B2
C
D
8
—
0.56
1.52
1.17
0.33
2.54 BSC
eA
Notes:
1. Controlling dimension: inches, unless otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E1 do not include mold flash protrusions and should
be measured from the bottom of the package.
4. Formed leads shall be planar with respect to one another within 0.004
inches at the seating plane.
—
0.022
0.060
0.046
0.013
0.375
0.325
0.100 BSC
Integrated Silicon Solution, Inc.
Advanced Information Rev. 00E
11/25/08
B2
17