IS66WV51216ALL IS66WV51216BLL 8Mb LOW VOLTAGE, ULTRA LOW POWER PSEUDO CMOS STATIC RAM JANUARY 2010 FEATURES DESCRIPTION The ISSI IS66WV51216ALL/BLL is a high-speed, 8M • High-speed access time: 55ns • CMOS low power operation – mW (typical) operating – µW (typical) CMOS standby • Single power supply – 1.7V--1.95V Vdd (66WV51216ALL) (70ns) – 2.5V--3.6V Vdd (66WV51216BLL) (55ns) • Three state outputs • Data control for upper and lower bytes • Industrial temperature available • Lead-free available bit static RAMs organized as 512K words by 16 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CS1 is HIGH (deselected) or when CS2 is low (deselected) or when CS1 is low, CS2 is high and both LB and UB are HIGH, the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS66WV51216ALL/BLL is packaged in the JEDEC standard 48-pin mini BGA (6mm x 8mm) and 44-Pin TSOP (TYPE II). The device is aslo available for die sales. FUNCTIONAL BLOCK DIAGRAM A0-A18 DECODER 512K x 16 MEMORY ARRAY I/O DATA CIRCUIT COLUMN I/O VDD GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte CS2 CS1 OE WE UB LB CONTROL CIRCUIT Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 12/02/09 1 IS66WV51216ALL IS66WV51216BLL PIN CONFIGURATIONS: 512k x 16 48-Pin mini BGA (6mm x 8mm) 1 A LB 2 OE 3 4 5 44-Pin TSOP (Type II) 6 A0 A1 A2 CS2 CS1 I/O0 B I/O8 UB A3 A4 C I/O9 I/O10 A5 A6 I/O1 I/O2 D GND I/O11 A17 A7 I/O3 VDD` E VDD I/O12 NC A16 I/O4 GND F I/O14 I/O13 A14 A15 I/O5 I/O6 G I/O15 NC A12 A13 WE I/O7 H A18 A9 A10 A11 NC A8 A4 A3 A2 A1 A0 CS1 I/O0 I/O1 I/O2 I/O3 VDD GND I/O4 I/O5 I/O6 I/O7 WE A16 A15 A14 A13 A12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O15 I/O14 I/O13 I/O12 GND VDD I/O11 I/O10 I/O9 I/O8 A18 A8 A9 A10 A11 A17 PIN DESCRIPTIONS A0-A18 Address Inputs I/O0-I/O15 Data Inputs/Outputs CS1, CS2 Chip Enable Input OE Output Enable Input WE Write Enable Input LB Lower-byte Control (I/O0-I/O7) UB Upper-byte Control (I/O8-I/O15) NC No Connection Power Vdd GND Ground 2 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 12/02/09 IS66WV51216ALL IS66WV51216BLL TRUTH TABLE I/O PIN Mode WE CS1 CS2 OE LB UB I/O0-I/O7 I/O8-I/O15 Not Selected X H X X X X High-Z High-Z X X L X X X High-Z High-Z X X X X H H High-Z High-Z Output Disabled H L H H L X High-Z High-Z H L H H X L High-Z High-Z Read H L H L L H Dout High-Z H L H L H L High-Z Dout H L H L L LDoutDout Write L L H X L H Din High-Z L L H X H L High-Z Din L L H X L LDinDin Vdd Current Isb1, Isb2 Isb1, Isb2 Isb1, Isb2 Icc Icc Icc Icc OPERATING RANGE (Vdd) Range Ambient Temperature (70ns) (55ns) Commercial 0°C to +70°C 1.7V - 1.95V 2.5V - 3.6V Industrial –40°C to +85°C 1.7V - 1.95V 2.5V - 3.6V Automotive –40°C to +105°C Integrated Silicon Solution, Inc. — www.issi.com Rev. A 12/02/09 (70ns) 2.5V-3.6V 3 IS66WV51216ALL IS66WV51216BLL ABSOLUTE MAXIMUM RATINGS(1) Symbol Vterm Tbias Vdd Tstg Pt Parameter Terminal Voltage with Respect to GND Temperature Under Bias Vdd Related to GND Storage Temperature Power Dissipation Value –0.2 to Vdd+0.3 –40 to +85 –0.2 to +3.8 –65 to +150 1.0 Unit V °C V °C W Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter Test Conditions Voh Output HIGH Voltage Ioh = -0.1 mA Ioh = -1 mA Vol Output LOW Voltage Iol = 0.1 mA Iol = 2.1 mA Vih Input HIGH Voltage Vil(1) Input LOW Voltage Ili Ilo Input Leakage Output Leakage Vdd 1.7-1.95V 2.5-3.6V 1.7-1.95V 2.5-3.6V 1.7-1.95V 2.5-3.6V 1.7-1.95V 2.5-3.6V GND ≤ Vin ≤ Vdd GND ≤ Vout ≤ Vdd, Outputs Disabled Min. 1.4 2.2 — — 1.4 2.2 –0.2 –0.2 –1 –1 Max. — — 0.2 0.4 Vdd + 0.2 Vdd + 0.3 0.4 0.6 1 1 Unit V V V V V V V V µA µA Notes: 1. Vil (min.) = –1.0V for pulse width less than 10 ns. 4 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 12/02/09 IS66WV51216ALL IS66WV51216BLL CAPACITANCE(1) Symbol Cin Cout Parameter Input Capacitance Input/Output Capacitance Conditions Vin = 0V Vout = 0V Max. 8 10 Unit pF pF Note: 1. Tested initially and after any design or process changes that may affect these parameters. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load R1(Ω) R2(Ω) Vref Vtm 1.7V-1.95V (Unit) 0.4V to Vdd-0.2 5 ns Vref See Figures 1 and 2 1.7V - 1.95V 3070 3150 0.9V 1.8V 2.5V-3.6V (Unit) 0.4V to Vdd-0.3V 5ns Vref See Figures 1 and 2 2.5V - 3.6V 1029 1728 1.4V 2.8V AC TEST LOADS R1 R1 VTM VTM OUTPUT OUTPUT 30 pF Including jig and scope R2 Figure 1 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 12/02/09 5 pF Including jig and scope R2 Figure 2 5 IS66WV51216ALL IS66WV51216BLL 1.7V-1.95V POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Test Conditions Icc Vdd Dynamic Operating Vdd = Max., Com. Supply Current Iout = 0 mA, f = fmax Ind. All Inputs 0.4V Auto. or Vdd – 0.2V typ.(1) Icc1 Operating Supply Vdd = Max., CS1 = 0.2V Com. Current WE = Vdd – 0.2V Ind. CS2 = Vdd – 0.2V, f = 1mhz Auto. Isb1 TTL Standby Current Vdd = Max., Com. (TTL Inputs) Vin = Vih or Vil Ind. CS1 = Vih , CS2 = Vil, Auto. f = 1 MHz Unit 4 4 10 0.6 0.6 1 mA 100 120 150 µA mA mA OR ULB Control Isb2 CMOS Standby Current (CMOS Inputs) Max. 70ns 20 25 30 Vdd = Max., Vin = Vih or Vil CS1 = Vil, f = 0, UB = Vih, LB = Vih Vdd = Max., Com. CS1 ≥ Vdd – 0.2V, Ind. CS2 ≤ 0.2V, Auto. Vin ≥ Vdd – 0.2V, or typ.(1) Vin ≤ 0.2V, f = 0 OR ULB Control Vdd = Max., CS1 = Vil, CS2=Vih Vin ≥ Vdd – 0.2V, or Vin ≤ 0.2V, f = 0; UB / LB = Vdd – 0.2V Note:. 1. Typical values are measured at Vdd = 1.8V, Ta = 25oC and not 100% tested. 6 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 12/02/09 IS66WV51216ALL IS66WV51216BLL 2.5V-3.6V POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Test Conditions Icc Vdd Dynamic Operating Vdd = Max., Com. Supply Current Iout = 0 mA, f = fmax Ind. All Inputs 0.4V Auto. or Vdd – 0.3V typ.(2) Icc1 Operating Supply Vdd = Max., CS1 = 0.2V Com. Current WE = Vdd – 0.2V Ind. CS2 = Vdd – 0.2V, f = 1mhzAuto. Isb1 TTL Standby Current Vdd = Max., Com. (TTL Inputs) Vin = Vih or Vil Ind. CS1 = Vih , CS2 = Vil, Auto. f = 1 MHz Unit 100 130 150 75 µA mA mA mA OR ULB Control Isb2 CMOS Standby Current (CMOS Inputs) Max. 55ns 25 28 35 15 5 5 10 0.6 0.6 1 Vdd = Max., Vin = Vih or Vil CS1 = Vil, f = 0, UB = Vih, LB = Vih Vdd = Max., Com. CS1 ≥ Vdd – 0.2V, Ind. CS2 ≤ 0.2V, Auto. Vin ≥ Vdd – 0.2V, or typ.(2) Vin ≤ 0.2V, f = 0 OR ULB Control Vdd = Max., CS1 = Vil, CS2=Vih Vin ≥ Vdd – 0.2V, or Vin ≤ 0.2V, f = 0; UB / LB = Vdd – 0.2V Note: 1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at Vdd = 3.0V, Ta = 25oC and not 100% tested. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 12/02/09 7 IS66WV51216ALL IS66WV51216BLL READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Read Cycle Time Address Access Time Output Hold Time CS1/CS2 Access Time OE Access Time OE to High-Z Output OE to Low-Z Output CS1/CS2 to High-Z Output CS1/CS2 to Low-Z Output LB, UB Access Time trc taa toha tacs1/tacs2 tdoe thzoe(2) tlzoe(2) thzcs1/thzcs2(2) tlzcs1/tlzcs2(2) tba thzb LB, UB to High-Z Output tlzb LB, UB to Low-Z Output 55 ns Min. Max. 55 — — 55 10 — — 55 — 25 — 20 5 — 0 20 10 — — 55 0 0 20 — 70 ns Min. Max. 70 — — 70 10 — — 70 — 35 — 25 5 — 0 25 10 — — 70 0 0 25 — Unit ns ns ns ns ns ns ns ns ns ns ns ns Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4 to Vdd-0.2V/0.4V to Vdd-0.3V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±100 mV from steady-state voltage. Not 100% tested. AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CS1 = OE = Vil, CS2 = WE = Vih, UB or LB = Vil) tRC ADDRESS tAA tOHA DQ0-D15 8 PREVIOUS DATA VALID tOHA DATA VALID Integrated Silicon Solution, Inc. — www.issi.com Rev. A 12/02/09 IS66WV51216ALL IS66WV51216BLL AC WAVEFORMS READ CYCLE NO. 2(1,3) (CS1, CS2, OE, AND UB/LB Controlled) tRC ADDRESS tAA tOHA OE tDOE CS1 tHZOE tLZOE tACE1/tACE2 CS2 tLZCE1/ tLZCE2 tHZCS1/ tHZCS1 LB, UB tLZB DOUT tBA HIGH-Z tHZB DATA VALID Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CS1, UB, or LB = Vil. CS2=WE=Vih. 3. Address is valid prior to or coincident with CS1 LOW transition. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 12/02/09 9 IS66WV51216ALL IS66WV51216BLL WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range) Symbol twc 55 ns Min. Max. Parameter Write Cycle Time 55 — 70 ns Min. Max. 70 — Unit ns tscs1/tscs2 CS1/CS2 to Write End 45 — 60 — ns taw Address Setup Time to Write End 45 — 60 — ns tha Address Hold from Write End 0 — 0 — ns tsa Address Setup Time 0 — 0 — ns tpwb LB, UB Valid to End of Write 45 — 60 — ns tpwe WE Pulse Width 45 — 60 — ns tsd Data Setup to Write End 25 — 30 — ns Data Hold from Write End 0 — 0 — ns (4) thd (3) thzwe WE LOW to High-Z Output — 20 — 30 ns tlzwe(3) WE HIGH to Low-Z Output 5 — 5 — ns Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4 to Vdd-0.2V/0.4V to Vdd-0.3V and output loading specified in Figure 1. 2. The internal write time is defined by the overlap of CS1 LOW, CS2 HIGH and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 3. Tested with the load in Figure 2. Transition is measured ±100 mV from steady-state voltage. Not 100% tested. 4. tpwe > thzwe + tsd when OE is LOW. AC WAVEFORMS WRITE CYCLE NO. 1(1,2) (CS1 Controlled, OE = HIGH or LOW) tWC ADDRESS tHA tSCS1 CS1 tSCS2 CS2 tAW tPWE WE tPWB LB, UB tSA DOUT DATA UNDEFINED tHZWE tLZWE HIGH-Z tSD DIN tHD DATA-IN VALID Notes: 1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CS1 , CS2 and WE inputs and at least one of the LB and UB inputs being in the LOW state. 2. WRITE = (CS1) [ (LB) = (UB) ] (WE). 10 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 12/02/09 IS66WV51216ALL IS66WV51216BLL WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle) tWC ADDRESS OE tHA tSCS1 CS1 tSCS2 CS2 tAW t PWE WE LB, UB tSA DOUT tHZWE tLZWE HIGH-Z DATA UNDEFINED tSD DIN tHD DATA-IN VALID WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle) tWC ADDRESS OE tHA tSCS1 CS1 tSCS2 CS2 tAW t PWE WE LB, UB tSA DOUT DATA UNDEFINED tHZWE tLZWE HIGH-Z tSD DIN Integrated Silicon Solution, Inc. — www.issi.com Rev. A 12/02/09 tHD DATA-IN VALID 11 IS66WV51216ALL IS66WV51216BLL WRITE CYCLE NO. 4 (UB/LB Controlled) t WC ADDRESS t WC ADDRESS 1 ADDRESS 2 OE t SA CS1 LOW CS2 HIGH t HA t SA WE UB, LB t HA t PBW t PBW WORD 1 WORD 2 t HZWE DOUT t LZWE HIGH-Z DATA UNDEFINED t HD t SD DIN DATAIN VALID t HD t SD DATAIN VALID UB_CSWR4.eps 12 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 12/02/09 IS66WV51216ALL IS66WV51216BLL Please avoid address change for less than trc during the cycle time longer than 15 ms (Figure 1). Figure 2 & 3 provide work around solution for this issue. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 12/02/09 13 IS66WV51216ALL IS66WV51216BLL IS66WV51216ALL Industrial Range: -40°C to +85°C Voltage Range: 1.7V to 1.95V Speed (ns) 70 Order Part No. IS66WV51216ALL-70TLI IS66WV51216ALL-70BLI Package TSOP-II, Lead-free mini BGA (6mm x 8mm), Lead-free IS66WV51216BLL Industrial Range: -40°C to +85°C Voltage Range: 2.5V to 3.6V Speed (ns) 55 14 Order Part No. IS66WV51216BLL-55TLI IS66WV51216BLL-55BLI Package TSOP-II, Lead-free mini BGA (6mm x 8mm), Lead-free Integrated Silicon Solution, Inc. — www.issi.com Rev. A 12/02/09 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 12/02/09 Θ Package Outline 06/04/2008 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION. 2. DIMENSION D AND E1 DO NOT INCLUDE MOLD PROTRUSION. 1. CONTROLLING DIMENSION : MM NOTE : Θ IS66WV51216ALL IS66WV51216BLL 15 16 Package Outline 08/12/2008 1. CONTROLLING DIMENSION : MM . 2. Reference document : JEDEC MO-207 NOTE : IS66WV51216ALL IS66WV51216BLL Integrated Silicon Solution, Inc. — www.issi.com Rev. A 12/02/09