Infineon HYS64T128021GDL-37-A 200-pin small outline dual-in-line memory module Datasheet

D a t a S he et , Rev. 0.91, J u n e 2 00 4
HYS64T32000[G/H]DL–[3.7/5]–A
HYS64T64020[G/H]DL–[3.7/5]–A
HYS64T128021[G/H]DL–[3.7/5]–A
200-Pin Small Outline Dual-In-Line Memory Module
SO-DIMM
DDR2 SDRAM
M e m or y P r o du c t s
N e v e r
s t o p
t h i n k i n g .
Edition 2004-06
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2004.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
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and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
D a t a S he et , Rev. 0.91, J u n e 2 00 4
HYS64T32000[G/H]DL–[3.7/5]–A
HYS64T64020[G/H]DL–[3.7/5]–A
HYS64T128021[G/H]DL–[3.7/5]–A
200-Pin Small Outline Dual-In-Line Memory Module
SO-DIMM
DDR2 SDRAM
Memor y Product s
N e v e r
s t o p
t h i n k i n g .
all
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
Revision History:
Rev. 0.91
2004-06
Previous Revision:
Rev. 0.83
2003-09
Page
Subjects (major changes since last revision)
all
editorial changes
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removed HYS64T128022HDL products and all -3 products
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added HYS64T128021[G/]DL products
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HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
Table of Contents
1
1.1
1.2
1.3
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
6
6
8
2
Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4
4.1
4.2
IDD Specifications and Conditions
5
Electrical Characteristics & AC Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6
SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8
Product Type Nomenclature (DDR2 DRAMs and DIMMs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
22
ODT (On Die Termination) Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
IDD Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Sheet
5
Rev. 0.91, 2004-06
09122003-FTXN-KM26
200-Pin Small Outline Dual-In-Line Memory Module
DDR2 SDRAM
1
HYS64T32000[G/H]DL–[3.7/5]–A
HYS64T64020[G/H]DL–[3.7/5]–A
HYS64T128021[G/H]DL–[3.7/5]–A
Overview
This chapter gives an overview of the 1.8 V 200-Pin Small Outline Dual-In-Line Memory Module, 256 MByte and
512 MByte and describes its main characteristics.
1.1
•
•
•
•
Features
•
200-pin Non-ECC Unbuffered 8-Byte Dual-In-Line
DDR2 SDRAM Module for Notebooks and other
application where small form factors are required.
One rank 32M × 64, two ranks 64M × 64 and
128M × 64 module organisation and 32M × 16 and
64M × 8 chip organisation
JEDEC standard Double-Data-Rate-Two
Synchronous DRAMs (DDR2 SDRAM) with a single
+ 1.8 V (± 0.1 V) power supply
256 ,512 MByte and 1GByte modules built with
512Mb DDR2 SDRAMs in 60-ball FBGA
(P–TFBGA–60) and 84-ball FBGA (P–TFBGA–84)
chipsize packages
Table 1
•
•
•
•
•
•
Programmable CAS Latencies (3, 4 and 5), Burst
Length (4 & 8) and Burst Type
Auto Refresh (CBR) and Self Refresh
All inputs and outputs SSTL_1.8 compatible
Off-Chip Driver Impedance Adjustment(OCD) and
On-Die Termination(ODT)
Serial Presence Detect with E2PROM
Low Profile Modules form factor: 67.60 mm x 30.00
mm (MO-224)
Based on JEDEC standard reference layouts Raw
Card “A”, “C” and “D”
Performance
Product Type Speed Code
–3.7
–5
Units
Speed Grade
PC2–4200 4–4–4
PC2–3200 3–3–3
—
266
200
MHz
266
200
MHz
200
200
MHz
15
15
ns
15
15
ns
45
40
ns
60
55
ns
max. Clock Frequency
@CL5
@CL4
@CL3
min. RAS-CAS-Delay
min. Row Precharge Time
min. Row Active Time
min. Row Cycle Time
1.2
fCK5
fCK4
fCK3
tRCD
tRP
tRAS
tRC
Description
The memory array is designed with 512Mb DoubleData-Rate-Two (DDR2) Synchronous DRAMs.
Decoupling capacitors are mounted on the PCB board.
The DIMMs feature serial presence detect based on a
serial E2PROM device using the 2-pin I2C protocol. The
first 128 bytes are programmed with configuration data
and are write protected; the second 128 bytes are
available to the customer.
The INFINEON
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
module family are low profile SO-DIMM modules with
30,0 mm height based on DDR2 technology. DIMMs
are available as Non-ECC modules in 32M × 64
(256 MByte),64M × 64 (512 MByte) and 128M × 64
(1 GByte) organisation and density, intended for
mounting into 200-pin connector sockets.
Data Sheet
6
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
Overview
Table 2
Ordering Information
Product Type
Compliance Code
Description
SDRAM
Technology
HYS64T32000GDL–3.7–A
PC2–4200S–444–10–C0
one rank 256 MByte SO–DIMM
512 Mbit (×16)
HYS64T64020GDL–3.7–A
PC2–4200S–444–10–A0
two ranks 512 MByte SO–DIMM
512 Mbit (×16)
HYS64T128021GDL–3.7–A
PC2–4200S–444–10–D0
two ranks 1 GByte SO–DIMM
512 Mbit (× 8)
HYS64T32000GDL–5–A
PC2–3200S–333–10–C0
one rank 256 MByte SO–DIMM
512 Mbit (×16)
HYS64T64020GDL–5–A
PC2–3200S–333–10–A0
two ranks 512 MByte SO–DIMM
512 Mbit (×16)
HYS64T128021GDL–5–A
PC2–3200S–333–10–D0
two ranks 1 GByte SO–DIMM
512 Mbit (× 8)
HYS64T32000HDL–3.7–A
PC2–4200S–444–10–C0
one rank 256 MByte SO–DIMM
512 Mbit (×16)
HYS64T64020HDL–3.7–A
PC2–4200S–444–10–A0
two ranks 512 MByte SO–DIMM
512 Mbit (×16)
HYS64T128021HDL–3.7–A
PC2–4200S–444–10–D0
two ranks 1 GByte SO–DIMM
512 Mbit (× 8)
HYS64T32000HDL–5–A
PC2–3200S–333–10–C0
one rank 256 MByte SO–DIMM
512 Mbit (×16)
HYS64T64020HDL–5–A
PC2–3200S–333–10–A0
two ranks 512 MByte SO–DIMM
512 Mbit (×16)
HYS64T128021HDL–5–A
PC2–3200S–333–10–D0
two ranks 1 GByte SO–DIMM
512 Mbit (× 8)
Note: The Compliance Code is printed on the module label and describes the speed grade,e.g. "512MB 2R×16
PC2–3200S–33310–A" where "512MB" tells the density in megabytes, "2Rx16" means 2 ranks on module
built of ×16 components, "PC2–3200S" means DDR2 SO-DIMM with 4.26 GB/s module bandwidth and "44411" means CAS latency of 4, RCD1) latency of 4, and RP2) latency of 4 using Jedec SPD revision 1.0. All
part numbers end with a place code, designating the silicon die revision. Example: HYS64T32000GDL–3.7–
A, indicating Rev. A dice are used for DDR2 SDRAM components. For all INFINEON DDR2 module and
component nomenclature see Chapter 8 of this datasheet.
Table 3
DIMM
Density
Address Format
Module
Organization
Memory
Ranks
# of
SDRAMs
# of row/bank/column bits
Raw
Card
256 MB
32M ×64
1
4
13/2/10
C
512 MB
64M ×64
2
8
13/2/10
A
1 GB
128M ×64
2
16
14/2/10
D
1) RCD: Row Column Delay
2) RP: Row Precharge
Data Sheet
7
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
Overview
Table 4
Components on Modules1)
Product Type
HYS64T32000GDL
DRAM Components
DRAM Density
DRAM Organisation
HYB18T512160AC
512 Mbit
32M ×16
HYB18T512160AF2)
512 Mbit
32M ×16
HYB18T512800AC
512 Mbit
64M ×8
512 Mbit
64M ×8
HYS64T64020GDL
HYS64T32000HDL2)
2)
HYS64T64020HDL
HYS64T128021GDL
2)
HYS64T128021HDL
HYB18T512800AF
2)
1) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet.
2) Green Product
1.3
Pin Configuration
The pin configuration of the Small Outline DDR2 SDRAM DIMM is listed by function in Table 5 (200 pins). The
abbreviations used in columns Pin and Buffer Type are explained in Table 6 and Table 7 respectively. The pin
numbering is depicted in Figure 1
Table 5
Pin Configuration of SO-DIMM
Pin#
Name
Pin
Type
Buffer
Type
Function
Clock Signals 2:0
Clock Signals
30
CK0
I
SSTL
164
CK1
I
SSTL
32
CK0
I
SSTL
166
CK1
I
SSTL
79
CKE0
I
SSTL
Clock Enable Rank 0
80
CKE1
I
SSTL
Clock Enable Rank 1
Complement Clock Signals 2:0
Note: 2-rank module
NC
NC
—
Note: 1-rank module
110
S0
I
SSTL
Chip Select Rank 0
115
S1
I
SSTL
Chip Select Rank 1
Control Signals
Note: 2-rank module
NC
NC
—
Note: 1-rank module
108
RAS
I
SSTL
Row Address Strobe
113
CAS
I
SSTL
Column Address Strobe
109
WE
I
SSTL
Write Enable
107
BA0
I
SSTL
Bank Address Bus 1:0
106
BA1
I
SSTL
102
A0
I
SSTL
101
A1
I
SSTL
100
A2
I
SSTL
99
A3
I
SSTL
98
A4
I
SSTL
Address Signals
Data Sheet
Address Bus 4:0
8
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
Overview
Table 5
Pin Configuration of SO-DIMM (cont’d)
Pin#
Name
Pin
Type
Buffer
Type
Function
97
A5
I
SSTL
Address Bus 11:5
94
A6
I
SSTL
92
A7
I
SSTL
93
A8
I
SSTL
91
A9
I
SSTL
105
A10
I
SSTL
AP
I
SSTL
90
A11
I
SSTL
89
A12
I
SSTL
Address Signal 12
116
A13
I
SSTL
Address Signal 13
Note: 512M ×4/×8
NC
NC
—
Note: Module based on 512 Mbit ×16
5
DQ0
I/O
SSTL
Data Bus 26:0
7
DQ1
I/O
SSTL
17
DQ2
I/O
SSTL
19
DQ3
I/O
SSTL
4
DQ4
I/O
SSTL
6
DQ5
I/O
SSTL
14
DQ6
I/O
SSTL
16
DQ7
I/O
SSTL
23
DQ8
I/O
SSTL
25
DQ9
I/O
SSTL
35
DQ10
I/O
SSTL
37
DQ11
I/O
SSTL
20
DQ12
I/O
SSTL
22
DQ13
I/O
SSTL
36
DQ14
I/O
SSTL
38
DQ15
I/O
SSTL
43
DQ16
I/O
SSTL
45
DQ17
I/O
SSTL
55
DQ18
I/O
SSTL
57
DQ19
I/O
SSTL
44
DQ20
I/O
SSTL
46
DQ21
I/O
SSTL
56
DQ22
I/O
SSTL
58
DQ23
I/O
SSTL
61
DQ24
I/O
SSTL
63
DQ25
I/O
SSTL
73
DQ26
I/O
SSTL
Data Signals
Data Sheet
9
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
Overview
Table 5
Pin Configuration of SO-DIMM (cont’d)
Pin#
Name
Pin
Type
Buffer
Type
Function
75
DQ27
I/O
SSTL
Data Bus 63:27
62
DQ28
I/O
SSTL
64
DQ29
I/O
SSTL
74
DQ30
I/O
SSTL
76
DQ31
I/O
SSTL
123
DQ32
I/O
SSTL
125
DQ33
I/O
SSTL
135
DQ34
I/O
SSTL
137
DQ35
I/O
SSTL
124
DQ36
I/O
SSTL
126
DQ37
I/O
SSTL
134
DQ38
I/O
SSTL
136
DQ39
I/O
SSTL
141
DQ40
I/O
SSTL
143
DQ41
I/O
SSTL
151
DQ42
I/O
SSTL
153
DQ43
I/O
SSTL
140
DQ44
I/O
SSTL
142
DQ45
I/O
SSTL
152
DQ46
I/O
SSTL
154
DQ47
I/O
SSTL
157
DQ48
I/O
SSTL
159
DQ49
I/O
SSTL
173
DQ50
I/O
SSTL
175
DQ51
I/O
SSTL
158
DQ52
I/O
SSTL
160
DQ53
I/O
SSTL
174
DQ54
I/O
SSTL
176
DQ55
I/O
SSTL
179
DQ56
I/O
SSTL
181
DQ57
I/O
SSTL
189
DQ58
I/O
SSTL
191
DQ59
I/O
SSTL
180
DQ60
I/O
SSTL
182
DQ61
I/O
SSTL
192
DQ62
I/O
SSTL
194
DQ63
I/O
SSTL
Data Strobe Signals
Data Sheet
10
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
Overview
Table 5
Pin Configuration of SO-DIMM (cont’d)
Pin#
Name
Pin
Type
Buffer
Type
Function
13
DQS0
I/O
SSTL
Data Strobe Bus 7:0
31
DQS1
I/O
SSTL
51
DQS2
I/O
SSTL
Note: See block diagram for corresponding DQ
signals
70
DQS3
I/O
SSTL
131
DQS4
I/O
SSTL
148
DQS5
I/O
SSTL
169
DQS6
I/O
SSTL
188
DQS7
I/O
SSTL
11
DQS0
I/O
SSTL
Complement Data Strobe Bus 7:0
29
DQS1
I/O
SSTL
49
DQS2
I/O
SSTL
Note: See block diagram for corresponding DQ
signals
68
DQS3
I/O
SSTL
129
DQS4
I/O
SSTL
146
DQS5
I/O
SSTL
167
DQS6
I/O
SSTL
186
DQS7
I/O
SSTL
10
DM0
I
SSTL
26
DM1
I
SSTL
52
DM2
I
SSTL
Data Mask Signals
Data Mask Bus 7:0
67
DM3
I
SSTL
130
DM4
I
SSTL
147
DM5
I
SSTL
170
DM6
I
SSTL
185
DM7
I
SSTL
197
SCL
I
CMOS
Serial Bus Clock
195
SDA
I/O
OD
Serial Bus Data
198
SA0
I
CMOS
Slave Address Select Bus 2:0
200
SA1
I
CMOS
EEPROM
Power Supplies
1
199
81,82,87,88,95,96,103,104,
111,112,117,118
VREF
AI
—
VDDSPD PWR —
VDD
PWR —
2,3,8,9,12,15,18,21,24,27,28, VSS
33,34,39,40,41,42,47,48,53,
54,59,60,65,66,71,72,77,78,
121,122,127,128,132,133,138,
139,144,145,149,150,155,156,
161,162,165,168,171,172,177,
178,183,184,187,190,193,196
Data Sheet
GND
I/O Reference Voltage
EEPROM Power Supply
Power Supply
—
Ground Plane
11
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
Overview
Table 5
Pin Configuration of SO-DIMM (cont’d)
Pin#
Name
Pin
Type
Buffer
Type
Function
Other Pins
114
ODT0
On-Die Termination Control 0
119
ODT1
On-Die Termination Control 1
NC
Note: 1 Rank modules
50,69,83,84,85,120,163
NC
NC
—
Not connected
Note: Pins not connected on Infineon SO-DIMMs
Table 6
Abbreviations for Pin Type
Abbreviation
Description
I
Standard input-only pin. Digital levels.
O
Output. Digital levels.
I/O
I/O is a bidirectional input/output signal.
AI
Input. Analog levels.
PWR
Power
GND
Ground
NC
Not Connected
Table 7
Abbreviation
Abbreviations for Buffer Type
Description
SSTL
Serial Stub Terminated Logic (SSTL_18)
LV-CMOS
Low Voltage CMOS
CMOS
OD
Data Sheet
CMOS Levels
Open Drain. The corresponding pin has 2 operational states, active low and tristate, and
allows multiple devices to share as a wire-OR.
12
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
Overview
Pin 001
Pin 005
Pin 009
Pin 013
Pin 017
Pin 021
Pin 025
Pin 029
Pin 033
Pin 037
V SS
DQ17
DQS2
V SS
DQ19
DQ24
V SS
NC
DQ26
V SS
V DD
NC
A12
A8
A5
A1
A10/AP
WE
CAS
V DD
V SS
DQ33
DQS4
V SS
DQ35
DQ40
V SS
V SS
DQ43
DQ48
V SS
V SS
DQS6
DQ50
V SS
DQ57
DM7
DQ58
V SS
SCL
-
Pin 041
Pin 045
Pin 049
Pin 053
Pin 057
Pin 061
Pin 065
Pin 069
Pin 073
Pin 077
Pin 081
Pin 085
Pin 089
Pin 093
Pin 097
Pin 101
Pin 105
Pin 109
Pin 113
Pin 117
Pin 121
Pin 125
Pin 129
Pin 133
Pin 137
Pin 141
Pin 145
Pin 149
Pin 153
Pin 157
Pin 161
Pin 165
Pin 169
Pin 173
Pin 177
Pin 181
Pin 185
Pin 189
Pin 193
Pin 197
V SS
DQ1
DQS0
V SS
DQ3
DQ8
V SS
DQS1
DQ10
V SS
-
Pin 003
Pin 007
Pin 011
Pin 015
Pin 019
Pin 023
Pin 027
Pin 031
Pin 035
Pin 039
Pin 004
Pin 008
Pin 012
Pin 016
Pin 020
Pin 024
Pin 028
Pin 032
Pin 036
Pin 040
-
DQ4
V SS
V SS
DQ7
DQ12
V SS
V SS
CK0
DQ14
V SS
DQ16
V SS
DQS2
DQ18
V SS
DQ25
DM3
V SS
DQ27
CKE0
NC
V DD
A9
V DD
A3
V DD
BA0
V DD
NC/CS1
ODT1
DQ32
V SS
DQS4
DQ34
V SS
DQ41
DM5
DQ42
V SS
DQ49
NC
DQS6
V SS
DQ51
DQ56
V SS
V SS
DQ59
SDA
V DD SPD
-
Pin 043
Pin 047
Pin 051
Pin 055
Pin 059
Pin 063
Pin 067
Pin 071
Pin 075
Pin 079
Pin 083
Pin 087
Pin 091
Pin 095
Pin 099
Pin 103
Pin 107
Pin 111
Pin 115
Pin 119
Pin 123
Pin 127
Pin 131
Pin 135
Pin 139
Pin 143
Pin 147
Pin 151
Pin 155
Pin 159
Pin 163
Pin 167
Pin 171
Pin 175
Pin 179
Pin 183
Pin 187
Pin 191
Pin 195
Pin 199
Pin 044
Pin 048
Pin 052
Pin 056
Pin 060
Pin 064
Pin 068
Pin 072
Pin 076
Pin 080
Pin 084
Pin 088
Pin 092
Pin 096
Pin 100
Pin 104
Pin 108
Pin 112
Pin 116
Pin 120
Pin 124
Pin 128
Pin 132
Pin 136
Pin 140
Pin 144
Pin 148
Pin 152
Pin 156
Pin 160
Pin 164
Pin 168
Pin 172
Pin 176
Pin 180
Pin 184
Pin 188
Pin 192
Pin 196
Pin 200
-
DQ20
V SS
DM2
DQ22
V SS
DQ29
DQS3
V SS
DQ31
NC/CKE1
NC
V DD
A7
V DD
A2
V DD
RAS
V DD
A13
NC
DQ36
V SS
V SS
DQ39
DQ44
V SS
DQS5
DQ46
V SS
DQ53
CK1
V SS
V SS
DQ55
DQ60
V SS
DQS7
DQ62
V SS
SA1
BACKSIDE
-
FRONTSIDE
V REF
DQ0
V SS
DQS0
DQ2
V SS
DQ9
DQS1
V SS
DQ11
Pin 002
Pin 006
Pin 010
Pin 014
Pin 018
Pin 022
Pin 026
Pin 030
Pin 034
Pin 038
-
V SS
DQ5
DM0
DQ6
V SS
DQ13
DM1
CK0
V SS
DQ15
Pin 042
Pin 046
Pin 050
Pin 054
Pin 058
Pin 062
Pin 066
Pin 070
Pin 074
Pin 078
Pin 082
Pin 086
Pin 090
Pin 094
Pin 098
Pin 102
Pin 106
Pin 110
Pin 114
Pin 118
Pin 122
Pin 126
Pin 130
Pin 134
Pin 138
Pin 142
Pin 146
Pin 150
Pin 154
Pin 158
Pin 162
Pin 166
Pin 170
Pin 174
Pin 178
Pin 182
Pin 186
Pin 190
Pin 194
Pin 198
-
V SS
DQ21
NC
V SS
DQ23
DQ28
V SS
DQS3
DQ30
V SS
V DD
A14
A11
A6
A4
A0
BA1
CS0
ODT0
V DD
V SS
DQ37
DM4
DQ38
V SS
DQ45
DQS5
V SS
DQ47
DQ52
V SS
CK1
DM6
DQ54
V SS
DQ61
DQS7
V SS
DQ63
SA0
MPPT0140
Figure 1
Data Sheet
Pin Configuration SO-DIMM (200 Pin)
13
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
Overview
Table 8
Input/Output Functional Description
Symbol
Type
Polarity Function
CK[1:0],
CK[1:0]
I
Cross
point
The system clock inputs. All address and command lines are sampled on the
cross point of the rising edge of CK and the falling edge of CK. A Delay Locked
Loop (DLL) circuit is driven from the clock inputs and output timing for read
operations is synchronized to the input clock.
CKE[1:0]
I
Active
High
Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal
when low. By deactivating the clocks, CKE low initiates the Power Down Mode
or the Self Refresh Mode.
S[1:0]
I
Active
Low
Enables the associated DDR2 SDRAM command decoder when low and
disables the command decoder when high. When the command decoder is
disabled, new commands are ignored but previous operations continue. Rank 0
is selected by S0; Rank 1 is selected by S1.
RAS, CAS, I
WE
Active
Low
When sampled at the cross point of the rising edge of CK,and falling edge of CK,
RAS, CAS and WE define the operation to be executed by the SDRAM.
BA[1:0]
I
—
Selects internal SDRAM memory bank
ODT[1:0]
I
Active
High
Asserts on-die termination for DQ, DM, DQS, and DQS signals if enabled via the
DDR2 SDRAM mode register.
A[9:0],
A10/AP,
A[13:11]
I
—
During a Bank Activate command cycle, defines the row address when sampled
at the crosspoint of the rising edge of CK and falling edge of CK. During a Read
or Write command cycle, defines the column address when sampled at the cross
point of the rising edge of CK and falling edge of CK. In addition to the column
address, AP is used to invoke autoprecharge operation at the end of the burst
read or write cycle. If AP is high, autoprecharge is selected and BA0-BAn
defines the bank to be precharged. If AP is low, autoprecharge is disabled.
During a Precharge command cycle, AP is used in conjunction with BA[1:0] to
control which bank(s) to precharge. If AP is high, all banks will be precharged
regardless of the state of BA[1:0] inputs. If AP is low, then BA[1:0] are used to
define which bank to precharge.
DQ[63:0]
I/O
—
Data Input/Output pins
DM[7:0]
I
Active
High
The data write masks, associated with one data byte. In Write mode, DM
operates as a byte mask by allowing input data to be written if it is low but blocks
the write operation if it is high. In Read mode, DM lines have no effect.
DQS[7:0],
DQS[7:0]
I/O
Cross
point
The data strobes, associated with one data byte, sourced with data transfers. In
Write mode, the data strobe is sourced by the controller and is centered in the
data window. In Read mode the data strobe is sourced by the DDR2 SDRAM
and is sent at the leading edge of the data window. DQS signals are
complements, and timing is relative to the crosspoint of respective DQS and
DQS. If the module is to be operated in single ended strobe mode, all DQS
signals must be tied on the system board to VSS through a 20 ohm to 10 Kohm
resistor and DDR2 SDRAM mode registers programmed appropriately.
VDD,
Supply —
VDDSPD, VSS
Power supplies for core, I/O, Serial Presence Detect, and ground for the module.
SDA
I/O
—
This is a bidirectional pin used to transfer data into or out of the SPD EEPROM.
A resistor must be connected from SDA to VDDSPD on the motherboard to act as
a pull-up.
SCL
I
—
This signal is used to clock data into and out of the SPD EEPROM.
SA[1:0]
I
—
Address pins used to select the Serial Presence Detect base address.
Data Sheet
14
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
Block Diagrams
2
Block Diagrams
CS0
3.0Ω+/- 5%
DQS0
DQS0
DM0
DQS1
DQS1
DM1
DQS2
DQS2
DM2
DQS3
DQS3
DM3
LDQS
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/0 14
I/O 15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
LDQS
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/ O 12
I/O 13
I/0 14
I/O 15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
VDDSPD
EEPROM
VDD
VREF
D0 - D3
(VDD&VDDQ)
D0 - D3
V SS
D0 - D3
CS
DQS4
DQS4
DM4
DQS5
DQS5
DM5
ODT0
Figure 2
CKE
ODT
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS6
DQS6
DM6
LDQS
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/0 14
I/O 15
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D1
DQS7
DQS7
DM7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
CS
D2
CS
D3
Clock Wiring
Serial PD
Clock Input
SDA
SCL
WP A0
A1 A2
CK0, CK0
CK1, CK1
SDRAMs
2 SDRAMs
2 SDRAMs
SA0 SA1
3.0Ω+/- 5%
BA0, BA1
BA0, BA1 : SDRAMs D0 - D3
A0 - A12
A0 - A12 : SDRAMs D0 - D3
RAS
RAS
: SDRAMs D0 - D3
CAS
CAS
: SDRAMs D0 - D3
WE
WE
: SDRAMs D0 - D3
CKE0
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
D0
CS
LDQS
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/ O 12
I/O 13
I/0 14
I/O 15
DQ-to-I/O wiring may be changed within a byte
DQ/DQS/DQS/DM/CKE/CS relationships must be maintained as shown
DQ/DQS/DQS/DM resistors are 22Ω +/- 5%
Address and control resistors are 3.0Ω +/- 5%
: SDRAMs D0 - D3
: SDRAMs D0 - D3
Block Diagram Raw Card C (32M x 64, 1 rank, x16)
Note
1. DQ, DQS, DQS, DM resistors are 22 Ω ±5 %
Data Sheet
2. S0, S1, BAn, An, RAS, CAS, WE, ODT0, ODT1,
CKEO, CKE1 resistors are 3 Ω ±5 %
15
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
Block Diagrams
CS1
3.0Ω+/- 5%
CS0
DQS0
DQS0
DM0
DQS1
DQS1
DM1
DQS2
DQS2
DM2
DQS3
DQS3
DM3
LDQS
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/0 14
I/O 15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
LDQS
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/ O 12
I/O 13
I/0 14
I/O 15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
LDQS
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/0 14
I/O 15
D0
CS
LDQS
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/0 14
I/O 15
D1
VDDSPD
EEPROM
VDD
D0 - D7
(VDD & VDDQ)
VREF
D0 - D7
V SS
D0 - D7
BA0, BA1
A0 - A12
RAS
CAS
Figure 3
CS
CS
DQS4
DQS4
DM4
D4
DQS5
DQS5
DM5
CS
DQS6
DQS6
DM6
D5
DQS7
DQS7
DM7
WE
: SDRAMs D0 - D3
CKE0
CKE1
CKE
CKE
: SDRAMs D0 - D3
: SDRAMs D4 - D7
ODT0
ODT1
ODT
ODT
: SDRAMs D0 - D3
: SDRAMs D4 - D7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
LDQS
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/ O 12
I/O 13
I/0 14
I/O 15
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
SDA
SCL
WP A0
CS
LDQS
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/0 14
I/O 15
D2
CS
LDQS
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/0 14
I/O 15
D3
CS
D6
CS
D7
Clock Wiring
Serial PD
A1 A2
Clock Input
CK0, CK0
CK1, CK1
SDRAMs
4 SDRAMs
4 SDRAMs
SA0 SA1
BA0, BA1 : SDRAMs D0 - D3
A0 - A12 : SDRAMs D0 - D3
RAS
: SDRAMs D0 - D3
CAS
: SDRAMs D0 - D3
WE
LDQS
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/0 14
I/O 15
DQ-to-I/O wiring may be changed within a byte
DQ/DQS/DQS/DM/CKE/CS relationships must be maintained as shown
DQ/DQS/DQS/DM resistors are 22Ω +/- 5%
Address and control resistors are 3.0Ω +/- 5%
Block Diagram Raw Card A (64M x 64, 2 ranks, x16)
Note
1. DQ, DQS, DQS, DM resistors are 22 Ω ±5 %
Data Sheet
2. S0, S1, BAn, An, RAS, CAS, WE, ODT0, ODT1,
CKEO, CKE1 resistors are 3 Ω ±5 %
16
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
Block Diagrams
10 Ω +/- 5%
CKE1
ODT1
CS1
CKE0
ODT0
CS0
DQS0
DQS0
DM0
DQS1
DQS1
DM1
CS0 ODT0 CKE0 CS1 ODT1 CKE1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS0 ODT0 CKE0 CS1 ODT1 CKE1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS0 ODT0 CKE0 CS1 ODT1 CKE1
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
CS0 ODT0 CKE0 CS1 ODT1 CKE1
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS2
DQS2
DM2
DQS3
DQS3
DM3
DQS4
DQS4
DM4
D0, D8 (dual die)
DQS5
DQS5
DM5
D1, D0 (dual die)
D1, D9 (dual die)
DQS6
DQS6
DM6
D2, D10 (dual die)
D2, D10 (dual die)
DQS7
DQS7
DM7
D3, D11 (dual die)
SDA
WP A0
A1
CS0 ODT0 CKE0 CS1 ODT1 CKE1
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS0 ODT0 CKE0 CS1 ODT1 CKE1
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
CS0 ODT0 CKE0 CS1 ODT1 CKE1
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQS
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D4, D12 (dual die)
D5, D13 (dual die)
D6, D14 (dual die)
D7, D15 (dual die)
VDDSPD
Serial PD
SCL
CS0 ODT0 CKE0 CS1 ODT1 CKE1
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
A2
SA0 SA1
EEPROM
VDD
D0 - D15, VDD, VDDQ
VREF
D0 - D15
V SS
D0 - D15
Clock Wiring
10 Ω +/- 5%
BA0, BA1
A0 - A13
RAS
CAS
BA0, BA1 : SDRAMs D0 - D15
A0 - A13 : SDRAMs D0 - D15
RAS
: SDRAMs D0 - D15
CAS
: SDRAMs D0 - D15
WE
WE
Clock Input
CK0, CK0
CK1, CK1
SDRAMs
8 loads
8 loads
: SDRAMs D0 - D15
Unless otherwise noted, resistor values are 22 Ω +/- 5%.
DQ wiring may differ from that described in this drawing, however
DQ, DM, DQS, DQS relationship are maintained as shown
Figure 4
Block Diagram Raw Card D (128M x 64, 2 ranks, x8)
Note
1. DQ, DQS, DQS, DM resistors are 22 Ω ±5 %
Data Sheet
2. S0, S1, BAn, An, RAS, CAS, WE, ODT0, ODT1,
CKEO, CKE1 resistors are 3 Ω ±5 %
17
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
Electrical Characteristics
3
Table 9
Electrical Characteristics
Absolute Maximum Ratings
Parameter
Symbol
Voltage on any pins relative to VSS
VIN, VOUT
VDD
VDDQ
Voltage on VDD relative to VSS
Voltage on VDD Q relative to VSS
Barometric Pressure (operating & storage)
HSTG
Storage Humidity (without condensation)
Limit Values
Unit
Note/Test
Condition
Min.
Max.
– 0.5
2.3
V
1)
– 1.0
2.3
V
1)
– 0.5
2.3
+69
+105
kPa
1)
5
95
%
1)
1)
1) Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
Table 10
Operating Temperature Range
Parameter
Symbol
TOPR
TCASE
TSTG
DIMM Module Operating Temperature Range (ambient)
DRAM Component Case Temperature Range
Storage temperature
Barometric Pressure (operating & storage)
HOPR
Operating Humidity (relative)
Limit Values
Unit
min.
max.
0
+65
°C
0
+95
°C
– 55
+100
°C
+69
+105
kPa
10
90
%
Notes
1)2)3)4)
5)
1) DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the DRAMs. For
measurement conditions, please refer to the JEDEC document JESD51-2
2) Within the DRAM Component Case Temperature Range all DRAM specifications will be supported
3) Above 85 °C DRAM case temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 µs.
4) Self-Refresh period is hard-coded in the DRAMs and therefore it is imperative that the system ensures the DRAM is below
85 °C case temperature before initiating self-refresh operation.
5) Up to 3000 m.
Table 11
Supply Voltage Levels and DC Operating Conditions
Parameter
Device Supply Voltage
Output Supply Voltage
Input Reference Voltage
SPD Supply Voltage
DC Input Logic High
DC Input Logic Low
In / Output Leakage Current
Symbol
VDD
VDDQ
VREF
VDDSPD
VIH (DC)
VIL (DC)
IL
Limit Values
Unit
Notes
Min.
Nom.
Max.
1.7
1.8
1.9
V
1.7
1.8
1.9
V
1)
0.49 × VDDQ
0.5 × VDDQ
0.51 × VDDQ
V
2)
1.7
—
3.6
V
VREF + 0.125
—
V
– 0.30
—
VDDQ +0.3
VREF –0.125
V
–5
—
5
µA
3)
1) Under all conditions, VDDQ must be less than or equal to VDD
2) Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC). VREF is also expected to track noise variations in VDDQ.
3) For any pin on the DIMM connector under test input of 0 V ≤ VIN ≤ VDDQ + 0.3 V.
Data Sheet
18
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
IDD Specifications and Conditions
4
IDD Specifications and Conditions
Table 12
IDD Measurement Conditions1)2)
Parameter
Symbol
Operating Current 0
IDD0
One bank Active - Precharge; tCK = tCKmin., tRC = tRCmin., tRAS = tRASmin., CKE is HIGH, CS is high between
valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING.
Operating Current 1
One bank Active - Read - Precharge; IOUT = 0 mA, BL = 4, tCK = tCKmin., tRC = tRCmin., tRAS = tRASmin.,
tRCD = tRCDmin.,AL = 0, CL = CLmin.; CKE is HIGH, CS is high between valid commands. Address and
control inputs are SWITCHING, Databus inputs are SWITCHING.
IDD1
Precharge Power-Down Current
Other control and address inputs are STABLE, Data bus inputs are FLOATING.
IDD2P
Precharge Standby Current
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCKmin.; Other control and address inputs are
SWITCHING, Data bus inputs are SWITCHING.
IDD2N
Precharge Quiet Standby Current
IDD2Q
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCKmin.; Other control and address inputs are STABLE,
Data bus inputs are FLOATING.
Active Power-Down Current
All banks open; tCK = tCKmin., CKE is LOW; Other control and address inputs are STABLE, Data bus
inputs are FLOATING. MRS A12 bit is set to “0” (Fast Power-down Exit);
IDD3P(0)
Active Power-Down Current
All banks open; tCK = tCKmin., CKE is LOW; Other control and address inputs are STABLE, Data bus
inputs are FLOATING. MRS A12 bit is set to “1” (Slow Power-down Exit);
IDD3P(1)
Active Standby Current
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLmin.; tCK = tCKmin.;
tRAS = tRASmax., tRP = tRPmin.; CKE is HIGH, CS is high between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA.
IDD3N
Operating Current
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLmin.; tCK = tCKmin.;
tRAS = tRASmax., tRP = tRPmin.; CKE is HIGH, CS is high between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA.
IDD4R
Operating Current
Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLmin.; tCK = tCKmin.;
tRAS = tRASmax., tRP = tRPmin.; CKE is HIGH, CS is high between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING;
IDD4W
Burst Refresh Current
tCK = tCKmin., Refresh command every tRFC = tRFCmin. interval, CKE is HIGH, CS is HIGH between valid
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
IDD5B
Distributed Refresh Current
IDD5D
tCK = tCKmin., Refresh command every tRFC = tREFI interval, CKE is LOW and CS is HIGH between valid
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Data Sheet
19
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
IDD Specifications and Conditions
Table 12
IDD Measurement Conditions1)2) (cont’d)
Parameter
Symbol
IDD6
Self-Refresh Current
CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING,
Data bus inputs are FLOATING. RESET = Low. IDD6 current values are guaranteed up to TCASE of 85 °C
max.
All Bank Interleave Read Current
IDD7
All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4. Control
and address bus inputs are STABLE during DESELECTS. Iout = 0 mA.
1)
VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V
2) For details and notes see the relevant INFINEON component data sheet
IDD Specification HYS64T[32000/64020][G/H]DL
×64
×64
×64
×64
×64
×64
1 Rank
1 Rank
Symbol
Max.
IDD0
IDD1
IDD2P
IDD2N
IDD2Q
IDD3P( MRS = 0)
IDD3P( MRS = 1)
IDD3N
IDD4R
IDD4W
IDD5B
IDD5D
IDD6
IDD7
HYS64T64020HDL-3.7-A
512 MB
HYS64T32000HDL-3.7-A
HYS64T32000GDL-3.7-A
256 MB 256 MB 512 MB
HYS64T64020GDL-5-A
512 MB
Organization
HYS64T32000HDL-5-A
256 MB 256 MB 512 MB
HYS64T32000GDL-5-A
HYS64T64020HDL-5-A
Product Type
HYS64T64020GDL-3.7-A
Table 13
Unit Notes
×64
×64
2 Ranks 2 Ranks 1 Rank
1 Rank
2 Ranks 2 Ranks
Max.
Max.
Max.
Max.
Max.
Max.
Max.
280
280
300
300
320
320
340
340
mA
1)2)
300
300
320
320
360
360
380
380
mA
1)2)
20
20
30
30
20
20
30
30
mA
1)3)
130
130
260
260
160
160
320
320
mA
1)3)
100
100
200
200
120
120
240
240
mA
1)3)
50
50
100
100
60
60
130
130
mA
1)3)
20
20
40
40
20
20
40
40
mA
1)3)
140
140
280
280
160
160
320
320
mA
1)3)
340
340
360
360
400
400
420
420
mA
1)2)
360
360
380
380
440
440
460
460
mA
1)2)
480
480
500
500
520
520
540
540
mA
1)2)
20
20
50
50
20
20
50
50
mA
1)3)
20
20
30
30
20
20
30
30
mA
1)4)
840
840
860
860
880
880
900
900
mA
1)2)
1) Calculated values from component data. ODT disabled. IDD1, IDD4R and IDD7 are defined with the outputs disabled
2) The other rank is in IDD2P Precharge Power-Down Standby Current mode
3) Both ranks are in the same IDD current mode
4) standard
Data Sheet
20
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
IDD Specifications and Conditions
Organization
HYS64T128021HDL-3.7-A
HYS64T128021GDL-3.7-A
Product Type
HYS64T128021HDL-5-A
IDD Specification HYS64T128021[G/H]DL
HYS64T128021GDL-5-A
Table 14
Unit
Notes
1 GB
1 GB
1 GB
1 GB
×64
×64
×64
×64
2 Ranks
2 Ranks
2 Ranks
2 Ranks
Symbol
Max.
Max.
Max.
Max.
IDD0
IDD1
IDD2P
IDD2N
IDD2Q
IDD3P( MRS = 0)
IDD3P( MRS = 1)
IDD3N
IDD4R
IDD4W
IDD5B
IDD5D
IDD6
IDD7
472
472
552
552
mA
1)2)
512
512
632
632
mA
1)2)
64
64
64
64
mA
1)3)
512
512
640
640
mA
1)3)
400
400
480
480
mA
1)3)
208
208
256
256
mA
1)3)
80
80
80
80
mA
1)3)
560
560
640
640
mA
1)3)
592
592
752
752
mA
1)2)
632
632
792
792
mA
1)2)
976
976
1060
1060
mA
1)2)
96
96
96
96
mA
1)3)
64
64
64
64
mA
1)4)
1072
1072
1312
1312
mA
1)2)
1) Calculated values from component data. ODT disabled. IDD1, IDD4R and IDD7 are defined with the outputs disabled
2) The other rank is in IDD2P Precharge Power-Down Standby Current mode
3) Both ranks are in the same IDD current mode
4) standard
Data Sheet
21
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
IDD Specifications and Conditions
4.1
IDD Test Conditions
For testing the IDD parameters, the timing parameters as in Table 15 are used.
Table 15
IDD Measurement Test Condition
Parameter
Symbol
-3.7
-5
Unit
PC2-4200-4-4-4 PC2-3200-3-3-3
CAS Latency
CLmin
4
3
tCK
Clock Cycle Time
tCKmin
tRCDmin
tRCmin
3.75
5
ns
15
15
ns
60
55
ns
Active bank A to Active bank B command
delay
tRRDmin
10
10
ns
Active to Precharge Command
tRASmin
tRASmax
tRPmin
tRFCmin
45
40
ns
70000
70000
ns
15
15
ns
105
105
ns
tREFI
7.8
7.8
µs
Active to Read or Write delay
Active to Active / Auto-Refresh command
period
Precharge Command Period
Auto-Refresh to Active / Auto-Refresh
command period
Average periodic Refresh interval
4.2
ODT (On Die Termination) Current
current consumption for any terminated input pin,
depends on the input pin is in tri-state or driving “0” or
“1”, as long a ODT is enabled during a given period of
time.
The ODT function adds additional current consumption
to the DDR2 SDRAM when enabled by the EMRS(1).
Depending on address bits A[6,2] in the EMRS(1) a
“weak” or “strong” termination can be selected. The
Table 16
ODT current per terminated pin
Parameter
Symbol
Min. Typ. Max.
Unit
EMRS(1) State
Enabled ODT current per DQ
ODT is HIGH; Data Bus inputs are FLOATING
IODTO
5
6
7.5
mA/DQ
A6 = 0, A2 = 1
2.5
3
3.75
mA/DQ
A6 = 1, A2 = 0
Active ODT current per DQ
ODT is HIGH; worst case of Data Bus inputs are
STABLE or SWITCHING.
IODTT
10
12
15
mA/DQ
A6 = 0, A2 = 1
5
6
7.5
mA/DQ
A6 = 1, A2 = 0
Note: For power consumption calculations the ODT duty cycle has to be taken into account
Data Sheet
22
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
Electrical Characteristics & AC Timings
5
Electrical Characteristics & AC Timings
Table 17
AC Timing - Absolute Specificatioins –5/–3.7
Parameter
Symbol –3.7
–5
PC2-4200S
tAC
DQS output access time from CK/CK tDQSCK
CK, CK high-level width
tCH
CK, CK low-level width
tCL
Clock Half Period
tHP
Clock cycle time
tCK
DQ output access time from CK/CK
Unit Notes
PC2-3200S
Min.
Max.
Min.
Max.
-500
+500
−600
+600
ps
1)
−450
+450
−500
+500
ps
1)
0.45
0.55
0.45
0.55
1)
0.45
0.55
0.45
0.55
tCK
tCK
tCK
min. (tCL, tCH)
min. (tCL, tCH)
1)
1)
5000
8000
5000
8000
ps
1)2)
3750
8000
5000
8000
ps
1)3)
600
—
600
—
ps
1)
tIH
tDH
tDS
tIPW
600
—
600
—
ps
1)
350
—
400
—
ps
1)
350
—
400
—
ps
1)
0.6
—
0.6
—
tCK
1)
DQ and DM input pulse width (each
input)
tDIPW
0.35
—
0.35
—
tCK
1)
Data-out high-impedance time from
CK/CK
tHZ
—
tACmax
—
tACmax
ps
1)
DQ low-impedance from CK / CK
tLZ(DQ)
tLZ(DQS)
tDQSQ
2×tACmin
2×tACmin
1)
tACmin
tACmax
tACmax
ps
tACmin
tACmax
tACmax
ps
1)
—
300
—
350
ps
1)
—
400
—
450
ps
1)
tHP−tQHS
—
tHP−tQHS
1)
WL - 0.25
WL + 0.25 WL − 0.25
tCK
WL + 0.25 tCK
Address and control input setup time tIS
Address and control input hold time
DQ and DM input hold time
DQ and DM input setup time
Control and Addr. input pulse width
(each input)
DQS low-impedance from CK / CK
DQS-DQ skew (for DQS &
associated DQ signals)
tQHS
Data Output hold time from DQS
tQH
Write command to 1st DQS latching tDQSS
Data hold skew factor
—
1)
transition
DQS input low (high) pulse width
(write cycle)
tDQSL,H
0.35
—
0.35
—
tCK
1)
DQS falling edge to CLK setup time
(write cycle)
tDSS
0.2
—
0.2
—
tCK
1)
DQS falling edge hold time from CLK tDSH
(write cycle)
0.2
—
0.2
—
tCK
1)
Mode register set command cycle
time
tMRD
2
—
2
—
tCK
1)
Write preamble
tWPRE
tWPST
tRPRE
tRPST
tRAS
0.25
—
0.25
—
1)
0.40
0.60
0.40
0.60
0.9
1.1
0.9
1.1
0.40
0.60
0.40
0.60
tCK
tCK
tCK
tCK
45
70000
40
70000
ns
1)
Write postamble
Read preamble
Read postamble
Active to Precharge command
Data Sheet
23
1)
1)
1)
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
Electrical Characteristics & AC Timings
Table 17
AC Timing - Absolute Specificatioins –5/–3.7
Parameter
Symbol –3.7
–5
PC2-4200S
Unit Notes
PC2-3200S
Min.
Max.
Min.
Max.
Active to Active/Auto-refresh
command period
tRC
60
—
55
—
ns
1)
Auto-refresh to Active/Auto-refresh
command period
tRFC
105
—
105
—
ns
1)
Active to Read or Write delay (with
and without Auto-Precharge) delay
tRCD
15
—
15
—
ns
1)
Precharge command period
tRP
tRRD
15
—
15
—
ns
1)
10
—
10
—
ns
1)
tCCD
tWR
tDAL
2
—
2
—
tCK
1)
15
—
15
—
ns
1)
WR + tRP
—
WR + tRP
—
tCK
1)
Internal write to read command delay tWTR
7.5
—
10
—
ns
1)
Internal read to precharge command tRTP
delay
7.5
—
7.5
—
ns
1)
2
—
2
—
tCK
1)
6 − AL
—
6 − AL
—
tCK
1)
Active bank A to Active bank B
command
CAS A to CAS B Command Period
Write recovery time
Auto precharge write recovery +
precharge time
Exit power down to any valid
command
(other than NOP or Deselect)
tXARD
Exit active power-down mode to read tXARDS
command (slew exit, lower power)
Exit precharge power-down to any
valid command (other than NOP or
Deselect)
tXP
2
—
2
—
tCK
1)
Exit Self-Refresh to read command
tXSRD
tXSNR
200
—
200
—
tCK
1)
tRFC + 10
—
tRFC + 10
—
ns
1)
CKE minimum high and low pulse
width
tCKE
3
—
3
—
tCK
1)
OCD drive mode output delay
tOIT
tDELAY
0
12
0
12
ns
1)
tIS + tCK + tIH —
tIS + tCK+ tIH —
ns
1)
tREFI
—
7.8
—
7.8
µs
1)4)
—
3.9
—
3.9
Exit Self-Refresh to non-read
command
Minimum time clocks remain ON
after CKE asynchronously drops low
Average Periodic Refresh Interval
1)5)
1) For details and notes see the relevant INFINEON component datasheet
2) CL = 3
3) CL = 4 & 5
4) 0 °C ≤
TCASE ≤ 85 °C
5) 85 °C < TCASE ≤ 95 °C
Data Sheet
24
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
Electrical Characteristics & AC Timings
Table 18
Symbol
tAOND
tAON
tAONPD
tAOFD
tAOF
tAOFPD
tANPD
tAXPD
ODT AC Electrical Characteristics and Operating Conditions (all speed bins)
Parameter / Condition
Min.
Max.
Unit
ODT turn-on delay
2
2
tCK
ODT turn-on
tAC(max) + 1 ns
2 tCK + tAC(max) + 1 ns
ns
ODT turn-on (Power-Down Modes)
tAC(min)
tAC(min) + 2 ns
ns
ODT turn-off delay
2.5
2.5
tCK
ODT turn-off
tAC(min)
tAC(min) + 2 ns
tAC(max) + 0.6 ns
2.5 tCK + tAC(max) + 1 ns
ns
tCK
tCK
ODT turn-off delay (Power-Down Modes)
ODT to Power Down Mode Entry Latency
3
—
ODT Power Down Exit Latency
8
—
Data Sheet
25
ns
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Product Type
HYS64T32000HDL–3.7–A
SPD Codes for HYS 64T[32000/64020] PC2–4200S
HYS64T32000GDL–3.7–A
Table 19
HYS64T64020HDL–3.7–A
SPD Codes
HYS64T64020GDL–3.7–A
6
Organization
512 MB
512 MB
256 MB
256 MB
×64
×64
×64
×64
2 Ranks (×16)
2 Ranks (×16)
1 Rank (×16)
1 Rank (×16)
Label Code
PC2–4200S–444
PC2–4200S–444
PC2–4200S–444
PC2–4200S–444
JEDEC SPD Revision
Rev. 1.1
Rev. 1.1
Rev. 1.1
Rev. 1.1
Byte#
Description
HEX
HEX
HEX
HEX
0
Programmed SPD
Bytes in EEPROM
80
80
80
80
1
Total number of Bytes 08
in EEPROM
08
08
08
2
Memory Type
(DDR2)
08
08
08
08
3
Number of Row
Addresses
0D
0D
0D
0D
4
Number of Column
Addresses
0A
0A
0A
0A
5
DIMM Rank and
Stacking Information
61
61
60
60
6
Data Width
40
40
40
40
7
Not used
00
00
00
00
8
Interface Voltage
Level
05
05
05
05
9
tCK @ CLmax (Byte 18) 3D
3D
3D
3D
50
50
50
50
[ns]
10
tAC SDRAM @ CLmax
(Byte 18) [ns]
11
Error Correction
Support (non-ECC,
ECC)
00
00
00
00
12
Refresh Rate and
Type
82
82
82
82
13
Primary SDRAM
Width
10
10
10
10
14
Error Checking
SDRAM Width
00
00
00
00
Data Sheet
26
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Product Type
HYS64T64020HDL–3.7–A
HYS64T32000GDL–3.7–A
HYS64T32000HDL–3.7–A
SPD Codes for HYS 64T[32000/64020] PC2–4200S
HYS64T64020GDL–3.7–A
Table 19
Organization
512 MB
512 MB
256 MB
256 MB
×64
×64
×64
×64
2 Ranks (×16)
2 Ranks (×16)
1 Rank (×16)
1 Rank (×16)
Label Code
PC2–4200S–444
PC2–4200S–444
PC2–4200S–444
PC2–4200S–444
JEDEC SPD Revision
Rev. 1.1
Rev. 1.1
Rev. 1.1
Rev. 1.1
Byte#
Description
HEX
HEX
HEX
HEX
15
Not used
00
00
00
00
16
Burst Length
Supported
0C
0C
0C
0C
17
Number of Banks on
SDRAM Device
04
04
04
04
18
Supported CAS
Latencies
38
38
38
38
19
Not used
00
00
00
00
20
DIMM Type
Information
04
04
04
04
21
DIMM Attributes
00
00
00
00
22
Component Attributes 01
01
01
01
23
tCK @ CLmax -1 (Byte
18) [ns]
3D
3D
3D
3D
24
tAC SDRAM @ CLmax - 50
50
50
50
1 [ns]
25
tCK @ CLmax -2 (Byte
18) [ns]
50
50
50
50
26
tAC SDRAM @ CLmax - 60
60
60
60
3C
3C
3C
3C
28
28
28
28
3C
3C
3C
3C
2D
2D
2D
2D
40
40
40
40
2 [ns]
27
28
29
30
tRP.min [ns]
tRRD.min [ns]
tRCD.min [ns]
tRAS.min [ns]
31
Module Density per
Rank
32
tAS.min and tCS.min [ns]
tAH.min and tCH.min [ns]
tDS.min [ns]
tDH.min [ns]
33
34
35
Data Sheet
25
25
25
25
37
37
37
37
10
10
10
10
22
22
22
22
27
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Product Type
HYS64T64020HDL–3.7–A
HYS64T32000GDL–3.7–A
HYS64T32000HDL–3.7–A
SPD Codes for HYS 64T[32000/64020] PC2–4200S
HYS64T64020GDL–3.7–A
Table 19
Organization
512 MB
512 MB
256 MB
256 MB
×64
×64
×64
×64
2 Ranks (×16)
2 Ranks (×16)
1 Rank (×16)
1 Rank (×16)
Label Code
PC2–4200S–444
PC2–4200S–444
PC2–4200S–444
PC2–4200S–444
JEDEC SPD Revision
Rev. 1.1
Rev. 1.1
Rev. 1.1
Rev. 1.1
Byte#
Description
HEX
HEX
HEX
HEX
36
tWR.min [ns]
tWTR.min [ns]
tRTP.min [ns]
3C
3C
3C
3C
1E
1E
1E
1E
1E
1E
1E
1E
39
Analysis
Characteristics
00
00
00
00
40
00
00
00
00
3C
3C
3C
3C
69
69
69
69
80
80
80
80
1E
1E
1E
1E
45
tRC and tRFC Extension
tRC.min [ns]
tRFC.min [ns]
tCK.max [ns]
tDQSQ.max [ns]
tQHS.max [ns]
28
28
28
28
46
PLL Relock Time
00
00
00
00
47
TCASE.max Delta /
∆ T4R4W Delta
53
53
53
53
48
Psi(T-A) DRAM
72
72
72
72
49
∆ T0 (DT0)
52
52
52
52
50
∆ T2N (DT2N, UDIMM) 2B
or ∆ T2Q ( (DT2Q,
RDIMM)
2B
2B
2B
51
∆ T2P (DT2P)
1D
1D
1D
1D
52
∆ T3N (DT3N)
1D
1D
1D
1D
53
∆ T3P.fast (DT3P fast)
23
23
23
23
54
∆ T3P.slow (DT3P slow) 16
16
16
16
55
∆ T4R (DT4R) / ∆ T4R4W 36
S Sign (DT4R4W)
36
36
36
56
∆ T5B (DT5B)
1C
1C
1C
1C
57
∆ T7 (DT7)
30
30
30
30
58
Psi(ca) PLL
00
00
00
00
59
Psi(ca) REG
00
00
00
00
37
38
41
42
43
44
Data Sheet
28
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Product Type
HYS64T64020HDL–3.7–A
HYS64T32000GDL–3.7–A
HYS64T32000HDL–3.7–A
SPD Codes for HYS 64T[32000/64020] PC2–4200S
HYS64T64020GDL–3.7–A
Table 19
Organization
512 MB
512 MB
256 MB
256 MB
×64
×64
×64
×64
2 Ranks (×16)
2 Ranks (×16)
1 Rank (×16)
1 Rank (×16)
Label Code
PC2–4200S–444
PC2–4200S–444
PC2–4200S–444
PC2–4200S–444
JEDEC SPD Revision
Rev. 1.1
Rev. 1.1
Rev. 1.1
Rev. 1.1
Byte#
Description
HEX
HEX
HEX
HEX
60
∆ TPLL (DTPLL)
00
00
00
00
61
∆ TREG (DTREG) /
Toggle Rate
00
00
00
00
62
SPD Revision
11
11
11
11
63
Checksum of Bytes 0- BC
62
BC
BB
BB
64
JEDEC ID Code of
Infineon (1)
C1
C1
C1
C1
65
JEDEC ID Code of
Infineon (2)
00
00
00
00
66
JEDEC ID Code of
Infineon (3)
00
00
00
00
67
JEDEC ID Code of
Infineon (4)
00
00
00
00
68
JEDEC ID Code of
Infineon (5)
00
00
00
00
69
JEDEC ID Code of
Infineon (6)
00
00
00
00
70
JEDEC ID Code of
Infineon (7)
00
00
00
00
71
JEDEC ID Code of
Infineon (8)
00
00
00
00
72
Module Manufacturer
Location
xx
xx
xx
xx
73
Product Type, Char 1 36
36
36
36
74
Product Type, Char 2 34
34
34
34
75
Product Type, Char 3 54
54
54
54
76
Product Type, Char 4 36
36
33
33
77
Product Type, Char 5 34
34
32
32
78
Product Type, Char 6 30
30
30
30
Data Sheet
29
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Product Type
HYS64T64020HDL–3.7–A
HYS64T32000GDL–3.7–A
HYS64T32000HDL–3.7–A
SPD Codes for HYS 64T[32000/64020] PC2–4200S
HYS64T64020GDL–3.7–A
Table 19
Organization
512 MB
512 MB
256 MB
256 MB
×64
×64
×64
×64
2 Ranks (×16)
2 Ranks (×16)
1 Rank (×16)
1 Rank (×16)
Label Code
PC2–4200S–444
PC2–4200S–444
PC2–4200S–444
PC2–4200S–444
JEDEC SPD Revision
Rev. 1.1
Rev. 1.1
Rev. 1.1
Rev. 1.1
Byte#
Description
HEX
HEX
HEX
HEX
79
Product Type, Char 7 32
32
30
30
80
Product Type, Char 8 30
30
30
30
81
Product Type, Char 9 47
48
47
48
82
Product Type, Char
10
44
44
44
44
83
Product Type, Char
11
4C
4C
4C
4C
84
Product Type, Char
12
33
33
33
33
85
Product Type, Char
13
2E
2E
2E
2E
86
Product Type, Char
14
37
37
37
37
87
Product Type, Char
15
41
41
41
41
88
Product Type, Char
16
20
20
20
20
89
Product Type, Char
17
20
20
20
20
90
Product Type, Char
18
20
20
20
20
91
Module Revision
Code
1x
1x
1x
1x
92
Test Program
Revision Code
xx
xx
xx
xx
93
Module Manufacturing xx
Date Year
xx
xx
xx
94
Module Manufacturing xx
Date Week
xx
xx
xx
95
Module Manufacturing xx
Date Week
xx
xx
xx
Data Sheet
30
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Product Type
HYS64T64020HDL–3.7–A
HYS64T32000GDL–3.7–A
HYS64T32000HDL–3.7–A
SPD Codes for HYS 64T[32000/64020] PC2–4200S
HYS64T64020GDL–3.7–A
Table 19
Organization
512 MB
512 MB
256 MB
256 MB
×64
×64
×64
×64
2 Ranks (×16)
2 Ranks (×16)
1 Rank (×16)
1 Rank (×16)
Label Code
PC2–4200S–444
PC2–4200S–444
PC2–4200S–444
PC2–4200S–444
JEDEC SPD Revision
Rev. 1.1
Rev. 1.1
Rev. 1.1
Rev. 1.1
Byte#
Description
HEX
HEX
HEX
HEX
96
Module Serial Number xx
(1)
xx
xx
xx
97
Module Serial Number xx
(2)
xx
xx
xx
98
Module Serial Number xx
(3)
xx
xx
xx
99
Module Serial Number xx
(4)
xx
xx
xx
100 127
Not used
00
00
00
00
128255
BLANK
FF
FF
FF
FF
Data Sheet
31
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
HYS64T64020HDL–5–A
HYS64T32000GDL–5–A
HYS64T32000HDL–5–A
SPD Codes for HYS 64T[32000/64020] PC2-3200S
Product Type
HYS64T64020GDL–5–A
Table 20
Organization
512 MB
512 MB
256 MB
256 MB
×64
×64
×64
×64
2 Ranks (×16)
2 Ranks (×16)
1 Rank (×16)
1 Rank (×16)
Label Code
PC2–3200S–333
PC2–3200S–333
PC2–3200S–333
PC2–3200S–333
JEDEC SPD Revision
Rev. 1.1
Rev. 1.1
Rev. 1.1
Rev. 1.1
Byte#
Description
HEX
HEX
HEX
HEX
0
Programmed SPD
Bytes in EEPROM
80
80
80
80
1
Total number of Bytes 08
in EEPROM
08
08
08
2
Memory Type
(DDR2)
08
08
08
08
3
Number of Row
Addresses
0D
0D
0D
0D
4
Number of Column
Addresses
0A
0A
0A
0A
5
DIMM Rank and
Stacking Information
61
61
60
60
6
Data Width
40
40
40
40
7
Not used
00
00
00
00
8
Interface Voltage
Level
05
05
05
05
9
tCK @ CLmax (Byte 18) 50
50
50
50
60
60
60
60
[ns]
10
tAC SDRAM @ CLmax
(Byte 18) [ns]
11
Error Correction
Support (non-ECC,
ECC)
00
00
00
00
12
Refresh Rate and
Type
82
82
82
82
13
Primary SDRAM
Width
10
10
10
10
14
Error Checking
SDRAM Width
00
00
00
00
15
Not used
00
00
00
00
Data Sheet
32
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Product Type
HYS64T64020HDL–5–A
HYS64T32000GDL–5–A
HYS64T32000HDL–5–A
SPD Codes for HYS 64T[32000/64020] PC2-3200S
HYS64T64020GDL–5–A
Table 20
Organization
512 MB
512 MB
256 MB
256 MB
×64
×64
×64
×64
2 Ranks (×16)
2 Ranks (×16)
1 Rank (×16)
1 Rank (×16)
Label Code
PC2–3200S–333
PC2–3200S–333
PC2–3200S–333
PC2–3200S–333
JEDEC SPD Revision
Rev. 1.1
Rev. 1.1
Rev. 1.1
Rev. 1.1
Byte#
Description
HEX
HEX
HEX
HEX
16
Burst Length
Supported
0C
0C
0C
0C
17
Number of Banks on
SDRAM Device
04
04
04
04
18
Supported CAS
Latencies
38
38
38
38
19
Not used
00
00
00
00
20
DIMM Type
Information
04
04
04
04
21
DIMM Attributes
00
00
00
00
22
Component Attributes 01
01
01
01
23
tCK @ CLmax -1 (Byte
18) [ns]
50
50
50
50
24
tAC SDRAM @ CLmax - 60
60
60
60
1 [ns]
25
tCK @ CLmax -2 (Byte
18) [ns]
50
50
50
50
26
tAC SDRAM @ CLmax - 60
60
60
60
3C
3C
3C
3C
28
28
28
28
3C
3C
3C
3C
2D
2D
2D
2D
2 [ns]
27
28
29
30
tRP.min [ns]
tRRD.min [ns]
tRCD.min [ns]
tRAS.min [ns]
31
Module Density per
Rank
40
40
40
40
32
tAS.min and tCS.min [ns]
tAH.min and tCH.min [ns]
tDS.min [ns]
tDH.min [ns]
tWR.min [ns]
35
35
35
35
47
47
47
47
15
15
15
15
27
27
27
27
3C
3C
3C
3C
33
34
35
36
Data Sheet
33
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Product Type
HYS64T64020HDL–5–A
HYS64T32000GDL–5–A
HYS64T32000HDL–5–A
SPD Codes for HYS 64T[32000/64020] PC2-3200S
HYS64T64020GDL–5–A
Table 20
Organization
512 MB
512 MB
256 MB
256 MB
×64
×64
×64
×64
2 Ranks (×16)
2 Ranks (×16)
1 Rank (×16)
1 Rank (×16)
Label Code
PC2–3200S–333
PC2–3200S–333
PC2–3200S–333
PC2–3200S–333
JEDEC SPD Revision
Rev. 1.1
Rev. 1.1
Rev. 1.1
Rev. 1.1
Byte#
Description
HEX
HEX
HEX
HEX
37
tWTR.min [ns]
tRTP.min [ns]
28
28
28
28
1E
1E
1E
1E
39
Analysis
Characteristics
00
00
00
00
40
00
00
00
00
3C
3C
3C
3C
69
69
69
69
80
80
80
80
23
23
23
23
45
tRC and tRFC Extension
tRC.min [ns]
tRFC.min [ns]
tCK.max [ns]
tDQSQ.max [ns]
tQHS.max [ns]
2D
2D
2D
2D
46
PLL Relock Time
00
00
00
00
47
TCASE.max Delta /
∆ T4R4W Delta
51
51
51
51
48
Psi(T-A) DRAM
72
72
72
72
49
∆ T0 (DT0)
42
42
42
42
50
∆ T2N (DT2N, UDIMM) 23
or ∆ T2Q ( (DT2Q,
RDIMM)
23
23
23
51
∆ T2P (DT2P)
1D
1D
1D
1D
52
∆ T3N (DT3N)
19
19
19
19
53
∆ T3P.fast (DT3P fast)
1C
1C
1C
1C
38
41
42
43
44
54
∆ T3P.slow (DT3P slow) 16
16
16
16
55
∆ T4R (DT4R) / ∆ T4R4W 2E
S Sign (DT4R4W)
2E
2E
2E
56
∆ T5B (DT5B)
1A
1A
1A
1A
57
∆ T7 (DT7)
2D
2D
2D
2D
58
Psi(ca) PLL
00
00
00
00
59
Psi(ca) REG
00
00
00
00
60
∆ TPLL (DTPLL)
00
00
00
00
Data Sheet
34
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Product Type
HYS64T64020HDL–5–A
HYS64T32000GDL–5–A
HYS64T32000HDL–5–A
SPD Codes for HYS 64T[32000/64020] PC2-3200S
HYS64T64020GDL–5–A
Table 20
Organization
512 MB
512 MB
256 MB
256 MB
×64
×64
×64
×64
2 Ranks (×16)
2 Ranks (×16)
1 Rank (×16)
1 Rank (×16)
Label Code
PC2–3200S–333
PC2–3200S–333
PC2–3200S–333
PC2–3200S–333
JEDEC SPD Revision
Rev. 1.1
Rev. 1.1
Rev. 1.1
Rev. 1.1
Byte#
Description
HEX
HEX
HEX
HEX
61
∆ TREG (DTREG) /
Toggle Rate
00
00
00
00
62
SPD Revision
11
11
11
11
63
Checksum of Bytes 0- 0E
62
0E
0D
0D
64
JEDEC ID Code of
Infineon (1)
C1
C1
C1
C1
65
JEDEC ID Code of
Infineon (2)
00
00
00
00
66
JEDEC ID Code of
Infineon (3)
00
00
00
00
67
JEDEC ID Code of
Infineon (4)
00
00
00
00
68
JEDEC ID Code of
Infineon (5)
00
00
00
00
69
JEDEC ID Code of
Infineon (6)
00
00
00
00
70
JEDEC ID Code of
Infineon (7)
00
00
00
00
71
JEDEC ID Code of
Infineon (8)
00
00
00
00
72
Module Manufacturer
Location
xx
xx
xx
xx
73
Product Type, Char 1 36
36
36
36
74
Product Type, Char 2 34
34
34
34
75
Product Type, Char 3 54
54
54
54
76
Product Type, Char 4 36
36
33
33
77
Product Type, Char 5 34
34
32
32
78
Product Type, Char 6 30
30
30
30
79
Product Type, Char 7 32
32
30
30
80
Product Type, Char 8 30
30
30
30
Data Sheet
35
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Product Type
HYS64T64020HDL–5–A
HYS64T32000GDL–5–A
HYS64T32000HDL–5–A
SPD Codes for HYS 64T[32000/64020] PC2-3200S
HYS64T64020GDL–5–A
Table 20
Organization
512 MB
512 MB
256 MB
256 MB
×64
×64
×64
×64
2 Ranks (×16)
2 Ranks (×16)
1 Rank (×16)
1 Rank (×16)
Label Code
PC2–3200S–333
PC2–3200S–333
PC2–3200S–333
PC2–3200S–333
JEDEC SPD Revision
Rev. 1.1
Rev. 1.1
Rev. 1.1
Rev. 1.1
Byte#
Description
HEX
HEX
HEX
HEX
81
Product Type, Char 9 47
48
47
48
82
Product Type, Char
10
44
44
44
44
83
Product Type, Char
11
4C
4C
4C
4C
84
Product Type, Char
12
35
35
35
35
85
Product Type, Char
13
41
41
41
41
86
Product Type, Char
14
20
20
20
20
87
Product Type, Char
15
20
20
20
20
88
Product Type, Char
16
20
20
20
20
89
Product Type, Char
17
20
20
20
20
90
Product Type, Char
18
20
20
20
20
91
Module Revision
Code
1x
1x
1x
1x
92
Test Program
Revision Code
xx
xx
xx
xx
93
Module Manufacturing xx
Date Year
xx
xx
xx
94
Module Manufacturing xx
Date Week
xx
xx
xx
95
Module Manufacturing xx
Date Week
xx
xx
xx
96
Module Serial Number xx
(1)
xx
xx
xx
Data Sheet
36
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Product Type
HYS64T64020HDL–5–A
HYS64T32000GDL–5–A
HYS64T32000HDL–5–A
SPD Codes for HYS 64T[32000/64020] PC2-3200S
HYS64T64020GDL–5–A
Table 20
Organization
512 MB
512 MB
256 MB
256 MB
×64
×64
×64
×64
2 Ranks (×16)
2 Ranks (×16)
1 Rank (×16)
1 Rank (×16)
Label Code
PC2–3200S–333
PC2–3200S–333
PC2–3200S–333
PC2–3200S–333
JEDEC SPD Revision
Rev. 1.1
Rev. 1.1
Rev. 1.1
Rev. 1.1
Byte#
Description
HEX
HEX
HEX
HEX
97
Module Serial Number xx
(2)
xx
xx
xx
98
Module Serial Number xx
(3)
xx
xx
xx
99
Module Serial Number xx
(4)
xx
xx
xx
100 127
Not used
00
00
00
00
128255
BLANK
FF
FF
FF
FF
Data Sheet
37
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
HYS64T128021GDL–3.7–A
HYS64T128021HDL–5–A
HYS64T128021GDL–5–A
SPD Codes for HYS64T128021[G/H]DL
Product Type
HYS64T128021HDL–3.7–A
Table 21
Organization
1 GByte
1 GByte
1 GByte
1 GByte
×64
×64
×64
×64
2 Ranks (×8)
2 Ranks (×8)
2 Ranks (×8)
2 Ranks (×8)
Label Code
PC2–4200S–444 PC2–4200S–444
PC2–3200S–444 PC2–3200S–444
JEDEC SPD Revision
Rev. 1.1
Rev. 1.1
Rev. 1.1
Rev. 1.1
Byte#
Description
HEX
HEX
HEX
HEX
0
Programmed SPD
Bytes in EEPROM
80
80
80
80
1
Total number of Bytes 08
in EEPROM
08
08
08
2
Memory Type (DDR2) 08
08
08
08
3
Number of Row
Addresses
0E
0E
0E
0E
4
Number of Column
Addresses
0A
0A
0A
0A
5
DIMM Rank and
Stacking Information
61
61
61
61
6
Data Width
40
40
40
40
7
Not used
00
00
00
00
8
Interface Voltage
Level
05
05
05
05
9
tCK @ CLmax (Byte 18) 3D
[ns]
3D
50
50
10
tAC SDRAM @ CLmax
50
50
60
60
(Byte 18) [ns]
11
Error Correction
Support (non-ECC,
ECC)
00
00
00
00
12
Refresh Rate and
Type
82
82
82
82
13
Primary SDRAM
Width
08
08
08
08
14
Error Checking
SDRAM Width
00
00
00
00
15
Not used
00
00
00
00
Data Sheet
38
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Product Type
HYS64T128021GDL–3.7–A
HYS64T128021HDL–5–A
HYS64T128021GDL–5–A
SPD Codes for HYS64T128021[G/H]DL
HYS64T128021HDL–3.7–A
Table 21
Organization
1 GByte
1 GByte
1 GByte
1 GByte
×64
×64
×64
×64
2 Ranks (×8)
2 Ranks (×8)
2 Ranks (×8)
2 Ranks (×8)
Label Code
PC2–4200S–444 PC2–4200S–444
PC2–3200S–444 PC2–3200S–444
JEDEC SPD Revision
Rev. 1.1
Rev. 1.1
Rev. 1.1
Rev. 1.1
Byte#
Description
HEX
HEX
HEX
HEX
16
Burst Length
Supported
0C
0C
0C
0C
17
Number of Banks on
SDRAM Device
04
04
04
04
18
Supported CAS
Latencies
38
38
38
38
19
Not used
00
00
00
00
20
DIMM Type
Information
04
04
04
04
21
DIMM Attributes
00
00
00
00
22
Component Attributes 01
01
01
01
23
tCK @ CLmax -1 (Byte
18) [ns]
3D
3D
50
50
24
tAC SDRAM @ CLmax - 50
50
60
60
1 [ns]
25
tCK @ CLmax -2 (Byte
18) [ns]
50
50
50
50
26
tAC SDRAM @ CLmax - 60
60
60
60
2 [ns]
tRP.min [ns]
tRRD.min [ns]
tRCD.min [ns]
tRAS.min [ns]
3C
3C
3C
3C
1E
1E
1E
1E
3C
3C
3C
3C
2D
2D
2D
2D
31
Module Density per
Rank
80
80
80
80
32
tAS.min and tCS.min [ns]
tAH.min and tCH.min [ns]
tDS.min [ns]
tDH.min [ns]
25
25
35
35
37
37
47
47
10
10
15
15
22
22
27
27
27
28
29
30
33
34
35
Data Sheet
39
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Product Type
HYS64T128021GDL–3.7–A
HYS64T128021HDL–5–A
HYS64T128021GDL–5–A
SPD Codes for HYS64T128021[G/H]DL
HYS64T128021HDL–3.7–A
Table 21
Organization
1 GByte
1 GByte
1 GByte
1 GByte
×64
×64
×64
×64
2 Ranks (×8)
2 Ranks (×8)
2 Ranks (×8)
2 Ranks (×8)
Label Code
PC2–4200S–444 PC2–4200S–444
PC2–3200S–444 PC2–3200S–444
JEDEC SPD Revision
Rev. 1.1
Rev. 1.1
Rev. 1.1
Rev. 1.1
Byte#
Description
HEX
HEX
HEX
HEX
36
tWR.min [ns]
tWTR.min [ns]
tRTP.min [ns]
3C
3C
3C
3C
1E
1E
28
28
1E
1E
1E
1E
37
38
39
Analysis
Characteristics
00
00
00
00
40
00
00
00
00
3C
3C
3C
3C
69
69
69
69
80
80
80
80
1E
1E
23
23
45
tRC and tRFC Extension
tRC.min [ns]
tRFC.min [ns]
tCK.max [ns]
tDQSQ.max [ns]
tQHS.max [ns]
28
28
2D
2D
46
PLL Relock Time
00
00
00
00
47
TCASE.max Delta /
∆ T4R4W Delta
51
51
51
51
48
Psi(T-A) DRAM
78
78
78
78
49
∆ T0 (DT0)
3E
3E
32
32
50
∆ T2N (DT2N, UDIMM) 2E
or ∆ T2Q ( (DT2Q,
RDIMM)
2E
24
24
51
∆ T2P (DT2P)
1E
1E
1E
1E
52
∆ T3N (DT3N)
1E
1E
1B
1B
53
∆ T3P.fast (DT3P fast)
24
24
1E
1E
54
∆ T3P.slow (DT3P slow)
17
17
17
17
∆ T4R (DT4R) / ∆ T4R4W 34
Sign (DT4R4W)
34
28
28
∆ T5B (DT5B)
1E
1B
1B
41
42
43
44
55
S
56
1E
57
∆ T7 (DT7)
20
20
1E
1E
58
Psi(ca) PLL
00
00
00
00
59
Psi(ca) REG
00
00
00
00
Data Sheet
40
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Product Type
HYS64T128021GDL–3.7–A
HYS64T128021HDL–5–A
HYS64T128021GDL–5–A
SPD Codes for HYS64T128021[G/H]DL
HYS64T128021HDL–3.7–A
Table 21
Organization
1 GByte
1 GByte
1 GByte
1 GByte
×64
×64
×64
×64
2 Ranks (×8)
2 Ranks (×8)
2 Ranks (×8)
2 Ranks (×8)
Label Code
PC2–4200S–444 PC2–4200S–444
PC2–3200S–444 PC2–3200S–444
JEDEC SPD Revision
Rev. 1.1
Rev. 1.1
Rev. 1.1
Rev. 1.1
Byte#
Description
HEX
HEX
HEX
HEX
60
∆ TPLL (DTPLL)
00
00
00
00
61
∆ TREG (DTREG) /
Toggle Rate
00
00
00
00
62
SPD Revision
11
11
11
11
63
Checksum of Bytes 0- D2
62
D2
26
26
64
JEDEC ID Code of
Infineon (1)
C1
C1
C1
C1
65
JEDEC ID Code of
Infineon (2)
00
00
00
00
66
JEDEC ID Code of
Infineon (3)
00
00
00
00
67
JEDEC ID Code of
Infineon (4)
00
00
00
00
68
JEDEC ID Code of
Infineon (5)
00
00
00
00
69
JEDEC ID Code of
Infineon (6)
00
00
00
00
70
JEDEC ID Code of
Infineon (7)
00
00
00
00
71
JEDEC ID Code of
Infineon (8)
00
00
00
00
72
Module Manufacturer
Location
xx
xx
xx
xx
73
Product Type, Char 1
36
36
36
36
74
Product Type, Char 2
34
34
34
34
75
Product Type, Char 3
54
54
54
54
76
Product Type, Char 4
31
31
31
31
77
Product Type, Char 5
32
32
32
32
78
Product Type, Char 6
38
38
38
38
Data Sheet
41
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Product Type
HYS64T128021GDL–3.7–A
HYS64T128021HDL–5–A
HYS64T128021GDL–5–A
SPD Codes for HYS64T128021[G/H]DL
HYS64T128021HDL–3.7–A
Table 21
Organization
1 GByte
1 GByte
1 GByte
1 GByte
×64
×64
×64
×64
2 Ranks (×8)
2 Ranks (×8)
2 Ranks (×8)
2 Ranks (×8)
Label Code
PC2–4200S–444 PC2–4200S–444
PC2–3200S–444 PC2–3200S–444
JEDEC SPD Revision
Rev. 1.1
Rev. 1.1
Rev. 1.1
Rev. 1.1
Byte#
Description
HEX
HEX
HEX
HEX
79
Product Type, Char 7
30
30
30
30
80
Product Type, Char 8
32
32
32
32
81
Product Type, Char 9
31
31
31
31
82
Product Type, Char 10 48
47
48
47
83
Product Type, Char 11 44
44
44
44
84
Product Type, Char 12 4C
4C
4C
4C
85
Product Type, Char 13 33
33
35
35
86
Product Type, Char 14 2E
2E
41
41
87
Product Type, Char 15 37
37
20
20
88
Product Type, Char 16 41
41
20
20
89
Product Type, Char 17 20
20
20
20
90
Product Type, Char 18 20
20
20
20
91
Module Revision
Code
0x
0x
0x
0x
92
Test Program
Revision Code
xx
xx
xx
xx
93
Module Manufacturing xx
Date Year
xx
xx
xx
94
Module Manufacturing xx
Date Week
xx
xx
xx
95
Module Manufacturing xx
Date Week
xx
xx
xx
96
Module Serial Number xx
(1)
xx
xx
xx
97
Module Serial Number xx
(2)
xx
xx
xx
98
Module Serial Number xx
(3)
xx
xx
xx
Data Sheet
42
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
SPD Codes
Product Type
HYS64T128021GDL–3.7–A
HYS64T128021HDL–5–A
HYS64T128021GDL–5–A
SPD Codes for HYS64T128021[G/H]DL
HYS64T128021HDL–3.7–A
Table 21
Organization
1 GByte
1 GByte
1 GByte
1 GByte
×64
×64
×64
×64
2 Ranks (×8)
2 Ranks (×8)
2 Ranks (×8)
2 Ranks (×8)
Label Code
PC2–4200S–444 PC2–4200S–444
PC2–3200S–444 PC2–3200S–444
JEDEC SPD Revision
Rev. 1.1
Rev. 1.1
Rev. 1.1
Rev. 1.1
Byte#
Description
HEX
HEX
HEX
HEX
99
Module Serial Number xx
(4)
xx
xx
xx
100 127
Not used
00
00
00
00
128255
BLANK
FF
FF
FF
FF
Data Sheet
43
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
Package Outlines
7
Package Outlines
67.6
3.8 MAX.
30
4 ±0.1
1.8 ±0.05
63.6 ±0.1
(2.15)
1
(2.45)
17.55 ±0.1
100
1±0.1
0.15
2.7 ±0.1
(1.5)
11.4 ±0.1
47.4 ±0.1
(1.8)
(2.15)
2.4 ±0.1
1±0.1
200
20 ±0.1
101
6 ±0.1
4 ±0.1
(2.45)
2 MIN.
2.55
0.25 -0.18
Detail of contacts
0.45 ±0.03
0.6 ±0.1
Burnished, no burr allowed
Figure 5
Data Sheet
GLD09648
Package Outline L-DIM-200-30
44
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
Package Outlines
67.6
3.8 MAX.
30
4 ±0.1
1.8 ±0.05
63.6 ±0.1
(2.15)
1
(2.45)
17.55 ±0.1
100
1±0.1
0.15
2.7 ±0.1
(1.5)
11.4 ±0.1
47.4 ±0.1
(1.8)
(2.15)
2.4 ±0.1
1±0.1
200
20 ±0.1
101
6 ±0.1
4 ±0.1
(2.45)
2 MIN.
2.55
0.25 -0.18
Detail of contacts
0.45 ±0.03
0.6 ±0.1
Burnished, no burr allowed
Figure 6
Data Sheet
GLD09649
Package Outline L-DIM-200-31
45
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
Package Outlines
67.6
± 0.15
3.8 max.
30.00
± 0.13
63.6
1
2.15
39
11.4
41
0.
199
1± 1
2.45
47.4
4.2
2.7
2
1.0
2.15
40 42
200
6
4
2.45
20
1.8
4
0.15
0.25
2.55
Detail of Chamfer
0.2 -
Detail of Contacts
0.2 -
0.45
0.15
0.6
Figure 7
Data Sheet
Package Outline L-DIM-200-33
46
Rev. 0.91, 2004-06
09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
512 Mbit DDR2 SDRAM
Product Type Nomenclature (DDR2 DRAMs and DIMMs)
8
Product Type Nomenclature (DDR2 DRAMs and DIMMs)
Infineon’s nomenclature uses simple coding combined with some propriatory coding. Table 22 provides examples
for module and component product type number as well as the field number. The detailed field description together
with possible values and coding explanation is listed for modules in Table 23 and for components in Table 24.
Table 22
Nomenclature Fields and Examples
Example for
Field Number
1
2
3
4
5
6
7
8
9
10
11
Micro-DIMM
HYS
64
T
64
0
2
0
K
M
–5
–A
DDR2 DRAM
HYB
18
T
512
16
0
A
C
–5
1
INFINEON
Modul Prefix
HYS
Constant
1) Multiplying “Memory Density per I/O” with “Module Data
Width” and dividing by 8 for Non-ECC and 9 for ECC
modules gives the overall module memory density in
MBytes as listed in column “Coding”.
2
Module Data
Width [bit]
64
Non-ECC
Table 24
72
ECC
Field Description
3
DRAM
Technology
T
DDR2
1
INFINEON
Component Prefix
4
Memory Density
per I/O [Mbit];
Module Density1)
32
256 MByte
2
Interface Voltage [V] 18
64
512 MByte
3
DRAM Technology
128
1 GByte
4
256
2 GByte
Component Density 256
[Mbit]
512
0 .. 9
look up table
Table 23
DDR2 DIMM Nomenclature
Field Description
Values Coding
5
Raw Card
Generation
6
Number of Module 0, 2, 4
Ranks
1, 2, 4
7
Product Variations 0 .. 9
look up table
8
Package,
Lead-Free Status
A .. Z
look up table
Module Type
S
SO-DIMM
M
Micro-DIMM
R
Registered
U
Unbuffered
–3.7
PC2–4200 4–4–4
–5
PC2–3200 3–3–3
–A
First
–B
Second
9
10
11
Speed Grade
Die Revision
Data Sheet
DDR2 DRAM Nomenclature
5+6 Number of I/Os
HYB
Constant
SSTL1.8
T
DDR2
256 Mbit
512 Mbit
1G
1 Gbit
2G
2 Gbit
40
×4
80
×8
16
×16
7
Product Variations
0 .. 9
look up table
8
Die Revision
A
First
B
Second
C
FBGA,
lead-containing
F
FBGA, lead-free
–3.7
DDR2-533
–5
DDR2-400
9
10
11
47
Values Coding
Package,
Lead-Free Status
Speed Grade
N/A for Components
Rev. 0.91, 2004-06
09122003-FTXN-KM26
www.infineon.com
Published by Infineon Technologies AG

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