A1 PROs IMP5245 Lvd scsii termiinattor Datasheet

IMP52 45/46
DATA COMMUNICATIONS
LVD SCSI Terminator
– Ultra2/3 SCSI
– 9 Channels
– Eliminates External VREF Capacitor
The IMP5245/5246 ICs are Low Voltage Differential (LVD) terminators
designed to comply with the LVD termination specification in the SPI-2
document. The IMP5245/5246 are designed specifically for LVD applications. Because the IMP5245/5246 support only LVD, they have lower
output capacitance than multimode terminators.
Key Features
◆
◆
◆
◆
◆
◆
◆
◆
◆
2.5pF typical disabled output capacitance
Fast response
No external VREF capacitors required
5µA supply current in disconnect mode
20mA supply current during normal operation
Logic command disconnects all termination lines
Diffsense line driver
Current limit and thermal protection
Compatible with the pending SPI-2 LVD
specification
◆ Pin compatible to the UCC5640
The IMP5245/5246 deliver the ultimate in SCSI bus performance while
saving component cost and board area. Elimination of the external
capacitors also mitigates the need for a lengthy capacitor selection
process. The individual high bandwidth drivers also maximize channel
separation and reduces channel-to-channel noise and cross talk. The
high-bandwidth architecture insures ULTRA-2 performance, while providing a clear migration path to ULTRA-3 and beyond.
voltage differential device, the IMP5245/5246 output will
also be in a high-impedance state.
When the IMP5245/5246 are enabled, the differential sense (DIFFSENSE) pin supplies a voltage between 1.2V and 1.4V. The terminator
DIFFSENSE output is connected to the system DIFFSENSE line. If there
are no single ended or HVD devices attached to the system the LVD
output will be enabled. If the DIFFSENSE line is LOW, indicating a
single ended device, the IMP5245/5246 output will be in a highimpedance state. If the DIFFSENSE line is HIGH, indicating a high
The IMP5245/5246 ICs have a TTL compatible disconnect
pin. The IMP5245 is active LOW and the IMP5246 is active
HIGH. During sleep mode, power supply current is
reduced to just 5µA. During sleep mode all outputs are in
a high-impedance state. Also during sleep mode, the
DIFFSENSE function is disabled and is placed in a highimpedance state.
Block Diagram
DIFFSENSE
OUT
1.3V
DIFFB
DISC
R–
DISC (IMP5246)
(–)
VOS/2
VCM
1.25V
VOS/2
R+
(+)
5245/46_01.eps
© 2002 IMP, Inc.
408-432-9100/www.impweb.com
1
IMP52 45/46
Pin Configuration
TSSOP Package
24 VTERM
NC 1
1+ 2
23 9–
1– 3
22 9+
2+ 4
21 8–
2– 5
3+ 6
20 8+
IMP5245/46
19 7–
3– 7
18 7+
4+ 8
17 6–
4– 9
16 6+
DIFFB 10
15 5–
DIFFSENSE 11
14 5+
GND 12
13 DISC
5245/46_05.eps
Ordering Information
Part Number
Temperature Range
Package
IMP5245CPW
0°C to 70°C
24-Pin Plastic TSSOP
IMP5246CPW
0°C to 70°C
24-Pin Plastic TSSOP
Absolute Maximum Ratings1
TermPwr Voltage . . . . . . . . . . . . . . . . . . . . . . . . +6.5V
Signal Line Voltage . . . . . . . . . . . . . . . . . . . . . 0V to 6.5V
Differential Voltage . . . . . . . . . . . . . . . . . . . . . 0V to 6.5V
Operating Junction Temperature
Plastic (PW Package) . . . . . . . . . . . . . . . . . 150°C
Storage Temperature Range . . . . . . . . . . . . . . –65°C to 150°C
Lead Temperature (Soldering, 10 sec.) . . . . . . 300°C
Note:
1. Exceeding these ratings could cause damage to the device. All
voltages are with respect to Ground. Currents are positive
into, negative out of the specified terminal.
Thermal Data
PW Package:
Thermal Resistance Junction-to-Ambient, θJA . . . . . . 100°C/W
Junction Temperature Calculation: TJ = TA + (PD x θJA).
The θJA numbers are guidelines for the thermal performance of
the device/pc-board system. No ambient airflow is assumed.
2
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© 2002 IMP, Inc.
IMP52 45/46
Recommended Operating Conditions
Parameter
Symbol
Min
VTERM
3.0
0
0
0
Termpwr Voltage
Signal Line Voltage
Disconnect Input Voltage
Operating Junction Temperature Range — IMP5245/5246
Note:
Typ
Max
Units
5.25
5.0
VTERM
70
V
V
V
°C
2. Range over which the device is functional.
Electrical Characteristics
Unless otherwise specified, these specifications apply over the operating ambient temperature range of 0°C ≤ TA ≤ 70°C. TermPwr = 3.3V,
DISCONNECT: IMP5245 = LOW, IMP5246 = HIGH. Low duty cycle pulse testing techniques are used which maintains junction and case
temperatures equal to the ambient temperature.
Parameter
LVD Terminator Section
TermPwr Supply Current
Power Down Mode
Common Mode Voltage
Offset Voltage
Differential Terminator
Impedance
Common Mode Impedance
Output Capacitance
Output Leakage
Symbol Conditions
Typ
Max
Units
1.125
100
100
20
5
1.25
112
105
25
10
1.375
125
110
mA
µA
V
mV
Ω
200
2.5
300
Ω
pF
0
2
µA
All term lines = Open
DISCONNECT: IMP5245 = HIGH, IMP5246 = LOW
VOM
VOS
Mode Change Delay
DIFFSENSE Section
DIFFSENSE Output Voltage
DIFFSENSE Output Source
Current
DIFFSENSE Sink Current
DIFFSENSE Output Leakage
DISCONNECT Section
DISCONNECT Threshold
Input Current
Note:
Min
Open circuit between – and + (see Note 3)
VOD = –1V to 1V
0V to 2.5V
DISCONNECT: IMP5245 = HIGH, IMP5246 = LOW
DISCONNECT: IMP5245 = HIGH, IMP5246 = LOW,
VLINE = 0 to 4V, TA = 25°C
DISCONNECT: IMP5245 = HIGH, IMP5246 = LOW,
VTERM = 0V, VLINE = 2.7V
DIFFSENSE = 1.4V to 0V
100
100
DIFFSENSE = 0V
1.2
5.0
VIN = 2.75V
DISCONNECT: IMP5245 = HIGH, IMP5246 = LOW,
TA = 25°C
0.8
DISCONNECT: IMP5245 = 0V
DISCONNECT: IMP5246 = 3.3V
µA
ms
1
150
1.3
1.4
15.0
V
mA
200
10
µA
µA
2.0
10
10
V
µA
µA
3. Open circuit failsafe voltage.
© 2002 IMP, Inc.
408-432-9100/www.impweb.com
3
IMP52 45/46
Application Information
VOD = V(-) - V(+), Logic = 0
V(+)
NEGATED
VCM
100mV
0V
V(-)
-100mV
Figure 1. Bus Voltage
Figure 2. VOD
IMP5245/46
IMP5245/46
Figure 3.
Table 1. DIFFSENSE/Power Up/Power Down Function Table
IMP5245
DISCONNECT
IMP5246
DISCONNECT
DIFFSENS
Status
Type
Current
L
L
L
H
Open
H
H
H
L
Open
L < 0.5V
0.7V to 1.9V
H > 2.4V
X
X
Disable
Enable
Disable
Disable
Disable
HiZ
LVD
HiZ
HiZ
HiZ
2mA
21mA
2mA
10µA
10µA
Note:
4
Outputs
IMP5245 Disconnect logic is compatible with the Unitrode UCC5640.
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© 2002 IMP, Inc.
IMP52 45/46
Application Information
HOST
PERIPHERAL
5V
2.2µF
VT
Disconnect
DIFFSENSE
DIFFSENSE
DIFFB
DIFFB
DISC
IMP5245
DB(0)DB(0)+
DB(0)DB(0)+
DB(8)DB(8)+
DB(8)DB(8)+
VT
Disconnect
DISC
IMP5245
2.2µF
DIFFB VT
VT DIFFB
DISC
IMP5245
ATNATN+
ATNATN+
REQREQ+
REQREQ+
SCSI
CABLE
VT DIFFB
DISC
IMP5245
DISC
IMP5245
DIFFB VT
DB(9)DB(9)+
DB(9)DB(9)+
DB(15)DB(15)+
DB(15)DB(15)+
DISC
IMP5245
Figure 4. Application Schematic
IMP, Inc.
Corporate Headquarters
2830 N. First Street
San Jose, CA 95134-2071
Tel: 408-432-9100
Fax: 408-432-1085
e-mail: [email protected]
http://www.impweb.com
The IMP logo is a registered trademark of IMP, Inc.
All other company and product names are trademarks of their respective owners.
© 2002 IMP, Inc.
Printed in USA
Publication #: 7003
Revision:
B
Issue Date:
08/12/02
Type:
Preliminary
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