Panasonic MN3307 1024-stage ultra low voltage operation bbd for audio signal Datasheet

MN3300 Series
MN3307
1024-Stage Ultra Low Voltage Operation BBD for Audio Signals
■ Overview
■ Pin Assignment
The MN3307 is a 1024-stage ultra low voltage operation BBD
variable delay line in audio frequency range. The device operates on
+3 V supply and provides a signal delay up to 51.2 ms and is suitable
for use as reverberation effect of low voltage operation audio equipment such as portable stereo, radio cassette recorder and microphone.
■ Features
• Variable signal delay of the audio signal : 1.024 to 51.2 ms
• Wide range of supply voltage : 1.8 to 5.0 V
• No insertion loss : Li=0 dB typ.
• Wide dynamic range : S/N=69 dB typ.
• Low distortion : THD=0.6 % typ. (Vi=0.22 Vrms)
• Clock frequency range : 10 to 200 kHz (1.8 V≤VDD<4.0 V)
10 to 500 kHz (4.0 V≤VDD≤5.0 V)
• N-channel 2-layer silicon gate process
• 8-Pin Dual-In-Line Plastic Package
GND
1
CP2
2
8
VD2
7
OUT
MN3307
IN
3
6
CP1
VDD
4
5
VD1
DIP008-P-0300
6
VDD
CP2
1
1024-Stage
BBD
4
IN
3
8
7
5
VD2
OUT
VD1
GND
• Reverberation and echo effects of audio equipment such as radio
cassette recorder, car radio, portable radio, portable stereo, echo
microphone and Karaoke machine, etc.
• Sound effect of electronic musical instruments
• Variable or fixed delay of analog signals
2
CP1
■ Block Diagram
■ Applications
■ Pin Descriptions
Pin No. Symbol
Pin Name
Description
1
GND
Ground pin
Connected to ground.
2
CP2
Clock input 2
Basic clock pulse is applied to transfer electric charge of BBD.
3
IN
Signal input pin
Analog signal to be delayed is input. Most suitable DC bias should be applied to this pin.
4
VDD
VDD apply pin
Bias is applied to the gate of MOS transistor which is inserted in series with clock pulse
input gate of the BBD transfer gate.
Furthermore, voltage is supplied to step-up circuit.
5
VD1
VD1 apply pin
The same phase clock pulse as CP1 is applied through capacitor.
6
CP1
Clock input 1
Clock pulse of inverted phase to CP2 is applied.
7
OUT
Output pin
Composed signal of 1024th and 1025th stages is output.
8
VD2
VD2 apply pin
The same phase clock pulse as CP2 is applied through capacitor.
1
MN3307
MN3300 Series
■ Absolute Maximum Ratings Ta=25°C
Parameter
Symbol
Ratings
Unit
VDD, VD1, VD2, VCP, VI
− 0.3 to +6.0
V
Output voltage
VO
− 0.3 to +6.0
V
Operating ambient temperature
Topr
−20 to +60
°C
Storage temperature
Tstg
−55 to +125
°C
Pin voltage
■ Operating Conditions Ta=25°C
Parameter
Symbol
Conditions
min
typ
max
Unit
+1.8
+3.0
+5.0
V
Supply voltage
VDD
Clock voltage "H"level
VCPH
VDD
V
Clock voltage "L"level
VCPL
0
V
Clock input capacitance
CCP
700
pF
fCP
200(500)*1
kHz
Clock frequency
10
Clock pulse width
tw(CP)*3
0.5T*2
Clock rise time
tr(CP)*3
500
ns
Clock fall time
tf(CP)
*3
500
ns
Clock cross point
V X* 3
0.3VCPH
V
0
Note) *1 : ( ) : VDD=4.0 to 5.0 V
*2 : T=1/fCP (Clock period)
*3 : Clock pulse waveforms
CP2
tr(CP)
tf(CP)
3V
90%
50%
10%
tw(CP)
CP1
VX
T
■ Electrical Characteristics VDD=VCPH=3V, VCPL=0V, RL=56kΩ, LPF : fC=20kHz, Att=48dB/oct., Ta=25°C
Parameter
Symbol
Conditions
min
typ
max
Unit
Supply current
IDD
fCP=40 kHz
0.05
mA
Signal delay time 1
tD1
VDD=1.8 to 4.0 V, fCP=10 to 200 kHz
N*
ms
Signal delay time 2
tD2
VDD=4.0 to 5.0 V, fCP=10 to 500 kHz
2·fCP
Input signal frequency
fi
fCP=40 kHz, Vi=0.22 Vrms
Output attenuation≤3 dB(0 dB at fi=1 kHz)
Input signal amplitude
υi
fCP=40 kHz, fi=1 kHz, THD=2.5 %
0.31
−4
11
kHz
0.45
Vrms
Li
fCP=40 kHz, fi=1 kHz, Vi=0.22 Vrms
0
4
dB
THD
fCP=40 kHz, fi=1 kHz, Vi=0.22 Vrms
0.6
2.5
%
Output noise voltage
Vno
fCP=100 kHz, Weighted by "A"curve
0.15
0.25
mVrms
Signal to noise ratio
S/N
Insertion loss
Total harmonic distortion
69
dB
Note) * : N=BBD stages
■ Circuit Diagram
8 VD2
IN 3
1
2
3
1024
1025
7 OUT
GND 1
VDD 4
CP1 6
CP2 2
2
5 VD1
MN3300 Series
MN3307
■ Test Circuit
GND
47µF
10kΩB
C2
1µF
1
100kΩ
Signal
Generator
8
2
1µF
3
4
6
VCPH
(
(
C1
1µF
5
CP2
VDD
Low Pass Filter
fC=20 kHz
Att=48dB/oct.
1µF
7
MN3307
)
Output
CP1
Clock Pulse
fCP=40 kHz
Duty=50 %
)
■ Typical Characteristics
4
10
0
−20
2
−30
1
0
1
2
3
−40
−40
4
DC input voltage VI (V)
−30
−20
−10
Input signal level
Vno  fCP
−100
5
4
3
2
1
0
−20
10
Vno (dBm)
Insertion gain
−70
−60
fCP=100kHz
−2
Clock frequency
fCP (kHz)
5
−5
−10
−15
10kHz
80 100 120 140 160 180
0
0
0
−6
0.1
−5
Gi  Vi
−4
−50
−10
5
VDD=3V
Ta=25°C
Insertion gain Gi (dB)
Gi (dB)
−80
60
−15
Input signal level Vi (dBm)
Vi (dBm)
2
40
VDD=3V
fCP=40kHz
fi=1kHz
Ta=25°C
Gi  fi
VDD=3V
Ta=25°C
−40
20
0
4
−90
Output noise voltage
VDD=3V
fCP=40kHz
fi=1kHz
Ta=25°C
−10
3
0
THD  Vi
6
Total harmonic distortion
Output signal level Vo (dBm)
VO (V)
5
DC output voltage
Vo  Vi
20
VDD=3V
fCP=40kHz
Ta=25°C
THD (%)
VO  VI
6
0.3
1
3
40kHz
10
30
Input frequency fi (kHz)
100
−20
−20
−15
−10
−5
Input signal level
VDD=3V
fi=1kHz
fCP=40kHz
Ta=25°C
0
5
10
Vi (dBm)
3
MN3307
MN3300 Series
■ Typical Characteristics (To be continued)
Gi  fCP
THD  VBias
1
0
−1
−2
−3
−4
−5
1
3
10
30
Clock frequency
3
2
1
fCP (kHz)
1.2
1.4
fi (kHz)
40
60
2.0
−1
−2
−3
−5
−20
2.2
VBias (V)
0
20
30
20
10
0
20
40
60
80
VDD=3V
fi=1kHz
fCP=40kHz
Vi=0.22Vrms
0.8
0.6
0.4
0.2
−40 −20
80 100 120
Ambient temperature Ta (°C)
Ambient temperature Ta (°C)
60
THD  Ta
1.0
0
−40 −20
80 100 120
40
Ambient temperature Ta (°C)
VDD=3V
fCP=40kHz
Vo(fi)=Vo(1kHz)−3dB
−6
20
0
fi  Ta
−5
0
1.8
40
−4
−7
−40 −20
1.6
Input bias voltage
VDD=3V
fCP=40kHz
fi=1kHz
THD=2.5%
−3
1
−4
0
1.0
1000
Input frequency
Vi(max) (dBm)
300
4
Vi(max)  Ta
−2
Input signal level
100
VDD=3V
fi=1kHz
fCP=40kHz
2
Gi (dB)
2
5
Total harmonic distortion THD (%)
Insertion gain Gi (dB)
3
Gi  Ta
3
VDD=3V
fi=1kHz
fCP=40kHz
Vi=0.22Vrms
Ta=25°C
Insertion gain
VDD=3V
fi=1kHz
Ta=25°C
4
6
Total harmonic distortion THD (%)
5
0
20
40
60
Ambient temperature
80 100 120
Ta (°C)
■ Supply Voltage Characteristics
THD  VDD
VBias  VDD
3
2
1
0
2
4
6
Supply voltage VDD (V)
4
8
fCP=40kHz
fi=1kHz
Vi=Vi(max)−6dB
Ta=25°C
fCP=40kHz
Vo(fi)=Vo(1Hz)−3dB
Ta=25°C
18
3
Input frequency
THD (%)
4
Total harmonic distortion
Input bias voltage
VBias (V)
5
0
fi  VDD
20
4
Ta=25°C
fi (kHz)
6
2
1
16
14
12
10
0
8
0
2
4
6
Supply voltage VDD (V)
8
0
2
4
6
Supply voltage VDD (V)
8
MN3300 Series
MN3307
■ Supply Voltage Characteristics(To be continued)
Vi(max)  VDD
Gi  VDD
110
fCP=40kHz
fi=1kHz
Vi=Vi(max)−6dB
Ta=25°C
10
0
−10
Gi (dB)
3
2
0
Signal to noise ratio S/N (dB)
fCP=40kHz
fi=1kHz
THD=2.5%
Ta=25°C
Insertion gain
Vi(max) (dBm)
Input signal level
S/N  VDD
4
20
1
−1
−2
−3
−20
0
2
4
6
−4
8
0
2
4
6
Supply voltage VDD (V)
Supply voltage VDD (V)
100
90
80
70
60
50
8
Ta=25°C
0
2
4
6
8
Supply voltage VDD (V)
■ Package Dimensions (Unit : mm)
• DIP008-P-0300
9.6±0.4
5
1
4
3.45±0.30 4.8max.
0.7min.
3.3±0.2
6.4±0.2
8
2.54
0.5±0.1
1.3±0.1
0 to 15˚
7.62±0.20
+0.20
.05
0.25 –0
SEATING PLANE
5
Similar pages