Holtek HT47C20-1 R-f type 8-bit mcu Datasheet

HT47R20A-1/HT47C20-1
R-F Type 8-Bit MCU
Technical Document
· Tools Information
· FAQs
· Application Note
- HA0029E Using the Time Base Function in the HT47R20A-1
- HA0030E Using the RTC in the HT47R20A-1
- HA0034E Using the Buzzer Function in the HT47R20A-1
- HA0036E Using the PFD Function in the HT47R20A-1
- HA0045E Distinguishing between the Different Devices in the HT47 MCU Series
Features
· Operating voltage: 2.2V~5.5V
· One low voltage reset circuit
· Eight bidirectional I/O lines
· One buzzer output
· Four input lines
· HALT function and wake-up feature reduce power
consumption
· One interrupt input
· LCD bias C type or R type
· One 16-bit programmable timer/event counter with
· One LCD driver with 20´2, 20´3 or 19´4 segments
PFD (programmable frequency divider) function
· On-chip crystal and RC oscillator for system clock
· One IR carrier output
· One 32.768kHz crystal oscillator for real time clock or
· Two channels RC type A/D converter
system clock
· Four-level subroutine nesting
· Watchdog Timer
· Bit manipulation instruction
· 2K´16 program memory
· 16-bit table read instruction
· 64´8 data memory RAM
· Up to 1ms instruction cycle with 4MHz system clock
· One Real Time Clock (RTC)
· All instructions in one or two machine cycles
· One 8-bit prescaler for RTC
· 63 powerful instructions
· One low voltage detector
· 64-pin QFP package
General Description
The HT47R20A-1/HT47C20-1 are 8-bit, high performance, RISC architecture microcontroller devices specifically designed for applications that interface directly
to analog signals, such as those from sensors. The
mask version HT47C20-1 is fully pin and functionally
compatible with the OTP version HT47R20A-1 device.
Rev. 1.70
The advantages of low power consumption, I/O flexibility, programmable frequency divider, timer functions,
oscillator options, 2-channel RC type A/D Converter,
LCD driver, HALT and wake-up functions, enhance the
versatility of these devices to suit a wide range of Resistor to Frequency application possibilities such as sensor
signal processing, remote metering, industrial control,
consumer products, subsystem controllers, etc.
1
June 14, 2005
HT47R20A-1/HT47C20-1
Block Diagram
P B 0 /IN T
S y s te m
M
In te rru p t
C ir c u it
P ro g ra m
E P R O M
IN T C
C 1
C 2
X
A /D
S
D
S
C O M 0 ~
C O M 2
C O M 3 /
S E G 1 9
1
0
1
0
T 0
1
U
R T C O S C
X
O S C 3
O S C 4
P B 0 /IN T
P B 2 /T M R
P B 3
L C D D r iv e r
L C D
0
P B 1
P B
P o rt A
P A
V 1 V 2 V
IN 0
C S
R S
C R
R T
IN 1
C S
R S
R T
W D T O S C
P o rt B
L C D
M e m o ry
H a lv e
V o lta g e
M
T im e B a s e
B P
C lo c k
S Y S C L K /4
W D T
A C C
P A 3 /P F D
T y p e
C o n v e rte r
R T C
S h ifte r
C 1
C 3
P F D
A /D
R C
D A T A
M e m o ry
S T A T U S
A L U
T im in g
G e n e ra to r
O S
O S
R E
V D
V S
U
R T C O u tp u t
P B 2 /T M R
X
T im e r B
M U X
In s tr u c tio n
D e c o d e r
O S C 2
O S C 4
M
M P
U
O v e r flo w
S T A C K
P ro g ra m
C o u n te r
In s tr u c tio n
R e g is te r
T im e r A
C lo c k
T 1
S E G 0 ~
S E G 1 8
H A L T
P A 0
P A 1
P A 2
P A 3
P A 4
/B
/B
/IR
/P
~ P
Z
Z
F D
A 7
E N /D IS
L V D /L V R
Rev. 1.70
2
June 14, 2005
HT47R20A-1/HT47C20-1
Pin Assignment
V 2
V L C D
V 1
C 2
C 1
O S C 4
O S C 3
V D D
O S C 2
O S C 1
R E S
N C
N C
6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2
P A 0 /B Z
1
5 1
S E G 0
P A 1 /B Z
2
5 0
S E G 1
P A 2 /IR
3
4 9
S E G 2
P A 3 /P F D
4
4 8
S E G 3
P A 4
5
4 7
S E G 4
P A 5
6
4 6
S E G 5
P A 6
7
4 5
S E G 6
P A 7
8
4 4
S E G 7
P B 0 /IN T
9
4 3
S E G 8
4 2
S E G 9
4 1
S E G 1 0
H T 4 7 R 2 0 A -1 /H T 4 7 C 2 0 -1
6 4 Q F P -A
P B 1
1 0
P B 2 /T M R
1 1
P B 3
1 2
4 0
S E G 1 1
N C
1 3
3 9
S E G 1 2
N C
1 4
3 8
S E G 1 3
N C
1 5
3 7
S E G 1 4
N C
1 6
3 6
S E G 1 5
N C
1 7
3 5
S E G 1 6
N C
1 8
3 4
S E G 1 7
V S S
1 9
3 3
S E G 1 8
2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2
C O M 3 /S E G 1 9
C O M 2
C O M 1
C O M 0
IN 0
C S 0
R S 0
C R T 0
R T 0
IN 1
C S 1
R S 1
R T 1
Pad Description
Pad Name
I/O
Option
Function
PA0/BZ
PA1/BZ
PA2/IR
PA3/PFD
PA4~PA7
I/O
Wake-up
Pull-high
or None
CMOS or
NMOS
Bidirectional 8-bit input/output port. The low nibble of the PA can be configured
as CMOS output or NMOS output with or without pull-high resistors (determined
by pull-high option). NMOS output can be configured as Schmitt trigger input with
or without pull-high resistors. Each bit of NMOS output can be configured as
wake up input by options. Of the eight bits, PA0~PA1 can be set as I/O pins or
buzzer outputs by options. PA2 can be set as an I/O pin or an IR carrier output
also by options. PA3 can be set as an I/O pin or a PFD output also by options.
PB0/INT
PB1
PB2/TMR
PB3
I
¾
4-bit Schmitt trigger input port. The PB is configured with pull-high resistors. Of
the four bits, PB0 can be set as an input pin or an external interrupt input pin (INT)
by software application. While PB2 can be set as an input pin or a timer/event
counter input pin also by software application.
¾
Oscillation input pin of channel 0
Reference capacitor connection pin of channel 0
Reference resistor connection pin of channel 0
Resistor/capacitor sensor connection pin for measurement of channel 0
Resistor sensor connection pin for measurement of channel 0
¾
Oscillation input pin of channel 1
Reference capacitor connection pin of channel 1
Reference resistor connection pin of channel 1
Resistor sensor connection pin for measurement of channel 1
IN0
CS0
RS0
CRT0
RT0
I
O
O
O
O
IN1
CS1
RS1
RT1
I
O
O
O
COM0~COM2
COM3/SEG19
O
SEG0~SEG18
O
Rev. 1.70
1/2, 1/3 or SEG19/COM3 can be set as segment or common output driver for LCD panel by
1/4 Duty options. COM0~COM2 are outputs for LCD panel plate.
¾
LCD driver outputs for LCD panel segments
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June 14, 2005
HT47R20A-1/HT47C20-1
Pad Name
I/O
Option
V1, V2, C1, C2
¾
¾
Voltage pump
VLCD
I
¾
LCD power supply
OSC2
OSC1
O
I
Crystal or
RC
OSC1 and OSC2 are connected to an RC network or a crystal (by options) for the internal system clock.
OSC4
OSC3
O
I
RTC or
System
Clock
Real time clock oscillators
OSC3 and OSC4 are connected to a 32768Hz crystal oscillator for timing purposes or to a system clock source (depending on the options).
RES
I
¾
Schmitt trigger reset input. Active low.
VSS
¾
¾
Negative power supply, ground
VDD
¾
¾
Positive power supply
I
¾
Test mode input pin it disconnects in normal operation.
TEST1~3
Function
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V
Storage Temperature ............................-50°C to 125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V
Operating Temperature...........................-40°C to 85°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
fSYS=4MHz
2.2
¾
5.5
V
fSYS=8MHz
3.3
¾
5.5
V
¾
0.7
1.5
mA
¾
1.7
3
mA
¾
0.7
1.5
mA
¾
1.7
3
mA
¾
4
8
mA
¾
0.25
0.5
mA
¾
0.8
1.5
mA
¾
¾
1
mA
¾
¾
2
mA
¾
2.5
5
mA
¾
10
20
mA
¾
2
5
mA
¾
6
10
mA
¾
17
30
mA
¾
34
60
mA
Conditions
VDD
VDD
IDD1
IDD2
Operating Voltage
¾
Operating Current
(Crystal OSC)
3V
Operating Current
(RC OSC)
3V
5V
Operating Current
(Crystal OSC, RC OSC)
IDD4
Operating Current
(fSYS=32768Hz)
3V
Standby Current
(*fS=T1)
3V
Standby Current
(*fS=32.768kHz OSC)
3V
Standby Current
(*fS=WDT RC OSC)
3V
Standby Current
(*fS=32.768kHz OSC)
3V
ISTB2
ISTB3
ISTB4
Rev. 1.70
No load, fSYS=4MHz
5V
IDD3
ISTB1
No load, fSYS=4MHz
5V
No load, fSYS=8MHz
No load
5V
5V
5V
5V
5V
No load, system HALT,
LCD off at HALT
No load, system HALT,
LCD On at HALT, C type
No load, system HALT
LCD On at HALT, C type
No load, system HALT,
LCD on at HALT, R type,
1/2 bias
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June 14, 2005
HT47R20A-1/HT47C20-1
Test Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
No load, system HALT,
LCD on at HALT, R type,
1/3 bias
¾
13
25
mA
¾
28
50
mA
No load, system HALT,
LCD on at HALT, R type,
1/2 bias
¾
14
25
mA
¾
26
50
mA
¾
10
20
mA
5V
No load, system HALT,
LCD on at HALT, R type,
1/3 bias
¾
19
40
mA
Input Low Voltage for I/O Ports,
TMR and INT
¾
¾
0
¾
0.3VDD
V
Input High Voltage for I/O Ports,
TMR and INT
3V
0.7VDD
¾
VDD
V
0.7VDD
¾
VDD
V
VIL2
Input Low Voltage (RES)
¾
¾
0
¾
0.4VDD
V
VIH2
Input High Voltage (RES)
¾
¾
0.9VDD
¾
VDD
V
IOL1
6
12
¾
mA
I/O Port Sink Current
10
25
¾
mA
-2
-4
¾
mA
-5
-8
¾
mA
210
420
¾
mA
350
700
¾
mA
-80
-160
¾
mA
-180
-360
¾
mA
VDD
Conditions
Standby Current
(*fS=32.768kHz OSC)
3V
Standby Current
(*fS=WDT RC OSC)
3V
Standby Current
(*fS=WDT RC OSC)
3V
VIL1
VIH1
ISTB5
ISTB6
ISTB7
5V
5V
¾
5V
3V
VOL=0.1VDD
5V
3V
IOH1
I/O Port Source Current
VOH=0.9VDD
5V
LCD Common and Segment
Current
3V
LCD Common and Segment
Current
3V
IOL3
RC Oscillation Output Sink Current
3V
VOL=0.3V
5
10
¾
mA
IOH3
RC Oscillation Output Source
Current
3V
VOH=2.7V
-5
-10
¾
mA
RPH
Pull-high Resistance of I/O Ports
and INT0, INT1
3V
20
60
100
kW
10
30
50
kW
VLVR
Low Voltage Reset
¾
2.5
3.2
3.6
V
VLVD
Low Voltage Detector Voltage
¾
3.0
3.3
3.6
V
IOL2
IOH2
Note:
VOL=0.1VDD
5V
VOH=0.9VDD
5V
¾
5V
¾
²*² tSYS= 1/fSYS
²**² for power on protection
Rev. 1.70
5
June 14, 2005
HT47R20A-1/HT47C20-1
A.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
fSYS1
fSYS2
System Clock
(Crystal OSC)
System Clock
(RC OSC)
Min.
Typ.
Max.
Unit
Conditions
VDD
¾
2.2V~5.5V
400
¾
4000
kHz
¾
3.3V~5.5V
400
¾
8000
kHz
¾
2.2V~5.5V
400
¾
4000
kHz
¾
3.3V~5.5V
400
¾
8000
kHz
fSYS3
System Clock
(32768Hz Crystal OSC)
¾
¾
¾
32768
¾
Hz
fRTCOSC
RTC Frequency
¾
¾
¾
32768
¾
Hz
fTIMER
Timer I/P Frequency
tWDTOSC
¾
2.2V~5.5V
0
¾
4000
kHz
¾
3.3V~5.5V
0
¾
8000
kHz
3V
¾
45
90
180
ms
5V
¾
35
65
130
ms
Watchdog Oscillator Period
tRES
External Reset Low Pulse Width
¾
¾
1
¾
¾
ms
tSST
System Start-up Timer Period
¾
Wake-up from HALT
¾
1024
¾
tSYS
tINT
Interrupt Pulse Width
¾
¾
1
¾
¾
ms
Rev. 1.70
6
June 14, 2005
HT47R20A-1/HT47C20-1
Functional Description
Execution Flow
incremented by 1. The program counter then points to
the memory word containing the next instruction code.
The system clock for the HT47R20A-1/HT47C20-1 is
derived from either a crystal or an RC oscillator. The
system clock is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles.
When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call or return
from subroutine, initial reset, internal interrupt, external
interrupt or return from interrupt, the PC manipulates the
program transfer by loading the address corresponding
to each instruction.
Instruction fetching and execution are pipelined in such
a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruction to effectively execute in one cycle. If an instruction
changes the program counter, two cycles are required to
complete the instruction.
The conditional skip is activated by instruction. Once the
condition is met, the next instruction, fetched during the
current instruction execution, is discarded and a dummy
cycle replaces it to get the proper instruction. Otherwise
proceed with the next instruction.
The lower byte of the program counter (PCL) is a readable and writeable register (06H). Moving data into the
PCL performs a short jump. The destination will be
within 256 locations.
Program Counter - PC
The 11-bit program counter (PC) controls the sequence
in which the instructions stored in the program memory
are executed and its contents specify a maximum of
2048 addresses.
When a control transfer takes place, an additional
dummy cycle is required.
After accessing a program memory word to fetch an instruction code, the contents of the program counter are
S y s te m
C lo c k
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
In s tr u c tio n C lo c k
P C
P C
P C + 1
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
P C + 2
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution Flow
Mode
Program Counter
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial reset
0
0
0
0
0
0
0
0
0
0
0
External interrupt
0
0
0
0
0
0
0
0
1
0
0
Time base interrupt
0
0
0
0
0
0
0
1
0
0
0
RTC interrupt
0
0
0
0
0
0
0
1
1
0
0
Timer/event counter interrupt
0
0
0
0
0
0
1
0
0
0
0
Skip
Program Counter + 2
Loading PCL
*10
*9
*8
@7
@6
@5
@4
@3
@2
@1
@0
Jump, call branch
#10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from subroutine
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program Counter
Note:
*10~*0: Program counter bits
S10~S0: Stack register bits
Rev. 1.70
#10~#0: Instruction code bits
@7~@0: PCL bits
7
June 14, 2005
HT47R20A-1/HT47C20-1
Program Memory - EPROM
0 0 0 H
The program memory is used to store the program instructions which are to be executed. It also contains
data, table, and interrupt entries, and is organized into
2048´16 bits, addressed by the program counter and table pointer.
0 0 4 H
D e v ic e in itia liz a tio n p r o g r a m
E x te r n a l in te r r u p t s u b r o u tin e
0 0 8 H
T im e b a s e in te r r u p t s u b r o u tin e
0 0 C H
R T C in te r r u p t s u b r o u tin e
0 1 0 H
n 0 0 H
· Location 000H
L o o k - u p ta b le ( 2 5 6 w o r d s )
n F F H
This area is reserved for the initialization program. After chip reset, the program always begins execution at
location 000H.
· Location 004H
L o o k - u p ta b le ( 2 5 6 w o r d s )
7 F F H
This area is reserved for the external interrupt service
program. If the INT interrupt is enabled and the stack
is not full, the program begins execution at location
004H.
P ro g ra m
M e m o ry
T im e r /e v e n t c o u n te r in te r r u p t s u b r o u tin e
Certain locations in the program memory are reserved
for special usage
1 6 b its
N o te : n ra n g e s fro m
0 to 7
Program Memory
· Location 008H
the table, the location must be placed in TBLP. The
TBLH is read only and cannot be restored. If the main
routine and the ISR (Interrupt Service Routine) both
employ the table read instruction, the contents of the
TBLH in the main routine are likely to be changed by
the table read instruction used in the ISR. Errors can
occur. In other words, using the table read instruction
in the main routine and the ISR simultaneously should
be avoided. However, if the table read instruction has
to be applied in both the main routine and the ISR, the
interrupt is supposed to be disabled prior to the table
read instruction. It will not be enabled until the TBLH
has been backed up. All table related instructions
need two cycles to complete the operation. These areas may function as normal program memory depending upon the requirements.
This area is reserved for the time base interrupt service program. If time base interrupt results from a time
base overflow, and if the interrupt is enabled and the
stack is not full, the program begins execution at location 008H.
· Location 00CH
This area is reserved for the real time clock interrupt
service program. If a real time clock interrupt results
from a real time clock overflow, and if the interrupt is
enabled and the stack is not full, the program begins
execution at location 00CH.
· Location 010H
This area is reserved for the timer/event counter interrupt service program. If a timer interrupt results from a
timer/event counter A or B overflow, and if the interrupt
is enabled and the stack is not full, the program begins
execution at location 010H.
Stack Register - STACK
This is a special part of the memory which is used to
save the contents of the program counter (PC) only. The
stack is organized into four levels and is neither part of
the data nor part of the program space, and is neither
readable nor writeable. The activated level is indexed by
the stack pointer (SP) and is neither readable nor
writeable. At a subroutine call or interrupt acknowledgment, the contents of the program counter are pushed
onto the stack. At the end of a subroutine or an interrupt
routine, signaled by a return instruction (RET or RETI),
the program counter is restored to its previous value
· Table location
Any location in the ROM space can be used as look up
tables. The instructions TABRDC [m] (the current
page, one page=256 words) and TABRDL [m] (the last
page) transfer the contents of the lower-order byte to
the specified data memory, and the higher-order byte
to TBLH (08H). Only the destination of the lower-order
byte in the table is well-defined, the higher-order byte
of the table word are transferred to the TBLH. The table higher-order byte register (TBLH) is read only. The
table pointer (TBLP) is a read/write register (07H),
which indicates the table location. Before accessing
Table Location
Instruction(s)
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P10
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note:
*10~*0: Table location bits
P10~P8: Current program counter bits
Rev. 1.70
@7~@0: Table pointer bits
8
June 14, 2005
HT47R20A-1/HT47C20-1
from the stack. After a chip reset, the SP will point to the
top of the stack.
0 0 H
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledgment will be inhibited. When the stack
pointer is decremented (by RET or RETI), the interrupt
will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily.
In a similar case, if the stack is full and a ²CALL² is subsequently executed, stack overflow occurs and the first
entry will be lost (only the most recent four return addresses are stored).
M P 0
0 2 H
In d ir e c t A d d r e s s in g R e g is te r 1
0 3 H
M P 1
0 4 H
B P
0 5 H
A C C
0 6 H
P C L
T B L P
0 7 H
0 8 H
T B L H
0 9 H
R T C C
0 A H
S T A T U S
0 B H
IN T C 0
0 C H
0 D H
Data Memory - RAM
0 E H
S p e c ia l P u r p o s e
D a ta M e m o ry
0 F H
The data memory is designed with 85´8 bits. The data
memory and is divided into two functional groups: special function registers and general purpose data memory (64´8). Most are read/write, but some are read only.
1 0 H
1 1 H
1 2 H
P A
1 3 H
1 4 H
The special function registers include the indirect addressing register 0 (00H), the memory pointer register 0
(mp0; 01H), the indirect addressing register 1 (02H), the
memory pointer register 1 (MP1;03H), the bank pointer
(BP;04H), the accumulator (ACC;05H), the program
counter lower-order byte register (PCL;06H), the table
pointer (TBLP;07H), the table higher-order byte register
(TBLH;08H), the real time clock control register
(RTCC;09H), the status register (STATUS;0AH), the interrupt control register 0 (INTC0;0BH), the I/O registers
(PA;12H, PB;14H), the interrupt control register 1
(INTC1;1EH), the timer/event counter A higher order byte
register (TMRAH;20H), the timer/event counter A lower order byte register (TMRAL;21H), the timer/event counter
control register (TMRC;22H), the timer/event counter B
higher order byte register (TMRBH;23H), the timer/event
counter B lower order byte register (TMRBL;24H), and the
RC oscillator type A/D converter control register (ADCR;
25H). The remaining space before the 40H are reserved
for future expanded usage and reading these location
will return the result 00H. The general purpose data
memory, addressed from 40H to 7FH, is used for data
and control information under instruction command.
P B
1 5 H
1 6 H
1 7 H
1 8 H
1 9 H
1 A H
1 B H
1 C H
1 D H
1 E H
IN T C 1
1 F H
2 0 H
T M R A H
2 1 H
T M R A L
2 2 H
T M R C
2 3 H
T M R B H
2 4 H
T M R B L
2 5 H
A D C R
: U n u s e d
R e a d a s "0 0 "
2 6 H
4 0 H
G e n e ra l P u rp o s e
D a ta M e m o ry
(6 4 B y te s )
7 F H
All data memory areas can handle arithmetic, logic, increment, decrement and rotate operations. Except for
some dedicated bits, each bit in the data memory can be
set and reset by the SET [m].i and CLR [m].i instruction,
respectively. They are also indirectly accessible through
memory pointer registers (MP0;01H, MP1;03H).
Rev. 1.70
In d ir e c t A d d r e s s in g R e g is te r 0
0 1 H
RAM Mapping (Bank 0)
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June 14, 2005
HT47R20A-1/HT47C20-1
Indirect Addressing Register
Status Register - STATUS
Location 00H and 02H are indirect addressing registers
that are not physically implemented. Any read/write operation of [00H] and [02H] access data memory pointed
to by MP0 (01H) and MP1 (03H) respectively. Reading
location 00H or 02H indirectly will return the result 00H.
Writing indirectly results in no operation.
This 8-bit register (0AH) contains the zero flag (Z), carry
flag (C), auxiliary carry flag (AC), overflow flag (OV),
power down flag (PDF) and watchdog time-out flag
(TO). It also records the status information and controls
the operation sequence.
Only MP0 can be applied to data memory, while MP1
can be applied to data memory and LCD display memory.
With the exception of the TO and flags, bits in the status
register can be altered by instructions like most other
registers. Any data written into the status register will not
change the TO or PDF flags. In addition it should be
noted that operations related to the status register may
give different results from those intended. The TO and
PDF flags can only be changed by the Watchdog Timer
overflow, system power-up, clearing the Watchdog
Timer and executing the HALT instruction.
Accumulator
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
The function of data movement between two indirect addressing registers are not supported. The memory
pointer registers, MP0 and MP1, are both 8-bit registers
which can be used to access the data memory by combining corresponding indirect addressing registers.
The accumulator is closely related to ALU operations. It
is also mapped to location 05H of the data memory and
is capable of carrying out immediate data operations.
The data movement between two data memory locations must pass through the accumulator.
In addition, on entering the interrupt sequence or executing the subroutine call, the status register will not be
pushed onto the stack automatically. If the contents of
the status are important and if the subroutine can corrupt the status register, precautions must be taken to
save it properly.
Arithmetic and Logic Unit - ALU
Interrupts
This circuit performs 8-bit arithmetic and logic operation.
The ALU provides the following functions:
The HT47R20A-1/HT47C20-1 provides an external interrupt, an internal timer/event counter interrupt, an internal time base interrupt, and an internal real time clock
interrupt. The interrupt control register 0 (INTC0;0BH)
and interrupt control register 1 (INTC1;1EH) both contain the interrupt control bits to set the enable or disable
and interrupt request flags.
· Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
· Logic operations (AND, OR, XOR, CPL)
· Rotation (RL, RR, RLC, RRC)
· Increment and Decrement (INC, DEC)
· Branch decision (SZ, SNZ, SIZ, SDZ ....)
The ALU not only saves the results of a data operation
but can change the status register.
Bit No.
Label
Function
0
C
C is set if the operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction.
1
AC
AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
2
Z
3
OV
OV is set if the operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
4
PDF
PDF is cleared when either a system power-up or executing the CLR WDT instruction. PDF
is set by executing the HALT instruction.
5
TO
TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is
set by a WDT time-out.
6, 7
¾
Unused bit, read as ²0²
Z is set if the result of an arithmetic or logic operation is 0; otherwise Z is cleared.
STATUS (0AH) Register
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HT47R20A-1/HT47C20-1
Bit No.
Label
0
EMI
Control the master (global) interrupt (1= enabled; 0= disabled)
Function
1
EEI
Control the external interrupt (1= enabled; 0= disabled)
2
ETBI
Control the time base interrupt (1= enabled; 0= disabled)
3
ERTI
Control the real time clock interrupt (1= enabled; 0= disabled)
4
EIF
External interrupt request flag (1= active; 0= inactive)
5
TBF
Time base request flag (1= active; 0= inactive)
6
RTF
Real time clock request flag (1= active; 0= inactive)
7
¾
Unused bit, read as ²0²
INTC0 (0BH) Register
Bit No.
Label
Function
0
ETI
Control the timer/event counter interrupt (1= enabled; 0=disabled)
1~3
¾
Unused bit, read as ²0²
4
TF
Internal timer/event counter request flag (1= active; 0= inactive)
5~7
¾
Unused bit, read as ²0²
INTC1 (1EH) Register
Once an interrupt subroutine is serviced, all other interrupts will be blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting.
Other interrupt requests may happen during this interval, but only the interrupt request flag is recorded. If a
certain interrupt needs servicing within the service routine, the EMI bit and the corresponding bit of INTC0 or
INTC1 may be set allow interrupt nesting. If the stack is
full, the interrupt request will not be acknowledged,
even if the related interrupt is enabled, until the SP is
decremented. If immediate service is desired, the stack
must be prevented from becoming full.
full and the TF bit is set, a subroutine call to location 10H
will occur. The related interrupt request flag (TF) will be
reset and the EMI bit cleared to disable further interrupts.
The time base interrupt is initialized by setting the time
base interrupt request flag (TBF; bit 5 of INTC0), caused
by a regular time base signal. When the interrupt is enabled, and the stack is not full and the TBF bit is set, a
subroutine call to location 08H will occur. The related interrupt request flag (TBF) will be reset and the EMI bit
cleared to disable further interrupts.
The real time clock interrupt is initialized by setting the
real time clock interrupt request flag (RTF; bit 6 of
INTC0), caused by a regular real time clock signal.
When the interrupt is enabled, and the stack is not full
and the RTF bit is set, a subroutine call to location 0CH
will occur. The related interrupt request flag (RTF) will be
reset and the EMI bit cleared to disable further interrupts.
All these kinds of interrupt have a wake-up capability.
As an interrupt is serviced, a control transfer occurs by
pushing the program counter onto the stack and then by
branching to subroutines at specified location(s) in the
program memory. Only the program counter is pushed
onto the stack. If the contents of the register and status
register (STATUS) is altered by the interrupt service
program which corrupts the desired control sequence,
the contents must be saved first.
During the execution of an interrupt subroutine, other interrupt acknowledgments are held until the RETI instruction is executed or the EMI bit and the related interrupt
control bit are set to 1 (if the stack is not full). To return
from the interrupt subroutine, RET or RETI instruction
may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET does not.
External interrupt is triggered by a high to low transition
of INT and the related interrupt request flag (EIF; bit 4 of
INTC0) will be set. When the interrupt is enabled, and
the stack is not full and the external interrupt is active, a
subroutine call to location 04H will occur. The interrupt
request flag (EIF) and EMI bits will be cleared to disable
other interrupts.
Interrupts occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
The internal timer/event counter interrupt is initialized
by setting the timer/event counter interrupt request flag
(TF; bit 4 of INTC1), caused by a timer A or timer B overflow. When the interrupt is enabled, and the stack is not
Rev. 1.70
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June 14, 2005
HT47R20A-1/HT47C20-1
Priority
Vector
External interrupt
Interrupt Source
1
04H
Time base interrupt
2
08H
Real time clock interrupt
3
0CH
Timer/event counter interrupt
4
10H
(RTC, time base, WDT) operation still runs even if the
system enters the HALT mode.
Of the three oscillators, if the RC oscillator is used, an
external resistor between OSC1 and is required, and
the range of the resistance should be from 24kW to
1MW. The system clock, divided by 4, is available on
OSC2 with pull-high resistor, which can be used to synchronize external logic. The RC oscillator provides the
most cost effective solution. However, the frequency of
the oscillation may vary with VDD, temperature, and the
chip itself due to process variations. It is therefore, not
suitable for timing sensitive operations where accurate
oscillator frequency is desired.
The external interrupt request flag (EIF), real time clock
interrupt request flag (RTF), time base interrupt request
flag (TBF), enable external interrupt bit (EEI), enable
real time clock interrupt bit (ERTI), enable time base interrupt bit (ETBI), and enable master interrupt bit (EMI)
constitute an interrupt control register 0 (INTC0) which
is located at 0BH in the data memory. The timer/event
counter interrupt request flag (TF), enable timer/event
counter interrupt bit (ETI) on the other hand, constitute
an interrupt control register 1 (INTC1) which is located
at 1EH in the data memory. EMI, EEI, ETI, ETBI, and
ERTI are used to control the enabling/disabling of interrupts. These bits prevent the requested interrupt being
serviced. Once the interrupt request flags (RTF, TBF,
TF, EIF) are set, they remain in the INTC1 or INTC0 respectively until the interrupts are serviced or cleared by
a software instruction.
On the other hand, if the crystal oscillator is selected, a
crystal across OSC1 and OSC2 is needed to provide the
feedback and phase shift required for the oscillator, and
no other external components are required. A resonator
may be connected between OSC1 and OSC2 to replace
the crystal and to get a frequency reference, but two external capacitors in OSC1 and OSC2 are required.
There is another oscillator circuit designed for the real
time clock. In this case, only the 32.768kHz crystal oscillator can be applied. The crystal should be connected
between OSC3 and OSC4.
It is recommended that a program does not use the
²CALL subroutine² within the interrupt subroutine. Because interrupts often occur in an unpredictable manner
or need to be serviced immediately in some applications, if only one stack is left, and enabling the interrupt
is not well controlled, once the ²CALL subroutine² operates in the interrupt subroutine will damage the original
control sequence.
The RTC oscillator circuit can be controlled to oscillate
quickly by setting the QOSC bit (bit 4 of RTCC). It is recommended to turn on the quick oscillating function upon
power on, and then turn it off after 2 seconds.
The oscillator is a free running on-chip RC oscillator,
and no external components are required. Although the
system enters the power down mode, the system clock
stops, and the WDT oscillator still works with a period of
approximately 90ms@3V. The WDT oscillator can be
disabled by options to conserve power.
Oscillator Configuration
The HT47R20A-1/HT47C20-1 provides three oscillator
circuits for system clocks, i.e., RC oscillator, crystal oscillator and 32768Hz crystal oscillator, determined by
options. No matter what type of oscillator is selected, the
signal is used for the system clock. The HALT mode
stops the system oscillator (RC and crystal oscillator
only) and ignores external signal to conserve power.
The 32768Hz crystal oscillator (system oscillator) still
runs at HALT mode. If the 32768Hz crystal oscillator is
selected as the system oscillator, the system oscillator is
not stopped; but the instruction execution is stopped.
Since the (used as system oscillator or RTC oscillator)
is also designed for timing purposes, the internal timing
Watchdog Timer - WDT
The clock source of the WDT (fS) is implemented by a
dedicated RC oscillator (WDT oscillator) or a instruction
clock (system clock divided by 4) or a real time clock oscillator (RTC oscillator), decided by options. The timer is
designed to prevent a software malfunction or sequence
jumping to an unknown location with unpredictable results. The Watchdog Timer can be disabled by options.
If the Watchdog Timer is disabled, all the executions related to the WDT result in no operation.
O S C 3
O S C 1
O S C 4
O S C 2
3 2 7 6 8 H z C r y s ta l/
R T C O s c illa to r
C r y s ta l O s c illa to r
O S C 1
fS
Y S
/4
O S C 2 : fS
O S C 2
Y S
/4 N M O S o p e n d r a in
System Oscillator
Rev. 1.70
12
June 14, 2005
HT47R20A-1/HT47C20-1
S y s te m
C lo c k /4
R T C
O S C 3 2 7 6 8 H z
R O M C o d e
O p tio n
S e le c tio n
fS
fS /2
D iv id e r
8
C K
P r e s c a le r
W D T
1 2 k H z
O S C
T
C K
R
T
T im e - o u t R e s e t
fS /2 1 5 ~ fS /2 1 6
R
W D T C le a r
Watchdog Timer
fS
fS /2
D iv id e r
R O M
8
P r e s c a le r
L C D D r iv e r f S /2
C o d e O p tio n
B u z z e r
fS /2 2 ~ fS /2
2
~ fS /2
8
9
T im e B a s e In te r r u p t
1 5
1 2
fS /2 ~ fS /2
Time Base
sists of a 8-stage divider and an 7-bit prescaler, with the
clock source coming from WDT OSC or RTC OSC or the
instruction clock (i.e., system clock divided by 4). The
multi-function timer also provides a selectable frequency signal (ranges from fS/22 to fS/28) for LCD driver
circuits, and a selectable frequency signal (ranges from
fS/22 to fS/29) for buzzer output by options. It is recommended to select a 4kHz signal for LCD driver circuits
for proper display.
If the clock source of WDT chooses the internal WDT
oscillator, the time-out period may vary with temperature, VDD, and process variations. On the other hand, if
the clock source selects the instruction clock and the
²HALT² instruction is executed, WDT may stop counting and lose its protecting purpose, and the logic can
only be restarted by external logic.
When the device operates in a noisy environment, using
the on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT can cease the system clock.
Time Base
The WDT overflow under normal operation will initialize
²chip reset² and set the status bit TO. Whereas in the
HALT mode, the overflow will initialize a ²warm reset²
only the program counter and SP are reset to 0. To clear
the contents of WDT, three methods are adopted, external
reset (a low level to RES), software instruction, or a HALT
instruction. The software instructions are of two types
which include CLR WDT and the other set - CLR WDT1
and CLR WDT2. Of these two types of instruction, only
one can be active depending on the ROM code option ²CLR WDT times selection option². If the ²CLR WDT² is
selected (i.e., CLR WDT times equal one), any execution
of the CLR WDT instruction will clear the WDT. In case ²CLR
WDT1² and ²CLR WDT2² are chosen (i.e. CLR WDT
times equal two), these two instructions must be executed to clear the WDT; otherwise, the WDT may reset
the chip because of time-out.
The time base offers a periodic time-out period to generate a regular internal interrupt. Its time-out period
ranges from fS/212 to fS/215 selected by options. If time
base time-out occurs, the related interrupt request flag
(TBF; bit 5 of INTC0) is set. But if the interrupt is enabled, and the stack is not full, a subroutine call to location 08H occurs.
When the HALT instruction is executed, the time base
still works (if WDT clock source comes from WDT RC
OSC or RTC OSC) and can wake up from HALT mode.
If the TBF is set ²1² before entering the HALT mode, the
wake up function will be disabled.
Real Time Clock - RTC
The real time clock (RTC) is operated in the same manner as the time base that is used to supply a regular internal interrupt. Its time-out period ranges from fS/28 to
fS/215 by software programming. Writing data to RT2,
RT1 and RT0 (bits 2, 1, 0 of RTCC;09H) yields various
The WDT time-out period ranges from 215/fS~216/fS. Because the ²CLR WDT² or ²CLR WDT1² and ²CLR
WDT2² instruction only clear the last two-stage of the
WDT.
fS
fS /2
D iv id e r
8
P r e s c a le r
Multi-function Timer
R T 2
R T 1
R T 0
The HT47R20A-1/HT47C20-1 provides a multi-function
timer for WDT, time base and real time clock but with different time-out periods. The multi-function timer con-
Rev. 1.70
8 to 1
M u x .
8
1 5
fS /2 ~ fS /2
R T C In te rru p t
Real Time Clock
13
June 14, 2005
HT47R20A-1/HT47C20-1
interrupt is enabled and the stack is not full, the regular
interrupt response takes place.
time-out periods. If the RTC time-out occurs, the related
interrupt request flag (RTF; bit 6 of INTC0) is set. But if
the interrupt is enabled, and the stack is not full, a subroutine call to location 0CH occurs. The real time clock
time-out signal can also be applied to be a clock source of
timer/event counter, so as to get a longer time-out period.
RT2
RT1
RT0
Clock Divided Factor
0
0
0
28*
0
0
1
29*
0
1
0
210*
0
1
1
211*
1
0
0
212
1
0
1
213
1
1
0
214
1
1
1
215
Note:
If an interrupt request flag is set to ²1² before entering
the HALT mode the wake-up function of the related interrupt will be disabled.
Once a wake-up event occurs, it takes 1024 (system
clock period) to resume normal operation. In other
words, a dummy period will be inserted after the
wake-up. If the wake-up results from an interrupt acknowledgment, the actual interrupt subroutine execution is delayed by one more cycle. If the wake-up results
in the next instruction execution, this will execute immediately after a dummy period has finished.
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
Reset
· There are three ways in which a reset may occur.
²*² not recommended to be used
· RES reset during normal operation
Power Down Operation - HALT
· RES reset during HALT
The HALT mode is initialized by the HALT instruction
and results in the following.
· WDT time-out reset during normal operation
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a warm reset
that just resets the program counter and SP leaving the
other circuits in their original state. Some registers remain unchanged during any other reset conditions.
Most registers are reset to the ²initial condition² when
the reset conditions are met. By examining the PDF and
TO flags, the program can distinguish between different
²chip resets².
· The system oscillator will turn off but the WDT oscilla-
tor or RTC oscillator keeps running (if the WDT oscillator or the real time clock is selected).
· The contents of the on-chip RAM and registers remain
unchanged.
· The WDT will be cleared and recounted again (if the
WDT clock comes from the WDT oscillator or the real
time clock oscillator).
· All I/O ports maintain their original status.
· The PDF flag is set and the TO flag is cleared.
· LCD driver is still running by ROM code option (if the
WDT OSC or RTC OSC is selected).
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge signal on port A or a overflow. An external reset causes a
device initialization and the WDT overflow performs a
²warm reset². Examining the TO and PDF flags, the reason for chip reset can be determined. The PDF flag is
cleared when the system power-up or executing the
CLR WDT instruction and is set when the HALT instruction is executed. The TO flag is set if a WDT time-out occurs, it causes a wake-up that only resets the program
counter and SP, the others maintain their original status.
PDF
RESET Conditions
0
0
RES reset during power-up
u
u
RES reset during normal operation
0
1
RES wake-up HALT
1
u
WDT time-out during normal operation
1
1
WDT wake-up HALT
Note: ²u² means ²unchanged².
V
D D
0 .0 1 m F *
1 0 0 k W
R E S
The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit
in port A can be independently selected to wake up the
device by ROM code option. Awakening from an I/O port
stimulus, the program will resume execution of the next
instruction. If awakening from an interrupt, two sequences may happen. If the related interrupt is disabled
or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. If the
Rev. 1.70
TO
1 0 k W
0 .1 m F *
Reset Circuit
Note:
14
²*² Make the length of the wiring, which is connected to the RES pin as short as possible, to
avoid noise interference.
June 14, 2005
HT47R20A-1/HT47C20-1
V D D
To guarantee that the system oscillator has started and
stabilized, the SST (System Start-up Timer) provides an
extra delay. There is an extra delay of 1024 system
clock pulses when the system awakes from the HALT
state or when the system powers up.
R E S
tS
C h ip R e s e t
The functional unit chip reset status are shown below.
Program Counter
000H
Interrupt
Disabled
Prescaler, Divider
Cleared
WDT, RTC, Time Base
Clear. After master reset,
begin counting
Timer/Event Counter
Off
Input/output ports
Input mode
SP
Points to the top of the stack
S T
S S T T im e - o u t
Reset Timing Chart
H A L T
W a rm
W D T
R e s e t
W D T
T im e - o u t
R e s e t
E x te rn a l
R E S
C o ld
R e s e t
S S T
1 0 - b it R ip p le
C o u n te r
O S C 1
P o w e r - o n D e te c tio n
Reset Configuration
The states of the registers are summarized in the following table:
Register
Reset
(Power On)
WDT Time-out
RES Reset
(Normal Operation) (Normal Operation)
RES Reset
(HALT)
WDT Time-out
(HALT)
TMRAH
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMRAL
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMRC
0000 1---
0000 1---
0000 1---
0000 1---
uuuu u---
TMRBH
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMRBL
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
ADCR
1xxx --00
1xxx --00
1xxx --00
1xxx --00
uuuu --uu
000H
000H
000H
000H
000H*
MP0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
--01 uuuu
--11 uuuu
INTC0
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
Program Counter
INTC1
---0 ---0
---0 ---0
---0 ---0
---0 ---0
---u ---u
RTCC
--00 0111
--00 0111
--00 0111
--00 0111
--uu uuuu
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
Note:
²*² refers to warm reset
²u² means unchanged
²x² means unknown
Rev. 1.70
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June 14, 2005
HT47R20A-1/HT47C20-1
Timer/Event Counter
time/event counter preload register (16-bit) simultaneously. The timer/event counter preload register is
changed by writing TMRBH operations and writing
TMRBL will keep the timer/event counter preload register unchanged.
One 16-bit timer/event counter with PFD output or two
channels of RC type A/D converter is implemented in
the HT47R20A-1/HT47C20-1. The ADC/TM bit (bit 1 of
ADCR register) decides whether timer A and timer B is
composed of one 16-bit timer/event counter or timer A
and timer B composed of two channels RC type A/D
converter.
Reading TMRAH will also latch the TMRAL into the low
byte buffer to avoid the false timing problem. Reading
TMRAL returns the contents of the low byte buffer. In
other words, the low byte of the timer/event counter can
not be read directly. It must read the TMRAH first to
make the low byte contents of the timer/event counter
be latched into the buffer.
The TMRAL, TMRAH, TMRBL, TMRBH compose one
16-bit timer/event counter, when ADC/TM bit is ²0². The
TMRBL and TMRBH are timer/event counter preload
registers for lower-order byte and higher-order byte respectively.
If the timer/event counter is on, the TMRAH, TMRAL,
TMRBH and TMRBL cannot be read or written. To
avoid conflicting between timer A and timer B, the
TMRAH, TMRAL, TMRBH and TMRBL registers
should be accessed with ²MOV² instruction under
timer off condition.
Using the internal clock, there are three reference time
base. The timer/event counter internal clock source may
come from the system clock or system clock/4 or RTC
time-out signal to generator an accurate time base.
Using external clock input allows the user to count external events, count external RC type A/D clock, measure
time intervals or pulse widths, or generate an accurate
time base.
The TMRC is the timer/event counter control register,
which defines the timer/event counter options.
The timer/event counter control register defines the operating mode, counting enable or disable and active
edge.
There are six registers related to the timer/event counter
operating mode. TMRAH ([20H]), TMRAL ([21H]),
TMRC ([22H]), TMRBH ([23H]), TMRBL ([24H]) and
ADCR ([25H]). Writing TMRBL only writes the data into
a low byte buffer, and writing TMRBH will write the data
and the contents of the low byte buffer into the
S y s te m C
S y s te m C lo
A /D C
R T C
lo
c k
lo
O
c k
/4
c k
u t
Writing to timer B makes the starting value be placed in
the timer/event counter preload register, while reading
timer A yields the contents of the timer/event counter.
Timer B is timer/event counter preload register.
D a ta B u s
M
U
T M R 0
O v e r flo w
1 6 - b it T im e r A
X
T
R
Q
P F D
T E
T M
T M
T M
T O
2
N
1
0
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
1 6 - b it T im e r B
T M 2
T M 1
T M 0
R e lo a d
P A 3 D a ta C T R L
Timer/Event Counter
Bit No.
Label
0~2
¾
Unused bit, read as ²0²
3
TE
Defines the TMR active edge of timer/event counter
(0=active on low to high; 1=active on high to low)
4
TON
Enable or disable timer counting (0=disable; 1=enable)
TM0
TM1
TM2
Defines the operating mode (TM2, TM1, TM0)
000=Timer mode (system clock)
001=Timer mode (system clock/4)
010=Timer mode (RTC output)
011=A/D clock mode (RC oscillation decided by ADCR register)
100=Event counter mode (external clock)
101=Pulse width measurement mode (system clock/4)
110=Unused
111=Unused
5
6
7
Function
TMRC (22H) Register
Rev. 1.70
16
June 14, 2005
HT47R20A-1/HT47C20-1
To enable the counting operation, the timer ON bit (TON;
bit 4 of TMRC) should be set to 1. In the pulse width
measurement mode, the TON will be automatically
cleared after the measurement cycle is completed. But
in the other three modes, the TON can only be reset by
instructions. The overflow of the timer/event counter is
one of the wake-up sources and can also be applied to a
PFD (Programmable Frequency Divider) output at PA3
by options. No matter what the operation mode is, writing a 0 to ETI can disable the corresponding interrupt
service. When the PFD function is selected, executing
²CLR PA.3² instruction to enable PFD output and executing ²SET PA.3² instruction to disable PFD output and
PA.3 output low level.
The TM0, TM1 and TM2 bits define the operation mode.
The event count mode is used to count external events,
which means that the clock source comes from an external (TMR) pin. The A/D clock mode is used to count external A/D clock, the RC oscillation mode is decided by
ADCR register. The timer mode functions as a normal
timer with the clock source coming from the internal selected clock source. Finally, the pulse width measurement mode can be used to count the high or low level
duration of the external signal (TMR). The counting is
based on the instruction clock.
In the event count, A/D clock or internal timer mode,
once the timer/event counter starts counting, it will count
from the current contents in the timer/event counter
(TMRAH and TMRAL) to FFFFH. Once overflow occurs,
the counter is reloaded from the timer/event counter
preload register (TMRBH and TMRBL) and generates
the corresponding interrupt request flag (TF; bit 4 of
INTC1) at the same time.
In the case of timer/event counter OFF condition, writing
data to the timer/event counter preload register also reloads that data to the timer/event counter. But if the
timer/event counter turns on, data written to the
timer/event counter preload register is kept only in the
timer/event counter preload register. The timer/event
counter will still operate until overflow occurs.
In the pulse width measurement mode with the TON and
TE bits are equal to 1, once the TMR has received a
transient from low to high (or high to low if the TE bit is 0)
it will start counting until the TMR returns to the original
level and resets the TON. The measured result will remain in the timer/event counter even if the activated
transient occurs again. In other words, only one cycle
measurement can be done. Until setting the TON, the
cycle measurement will function again as long as it receives further transient pulse. Note that in this operation
mode, the timer/event counter starts counting not according to the logic level but according to the transient
edges. In the case of counter overflows, the counter is
reloaded from the timer/event counter preload register
and issues interrupt request just like the other three
modes.
When the timer/event counter (reading TMRAH) is
read, the clock will be blocked to avoid errors. As this
may result in a counting error, this must be taken into
consideration by the programmer.
It is strongly recommended to load first the desired
value for TMRBL, TMRBH, TMRAL, and TMRAH registers, before turning on the related timer/event counter
for proper operation. Because the initial value of
TMRBL, TMRBH, TMRAL and TMRAH are unknown.
If the timer/event counter is on, the TMRAH, TMRAL,
TMRBH and TMRBL cannot be read or written. Only
when the timer/event counter is off and when the instruction ²MOV² is used could those four registers
be read or written.
Example for Timer/event counter mode (disable interrupt):
clr tmrc
clr adcr.1
clr intc1.4
mov a, low (65536-1000)
mov tmrbl, a
mov a, high (65536-1000)
mov tmrbh, a
mov a, 00110000b
mov tmrc, a
P10:
clr wdt
snz intcl.4
P10
clr intcl.4
Rev. 1.70
; set timer mode
; clear timer/event counter interrupt request flag
; give timer initial value
; count 1000 time and then overflow
; timer clock source=T1 and timer on
; polling timer/event counter interrupt request flag
; clear timer/event counter interrupt request flag
; program continue
17
June 14, 2005
HT47R20A-1/HT47C20-1
tions and writing TMRAL/TMRBL will keep timer A/timer
B unchanged.
A/D Converter
Two channels of RC type A/D converter are implemented in the HT47R20A-1/HT47C20-1. The A/D converter contains two 16-bit programmable count-up
counter and the Timer A clock source may come from
the system clock, instruction clock or RTC output. The
timer B clock source may come from the external RC oscillator. The TMRAL, TMRAH, TMRBL, TMRBH is composed of the A/D converter when ADC/TM bit (bit 1 of
ADRC register) is ²1².
Reading /TMRBH will also latch the TMRAL/TMRBL into
the low byte buffer to avoid the false timing problem.
Reading TMRAL/TMRBL returns the contents of the low
byte buffer. In other word, the low byte of timer A/timer B
ca n n o t b e r e a d d i r e ct l y. I t m u st r e a d t h e
TMRAH/TMRBH first to make the low byte contents of
timer A/timer B be latched into the buffer.
If the A/D converter timer A and timer B are counting, the TMRAH, TMRAL, TMRBH and TMRBL cannot be read or written. To avoid conflicting between
timer A and timer B, the TMRAH, TMRAL, TMRBH
and TMRBL registers should be accessed with
²MOV² instruction under timer A and timer B off condition.
The A/D converter timer B clock source may come from
channel 0 (IN0 external clock input mode, RS0~CS0 oscillation, RT0~CS0 oscillation, CRT0~CS0 oscillation
(CRT0 is a resistor), or RS0~CRT0 oscillation (CRT0 is
a capacitor) or channel 1 (RS1~CS1 oscillation,
RT1~CS1 oscillation or IN1 external clock input). The
timer A clock source is from the system clock, instruction
clock or RTC prescaler clock output decided by TMRC
register.
The bit4~bit7 of ADCR decides which resistor and capacitor compose an oscillation circuit and input to
TMRBH and TMRBL.
There are six registers related to the A/D converter, i.e.,
TMRAH, TMRAL, TMRC, TMRBH, TMRBL and ADCR.
The internal timer clock is input to TMRAH and TMRAL,
the A/D clock is input to TMRBH and TMRBL. The
OVB/OVA bit (bit 0 of ADCR register) decides whether
timer A overflows or timer B overflows, then the TF bit is
set and timer interrupt occurs. When the A/D converter
mode timer A or timer B overflows, the TON bit is reset
and stop counting. Writing TMRAH/TMRBH makes the
starting value be placed in the timer A/timer B and reading TMRAH/TMRBH gets the contents of the timer
A/timer B. Writing TMRAL/TMRBL only writes the data
into a low byte buffer, and writing TMRAH/TMRBH will
write the data and the contents of the low byte buffer into
the timer A/timer B (16-bit) simultaneously. The timer
A/timer B is changed by writing TMRAH/TMRBH opera-
The TM0, TM1 and TM2 bits of TMRC define the clock
source of timer A. It is recommended that the clock
source of timer A use the system clock, instruction clock
or RTC prescaler clock.
The TON bit (bit 4 of TMRC) is set ²1² the timer A and
timer B will start counting until timer A or timer B overflows, the timer/event counter generates the interrupt
request flag (TF; bit 4 of INTC1) and the timer A and
timer B stop counting and reset the TON bit to ²0² at the
same time.
If the TON bit is ²1², the TMRAH, TMRAL, TMRBH
and TMRBL cannot be read or written. Only when
the timer/event counter is off and when the instruction ²MOV² is used could those four registers be
read or written.
Bit No.
Label
Function
0
OVB/OVA
In the RC type A/D converter mode, this bit is used to define the timer/event counter interrupt
which comes from timer A overflow or timer B overflow.
(0= timer A overflow; 1= timer B overflow)
In the timer/event counter mode, this bit is void.
1
ADC/TM
2~3
¾
Unused bit, read as ²0².
M0
M1
M2
M3
Defines the A/D converter operating mode (M3, M2, M1, M0)
0000= IN0 external clock input mode
0001= RS0~CS0 oscillation (reference resistor and reference capacitor)
0010= RT0~CS0 oscillation (resistor sensor and reference capacitor)
0011= CRT0~CS0 oscillation (resistor sensor and reference capacitor)
0100= RS0~CRT0 oscillation (reference resistor and sensor capacitor)
0101= RS1~CS1 oscillation (reference resistor and reference capacitor)
0110= RT1~CS1 oscillation (resistor sensor and reference capacitor)
0111= IN1 external clock input mode
1XXX= Unused mode
4
5
6
7
Defines 16 timer/event counters or RC type A/D converter is enabled.
(0= timer/event counter enable; 1= A/D converter is enabled)
ADCR (25H) Register
Rev. 1.70
18
June 14, 2005
HT47R20A-1/HT47C20-1
Example for RC type AD converter mode (Timer A overflow):
clr tmrc
clr adcr.1
clr intc1.4
mov a, low (65536-1000)
mov tmrbl, a
mov a, high (65536-1000)
mov tmrbh, a
; set timer mode
; clear timer/event counter interrupt request flag
; give timer A initial value
; count 1000 time and then overflow
mov a, 00010010b
mov adcr,a
mov a, 00h
mov tmrbl, a
mov a, 00h
mov tmrbh, a
; RS0~CS0; set RC type ADC mode; set Timer A overflow
mov a, 00110000b
mov tmrc, a
; timer A clock source=T1 and timer on
p10:
clr wdt
snz intcl.4
jmp p10
clr intcl.4
; give timer B initial value
; polling timer/event counter interrupt request flag
; clear timer/event counter interrupt request flag
; program continue
Example for RC type AD converter mode (Timer B overflow):
clr tmrc
clr adcr.1
clr intc1.4
mov a, 00h
mov tmrbl, a
mov a, 00h
mov tmrbh, a
; set timer mode
; clear timer/event counter interrupt request flag
; give timer A initial value
mov a, 00010011b
adcr, a
; RS0~CS0; set RC type ADC mode; set Timer B overflow
mov a, low (65536-1000)
mov tmrbl, a
mov a, high (65536-1000)
mov tmrbh, a
; give timer B initial value
; count 1000 time and then overflow
mov a, 00110000b
mov tmrc, a
; timer A clock source=T1 and timer on
p10:
clr wdt
snz intcl.4
jmp p10
clr intcl.4
Rev. 1.70
; polling timer/event counter interrupt request flag
; clear timer/event counter interrupt request flag
; program continue
19
June 14, 2005
HT47R20A-1/HT47C20-1
S 1
S y s te m
C lo c k
O V B /O V A = 0
S 2
S y s te m
T im e r A
C lo c k /4
In te rru p t
S 3
R T C
O u tp u t
T O N
O V B /O V A = 1
T im e r B
R e s e t T O N
S 1 2
S 1 3
S 4
S 5
IN 0
C S 0
S 6
S 7
S 8
C R T 0
R S 0
S 9
R T 0
S 1 0
IN 1
S 1 1
C S 1
R S 1
R T 1
T N 2
T N 1
T N 0
S 1
S 2
S 3
M 3
M 2
M 1
M 0
S 4
S 5
S 6
S 7
S 8
S 9
S 1 0
S 1 1
S 1 2
S 1 3
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
0
1
0
0
0
1
0
0
1
0
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
1
1
1
0
1
0
0
0
0
0
1
0
1
0
0
0
1
0
1
0
0
0
0
0
1
1
0
0
1
0
1
1
0
0
0
0
0
0
1
0
1
0
1
0
1
1
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
O th e r
N o te : 0 = o ff, 1 = o n
1
0
0
1
0
0
0
0
1
0
1
0
N o te : 0 = o ff, 1 = o n
RC Type A/D Converter
When the structures of PA are open drain NMOS type, it
should be noted that, before reading data from the pads,
a ²1² should be written to the related bits to disable the
NMOS device. That is done first before executing the instruction ²MOV A, 0FFH² and ²MOV [12H], A² to disable
related NMOS device, and then ²MOV A, [12H]² to get
stable data.
Input/Output Ports
There are 8-bit bidirectional input/output port and 4-bit
input port in the HT47R20A-1/HT47C20-1, labeled PA
and PB which are mapped to the data memory of [12H]
and [14H] respectively. The high nibble of the PA is
NMOS output and input with pull-high resisters. The low
nibble of the PA can be used for input/output or output
operation by selecting NMOS or CMOS output by options. Each bit on the PA can be configured as a
wake-up input, and the low nibble of the PA with or without pull-high resistor by options. PB can only be used for
input operation, and each bit is with pull high resistor.
Both are for the input operation, these ports are
non-latched, that is, the inputs should be ready at the T2
rising edge of the instruction ²MOV A, [m]² (m=12H or
14H). For PA output operation, all data are latched and
remain unchanged until the output latch is rewritten.
Rev. 1.70
After chip reset, these input lines remain at a high level
or are left floating (by ROM code option).
Some instructions first input data and then follow the
output operations. For example, ²SET [m].i², ²CLR
[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or to the accumulator. Each bit of the PA output
latches can not use these instruction, which may
change the input lines to output lines (when input line is
at low level).
20
June 14, 2005
HT47R20A-1/HT47C20-1
V
V
D D
V
D D
V
D D
W E A K
P u ll- u p
D
D a ta B u s
C K
W R
B Z O p tio n
Q
S
O p tio n
M
U
C K
W R
B Z O p tio n
Q
O p tio n
P A 1 /B Z
Q
S
M
U
C h ip R e s e t
X
C h ip R e s e t
D
D a ta B u s
P A 0 /B Z
Q
D D
W E A K
P u ll- u p
X
B Z S ig n a l
M
S y s te m
M
U
R e a d P a th
U
R e a d P a th
X
X
S y s te m
W a k e -u p
W a k e -u p
O p tio n
O p tio n
PA0/BZ, PA1/BZ Input/Output Port
IR
D A T A B U S
W R
V
Q
D
C K
S
Q
D D
D D
W E A K
P u ll- u p
O p tio n
M
U
C h ip R e s e t
P F D
V
O p tio n
O p tio n
X
P A 3 /P F D
S ig n a l
M
U
R e a d P a th
X
S y s te m
W a k e -u p
O p tio n
PA2/IR, PA3/PFD Input/Output Port
V
D D
V
W E A K
P u ll- u p
D a ta B u s
W r ite
Q
D
C K
S
W E A K
P u ll- u p
P A 4 ~ P A 7
Q
C h ip R e s e t
R e a d D a ta
D a ta B u s
R e a d I/O
S y s te m
D D
P B 0 ~ P B 3
W a k e -u p
O p tio n
PA4~PA7 Input/Output Ports
Rev. 1.70
PB Input Lines
21
June 14, 2005
HT47R20A-1/HT47C20-1
C O M
LCD Display Memory
4 0 H
4 1 H
4 2 H
4 3 H
5 1 H
5 2 H
5 3 H
0
0
The HT47R20A-1/HT47C20-1 provides an area of embedded data memory for LCD display. The LCD display
memory is designed into 20´3 bits. If the LCD selected
19´4 segments output, the 53H of the LCD display
memory can not be accessed. This area is located from
40H to 53H of the RAM at Bank 1. Bank pointer (BP; located at 04H of the data memory) is the switch between
the general data memory and the LCD display memory.
When the BP is set ²1² any data written into 40H~53H
will effect the LCD display (indirect addressing mode using MP1). When the BP is cleared ²0², any data written
into 40H~53H means to access the general purpose
data memory. The LCD display memory can be read
and written only by indirect addressing mode using
MP1. When data is written into the display data area, it is
automatically read by the LCD driver which then generates the corresponding LCD driving signals. To turn the
display on or off, a ²1² or a ²0² is written to the corresponding bit of the display memory, respectively. The
figure illustrates the mapping between the display memory and LCD pattern for the HT47R20A-1/HT47C20-1.
B it
1
1
2
2
3
3
0
S E G M E N T
1
2
3
1 7
1 8
1 9
Display Memory (Bank 1)
LCD Driver Output
The output number of the HT47R20A-1/HT47C20-1
LCD driver can be 20´2, 20´3 or 19´4 by options (i.e., 1/2
duty, 1/3 duty or 1/4 duty).
The bias type of the LCD driver can be ²C² type or ²R²
type. A capacitor mounted between C1 and C2 pins is
needed. The bias voltage of the LCD driver can be 1/2 bias
or 1/3 bias by options. If 1/2 bias is selected, a capacitor
mounted between V2 pin and the ground is required. If 1/3
bias is selected, two capacitors are needed for V1 and V2
pins. Refer to the application diagram. If the ²R² bias
type is selected, no external capacitor is required.
D u r in g a R e s e t P u ls e
C O M 0 ,C O M 1 ,C O M 2
A ll L C D
d r iv e r o u tp u ts
N o r m a l O p e r a tio n M o d e
*
*
*
C O M 0
C O M 1
C O M 2 *
L C D s e g m e n ts O N
C O M 0 ,1 , 2 s id e s a r e u n lig h te d
O n ly L C D s e g m e n ts O N
C O M 0 s id e a r e lig h te d
O n ly L C D s e g m e n ts O N
C O M 1 s id e a r e lig h te d
O n ly L C D s e g m e n ts O N
C O M 2 s id e a r e lig h te d
L C D s e g m e n ts O N
C O M 0 ,1 s id e s a r e lig h te d
L C D s e g m e n ts O N
C O M 0 , 2 s id e s a r e lig h te d
L C D s e g m e n ts O N
C O M 1 , 2 s id e s a r e lig h te d
L C D s e g m e n ts O N
C O M 0 ,1 , 2 s id e s a r e lig h te d
H A L T M o d e
V L
1 /2
V S
V L
1 /2
V S
C D
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
C D
V L
1 /2
V S
V L
1 /2
V S
C O M 0 , C O M 1 , C O M 2
A ll L C D d r iv e r o u tp u ts
N o te : " * " O m it th e C O M 2 s ig n a l, if th e 1 /2 d u ty L C D
S
C D
S
V L C D
V L C D
V L
S
C D
V L
S
C D
V L
S
C D
V L
S
C D
V L
S
C D
V L
S
C D
V L
S
C D
V L
S
C D
V L
S
C D
V L
S
C D
V L
S
C D
S
C D
S
C D
C D
C D
C D
C D
C D
C D
C D
C D
C D
C D
V L C D
V L C D
is u s e d .
LCD Driver Output (1/3 Duty, 1/2 Bias, R/C Type)
Rev. 1.70
22
June 14, 2005
HT47R20A-1/HT47C20-1
V A
V B
V C
C O M 0
V S S
V A
V B
V C
C O M 1
V S S
V A
V B
V C
C O M 2
V S S
V A
V B
C O M 3
V C
V S S
V A
V B
V C
L C D s e g m e n ts O N
C O M 2 s id e lig h te d
V S S
N o te : 1 /4 d u ty , 1 /3 b ia s , C ty p e : " V A " 3 /2 V L C D , " V B " V L C D , " V C " 1 /2 V L C D
1 /4 d u ty , 1 /3 b ia s , R ty p e : " V A " V L C D , " V B " 2 /3 V L C D , " V C " 1 /3 V L C D
LCD Driver Output
Low Voltage Reset/Detector Functions
There is a low voltage detector (LVD) and a low voltage
reset circuit (LVR) implemented in the microcontrollers.
These two functions can be enabled/disabled by ROM
code options. The LVD can be enabled/disabled by
ROM code options. Once the ROM code options of LVD
is enabled, the user can use the RTCC.3 to enable or
disable (1/0) the LVD circuit and read the LVD detector
status (0/1) from RTCC.5; otherwise, the LVD function is
disabled.
1 /2 b ia s
C 1
C 1
C 2
C 2
V 1
V L C D
V 2
The LVR has the same effect or function with the external RES signal which performs chip reset. During HALT
state, LVR is disabled.
Rev. 1.70
1 /3 b ia s
V
V 1
D D
V L C D
V
D D
V 2
V1, V2, VLCD Application Diagram (C Type)
23
June 14, 2005
HT47R20A-1/HT47C20-1
The definitions of RTCC register are listed in the following table.
Bit No.
Label
Read/Write
Reset
Function
0~2
RT0~RT2
R/W
1
8 to 1 multiplexer control inputs to select the real clock prescaler output
3
LVDC*
R/W
0
LVD enable/disable (1/0)
4
QOSC
R/W
0
32768Hz OSC quick start-up oscillating
0/1: quickly/slowly start
5
LVDO
R/W
0
LVD detection output (1/0)
1: low voltage detected
6~7
¾
¾
¾
Unused bit, read as ²0²
²*² Once the function is enabled the reference generator should be enabled; otherwise the reference generator is controlled by LVR ROM code option.
Note:
RTCC (09H) Register
Buzzer
Programmable Frequency Divider - PFD
HT47R20A-1/HT47C20-1 provides a pair of buzzer output BZ and BZ, which share pins with PA0 and PA1 respectively, as determined by options. Its output frequency
can also be selected by options.
The PFD output shares pin with PA3, as determined by
options.
When the PFD option is selected, setting PA3 ²0² (²CLR
PA.3²) will enable the PFD output and setting PA3 ²1²
(²SET PA.3²) will disable the PFD output and PA3 output
at low level.
When the buzzer function is selected, setting PA.0 and
PA.1 ²0² simultaneously will enable the buzzer output
and setting PA.0 ²1² will disable the buzzer output and
setting PA.0 ²0² and PA.1 ²1² will only enable the BZ
output and disable the BZ output.
PA1
PA0
PFD output frequency =
1
1
´
2 timer overflow period
Function
PA3
Function
0 (CLR PA.1)
0 (CLR PA.0)
PA0=BZ, PA1=BZ
1 (SET PA.1)
0 (CLR PA.0)
PA0=BZ, PA1=0
0 (CLR PA.3)
PA3=PFD output
1 (SET PA.0)
PA0=0, PA1=0
1 (SET PA.3)
PA3=0
X
Buzzer Enable
IR Carrier
HT47R20A-1/HT47C20-1 provides carrier driving capability that allows for easy interfacing to an infrared diode,
which share pin with PA2, as determined by options.
When the carrier option is selected, setting PA2 ²0²
(²CLR PA.2²) will enable the carrier output and setting
PA2 ²1² (²SET PA.2²) will disable the carrier output and
the PA2 output is at low level. The IR carrier frequency is
system clock divided by 12 and it is 1/4 duty.
PA2
Function
0 (CLR PA.2)
PA2=IR carrier output
1 (SET PA.2)
PA2=0
Rev. 1.70
24
June 14, 2005
HT47R20A-1/HT47C20-1
Option
The following shows many kinds of options in the HT47R20A-1/HT47C20-1. All these options should be defined in order to ensure proper system functioning.
No.
Option
1
OSC type selection.
This option is to decide if an RC, a crystal oscillator or RTC oscillator is chosen as system clock.
2
Clock source selection of WDT, RTC and Time Base.
There are three types of selection: system clock/4 or RTC OSC or WDT OSC.
3
WDT enable or disable selection.
WDT can be enabled or disabled.
4
CLR WDT times selection.
This option defines how to clear the WDT by instruction. One time” means that the ²CLR WDT² can clear the
WDT. ²Two times² means that only if both of the ²CLR WDT1² and ²CLR WDT2² have been executed, then
WDT can be cleared.
5
Time Base time-out period selection.
The Time Base time-out period ranges from fS/212 to fS/215. ²fS² means the clock source of WDT.
6
Buzzer output frequency selection.
There are eight types frequency signals for buzzer output: fS/22~fS/29. ²fS² means the clock source of WDT.
7
Wake-up selection.
This option defines the wake-up function activity. External I/O pins (PA only) all have the capability to
wake-up the chip from a HALT mode by a following edge.
8
Pull high selection.
This option is to decide whether the pull high resistance is viable or not on the low nibble of the PA.
9
PA CMOS or NMOS selection.
The structure of the low nibble of the PA can be selected to be CMOS or NMOS. When the CMOS is selected,
the related pins only can be used for output operations. When the NMOS is selected, the related pins can be
used for input or output operations.
10
I/O pins share with other function selection.
PA0/BZ, PA1/BZ: PA0 and PA1 can be set as I/O pins or buzzer outputs.
PA2/IR: PA2 can be set as I/O pins or IR carrier output.
PA3/PFD: PA3 can be set as I/O pins or PFD output.
11
LCD common selection.
There are three types of selection: 2 common (1/2 duty) or 3 common (1/3 duty) or 4 common (1/4 duty). If the
4 common is selected, the segment output pin ²SEG32² will be set as a common output.
12
LCD driver clock selection.
There are seven types of frequency signals for the LCD driver circuits: fS/22~fS/28. ²fS² means the clock
source of WDT.
13
LCD on or LCD off at the HALT mode selection.
The LCD can be enable or disable at the HALT mode.
14
LVD enable or disable
15
LVR enable or disable
Rev. 1.70
25
June 14, 2005
HT47R20A-1/HT47C20-1
Application Circuits
V
D D
0 .0 1 m F *
C O M 0 ~ C O M 3
S E G 0 ~ S E G 1 8
V D D
L C D
P A N E L
1 0 0 k W
0 .1 m F
R E S
V L C D
1 0 k W
0 .1 m F *
C 2
V
0 .1 m F
R
0 .1 m F
O S C 2
D D
4 7 0 p F
V 1
O S C 1
S e e r ig h t s id e
3 2 7 6 8 H z
P o w e r S u p p ly
C 1
V S S
O S C
C ir c u it
L C D
fS Y S /4
o p e n d r a in
O S C
C 1
V 2
1 0 p F
C 2
P A 0 ~ P A 7
O S C 4
R 1
C ry s ta l S y s te m
F o r th e v a lu e s ,
s e e ta b le b e lo w
O s c illa to r
O S C 2
P B 0 ~ P B 3
IN 0
IN 1
C S 1
O S C 1
C S 0
R S 0
R S 1
C R T 0
R T 1
O S C 2
R T 0
H T 4 7 R 2 0 A -1 /H T 4 7 C 2 0 -1
Note:
O S C 2
O S C 1
0 .1 m F
O S C 3
O S C 1
R C S y s te m O s c illa to r
2 4 k W < R O S C < 1 M W
O S C
3 2 7 6 8 H z C ry s ta l S y s te m
O s c illa to r
O S C 1 a n d O S C 2 le ft
u n c o n n e c te d
C ir c u it
The resistance and capacitance for reset circuit should be designed in such a way as to ensure that the VDD is
stable and remains within a valid operating voltage range before bringing RES to high.
²*² Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise
interference.
The following table shows the C1, C2 and R1 value according different crystal values. (For reference only)
Crystal or Resonator
C1, C2
R1
0pF
10kW
4MHz Resonator (3 pin)
0pF
12kW
4MHz Resonator (2 pin)
10pF
12kW
3.58MHz Crystal
0pF
10kW
3.58MHz Resonator (2 pin)
25pF
10kW
2MHz Crystal & Resonator (2 pin)
25pF
10kW
1MHz Crystal
35pF
27kW
480kHz Resonator
300pF
9.1kW
455kHz Resonator
300pF
10kW
429kHz Resonator
300pF
10kW
4MHz Crystal
The function of the resistor R1 is to ensure that the oscillator will switch off should low voltage conditions occur. Such a low voltage, as mentioned here, is one which is less than the lowest value of the
MCU operating voltage. Note however that if the LVR is enabled then R1 can be removed.
Rev. 1.70
26
June 14, 2005
HT47R20A-1/HT47C20-1
Instruction Set Summary
Description
Instruction
Cycle
Flag
Affected
Add data memory to ACC
Add ACC to data memory
Add immediate data to ACC
Add data memory to ACC with carry
Add ACC to data memory with carry
Subtract immediate data from ACC
Subtract data memory from ACC
Subtract data memory from ACC with result in data memory
Subtract data memory from ACC with carry
Subtract data memory from ACC with carry and result in data memory
Decimal adjust ACC for addition with result in data memory
1
1(1)
1
1
1(1)
1
1
1(1)
1
1(1)
1(1)
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
C
1
1
1
1(1)
1(1)
1(1)
1
1
1
1(1)
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Increment data memory with result in ACC
Increment data memory
Decrement data memory with result in ACC
Decrement data memory
1
1(1)
1
1(1)
Z
Z
Z
Z
Rotate data memory right with result in ACC
Rotate data memory right
Rotate data memory right through carry with result in ACC
Rotate data memory right through carry
Rotate data memory left with result in ACC
Rotate data memory left
Rotate data memory left through carry with result in ACC
Rotate data memory left through carry
1
1(1)
1
1(1)
1
1(1)
1
1(1)
None
None
C
C
None
None
C
C
Move data memory to ACC
Move ACC to data memory
Move immediate data to ACC
1
1(1)
1
None
None
None
Clear bit of data memory
Set bit of data memory
1(1)
1(1)
None
None
Mnemonic
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
AND data memory to ACC
OR data memory to ACC
Exclusive-OR data memory to ACC
AND ACC to data memory
OR ACC to data memory
Exclusive-OR ACC to data memory
AND immediate data to ACC
OR immediate data to ACC
Exclusive-OR immediate data to ACC
Complement data memory
Complement data memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Rev. 1.70
27
June 14, 2005
HT47R20A-1/HT47C20-1
Instruction
Cycle
Flag
Affected
Jump unconditionally
Skip if data memory is zero
Skip if data memory is zero with data movement to ACC
Skip if bit i of data memory is zero
Skip if bit i of data memory is not zero
Skip if increment data memory is zero
Skip if decrement data memory is zero
Skip if increment data memory is zero with result in ACC
Skip if decrement data memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1(2)
1(2)
1(2)
1(2)
1(3)
1(3)
1(2)
1(2)
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read ROM code (current page) to data memory and TBLH
Read ROM code (last page) to data memory and TBLH
2(1)
2(1)
None
None
No operation
Clear data memory
Set data memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of data memory
Swap nibbles of data memory with result in ACC
Enter power down mode
1
1(1)
1(1)
1
1
1
1(1)
1
1
None
None
None
TO,PDF
TO(4),PDF(4)
TO(4),PDF(4)
None
None
TO,PDF
Mnemonic
Description
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note:
x: Immediate data
m: Data memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Ö: Flag is affected
-: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle
(four system clocks).
(2)
: If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more
cycle (four system clocks). Otherwise the original instruction cycle is unchanged.
(3) (1)
:
(4)
Rev. 1.70
and (2)
: The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the
CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared.
Otherwise the TO and PDF flags remain unchanged.
28
June 14, 2005
HT47R20A-1/HT47C20-1
Instruction Definition
ADC A,[m]
Add data memory and carry to the accumulator
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADCM A,[m]
Add the accumulator and carry to data memory
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,[m]
Add data memory to the accumulator
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the accumulator.
Operation
ACC ¬ ACC+[m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,x
Add immediate data to the accumulator
Description
The contents of the accumulator and the specified data are added, leaving the result in the
accumulator.
Operation
ACC ¬ ACC+x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADDM A,[m]
Add the accumulator to the data memory
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the data memory.
Operation
[m] ¬ ACC+[m]
Affected flag(s)
Rev. 1.70
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
29
June 14, 2005
HT47R20A-1/HT47C20-1
AND A,[m]
Logical AND accumulator with data memory
Description
Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
AND A,x
Logical AND immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_AND operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ANDM A,[m]
Logical AND data memory with the accumulator
Description
Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
CALL addr
Subroutine call
Description
The instruction unconditionally calls a subroutine located at the indicated address. The
program counter increments once to obtain the address of the next instruction, and pushes
this onto the stack. The indicated address is then loaded. Program execution continues
with the instruction at this address.
Operation
Stack ¬ Program Counter+1
Program Counter ¬ addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR [m]
Clear data memory
Description
The contents of the specified data memory are cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
Rev. 1.70
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
30
June 14, 2005
HT47R20A-1/HT47C20-1
CLR [m].i
Clear bit of data memory
Description
The bit i of the specified data memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR WDT
Clear Watchdog Timer
Description
The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are
cleared.
Operation
WDT ¬ 00H
PDF and TO ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
0
0
¾
¾
¾
¾
CLR WDT1
Preclear Watchdog Timer
Description
Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
PDF
OV
Z
AC
C
0*
0*
¾
¾
¾
¾
CLR WDT2
Preclear Watchdog Timer
Description
Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
PDF
OV
Z
AC
C
0*
0*
¾
¾
¾
¾
CPL [m]
Complement data memory
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa.
Operation
[m] ¬ [m]
Affected flag(s)
Rev. 1.70
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
31
June 14, 2005
HT47R20A-1/HT47C20-1
CPLA [m]
Complement data memory and place result in the accumulator
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa. The complemented result
is stored in the accumulator and the contents of the data memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DAA [m]
Decimal-Adjust accumulator for addition
Description
The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal
carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a
carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored
in the data memory and only the carry flag (C) may be affected.
Operation
If ACC.3~ACC.0 >9 or AC=1
then [m].3~[m].0 ¬ (ACC.3~ACC.0)+6, AC1=AC
else [m].3~[m].0 ¬ (ACC.3~ACC.0), AC1=0
and
If ACC.7~ACC.4+AC1 >9 or C=1
then [m].7~[m].4 ¬ ACC.7~ACC.4+6+AC1,C=1
else [m].7~[m].4 ¬ ACC.7~ACC.4+AC1,C=C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
DEC [m]
Decrement data memory
Description
Data in the specified data memory is decremented by 1.
Operation
[m] ¬ [m]-1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DECA [m]
Decrement data memory and place result in the accumulator
Description
Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]-1
Affected flag(s)
Rev. 1.70
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
32
June 14, 2005
HT47R20A-1/HT47C20-1
HALT
Enter power down mode
Description
This instruction stops program execution and turns off the system clock. The contents of
the RAM and registers are retained. The WDT and prescaler are cleared. The power down
bit (PDF) is set and the WDT time-out bit (TO) is cleared.
Operation
Program Counter ¬ Program Counter+1
PDF ¬ 1
TO ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
0
1
¾
¾
¾
¾
INC [m]
Increment data memory
Description
Data in the specified data memory is incremented by 1
Operation
[m] ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
INCA [m]
Increment data memory and place result in the accumulator
Description
Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
JMP addr
Directly jump
Description
The program counter are replaced with the directly-specified address unconditionally, and
control is passed to this destination.
Operation
Program Counter ¬addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV A,[m]
Move data memory to the accumulator
Description
The contents of the specified data memory are copied to the accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
Rev. 1.70
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
33
June 14, 2005
HT47R20A-1/HT47C20-1
MOV A,x
Move immediate data to the accumulator
Description
The 8-bit data specified by the code is loaded into the accumulator.
Operation
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV [m],A
Move the accumulator to data memory
Description
The contents of the accumulator are copied to the specified data memory (one of the data
memories).
Operation
[m] ¬ACC
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
Program Counter ¬ Program Counter+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
OR A,[m]
Logical OR accumulator with data memory
Description
Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
OR A,x
Logical OR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_OR operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ORM A,[m]
Logical OR data memory with the accumulator
Description
Data in the data memory (one of the data memories) and the accumulator perform a
bitwise logical_OR operation. The result is stored in the data memory.
Operation
[m] ¬ACC ²OR² [m]
Affected flag(s)
Rev. 1.70
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
34
June 14, 2005
HT47R20A-1/HT47C20-1
RET
Return from subroutine
Description
The program counter is restored from the stack. This is a 2-cycle instruction.
Operation
Program Counter ¬ Stack
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RET A,x
Return and place immediate data in the accumulator
Description
The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RETI
Return from interrupt
Description
The program counter is restored from the stack, and interrupts are enabled by setting the
EMI bit. EMI is the enable master (global) interrupt bit.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RL [m]
Rotate data memory left
Description
The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RLA [m]
Rotate data memory left and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the
rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ [m].7
Affected flag(s)
Rev. 1.70
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
35
June 14, 2005
HT47R20A-1/HT47C20-1
RLC [m]
Rotate data memory left through carry
Description
The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RLCA [m]
Rotate left through carry and place result in the accumulator
Description
Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the
carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored
in the accumulator but the contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RR [m]
Rotate data memory right
Description
The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRA [m]
Rotate right and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving
the rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRC [m]
Rotate data memory right through carry
Description
The contents of the specified data memory and the carry flag are together rotated 1 bit
right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
Rev. 1.70
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
36
June 14, 2005
HT47R20A-1/HT47C20-1
RRCA [m]
Rotate right through carry and place result in the accumulator
Description
Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces
the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is
stored in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
SBC A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SBCM A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SDZ [m]
Skip if decrement data memory is 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. If the result is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, [m] ¬ ([m]-1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SDZA [m]
Decrement data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. The result is stored in the accumulator but the data memory remains
unchanged. If the result is 0, the following instruction, fetched during the current instruction
execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, ACC ¬ ([m]-1)
Affected flag(s)
Rev. 1.70
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
37
June 14, 2005
HT47R20A-1/HT47C20-1
SET [m]
Set data memory
Description
Each bit of the specified data memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SET [m]. i
Set bit of data memory
Description
Bit i of the specified data memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZ [m]
Skip if increment data memory is 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a
dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with
the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, [m] ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZA [m]
Increment data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the next
instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper
instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, ACC ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SNZ [m].i
Skip if bit i of the data memory is not 0
Description
If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data
memory is not 0, the following instruction, fetched during the current instruction execution,
is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i¹0
Affected flag(s)
Rev. 1.70
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
38
June 14, 2005
HT47R20A-1/HT47C20-1
SUB A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the accumulator.
Operation
ACC ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUBM A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the data memory.
Operation
[m] ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUB A,x
Subtract immediate data from the accumulator
Description
The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+x+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SWAP [m]
Swap nibbles within the data memory
Description
The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged.
Operation
[m].3~[m].0 « [m].7~[m].4
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SWAPA [m]
Swap data memory and place result in the accumulator
Description
The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.3~ACC.0 ¬ [m].7~[m].4
ACC.7~ACC.4 ¬ [m].3~[m].0
Affected flag(s)
Rev. 1.70
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
39
June 14, 2005
HT47R20A-1/HT47C20-1
SZ [m]
Skip if data memory is 0
Description
If the contents of the specified data memory are 0, the following instruction, fetched during
the current instruction execution, is discarded and a dummy cycle is replaced to get the
proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZA [m]
Move data memory to ACC, skip if 0
Description
The contents of the specified data memory are copied to the accumulator. If the contents is
0, the following instruction, fetched during the current instruction execution, is discarded
and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed
with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZ [m].i
Skip if bit i of the data memory is 0
Description
If bit i of the specified data memory is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDC [m]
Move the ROM code (current page) to TBLH and data memory
Description
The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved
to the specified data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDL [m]
Move the ROM code (last page) to TBLH and data memory
Description
The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to
the data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
Rev. 1.70
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
40
June 14, 2005
HT47R20A-1/HT47C20-1
XOR A,[m]
Logical XOR accumulator with data memory
Description
Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XORM A,[m]
Logical XOR data memory with the accumulator
Description
Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XOR A,x
Logical XOR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Rev. 1.70
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
41
June 14, 2005
HT47R20A-1/HT47C20-1
Package Information
64-pin QFP (14´20) Outline Dimensions
C
H
D
5 1
G
3 3
I
5 2
3 2
F
A
B
E
2 0
6 4
K
a
J
1
Symbol
Rev. 1.70
1 9
Dimensions in mm
Min.
Nom.
Max.
A
18.80
¾
19.20
B
13.90
¾
14.10
C
24.80
¾
25.20
D
19.90
¾
20.10
E
¾
1
¾
F
¾
0.40
¾
G
2.50
¾
3.10
H
¾
¾
3.40
I
¾
0.10
¾
J
1.15
¾
1.45
K
0.10
¾
0.20
a
0°
¾
7°
42
June 14, 2005
HT47R20A-1/HT47C20-1
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor Inc. (Shanghai Sales Office)
7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233
Tel: 021-6485-5560
Fax: 021-6485-0313
http://www.holtek.com.cn
Holtek Semiconductor Inc. (Shenzhen Sales Office)
43F, SEG Plaza, Shen Nan Zhong Road, Shenzhen, China 518031
Tel: 0755-8346-5589
Fax: 0755-8346-5590
ISDN: 0755-8346-5591
Holtek Semiconductor Inc. (Beijing Sales Office)
Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031
Tel: 010-6641-0030, 6641-7751, 6641-7752
Fax: 010-6641-0125
Holmate Semiconductor, Inc. (North America Sales Office)
46712 Fremont Blvd., Fremont, CA 94538
Tel: 510-252-9880
Fax: 510-252-9885
http://www.holmate.com
Copyright Ó 2005 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.70
43
June 14, 2005