Order Now Product Folder Support & Community Tools & Software Technical Documents CSD95481RWJ SLPS674 – JUNE 2017 CSD95481RWJ Synchronous Buck NexFET™ Smart Power Stage 1 Features 2 Applications • • • • • • 1 • • • • • • • • • • • • 60-A Continuous Operating Current Capability Over 95% System Efficiency at 30 A High-Frequency Operation (up to 1.25 MHz) Diode Emulation Function Temperature Compensated Bi-Directional Current Sense Analog Temperature Output Fault Monitoring 3.3-V and 5-V PWM Signal Compatible Tri-State PWM Input Integrated Bootstrap Switch Optimized Dead Time for Shoot-Through Protection High-Density QFN 5-mm × 6-mm Footprint Ultra-Low-Inductance Package System Optimized PCB Footprint Thermally Enhanced Topside Cooling RoHS Compliant – Lead-Free Terminal Plating Halogen Free Multiphase Synchronous Buck Converters – High-Frequency Applications – High-Current, Low-Duty Cycle Applications POL DC-DC Converters Memory and Graphic Cards Desktop and Server VR12.x / VR13.x V-Core Synchronous Buck Converters • • • 3 Description The CSD95481RWJ NexFET™ power stage is a highly optimized design for use in a high-power, highdensity synchronous buck converter. This product integrates the driver IC and power MOSFETs to complete the power stage switching function. This combination produces high-current, high-efficiency, and high-speed switching capability in a small 5-mm × 6-mm outline package. It also integrates the accurate current sensing and temperature sensing functionality to simplify system design and improve accuracy. In addition, the PCB footprint has been optimized to help reduce design time and simplify the completion of the overall system design. Device Information(1) Application Diagram P12V AVSP AVSN TPS53679 VIN PWM PWM1 ASKIP# P5V DEVICE MEDIA QTY PACKAGE SHIP CSD95481RWJ 13-Inch Reel 2500 CSD95481RWJT 7-Inch Reel 250 QFN 5.00-mm × 6.00-mm Package Tape and Reel BOOT BOOT_R CSD95481RWJ EN/FCCM VOS VSW VDD PVDD LSET TAO LOAD (1) For all available packages, see the orderable addendum at the end of the data sheet. PGND IOUT REFIN Typical Power Stage Efficiency and Power Loss ACSP1 TSEN 100 14 90 12 80 10 70 8 60 6 50 4 40 2 P12V PWM VREF P5V ADDR BOOT BOOT_R CSD95481RWJ EN/FCCM VOS VSW VDD TAO PGND IOUT REFIN Efficiency (%) PVDD LSET 3.3 V V3P3 ACSP6 VREF P12V VIN_CSNIN CSPIN VCCIO BEN_VCCIO SCLK SDIO SALERT# PIN_ALT# VR_HOT# SMB_CLK SMB_ALERT # SMB_DIO AVR_RDY BVR_RDY AVR_EN VR_FAULT# RESET# BVSN BVSP Power Loss (W) VIN APWM6 P12V VIN PWM BPWM1 BSKIP# P5V BOOT BOOT_R CSD95492QVM EN/FCCM VOS VSW VDD PVDD LSET TAO LOAD PGND IOUT REFIN 30 0 BCSP1 10 20 30 40 Output Current (A) 50 0 60 D000 AGND Copyright © 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CSD95481RWJ SLPS674 – JUNE 2017 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 4 4 4 5 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. 8 Device and Documentation Support.................... 7 8.1 8.2 8.3 8.4 8.5 9 Receiving Notification of Documentation Updates.... Community Resources.............................................. Trademarks ............................................................... Electrostatic Discharge Caution ................................ Glossary .................................................................... 7 7 7 7 7 Mechanical, Packaging, and Orderable Information ............................................................. 8 9.1 Mechanical Drawing.................................................. 8 9.2 Recommended PCB Land Pattern............................ 9 9.3 Recommended Stencil Opening ............................. 10 Application Schematic .......................................... 6 4 Revision History 2 DATE REVISION NOTES June 2017 * Initial release. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: CSD95481RWJ CSD95481RWJ www.ti.com SLPS674 – JUNE 2017 5 Pin Configuration and Functions VOS 1 AGND 2 VDD 3 PVDD 4 PGND 5 NC 6 NC 35 VIN 36 BOOTR EN/FCCM 37 PWM TAO/FLT 38 BOOT IOUT 39 LSET REFIN Top View 34 33 32 31 30 VIN 40 29 VIN 28 VIN 27 VIN 26 VIN 25 VIN 24 PGND 41 23 PGND 21 PGND 13 14 15 16 17 18 19 SW 12 SW 11 SW 10 SW 20 PGND SW 9 SW PGND 22 PGND SW 8 SW PGND PGND SW 7 SW PGND Pin Functions PIN NAME DESCRIPTION NO. VOS 1 Output voltage sensing pin for the internal current sensing circuitry. AGND 2 This pin is internally connected to PGND. VDD 3 Supply voltage for internal circuitry. This pin should be bypassed directly to pin 2. PVDD 4 Supply voltage for gate drivers. This pin should be bypassed to PGND. PGND 5 Power ground. NC 6 Not connected. This pin needs to be left floating in application. PGND 7-9 Power ground. VSW 10-19 Phase node connecting the HS MOSFET source and LS MOSFET drain – pin connection to the output inductor. PGND 20-24 Power ground. VIN 25-30 Input voltage pin. Connect input capacitors close to this pin. NC 31 Not connected. This pin needs to be left floating in application. BOOTR 32 Return path for HS gate driver. It is connected to VSW internally. BOOT 33 Bootstrap capacitor connection. Connect a minimum 0.1-µF, 16-V, X5R ceramic capacitor from BOOT to BOOTR pins. The bootstrap capacitor provides the charge to turn on the control FET. The bootstrap diode is integrated. PWM 34 Tri-state input from external controller. Logic low sets control FET gate low and sync FET gate high. Logic high sets control FET gate high and sync FET gate low. Both MOSFET gates are set low if PWM stays in Hi-Z for greater than the tri-state shutdown hold-off time (T3HT). 35 This dual function pin either enables the diode emulation function or can be used as a simple enable for the device. When this pin is driven into the tri-state window and held there for more than the tri-state hold-off time, Diode Emulation Mode is enabled for sync FET. When the pin is high, device operates in Forced Continuous Conduction Mode. When the pin is low, both FETs are held off. An internal resistor pulls this pin low if left floating. TAO/FLT 36 Temperature amplifier output. Reports a voltage proportional to the IC temperature. An ORing diode is integrated in the IC. When used in multiphase application, a single wire can be used to connect the TAO pins of all the ICs. Only the highest temperature will be reported. TAO will be pulled up to 3.3 V if thermal shutdown LSOC or HSS detection circuit is tripped. LSET 37 A resistor from this pin to PGND pin sets the inductor value for the internal current sensing circuitry. IOUT 38 Output of current sensing amplifier. V(IOUT) – V(REFIN) is proportional to the phase current. REFIN 39 External reference voltage input for current sensing amplifier. PGND 40 Power ground. NC 41 Not connected. This pin needs to be left floating in application. EN/FCCM Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: CSD95481RWJ 3 CSD95481RWJ SLPS674 – JUNE 2017 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings TA = 25°C (unless otherwise stated) (1) MIN MAX UNIT VIN to PGND –0.3 20 V VIN to VSW –0.3 20 V 23 V –0.3 20 V VIN to VSW (10 ns) VSW to PGND VSW to PGND (10 ns) –7 23 V VDD to PGND –0.3 7 V PVDD to PGND –0.3 7 V EN/FCCM, TAO/FLT, LSET to PGND –0.3 VDD + 0.3 V IOUT, VOS, PWM to PGND –0.3 7 V REFIN –0.3 3.6 V BOOT to BOOTR (2) –0.3 VDD + 0.3 V BOOT to PGND –0.3 30 V TJ Operating junction temperature –55 150 °C Tstg Storage temperature –55 150 °C (1) (2) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Should not exceed 7 V. 6.2 ESD Ratings VALUE V(ESD) Electrostatic discharge Human-body model (HBM) ±2000 Charged-device model (CDM) ±500 UNIT V 6.3 Recommended Operating Conditions TA = 25°C (unless otherwise stated) MIN MAX UNIT VDD Driver supply voltage 4.5 5.5 V PVDD Gate drive voltage 4.5 5.5 V VIN Input supply voltage (1) 4.5 16 V VOUT Output voltage PWM to PGND IOUT Continuous output current (3) VIN = 12 V, VDD = 5 V, PVDD = 5 V, VOUT = 1.2 V, ƒSW = 500 kHz (2) IOUT-PK Peak output current ƒSW Switching frequency CBST = 0.1 µF (min), VOUT = 2.5 V (max) On-time duty cycle ƒSW = 1 MHz Minimum PWM on-time (2) (3) 4 V V 60 A 90 A 1250 kHz 85% 20 Operating junction temperature (1) 5.5 VDD + 0.3 –40 ns 125 °C Operating at high VIN can create excessive AC voltage overshoots on the switch node (VSW) during MOSFET switching transients. For reliable operation, the switch node (VSW) to ground voltage must remain at or below the Absolute Maximum Ratings. Measurement made with six 10-µF (TDK C3216X7R1C106KT or equivalent) ceramic capacitors across VIN to PGND pins. System conditions as defined in Note 2. Peak output current is applied for tp = 50 µs. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: CSD95481RWJ CSD95481RWJ www.ti.com SLPS674 – JUNE 2017 6.4 Thermal Information TA = 25°C (unless otherwise stated) THERMAL METRIC MIN TYP MAX UNIT θJC Thermal resistance, junction-to-case (top of package) 7.4 °C/W θJB Thermal resistance, junction-to-board (1) 2.2 °C/W ΨJT Junction-to-top characterization parameter 0.9 °C/W (1) 2 2 θJB is determined with the device mounted on a 1-in (6.45-cm ), 2-oz (0.071-mm) thick Cu pad on a 1.5-in × 1.5-in, 0.06-in (1.52-mm) thick FR4 board based on hottest board temperature within 1 mm of the package. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: CSD95481RWJ 5 CSD95481RWJ SLPS674 – JUNE 2017 www.ti.com 7 Application Schematic P12V AVSP TPS53679 AVSN VIN PWM PWM1 ASKIP# P5V BOOT BOOT_R CSD95481RWJ EN/FCCM VOS VSW VDD PVDD LSET TAO LOAD PGND IOUT REFIN ACSP1 TSEN P12V VIN PWM APWM6 VREF P5V ADDR BOOT BOOT_R CSD95481RWJ EN/FCCM VOS VSW VDD PVDD LSET TAO PGND IOUT REFIN 3.3 V V3P3 ACSP6 VREF P12V VIN_CSNIN CSPIN VCCIO BEN_VCCIO SCLK SDIO SALERT# PIN_ALT# VR_HOT# SMB_CLK SMB_ALERT # SMB_DIO AVR_RDY BVR_RDY AVR_EN VR_FAULT# RESET# BVSN BVSP P12V VIN PWM BPWM1 BSKIP# P5V BOOT BOOT_R CSD95492QVM EN/FCCM VOS VSW VDD PVDD LSET TAO LOAD PGND IOUT REFIN BCSP1 AGND Copyright © 2016, Texas Instruments Incorporated Figure 1. Application Schematic Note: The schematic in Figure 1 is a conceptual drawing only. Actual designs may require additional components not shown. 6 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: CSD95481RWJ CSD95481RWJ www.ti.com SLPS674 – JUNE 2017 8 Device and Documentation Support 8.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 8.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 8.3 Trademarks NexFET, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 8.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 8.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: CSD95481RWJ 7 CSD95481RWJ SLPS674 – JUNE 2017 www.ti.com 9 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 9.1 Mechanical Drawing 5.1 4.9 B A PIN 1 INDEX AREA 6.1 5.9 C 1.05 MAX 10 2.225 0.1 TYP 9 0.3 0.2 13X 20 1.95 0.8 0.1 0.4 0.1 0.1 0.1 19 2.05 1.3 0.1 0.9 0.1 2.6 0.1 2.2 0.1 (0.203) TYP 0.05 0.00 0.3 10X 0.2 9X 0.45 0.13 TYP 2.025 0.000 PKG 1.75 0.1 SEATING PLANE 0.08 7 10X 0.45 R0.05 TYP 41 24 0.000 PKG 6 0.3 0.1 25 16X 2.25 0.1 30 39 14X 0.45 0.4 0.1 PIN 1 ID (45 X0.3) 2.175 29 1 16X 2.05 2.275 0.45 0.35 40 0.3 0.2 0.1 0.05 C A B 4221590/C 01/2017 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pads must be soldered to the printed circuit board for optimal thermal and mechanical performance. 8 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: CSD95481RWJ CSD95481RWJ www.ti.com SLPS674 – JUNE 2017 16X (0.6) 39 (2.7) TYP (2.22) TYP 2X (2.11) 3X (1.15) (0.4) (0.2) 0.000 3X (0.875) (1.75) (1.55) (2) (2.4) 9.2 Recommended PCB Land Pattern METAL UNDER SOLDER MASK TYP 30 (2.9) 16X (0.25) 1 (2.25) 29 (2.25) (2.175) (2.05) SOLDER MASK OPENING, TYP (1.275) 40 14X (0.45) (0.5) 25 (0.3) (0.025) (0.1) (0.4) (0.3) 0.000 PKG 6 24 41 (0.3) (R0.05) TYP (0.8) 7 (1.05) 5X (1.15) 19X (0.45) ( 0.2) VIA TYP 9 20 (2.2) (0.05) MIN TYP 5X (2) (2.05) (2.6) (2.75) TYP (3.2) TYP 19 10 (2.225) TYP 20X (0.25) 3X (2) (2.025) 3X (1) (0.9) 2X (1) (1.3) (1.75) 2X (2) (2.225) TYP (2.7) TYP PKG LAND PATTERN EXAMPLE 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This package is designed to be soldered to thermal pads on the board. For more information, see QFN/SON PCB Attachment (SLUA271). Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: CSD95481RWJ 9 CSD95481RWJ SLPS674 – JUNE 2017 www.ti.com 29X (0.6) (2.4) TYP 2X (1.9) 2X (1.05) 2X (1.25) 2X (0.42) 2X (0.085) 0.000 PKG 2X (0.775) 2X (0.975) 2X (1.665) (2) (2.4) TYP 9.3 Recommended Stencil Opening 30 39 29X (0.25) EXPOSED METAL 1 29 24X (0.45) 4X (1.375) 4X (1.175) 40 EXPOSED METAL SOLDER MASK OPENING TYP (0.025) 25 6 (0.1) (0.4) 41 (0.84) 24 7 (R0.05) TYP (0.375) 4X (0.305) 0.000 PKG 3X (0.13) (0.25) 3X (1.05) 3X (1.25) (1.3) (1.75) (1.05) 4X (2.245) 9 20 EXPOSED METAL 4X (2.17) (2.6) (2.75) TYP METAL UNDER SOLDER MASK TYP 10 (3.2) TYP 19 (2.025) 2X (1.9) 2X (0.9) 2X (1.1) 2X (0.1) 2X (0.1) 9X (0.45) (1.1) 2X (0.9) (1.9) 10X (0.25) SOLDER PAST EXAMPLE BASED ON 0.125 mm THICK STENCIL PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 10 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: CSD95481RWJ PACKAGE OPTION ADDENDUM www.ti.com 17-Sep-2017 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) CSD95481RWJ ACTIVE VQFN-CLIP RWJ 41 2500 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -55 to 150 95481RWJ CSD95481RWJT ACTIVE VQFN-CLIP RWJ 41 250 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -55 to 150 95481RWJ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. 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Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 17-Sep-2017 Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 15-Sep-2017 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant CSD95481RWJ VQFNCLIP RWJ 41 2500 330.0 12.4 5.3 6.3 1.2 8.0 12.0 Q1 CSD95481RWJT VQFNCLIP RWJ 41 250 180.0 12.4 5.3 6.3 1.2 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 15-Sep-2017 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CSD95481RWJ VQFN-CLIP RWJ 41 2500 370.0 355.0 55.0 CSD95481RWJT VQFN-CLIP RWJ 41 250 195.0 200.0 45.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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