TI1 DS10CP152 1.5 gbps 2x2 lvds crosspoint switch Datasheet

DS10CP152
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SNLS261E – OCTOBER 2007 – REVISED APRIL 2013
DS10CP152 1.5 Gbps 2X2 LVDS Crosspoint Switch
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FEATURES
DESCRIPTION
•
The DS10CP152 is a 1.5 Gbps 2x2 LVDS crosspoint
switch optimized for high-speed signal routing and
switching over lossy FR-4 printed circuit board
backplanes and balanced cables. Fully differential
signal paths ensure exceptional signal integrity and
noise immunity. The non-blocking architecture allows
connections of any input to any output or outputs.
1
2
•
•
•
•
•
DC - 1.5 Gbps Low Jitter, Low Skew, Low
Power Operation
Pin Configurable, Fully Differential, NonBlocking Architecture
Wide Input Common Mode Voltage Range
Allows DC-Coupled Interface to LVDS, CML
and LVPECL Drivers
On-chip 100Ω Input and Output Termination
Minimizes Insertion and Return Losses,
Reduces Component Count and Minimizes
Board Space
7 kV ESD on LVDS I/O Pins Protects Adjoining
Components
Small SOIC-16 Space Saving Package
Wide input common mode range allows the switch to
accept signals with LVDS, CML and LVPECL levels;
the output levels are LVDS. A very small package
footprint requires a minimal space on the board while
the flow-through pinout allows easy board layout.
Each differential input and output is internally
terminated with a 100Ω resistor to lower device return
losses, reduce component count and further minimize
board space.
APPLICATIONS
•
•
•
High-Speed Channel Select Applications
Clock and Data Buffering and Muxing
SD/HD SDI Routers
Typical Application
INPUT CARD
SD/HD
Adaptive Equalizer
OUTPUT CARD
BACKPLANES
DS10CP152
2 x 2 LVDS
Crosspoint Switch
DS10CP152
2 x 2 LVDS
Crosspoint Switch
SD/HD
Reclocker +
Cable Driver
SD/HD
Adaptive Equalizer
SD/HD
Reclocker +
Cable Driver
SD/HD
Adaptive Equalizer
SD/HD
Reclocker +
Cable Driver
DS10CP152
2 x 2 LVDS
Crosspoint Switch
DS10CP152
2 x 2 LVDS
Crosspoint Switch
SD/HD
Adaptive Equalizer
SD/HD
Reclocker +
Cable Driver
Large
(e.g. 128 x 128)
Crosspoint Switch
CROSSPOINT
CARD
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2013, Texas Instruments Incorporated
DS10CP152
SNLS261E – OCTOBER 2007 – REVISED APRIL 2013
www.ti.com
Block Diagram
SEL1
SEL0
EN0
IN0+
OUT0+
OUT0-
IN02x2
EN1
IN1+
OUT1+
IN1-
OUT1-
Connection Diagram
DS10CP152 Pin Diagram
See Package Number D (R-PDSO-G16)
PIN DESCRIPTIONS
Pin Name
Pin
Number
IN0+, IN0- ,
IN1+, IN1-
I/O, Type
Pin Description
3, 4,
6, 7
I, LVDS
Inverting and non-inverting high speed LVDS input pins.
OUT0+, OUT0-,
OUT1+, OUT1-
14, 13,
11, 10
O, LVDS
Inverting and non-inverting high speed LVDS output pins.
SEL1, SEL0
1, 2
I, LVCMOS
Switch configuration pins.
EN0, EN1
16, 15
I, LVCMOS
Output enable pins.
NC
8, 9
NC
"NO CONNECT" pins.
VDD
5
Power
Power supply pin.
GND
12
Power
Ground pin.
2
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SNLS261E – OCTOBER 2007 – REVISED APRIL 2013
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings
(1) (2)
−0.3V to +4V
Supply Voltage
−0.3V to (VCC + 0.3V)
LVCMOS Input Voltage
−0.3V to +4V
LVDS Input Voltage
Differential Input Voltage |VID|
1V
−0.3V to (VCC + 0.3V)
LVDS Output Voltage
LVDS Differential Output Voltage
0V to 1V
LVDS Output Short Circuit Current Duration
5 ms
Junction Temperature
+150°C
−65°C to +150°C
Storage Temperature Range
Lead Temperature Range
Soldering (4 sec.)
+260°C
Maximum Package Power Dissipation at 25°C
D Package
1.72W
Derate D Package
13.75 mW/°C above +25°C
Package Thermal Resistance
θJA
+72.7°C/W
θJC
+41.2°C/W
ESD Susceptibility
HBM
MM
(2)
(3)
(4)
(5)
≥7 kV
(4)
CDM
(1)
(3)
≥250V
(5)
≥1250V
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
Human Body Model, applicable std. JESD22-A114C
Machine Model, applicable std. JESD22-A115-A
Field Induced Charge Device Model, applicable std. JESD22-C101-C
Recommended Operating Conditions
Supply Voltage (VCC)
Receiver Differential Input Voltage (VID)
Operating Free Air Temperature (TA)
Min
Typ
Max
Units
3.0
3.3
3.6
V
1
V
+25
+85
°C
0
−40
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DC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
(1) (2) (3)
Min
Typ
Max
Units
V
LVCMOS DC SPECIFICATIONS
VIH
High Level Input Voltage
2.0
VDD
VIL
Low Level Input Voltage
GND
0.8
V
IIH
High Level Input Current
VIN = 3.6V
VCC = 3.6V
175
250
μA
IIL
Low Level Input Current
VIN = GND
VCC = 3.6V
±1
±10
μA
VCL
Input Clamp Voltage
ICL = −18 mA, VCC = 0V
−0.9
−1.5
V
1
V
0
+100
mV
40
LVDS INPUT DC SPECIFICATIONS
VID
Input Differential Voltage
VTH
Differential Input High Threshold
0
VTL
Differential Input Low Threshold
VCMR
Common Mode Voltage Range
VID = 100 mV
IIN
Input Current
VIN = 3.6V or 0V
VCC = 3.6V or 0V
CIN
Input Capacitance
Any LVDS Input Pin to GND
1.7
pF
RIN
Input Termination Resistor
Between IN+ and IN-
100
Ω
VCM = +0.05V or VCC-0.05V
−100
0
0.05
±1
mV
VCC 0.05
V
±10
μA
LVDS OUTPUT DC SPECIFICATIONS
VOD
Differential Output Voltage
ΔVOD
Change in Magnitude of VOD for Complimentary
Output States
250
VOS
Offset Voltage
ΔVOS
Change in Magnitude of VOS for Complimentary
Output States
IOS
Output Short Circuit Current
RL = 100Ω
-35
1.05
(4)
350
RL = 100Ω
1.2
-35
450
mV
35
mV
1.375
V
35
mV
OUT to GND
-23
-55
mA
OUT to VCC
8
55
mA
COUT
Output Capacitance
Any LVDS Output Pin to GND
1.2
pF
ROUT
Output Termination Resistor
Between OUT+ and OUT-
100
Ω
SUPPLY CURRENT
ICC
Supply Current
EN0 = EN1 = H
58
70
mA
ICCZ
Outputs Powered Down Supply Current
EN0 = EN1 = L
25
30
mA
(1)
(2)
(3)
(4)
4
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground
except VOD and ΔVOD.
Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions
at the time of product characterization and are not ensured.
Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.
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SNLS261E – OCTOBER 2007 – REVISED APRIL 2013
AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
(1) (2)
Min
Typ
Max
Units
440
650
ps
400
650
ps
LVDS OUTPUT AC SPECIFICATIONS
tPLHD
Differential Propagation Delay Low to
High (3)
tPHLD
Differential Propagation Delay High to
Low (3)
tSKD1
Pulse Skew |tPLHD − tPHLD|
40
120
ps
tSKD2
Channel to Channel Skew
25
60
ps
tSKD3
Part to Part Skew
45
190
ps
tLHT
Rise Time
170
350
ps
170
350
ps
RL = 100Ω
(3) (4)
(3) (5)
(3) (6)
(3)
RL = 100Ω
(3)
tHLT
Fall Time
tON
Output Enable Time
5
20
μs
tOFF
Output Disable Time
3
12
ns
tSEL
Select Time
3
12
ns
135 MHz
0.5
1.2
ps
311 MHz
0.5
1.2
ps
503 MHz
0.5
1.2
ps
750 MHz
0.5
1.2
ps
270 Mbps
9
38
ps
622 Mbps
7
36
ps
1.06 Gbps
7
34
ps
1.5 Gbps
9
35
ps
270 Mbps
0.01
0.03
UIP-P
622 Mbps
0.01
0.04
UIP-P
1.06 Gbps
0.01
0.05
UIP-P
1.5 Gbps
0.01
0.07
UIP-P
JITTER PERFORMANCE
(3)
tRJ1
tRJ2
tRJ3
Random Jitter (RMS Value)
VID = 350 mV
VCM = 1.2V
Clock (RZ)
(7)
tRJ4
tDJ1
tDJ2
tDJ3
Deterministic Jitter (Peak-to-Peak
Value ) (8)
VID = 350 mV
VCM = 1.2V
Clock (RZ)
tDJ4
tTJ1
tTJ2
tTJ3
Total Jitter (Peak to Peak Value)
tTJ4
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(9)
VID = 350 mV
VCM = 1.2V
PRBS-23 (NRZ)
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions
at the time of product characterization and are not ensured.
Specification is ensured by characterization and is not tested in production.
tSKD1, |tPLHD − tPHLD|, Pulse Skew, is the magnitude difference in differential propagation delay time between the positive going edge and
the negative going edge of the same channel.
tSKD2, Channel to Channel Skew, is the difference in propagation delay (tPLHD or tPHLD) among all output channels in Broadcast mode
(any one input to all outputs).
tSKD3, Part to Part Skew, is defined as the difference between the minimum and maximum differential propagation delays. This
specification applies to devices at the same VCC and within 5°C of each other within the operating temperature range.
Measured on a clock edge with a histogram and an accumulation of 1500 histogram hits. Input stimulus jitter is subtracted geometrically.
Tested with a combination of the 1100000101 (K28.5+ character) and 0011111010 (K28.5- character) patterns. Input stimulus jitter is
subtracted algebraically.
Measured on an eye diagram with a histogram and an accumulation of 3500 histogram hits. Input stimulus jitter is subtracted.
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DS10CP152
SNLS261E – OCTOBER 2007 – REVISED APRIL 2013
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DC Test Circuits
VOH
Power Supply
OUT+
IN+
R
D
RL
Power Supply
IN-
OUTVOL
Figure 1.
AC Test Circuits and Timing Diagrams
OUT+
IN+
R
Signal Generator
D
IN-
RL
OUT-
Figure 2.
Figure 3.
Figure 4.
6
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DS10CP152
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SNLS261E – OCTOBER 2007 – REVISED APRIL 2013
FUNCTIONAL DESCRIPTION
The DS10CP152 is a 1.5 Gbps 2x2 LVDS digital crosspoint switch optimized for high-speed signal routing and
switching over lossy FR-4 printed circuit board backplanes and balanced cables.
Table 1. Switch Configuration Truth Table
SEL1
SEL0
OUT1
OUT0
0
0
IN0
IN0
0
1
IN0
IN1
1
0
IN1
IN0
1
1
IN1
IN1
Table 2. Output Enable Truth Table
EN1
EN0
OUT1
OUT0
0
0
Disabled
Disabled
0
1
Disabled
Enabled
1
0
Enabled
Disabled
1
1
Enabled
Enabled
Input Interfacing
The DS10CP152 accepts differential signals and allows simple AC or DC coupling. With a wide common mode
range, the DS10CP152 can be DC-coupled with all common differential drivers (i.e. LVPECL, LVDS, CML). The
following three figures illustrate typical DC-coupled interface to common differential drivers. Note that the
DS10CP152 inputs are internally terminated with a 100Ω resistor.
LVDS
Driver
DS10CP152
Receiver
100: Differential T-Line
OUT+
IN+
100:
IN-
OUT-
Figure 5. Typical LVDS Driver DC-Coupled Interface to an DS10CP152 Input
CML3.3V or CML2.5V
Driver
VCC
50:
DS10CP152
Receiver
100: Differential T-Line
50:
OUT+
IN+
100:
IN-
OUT-
Figure 6. Typical CML Driver DC-Coupled Interface to an DS10CP152 Input
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DS10CP152
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LVPECL
Driver
OUT+
www.ti.com
100: Differential T-Line
LVDS
Receiver
IN+
100:
OUT150-250:
IN150-250:
Figure 7. Typical LVPECL Driver DC-Coupled Interface to an DS10CP152 Input
Output Interfacing
The DS10CP152 outputs signals compliant to the LVDS standard. Its outputs can be DC-coupled to most
common differential receivers. The following figure illustrates typical DC-coupled interface to common differential
receivers and assumes that the receivers have high impedance inputs. While most differential receivers have a
common mode input range that can accommodate LVDS compliant signals, it is recommended to check
respective receiver's data sheet prior to implementing the suggested interface implementation.
DS10CP152
Driver
Differential
Receiver
100: Differential T-Line
OUT+
IN+
CML or
LVPECL or
LVDS
100:
100:
IN-
OUT-
Figure 8. Typical DS10CP152 Output DC-Coupled Interface to an LVDS, CML or LVPECL Receiver
8
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DS10CP152
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Typical Performance Characteristics
Figure 9. A 270 Mbps NRZ PRBS-7 After 2"
Differential FR-4 Stripline
V:100 mV / DIV, H:500 ps / DIV
Figure 10. A 622 Mbps NRZ PRBS-7 After 2"
Differential FR-4 Stripline
V:100 mV / DIV, H:200 ps / DIV
Figure 11. A 1.06 Gbps NRZ PRBS-7 After 2"
Differential FR-4 Stripline
V:100 mV / DIV, H:200 ps / DIV
Figure 12. A 1.5 Gbps NRZ PRBS-7 After 2"
Differential FR-4 Stripline
V:100 mV / DIV, H:100 ps / DIV
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SNLS261E – OCTOBER 2007 – REVISED APRIL 2013
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REVISION HISTORY
Changes from Revision D (April 2013) to Revision E
•
10
Page
Changed layout of National Data Sheet to TI format ............................................................................................................ 9
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PACKAGE OPTION ADDENDUM
www.ti.com
12-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
DS10CP152TMA/NOPB
ACTIVE
SOIC
D
16
48
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
DS10CP152
TMA
DS10CP152TMAX/NOPB
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
DS10CP152
TMA
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
DS10CP152TMAX/NOPB
Package Package Pins
Type Drawing
SOIC
D
16
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
16.4
Pack Materials-Page 1
6.5
B0
(mm)
K0
(mm)
P1
(mm)
10.3
2.3
8.0
W
Pin1
(mm) Quadrant
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DS10CP152TMAX/NOPB
SOIC
D
16
2500
367.0
367.0
35.0
Pack Materials-Page 2
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