Dallas DS3152 Single/dual/triple/quad ds3/e3/sts-1 lius Datasheet

DEMO KIT AVAILABLE
DS3151/DS3152/DS3153/DS3154
Single/Dual/Triple/Quad
DS3/E3/STS-1 LIUs
www.maxim-ic.com
GENERAL DESCRIPTION
FEATURES
The DS3151 (single), DS3152 (dual), DS3153
(triple), and DS3154 (quad) line interface units (LIUs)
perform the functions necessary for interfacing at the
physical layer to DS3, E3, or STS-1 lines. Each LIU
has independent receive and transmit paths and a
built-in jitter attenuator.
§
Single, Dual, Triple, or Quad Integrated
Transmitter, Receiver, and Jitter Attenuators for
DS3, E3, and STS-1
Each Port Independently Configurable
Perform Receive Clock/Data Recovery and
Transmit Waveshaping
Hardware or CPU Bus Configuration Options
Jitter Attenuators can be Placed in Either the
Receive or Transmit Paths
Interface to 75W Coaxial Cable at Lengths Up to
380m (DS3), 440m (E3), or 360m (STS-1)
Use 1:2 Transformers on Tx and Rx
Require Minimal External Components
Local and Remote Loopbacks
Low-Power 3.3V Operation (5V Tolerant I/O)
Industrial Temperature Range:
-40°C to +85°C
Small Package: 144-Pin, 13mm x 13mm
Thermally Enhanced CSBGA
IEEE 1149.1 JTAG Support
§
§
§
§
APPLICATIONS
SONET/SDH and PDH Multiplexers
Digital Cross-Connects
Access Concentrators
ATM and Frame Relay Equipment
Routers
PBXs
DSLAMs
CSUs/DSUs
§
§
§
§
§
§
§
FUNCTIONAL DIAGRAM
§
EACH LIU
LINE IN
DS3, E3,
OR STS-1
LINE OUT
DS3, E3,
OR STS-1
RXP
RXN
CLK
DATA
Dallas
Semiconductor
DS315x
TXP
TXN
CLK
DATA
Features continued on page 5.
RECEIVE
CLOCK
AND DATA
CONTROL
STATUS
TRANSMIT
CLOCK
AND DATA
ORDERING INFORMATION
PART
DS3151
DS3151N
DS3152
DS3152N
DS3153
DS3153N
DS3154
DS3154N
LIUs
TEMP RANGE
PIN-PACKAGE
1
1
2
2
3
3
4
4
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
144 TE-CSBGA
144 TE-CSBGA
144 TE-CSBGA
144 TE-CSBGA
144 TE-CSBGA
144 TE-CSBGA
144 TE-CSBGA
144 TE-CSBGA
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
TABLE OF CONTENTS
1.
DETAILED DESCRIPTION.................................................................................................5
2.
APPLICATIONS .................................................................................................................7
3.
HARDWARE MODE AND CPU BUS MODE......................................................................8
4.
PIN DESCRIPTIONS ........................................................................................................10
5.
REGISTER DESCRIPTIONS ............................................................................................15
6.
RECEIVER........................................................................................................................22
7.
TRANSMITTER ................................................................................................................25
8.
DIAGNOSTICS .................................................................................................................28
9.
JITTER ATTENUATOR ....................................................................................................29
10.
RESET LOGIC..................................................................................................................30
11.
TRANSFORMERS............................................................................................................31
12.
JTAG TEST ACCESS PORT AND BOUNDARY SCAN ..................................................32
13.
ELECTRICAL CHARACTERISTICS ................................................................................37
14.
PIN ASSIGNMENTS.........................................................................................................46
15.
PACKAGE INFORMATION..............................................................................................59
16.
THERMAL INFORMATION ..............................................................................................60
17.
REVISION HISTORY ........................................................................................................60
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DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
LIST OF FIGURES
Figure 1-1. External Connections ............................................................................................................ 7
Figure 2-1. 4-Port Unchannelized DS3/E3 Card ...................................................................................... 7
Figure 3-1. Hardware Mode Block Diagram ............................................................................................. 8
Figure 3-2. CPU Bus Mode Block Diagram.............................................................................................. 9
Figure 5-1. Status Register Logic .......................................................................................................... 16
Figure 6-1. Receiver Jitter Tolerance..................................................................................................... 24
Figure 7-1. E3 Waveform Template....................................................................................................... 27
Figure 7-2. DS3 AIS Structure ............................................................................................................... 28
Figure 8-1. PRBS Output with Normal RCLK Operation ........................................................................ 29
Figure 8-2. PRBS Output with Inverted RCLK Operation....................................................................... 29
Figure 9-1. Jitter Attenuation/Jitter Transfer........................................................................................... 30
Figure 12-1. JTAG Block Diagram ......................................................................................................... 32
Figure 12-2. JTAG TAP Controller State Machine ................................................................................. 33
Figure 13-1. Transmitter Framer Interface Timing Diagram ................................................................... 38
Figure 13-2. Receiver Framer Interface Timing Diagram ....................................................................... 39
Figure 13-3. CPU Bus Timing Diagram (Nonmultiplexed) ...................................................................... 41
Figure 13-4. CPU Bus AC Timing Diagram (Multiplexed)....................................................................... 43
Figure 13-5. JTAG Timing Diagram ....................................................................................................... 45
Figure 14-1. DS3151 Hardware Mode Pin Assignment.......................................................................... 51
Figure 14-2. DS3151 CPU Bus Mode Pin Assignment .......................................................................... 52
Figure 14-3. DS3152 Hardware Mode Pin Assignment.......................................................................... 53
Figure 14-4. DS3152 CPU Bus Mode Pin Assignment .......................................................................... 54
Figure 14-5. DS3153 Hardware Mode Pin Assignment.......................................................................... 55
Figure 14-6. DS3153 CPU Bus Mode Pin Assignment .......................................................................... 56
Figure 14-7. DS3154 Hardware Mode Pin Assignment.......................................................................... 57
Figure 14-8. DS3154 CPU Bus Mode Pin Assignment .......................................................................... 58
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DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
LIST OF TABLES
Table 1-A. Applicable Telecommunications Standards ............................................................................ 6
Table 4-A. Active I/O Pins—Hardware and CPU Bus Modes................................................................. 10
Table 4-B. Transmitter Pin Descriptions ................................................................................................ 11
Table 4-C. Receiver Pin Descriptions .................................................................................................... 12
Table 4-D. Global Pin Descriptions........................................................................................................ 13
Table 4-E. JTAG and Test Pin Descriptions .......................................................................................... 14
Table 4-F. Transmitter Data Select Options........................................................................................... 14
Table 4-G. Receiver PRBS Pattern Select Options................................................................................ 14
Table 5-A. Register Map........................................................................................................................ 15
Table 7-A. DS3 Waveform Template ..................................................................................................... 26
Table 7-B. DS3 Waveform Test Parameters and Limits......................................................................... 26
Table 7-C. STS-1 Waveform Template.................................................................................................. 26
Table 7-D. STS-1 Waveform Test Parameters and Limits ..................................................................... 27
Table 7-E. E3 Waveform Test Parameters and Limits ........................................................................... 27
Table 11-A. Transformer Characteristics ............................................................................................... 31
Table 11-B. Recommended Transformers............................................................................................. 31
Table 12-A. JTAG Instruction Codes ..................................................................................................... 35
Table 12-B. JTAG ID Code.................................................................................................................... 35
Table 13-A. Recommended DC Operating Conditions........................................................................... 37
Table 13-B. DC Characteristics ............................................................................................................. 37
Table 13-C. Framer Interface Timing..................................................................................................... 38
Table 13-D. Receiver Input Characteristics—DS3 and STS-1 Modes.................................................... 39
Table 13-E. Receiver Input Characteristics—E3 Mode .......................................................................... 39
Table 13-F. Transmitter Output Characteristics—DS3 and STS-1 Modes ............................................. 40
Table 13-G. Transmitter Output Characteristics—E3 Mode ................................................................... 40
Table 13-H. CPU Bus Timing ................................................................................................................ 40
Table 13-I. JTAG Interface Timing......................................................................................................... 45
Table 14-A. Pin Assignments Sorted by Signal Name ........................................................................... 46
Table 14-B. Pin Assignments Sorted by Pin Number............................................................................. 48
Table 16-A. Thermal Properties, Natural Convection............................................................................. 60
Table 16-B. Theta-JA (qJA) vs. Airflow.................................................................................................... 60
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DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
FEATURES (continued)
Receiver
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§
§
§
§
§
§
§
AGC/equalizer block handles from 0 to 15dB of cable loss
Loss-of-lock (LOL) PLL status indication
Interfaces directly to a DSX monitor signal (~20dB flat loss) using built-in preamp
Digital and analog loss-of-signal (LOS) detectors (ANSI T1.231 and ITU G.775)
Optional B3ZS/HDB3 decoder
Line-code violation output pin and counter
Binary or bipolar framer interface
15
23
On-board 2 - 1 and 2 - 1 PRBS detector
Clock inversion for glueless interfacing
Tri-state clock and data outputs support protection switching applications
Per-channel power-down control
Transmitter
§
§
§
§
§
§
§
§
§
§
§
§
Binary or bipolar framer interface
Gapped clock capable up to 51.84MHz
Wide 50 ±20% transmit clock duty cycle
Clock inversion for glueless interfacing
Optional B3ZS/HDB3 encoder
15
23
On-board 2 - 1 and 2 - 1 PRBS generator
Complete DS3 AIS generator (ANSI T1.107)
Unframed all-ones generator (E3 AIS)
Line build-out (LBO) control
Tri-state line driver outputs support protection switching applications
Per-channel power-down control
Output driver monitor
1. DETAILED DESCRIPTION
The DS3151 (single), DS3152 (dual), DS3153 (triple), and DS3154 (quad) LIUs perform the functions necessary
for interfacing at the physical layer to DS3, E3, or STS-1 lines. Each LIU has independent receive and transmit
paths and a built-in jitter attenuator. The receiver performs clock and data recovery from a B3ZS- or HDB3-coded
alternate mark inversion (AMI) signal and monitors for loss of the incoming signal. The receiver optionally performs
B3ZS/HDB3 decoding and outputs the recovered data in either binary or bipolar format. The transmitter accepts
data in either binary or bipolar format, optionally performs B3ZS/HDB3 encoding, and drives standard pulse-shape
waveforms onto 75W coaxial cable. The jitter attenuator can be mapped into the receiver data path, mapped into
the transmitter data path, or be disabled. The DS315x LIUs conform to the telecommunications standards listed in
Table 1-A. Figure 1-1 shows the external components required for proper operation.
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DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
Table 1-A. Applicable Telecommunications Standards
SPECIFICATION
T1.102-1993
T1.107-1995
T1.231-1997
T1.404-1994
G.703
G.751
G.775
G.823
G.824
O.151
ETS 300 686
ETS 300 687
ETS EN 300 689
TBR 24
GR-253-CORE
GR-499-CORE
SPECIFICATION TITLE
ANSI
Digital Hierarchy—Electrical Interfaces
Digital Hierarchy—Formats Specification
Digital Hierarchy—Layer 1 In-Service Digital Transmission Performance Monitoring
Network-to-Customer Installation—DS3 Metallic Interface Specification
ITU-T
Physical/Electrical Characteristics of Hierarchical Digital Interfaces, 1991
Digital Multiplex Equipment Operating at the Third-Order Bit Rate of 34,368kbps and the
Fourth-Order Bit Rate of 139,264kbps and Using Positive Justification, 1993
Loss of Signal (LOS) and Alarm Indication Signal (AIS) Defect Detection and Clearance
Criteria, November 1994
The Control of Jitter and Wander within Digital Networks that are Based on the 2048kbps
Hierarchy, 1993
The Control of Jitter and Wander within Digital Networks that are Based on the 1544kbps
Hierarchy, 1993
Error Performance Measuring Equipment Operating at the Primary Rate and Above,
October 1992
ETSI
Business TeleCommunications; 34Mbps and 140Mbps Digital Leased Lines (D34U,
D34S, D140U, and D140S); Network Interface Presentation, 1996
Business TeleCommunications; 34Mbps Digital Leased Lines (D34U and D34S);
Connection Characteristics, 1996
Access and Terminals (AT); 34Mbps Digital Leased Lines (D34U and D34S); Terminal
equipment interface, July 2001
Business TeleCommunications; 34Mbps Digital Unstructured and Structured Lease Lines;
Attachment Requirements for Terminal Equipment Interface, 1997
TELCORDIA
SONET Transport Systems: Common Generic Criteria, Issue 2, December 1995
Transport Systems Generic Requirements (TSGR): Common Requirements, Issue 1,
December 1998
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DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
Figure 1-1. External Connections
TRANSMIT
EACH LIU
TXP
0.05mF
VDD
VDD
330W
(1%)
0.01mF
0.1mF
1mF
0.01mF
0.1mF
1mF
0.01mF
0.1mF
1mF
(OPTIONAL)
VDD
TXN
1:2ct
Dallas
Semiconductor
DS315x
RECEIVE
VSS
RXP
0.05mF
3.3V
POWER
PLANE
GROUND
PLANE
VSS
330W
(1%)
(OPTIONAL)
RXN
VSS
1:2ct
2. APPLICATIONS
DS3154
DS3144
QUAD
DS3/E3/STS-1
LIU
QUAD
DS3/E3
FRAMER
BACKPLANE
Figure 2-1. 4-Port Unchannelized DS3/E3 Card
Shorthand Notations. The notation “DS315x” throughout this data sheet refers to either the DS3151, DS3152,
DS3153, or DS3154. This data sheet is the specification for all four parts. The LIUs on the DS315x are identical.
For brevity, this document uses the pin name and register name shorthand “NAMEn,” where “n” stands in place of
the LIU port number. For example, on the DS3154 quad LIU, TCLKn is shorthand notation for pins TCLK1, TCLK2,
TCLK3, and TCLK4 on LIU ports 1, 2, 3, and 4, respectively. This document also uses generic pin and register
names such as TCLK (without a number suffix) when describing LIU operation. When working with a specific LIU
on the DS315x devices, generic names like TCLK should be converted to actual pin names, such as TCLK1.
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DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
3. HARDWARE MODE AND CPU BUS MODE
The DS315x can operate in either hardware mode or CPU bus mode. In hardware mode, pulling configuration input
pins high or low does all configuration, and all status information is reported on status output pins. Internal registers
are not accessible in hardware mode. The device is configured for hardware mode when the HW pin is wired high
(HW = 1).
In CPU bus mode, most of the configuration and status pins used in hardware mode are reassigned to be address,
data, and control lines that provide a glueless interface to an 8-bit microprocessor bus. Through the CPU bus, an
external processor can access a set of internal registers. Setting configuration register bits high or low can do
configuration, and status information can be read from status register bits. Events indicated by status register bits
can also activate the interrupt output pin (INT), if configured to do so by a set of interrupt-enable bits. A few
configuration and status pins are active in hardware mode and CPU bus mode to support specialized applications,
such as protection switching. The device is configured for CPU bus mode when the HW pin is wired low (HW = 0).
With the exception of the HW pin, configuration and status pins available in hardware mode have corresponding
register bits in the CPU bus mode. The hardware mode pins and the CPU bus mode register bits have identical
names and functions, with the exception that all register bits are active high. For example, LOS is indicated by the
receiver on the RLOS pin (active low) in hardware mode and the RLOS register bit (active high) in CPU bus mode.
The few configuration input pins that are active in CPU bus mode also have corresponding register bits. In these
cases, the actual configuration is the logical OR of pin assertion and register bit assertion. For example, the
transmitter output driver is tri-stated if the TTS pin is asserted (i.e., low) or the TTS register bit is asserted (high).
Figure 3-1 and Figure 3-2 show block diagrams of the DS315x in hardware mode and in CPU bus mode. Table 4-A
lists the pins that are active in each mode.
Figure 3-1. Hardware Mode Block Diagram
RMONn T3MCLK E3MCLK STMCLK
squelch
Analog
Local
Loopback
Waveshaping
TXNn
Line Driver
TXPn
Driver
Monitor
LLBn
RLBn
TLBOn
TJAn
Global
Configuration
TBIN
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RPOSn/RDATn
RNEGn/RLCVn
RCLKn
RCINV
Digital
Local
Loopback
Loopback Control
TTSn
Output
Drivers,
Clock
Invert
Remote
Loopback
B3ZS/
HDB3
Encoder
PRBSn
RTSn
Mux
Clock &
Data
Recovery
ALOS
TDMn
PRBS
Detector
B3ZS/HDB3
Decoder
Automatic
Gain
Control
+
Adaptive
Equalizer
Preamp
RXNn
Digital LOS
Detector
Clock Mux
RXPn
RBIN
Clock
Invert
Mux
Power
Supply
Mux
VSS
Jitter Attenuator
(can be placed in either the receive path or the transmit path)
VDD
RLOSn
RJAn
AIS, 100100…,
PRBS Pattern
Generation
TDSAn,
TDSBn
HIZ
RST
HW
E3Mn
STSn
TPOSn/TDATn
TNEGn
TCLKn
TCINV
Dallas
Semiconductor
DS315x
DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
Figure 3-2. CPU Bus Mode Block Diagram
RLOSn
T3MCLK E3MCLK STMCLK
Clock &
Data
Recovery
ALOS
squelch
Analog
Local
Loopback
Driver
Monitor
Line Driver
TXPn
TXNn
Waveshaping
TDMn
Output
Drivers,
Clock
Invert
Remote
Loopback
Digital
Local
Loopback
Loopback Control
TTSn
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CPU Bus
Interface
and
Global
Configuration
B3ZS/
HDB3
Encoder
PRBSn
RTSn
Mux
Preamp
RXNn
PRBS
Detector
B3ZS/HDB3
Decoder
Automatic
Gain
Control
+
Adaptive
Equalizer
RXPn
Digital LOS
Detector
Dallas
Semiconductor
DS315x
Clock Mux
Clock
Invert
Mux
Power
Supply
Mux
VSS
Jitter Attenuator
(can be placed in either the receive path or the transmit path)
VDD
AIS, 100100…,
PRBS Pattern
Generation
RPOSn/RDATn
RNEGn/RLCVn
RCLKn
HIZ
RST
HW
MOT
ALE
CS
WR/R/W
RD/DS
A[5:0]
D[7:0]
INT
TPOSn/TDATn
TNEGn
TCLKn
DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
4. PIN DESCRIPTIONS
Table 4-A. Active I/O Pins—Hardware and CPU Bus Modes
NAME
TYPE
TCLKn
TPOSn/TDATn
TNEGn
TXPn, TXNn
TTSn
TDMn
TDSAn, TDSBn
TLBOn
TJAn
I
I
I
O
I
O
I
I
I
RXPn, RXNn
RCLKn
RPOSn/RDATn
RNEGn/RLCVn
RTSn
RLOSn
RMONn
RJAn
I
O
O
O
I
O
I
I
HIZ
RST
HW
T3MCLK
E3MCLK
STMCLK
PRBSn
LLBn, RLBn
E3Mn, STSn
RBIN
TBIN
RCINV
TCINV
MOT
ALE
CS
WR / R/W
RD/DS
A[5:0]
D[7:0]
INT
I
I
I
I
I
I
O
I
I
I
I
I
I
I
I
I
I
I
I
I/O
O
FUNCTION
TRANSMITTER
Transmitter Clock
Transmitter Positive AMI/Transmitter Data
Transmitter Negative AMI
Transmitter Analog Outputs
Transmitter Tri-State Enable
Transmitter Driver Monitor Output
Transmitter Data Select
Transmitter Line Build-Out Enable
Transmitter Jitter Attenuator Enable
RECEIVER
Receiver Analog Inputs
Receiver Clock
Receiver Positive AMI/Receiver Data
Receiver Negative AMI/Line-Code Violation
Receiver Tri-State Enable
Receiver LOS Output
Receiver Monitor Enable
Receiver Jitter Attenuator Enable
GLOBAL
High-Z Enable
Reset Enable
Hardwired Mode Enable
T3 Master Clock (44.736MHz ±20ppm)
E3 Master Clock (34.368MHz ±20ppm)
STS-1 Master Clock (51.840MHz ±20ppm)
PRBS Detector Output
Local Loopback, Remote Loopback Select
E3 Mode Enable, STS-1 Mode Enable
Receiver Binary Interface Enable
Transmitter Binary Interface Enable
Receiver Clock Invert
Transmitter Clock Invert
Motorola CPU Bus Enable
Address Latch Enable
Chip Select
Write Enable / Read/Write Select
Read Enable/Data Strobe
Address Bus
Data Bus
Interrupt Output
HARDWARE
MODE
CPU BUS
MODE
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Note: In CPU bus mode, status/control pins are replaced by register bits. See Register Map in Section 5. For pin names of the form PINn,
n = LIU# = 1, 2, 3, or 4. PIN1 is on LIU 1, PIN2 is on LIU 2, etc.
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Table 4-B. Transmitter Pin Descriptions
NAME
I/O
TCLKn
I
TPOSn/
TDATn
I
TNEGn
I
TXPn,
TXNn
O3
TTSn
I
TDMn
O
TDSAn,
TDSBn
I
TLBOn
I
TJAn
I
FUNCTION
Transmitter Clock. A DS3 (44.736MHz ±20ppm), E3 (34.368MHz ±20ppm), or STS-1 (51.840MHz
±20ppm) clock should be applied at this signal. Data to be transmitted is clocked into the device at
TPOS/TDAT and TNEG either on the rising edge of TCLK (TCINV = 0) or the falling edge of TCLK
(TCINV = 1). See Section 7 for additional details.
Transmitter Positive AMI/Transmitter Data. When the transmitter is configured to have a bipolar
interface (TBIN = 0), a positive pulse is transmitted on the line when TPOS is high. When the
transmitter is configured to have a binary interface (TBIN = 1), the data on TDAT is transmitted after
B3ZS or HDB3 encoding. TPOS/TDAT is sampled either on the rising edge of TCLK (TCINV = 0) or
on the falling edge of TCLK (TCINV = 1).
Transmitter Negative AMI. When the transmitter is configured to have a bipolar interface (TBIN = 0), a
negative pulse is transmitted on the line when TNEG is high. When the transmitter is configured to
have a binary interface (TBIN = 1), TNEG is ignored and should be wired either high or low. TNEG is
sampled either on the rising edge of TCLK (TCINV = 0) or on the falling edge of TCLK (TCINV = 1).
Transmitter Analog Outputs. These differential AMI outputs are coupled to the outbound 75W coaxial
cable through a 2:1 step-down transformer (Figure 1-1). These outputs can be tri-stated using the TTS
pin or the TTS or TPS configuration bits.
Transmitter Tri-State Enable (Active Low). TTS tri-states the transmitter outputs (TXP and TXN). This
feature supports applications requiring LIU redundancy. Transmitter outputs from multiple LIUs can be
wire-ORed together, eliminating external switches. The transmitter continues to operate internally
when TTS is active.
0 = tri-state the transmitter output driver
1 = enable the transmitter output driver
Transmitter Driver Monitor (Active Low, Open Drain). TDM reports the status of the transmit driver
monitor. When the transmit driver monitor detects a faulty transmitter, TDM is driven low. TDM
requires an external pullup to VDD.
Transmitter Data Select. These inputs select the source of the transmit data. See Table 4-F for details.
Transmitter Line Build-Out Enable. TLBO indicates cable length for waveform shaping in DS3 and
STS-1 modes. TLBO is ignored for E3 mode and should be wired high or low.
0 = cable length ³ 225ft
1 = cable length < 225ft
Transmitter Jitter Attenuator Enable
0 = remove jitter attenuator from the transmitter path
1 = insert jitter attenuator into the transmitter path
(Note that TJA = 1 takes precedence over RJA = 1.)
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DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
Table 4-C. Receiver Pin Descriptions
NAME
RXPn,
RXNn
I/O
RCLKn
O3
RPOSn/
RDATn
O3
RNEGn/
RLCVn
O3
RTSn
I
RLOSn
O
RMONn
I
RJAn
I
I
FUNCTION
Receiver Analog Inputs. These differential AMI inputs are coupled to the inbound 75W coaxial cable
through a 1:2 step-up transformer (Figure 1-1).
Receiver Clock. The recovered clock is output on the RCLK pin. Recovered data is output on the
RPOS/RDAT and RNEG/RLCV pins on the falling edge of RCLK (RCINV = 0) or the rising edge of
RCLK (RCINV = 1). During a loss of signal (RLOS = 0), the RCLK output signal is derived from the
LIU’s master clock.
Receiver Positive AMI/Receiver Data. When the receiver is configured to have a bipolar interface
(RBIN = 0), RPOS pulses high for each positive AMI pulse received. When the receiver is
configured to have a binary interface (RBIN = 1), RDAT outputs decoded binary data. RPOS/RDAT
is updated either on the falling edge of RCLK (RCINV = 0) or the rising edge of RCLK (RCINV = 1).
Receiver Negative AMI/Line-Code Violation. When the receiver is configured to have a bipolar
interface (RBIN = 0), RNEG pulses high for each negative AMI pulse received. When the receiver is
configured to have a binary interface (RBIN = 1), RLCV pulses high to flag code violations. See
Section 6 for further details on code violations. RNEG/RLCV is updated either on the falling edge of
RCLK (RCINV = 0) or the rising edge of RCLK (RCINV = 1).
Receiver Tri-State Enable (Active Low). RTS tri-states the RPOS/RDAT, RNEG/RLCV, and RCLK
receiver outputs. This feature supports applications requiring LIU redundancy. Receiver outputs
from multiple LIUs can be wire-ORed together, eliminating the need for external switches or muxes.
The receiver continues to operate internally when RTS is low.
0 = tri-state the receiver outputs
1 = enable the receiver outputs
Receiver Loss of Signal (Active Low, Open Drain). RLOS is asserted upon detection of 175 ±75
consecutive zeros in the receive data stream. RLOS is deasserted when there are no excessive
zero occurrences over a span of 175 ±75 clock periods. An excessive zero occurrence is defined as
three or more consecutive zeros in the DS3 and STS-1 modes or four or more zeros in the E3
mode. See Section 6 for additional details.
Receive Monitor-Preamp Enable. RMON determines whether or not the receiver’s preamp is
enabled to provide flat gain to the incoming signal before the AGC/equalizer block processes it. This
feature should be enabled when the device is being used to monitor signals that have been
resistively attenuated by a monitor jack.
0 = disable the monitor preamp
1 = enable the monitor preamp
Receiver Jitter Attenuator Enable
0 = remove jitter attenuator from the receiver path
1 = insert jitter attenuator into the receiver path
(Note that TJA = 1 takes precedence over RJA = 1.)
12 of 60
DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
Table 4-D. Global Pin Descriptions
NAME
I/O
HIZ
IPU
RST
IPU
HW
I
T3MCLK
I
E3MCLK
I
STMCLK
I
PRBSn
O
LLBn,
RLBn
I
E3Mn
I
STSn
I
RBIN
I
TBIN
I
RCINV
I
TCINV
I
MOT
I
ALE
I
CS
I
WR / R/W
I
FUNCTION
High-Z Enable Input (Active Low, Open Drain)
0 = tri-state all output pins (Note that the JTRST pin must be low.)
1 = normal operation
Reset Input (Active Low, Open Drain, Internal 10kW Pullup to VDD). When this global asynchronous
reset is pulled low, the internal circuitry is reset and the internal registers (CPU bus mode) are forced
to their default values. The device is held in reset as long as RST is low. RST should be held low for
at least two master clock cycles.
Hardwired Mode Select
0 = CPU bus mode
1 = hardwired mode
See Section 3 for details.
T3 Master Clock. A transmission-quality DS3 (44.736MHz ±20ppm, low jitter) clock should be applied
at this pin. Wiring T3MCLK high forces LIUs in DS3 mode to use TCLK for receiver clock and data
recovery.
E3 Master Clock. A transmission-quality E3 (34.368MHz ±20ppm, low jitter) clock should be applied
at this pin. Wiring E3MCLK high forces LIUs in E3 mode to use TCLK for receiver clock and data
recovery.
STS-1 Master Clock. A transmission-quality STS-1 (51.840MHz ±20ppm, low jitter) clock should be
applied at this pin. Wiring STMCLK high forces LIUs in STS-1 mode to use TCLK for receiver clock
and data recovery.
PRBS Detector Output. This signal reports the status of the PRBS detector. See Section 8 for further
details.
Local Loopback Select, Remote Loopback Select
{LLB, RLB} =
00 = no loopback
01 = remote loopback
10 = analog local loopback
11 = digital local loopback
E3 Mode Enable
0 = DS3 operation
1 = E3 or STS-1 operation
STS-1 Mode Enable
When E3M = 1,
0 = E3 operation
1 = STS-1 operation
When E3M = 0, STS selects the DS3 AIS pattern.
Receiver Binary Framer-Interface Enable
0 = Receiver framer interface is bipolar on the RPOS and RNEG pins. The B3ZS/HDB3 decoder is
disabled.
1 = Receiver framer interface is binary on the RDAT pin with the RLCV pin indicating line-code
violations. The B3ZS/HDB3 encoder is enabled.
Transmitter Binary Framer-Interface Enable
0 = Transmitter framer interface is bipolar on the TPOS and TNEG pins. The B3ZS/HDB3 encoder is
disabled.
1 = Transmitter framer interface is binary on the TDAT pin. (TNEG is ignored and should be wired
low.) The B3ZS/HDB3 encoder is enabled.
Receiver Clock Invert
0 = RPOS/RDAT and RNEG/RLCV update on the falling edge of RCLK.
1 = RPOS/RDAT and RNEG/RLCV update on the rising edge of RCLK.
Transmitter Clock Invert
0 = TPOS/TDAT and TNEG are sampled on the rising edge of TCLK.
1 = TPOS/TDAT and TNEG are sampled on the falling edge of TCLK.
Motorola Bus Mode Enable
0 = Intel bus mode
1 = Motorola bus mode
Address Latch Enable. This signal controls a latch on the A[5:0] inputs. In nonmultiplexed bus
applications, ALE should be wired high to make the latch transparent. In multiplexed bus
applications, A[5:0] should be wired to D[5:0]. The falling edge of ALE latches the address.
Chip Select (Active Low). CS must be asserted in order to read or write internal registers.
Write Enable (Active Low) or Read/Write Select. In Intel bus mode (MOT = 0), WR is asserted to
write internal registers. In Motorola bus mode (MOT = 1), R/W determines the type of bus
13 of 60
DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
NAME
I/O
RD/DS
I
A[5:0]
I
D[7:0]
I/O
INT
O
VDD
VSS
P
P
FUNCTION
transaction, with R/W = 1 indicating a read and R/W = 0 indicating a write.
Read Enable (Active Low) or Data Strobe (Active Low). In Intel bus mode (MOT = 0), RD is asserted
to read internal registers. In Motorola bus mode (MOT = 1), the rising edge of DS writes data to
internal registers.
Address Bus. These inputs specify the address of the internal register to be accessed. A5 is not
present on the DS3152. A5 and A4 are not present on the DS3151.
Data Bus. These bidirectional lines are inputs during writes to internal registers. They are outputs
during reads from internal registers.
Interrupt Output (Active Low, Open Drain). This pin is forced low in response to one or more
unmasked, active interrupt sources within the device. INT remains low until the interrupt is serviced or
masked.
Positive Supply. 3.3V ±5%. All VDD signals should be wired together.
Ground Reference. All VSS signals should be wired together.
Table 4-E. JTAG and Test Pin Descriptions
NAME
I/O
JTCLK
I
JTDI
IPU
JTDO
O
JTRST
IPU
JTMS
IPU
TEST
IPU
FUNCTION
JTAG IEEE 1149.1 Test Serial Clock. JTCLK shifts data into JTDI on the rising edge and out of
JTDO on the falling edge. If boundary scan is not used, JTCLK should be pulled high.
JTAG IEEE 1149.1 Test Serial-Data Input (Internal 10kW Pullup). Test instructions and data are
clocked in on this pin on the rising edge of JTCLK. If boundary scan is not used, JTDI should be left
unconnected or pulled high.
JTAG IEEE 1149.1 Test Serial-Data Output. Test instructions and data are clocked out on this pin on
the falling edge of JTCLK.
JTAG IEEE 1149.1 Test Reset (Internal 10kW Pullup). This pin is used to asynchronously reset the
test access port (TAP) controller. If boundary scan is not used, JTRST can be held low or high.
JTAG IEEE 1149.1 Test Mode Select (Internal 10kW Pullup). This pin is sampled on the rising edge
of JTCLK and is used to place the port into the various defined IEEE 1149.1 states. If boundary scan
is not used, JTMS should be left unconnected or pulled high.
Factory Test Pin. Leave unconnected or wire high for normal operation.
Note 1: Pin type I = input pin. Pin type O = output pin. Pin type P = power-supply pin.
Note 2: Pin type O3 is an output that can be tri-stated.
Note 3: Pin type IPU is an input with an internal 10kW pullup.
Note 4: For pin names of the form PINn, n = LIU# = 1, 2, 3, or 4. PIN1 is on LIU 1, PIN2 is on LIU 2, etc.
Note 5: Section 14 shows hardware mode and CPU bus mode pin assignments.
Table 4-F. Transmitter Data Select Options
TDSA
0
0
0
0
0
1
1
1
1
TDSB
0
1
1
1
1
0
1
1
1
E3M
X
0
1
1
0
X
1
0
1
STS
X
0
0
1
1
X
0
X
1
Tx MODE
Any
DS3
E3
STS-1
DS3
Any
E3
DS3
STS-1
TRANSMIT DATA SELECTED
Normal data as input at TPOS and TNEG
Unframed all ones
DS3 AIS per ANSI T1.107 (Figure 7-2)
Unframed 100100… pattern
23
2 - 1 PRBS pattern per ITU O.151
2
15
- 1 PRBS pattern per ITU O.151
Note 1: This coding of the TDSA, TDSB, E3M, and STS bits allows AIS generation to be enabled by holding TDSA = 0 and changing TDSB
from 0 to 1. The type of DS3 AIS signal is selected by the STS bit with E3M = 0.
Note 2: If E3M and/or STS are changed when {TDSA,TDSB} ¹ 00, TDSA and TDSB must both be cleared to 0. After they are cleared, TDSA
and TDSB can be configured to transmit a pattern in the new operating mode.
Table 4-G. Receiver PRBS Pattern Select Options
E3M
1
0
1
STS
0
X
1
Rx MODE
E3
DS3
STS-1
RECEIVER PRBS PATTERN SELECTED
23
2 - 1 PRBS pattern per ITU O.151
2
15
- 1 PRBS pattern per ITU O.151
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DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
5. REGISTER DESCRIPTIONS
When the DS315x is configured in CPU bus mode (HW = 0), the registers shown in Table 5-A are accessible
through the CPU bus interface. All registers for the LIU ports are forced to their default values during an internal
power-on reset or when the RST pin is driven low. Setting an LIU’s RST bit high forces all registers for that LIU to
their default values. All register bits marked “—” must be written 0 and ignored when read. The TEST registers
must be left at their reset value of 00h for normal operation.
On the DS3153, only registers for LIUs 1, 2, and 3 are available. Writes into LIU 4 address space are ignored.
Reads from LIU 4 address space return all zeros. On the DS3152, address line A5 is not present, limiting the
address space to the LIU 1 and 2 registers. On the DS3151, address lines A5 and A4 are not present, limiting the
address space to the LIU 1 registers.
Table 5-A. Register Map
ADDRESS
REGISTER
BIT 7
BIT 6
00h
01h
02h
03h
04h
05h
06h
07h
08h–0Fh
GCR1
TCR1
RCR1
SR1
SRL1
SRIE1
RCVL1
RCVH1
TEST
E3M
—
ITU
—
—
—
RCV[7]
RCV[15]
—
STS
TBIN
RBIN
—
—
—
RCV[6]
RCV[14]
—
10h
11h
12h
13h
14h
15h
16h
17h
18h–1Fh
GCR2
TCR2
RCR2
SR2
SRL2
SRIE2
RCVL2
RCVH2
TEST
E3M
—
ITU
—
—
—
RCV[7]
RCV[15]
—
STS
TBIN
RBIN
—
—
—
RCV[6]
RCV[14]
—
20h
21h
22h
23h
24h
25h
26h
27h
28h–2Fh
GCR3
TCR3
RCR3
SR3
SRL3
SRIE3
RCVL3
RCVH3
TEST
E3M
—
ITU
—
—
—
RCV[7]
RCV[15]
—
STS
TBIN
RBIN
—
—
—
RCV[6]
RCV[14]
—
30h
31h
32h
33h
34h
35h
36h
37h
38h–3Fh
GCR4
TCR4
RCR4
SR4
SRL4
SRIE4
RCVL4
RCVH4
TEST
E3M
—
ITU
—
—
—
RCV[7]
RCV[15]
—
STS
TBIN
RBIN
—
—
—
RCV[6]
RCV[14]
—
BIT 5
LIU 1
LLB
TCINV
RCINV
TDM
TDML
TDMIE
RCV[5]
RCV[13]
—
LIU 2
LLB
TCINV
RCINV
TDM
TDML
TDMIE
RCV[5]
RCV[13]
—
LIU 3
LLB
TCINV
RCINV
TDM
TDML
TDMIE
RCV[5]
RCV[13]
—
LIU 4
LLB
TCINV
RCINV
TDM
TDML
TDMIE
RCV[5]
RCV[13]
—
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RLB
TJA
RJA
PRBS
PRBSL
PRBSIE
RCV[4]
RCV[12]
—
TDSA
TPD
RPD
—
PBERL
PBERIE
RCV[3]
RCV[11]
—
TDSB
TTS
RTS
—
RCVL
RCVIE
RCV[2]
RCV[10]
—
—
TLBO
RMON
RLOL
RLOLL
RLOLIE
RCV[1]
RCV[9]
—
RST
—
RCVUD
RLOS
RLOSL
RLOSIE
RCV[0]
RCV[8]
—
RLB
TJA
RJA
PRBS
PRBSL
PRBSIE
RCV[4]
RCV[12]
—
TDSA
TPD
RPD
—
PBERL
PBERIE
RCV[3]
RCV[11]
—
TDSB
TTS
RTS
—
RCVL
RCVIE
RCV[2]
RCV[10]
—
-TLBO
RMON
RLOL
RLOLL
RLOLIE
RCV[1]
RCV[9]
—
RST
-RCVUD
RLOS
RLOSL
RLOSIE
RCV[0]
RCV[8]
—
RLB
TJA
RJA
PRBS
PRBSL
PRBSIE
RCV[4]
RCV[12]
—
TDSA
TPD
RPD
—
PBERL
PBERIE
RCV[3]
RCV[11]
—
TDSB
TTS
RTS
—
RCVL
RCVIE
RCV[2]
RCV[10]
—
—
TLBO
RMON
RLOL
RLOLL
RLOLIE
RCV[1]
RCV[9]
—
RST
—
RCVUD
RLOS
RLOSL
RLOSIE
RCV[0]
RCV[8]
—
RLB
TJA
RJA
PRBS
PRBSL
PRBSIE
RCV[4]
RCV[12]
—
TDSA
TPD
RPD
—
PBERL
PBERIE
RCV[3]
RCV[11]
—
TDSB
TTS
RTS
—
RCVL
RCVIE
RCV[2]
RCV[10]
—
—
TLBO
RMON
RLOL
RLOLL
RLOLIE
RCV[1]
RCV[9]
—
RST
—
RCVUD
RLOS
RLOSL
RLOSIE
RCV[0]
RCV[8]
—
Note 1: Underlined bits are read-only; all other bits are read-write.
Note 2: The registers are named REGn, where n = the LIU number (1, 2, 3, or 4).
Note 3: The bit names are the same for each LIU register set.
15 of 60
DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
Status Register Description
The status registers have two types of status bits. Real-time status bits—located in the SRn registers—indicate the
state of a signal at the time it was read. Latched status bits—located in the SRLn registers—are set when a signal
changes state (low-to-high, high-to-low, or both, depending on the bit) and cleared when written with a logic 1
value. After clearing, latched status bits remain cleared until the signal changes state again. Interrupt-enable bits—
located in the SRIEn registers—control whether or not the INT pin is driven low when latched register bits are set.
Figure 5-1. Status Register Logic
REAL-TIME STATUS
EVENT
WR
SR
LATCHED STATUS
LATCHED STATUS REGISTER
SET ON EVENT DETECT CLEAR
ON WRITE LOGIC 1
SRL
INT
WR
Register Name:
Register Description:
Register Address:
Bit
Name
Default
7
E3M
0
INT ENABLE
REGISTER
OTHER INT
SOURCE
GCRn
Global Configuration Register
00h, 10h, 20h, 30h
6
STS
0
5
LLB
0
4
RLB
0
3
TDSA
0
2
TDSB
0
1
—
—
0
RST
0
Bit 7: E3 Mode Enable (E3M)
0 = DS3 operation
1 = E3 or STS-1 operation
Bit 6: STS-1 Mode Enable (STS)
When E3M = 1,
0 = E3 operation
1 = STS-1 operation
When E3M = 0, STS selects the DS3 AIS pattern (Table 4-F).
Bits 5, 4: Local Loopback, Remote Loopback Select (LLB, RLB)
00 = no loopback
01 = remote loopback
10 = analog local loopback
11 = digital local loopback
Bits 3, 2: Transmitter Data Select (TDSA, TDSB). See Table 4-F for details.
Bit 0: Reset (RST). When this bit is high, the digital logic of the LIU is held in reset and all registers for that LIU
(except the RST bit) are forced to their default values. RST is cleared to 0 at power-up and when the RST pin is
activated.
0 = normal operation
1 = reset LIU
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DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
TCRn
Transmitter Configuration Register
01h, 11h, 21h, 31h
Register Name:
Register Description:
Register Address:
Bit
Name
Default
7
—
0
6
TBIN
0
5
TCINV
0
4
TJA
0
3
TPD
0
2
TTS
1
1
TLBO
0
0
—
—
Bit 6: Transmitter Binary Interface Enable (TBIN)
0 = Transmitter framer interface is bipolar on the TPOS and TNEG pins. The B3ZS/HDB3 encoder is
disabled.
1 = Transmitter framer interface is binary on the TDAT pin. The B3ZS/HDB3 encoder is enabled.
Bit 5: Transmitter Clock Invert (TCINV)
0 = TPOS/TDAT and TNEG are sampled on the rising edge of TCLK.
1 = TPOS/TDAT and TNEG are sampled on the falling edge of TCLK.
Bit 4: Transmitter Jitter Attenuator Enable (TJA)
0 = Remove jitter attenuator from the transmitter path.
1 = Insert jitter attenuator into the transmitter path.
Bit 3: Transmitter Power-Down Enable (TPD)
0 = enable the transmitter
1 = power-down the transmitter (output driver tri-stated)
Bit 2: Transmitter Tri-State Enable (TTS). This bit is set to 1 on reset, which tri-states the transmitter TXP and
TXN pins. The transmitter circuitry is left powered up in this mode. The TTS input pin is inverted and logically ORed
with this bit.
0 = enable the transmitter output driver
1 = tri-state the transmitter output driver
Bit 1: Transmitter Line Build-Out (TLBO). TLBO indicates cable length for waveform shaping in DS3 and STS-1
modes. TLBO is ignored in E3 mode.
0 = cable length ³ 225ft
1 = cable length < 225ft
17 of 60
DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
Register Name:
Register Description:
Register Address:
Bit
Name
Default
7
ITU
0
RCRn
Receiver Configuration Register
02h, 12h, 22h, 32h
6
RBIN
0
5
RCINV
0
4
RJA
0
3
RPD
0
2
RTS
1
1
RMON
0
0
RCVUD
0
Bit 7: ITU CV Mode (ITU). This bit controls what types of bipolar violations (BPVs) are flagged as code violations
on the RLCV pin and counted in the RCV register. It also controls whether or not excessive zero (EXZ) events are
flagged and counted. An EXZ event is the occurrence of a third consecutive zero (DS3 or STS-1 modes) or fourth
consecutive zero (E3 mode) in a sequence of zeros.
0 = In all three modes (DS3, E3, and STS-1) BPVs that are not part of a valid codeword are flagged and
counted. EXZ events are also flagged and counted.
1 = In DS3 and STS-1 modes, BPVs that are not part of valid codewords are flagged and counted. In E3
mode, BPVs that are the same polarity as the last BPV are flagged and counted. EXZ events are not
flagged and counted in any mode.
Bit 6: Receiver Binary Interface Enable (RBIN)
0 = Receiver framer interface is bipolar on the RPOS and RNEG pins. The B3ZS/HDB3 decoder is
disabled.
1 = Receiver framer interface is binary on the RDAT pin with the RLCV pin indicating line-code violations.
The B3ZS/HDB3 encoder is enabled.
Bit 5: Receiver Clock Invert (RCINV)
0 = RPOS/RDAT and RNEG/RLCV are sampled on the rising edge of RCLK.
1 = RPOS/RDAT and RNEG/RLCV are sampled on the falling edge of RCLK.
Bit 4: Receiver Jitter Attenuator Enable (RJA). (Note that TJA = 1 takes precedence over RJA = 1.)
0 = remove jitter attenuator from the receiver path
1 = insert jitter attenuator into the receiver path
Bit 3: Receiver Power-Down Enable (RPD)
0 = enable the receiver
1 = power-down the receiver (RPOS/RDAT, RNEG/RLCV, and RCLK tri-stated)
Bit 2: Receiver Tri-State Enable (RTS). This signal is set to 1 on reset, which tri-states the receiver RPOS/RDAT,
RNEG/RLCV, and RCLK pins. The receiver is left powered up in this mode. The RTS pin is inverted and logically
ORed with this bit.
0 = enable the receiver outputs
1 = tri-state the receiver outputs (RPOS/RDAT, RNEG/RLCV, and RCLK)
Bit 1: Receiver Monitor Preamp Enable (RMON)
0 = disable the monitor preamp
1 = enable the monitor preamp
Bit 0: Receive Code-Violation Counter Update (RCVUD). When this control bit transitions from low to high, the
RCVLn and RCVHn registers are loaded with the current code-violation count, and the internal code-violation
counter is cleared.
0®1 = Update RCV registers and clear internal code-violation counter
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DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
SRn
Status Register
03h, 13h, 23h, 33h
Register Name:
Register Description:
Register Address:
Bit
Name
Default
7
—
—
6
—
—
5
TDM
0
4
PRBS
0
3
—
—
2
—
—
1
RLOL
1
0
RLOS
1
Bit 5: Transmitter Driver Monitor (TDM). This read-only status bit indicates the current state of the transmit driver
monitor.
0 = the transmitter is operating normally
1 = the transmitter has a fault condition
Bit 4: PRBS Detector Output (PRBS). This read-only status bit indicates the current state of the receiver’s PRBS
detector. See Table 4-G for the expected PRBS pattern.
0 = in sync with expected pattern
1 = out of sync, expected pattern not detected
Bit 1: Receiver Loss of Lock (RLOL). This read-only status bit indicates the current state of the receiver clock
recovery PLL.
0 = the receiver PLL is locked onto the incoming signal
1 = the receiver PLL is not locked onto the incoming signal
Bit 0: Receiver Loss of Signal (RLOS). This read-only status bit indicates the current state of the receiver loss-ofsignal detector.
0 = signal present
1 = loss of signal
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DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
SRLn
Status Register Latched
04h, 14h, 24h, 34h
Register Name:
Register Description:
Register Address:
Bit
Name
Default
7
—
—
6
—
—
5
TDML
0
4
PRBSL
0
3
PBERL
0
2
RCVL
0
1
RLOLL
0
0
RLOSL
0
Bit 5: Transmitter Driver Monitor Latched (TDML). This latched status bit is set to one when the TDM status bit
changes state (low to high or high to low). TDML is cleared when the host processor writes a one to it and is not set
again until TDM changes state again. When TDML is set, it can cause a hardware interrupt to occur if the TDMIE
interrupt-enable bit is set to one. The interrupt is cleared when TDML is cleared or TDMIE is set to zero.
Bit 4: PRBS Detector Output Latched (PRBSL). This latched status bit is set to one when the PRBS status bit
changes state (low to high or high to low). PRBSL is cleared when the host processor writes a one to it and is not
set again until PRBS changes state again. When PRBSL is set, it can cause a hardware interrupt to occur if the
PRBSIE interrupt-enable bit is set to one. The interrupt is cleared when PRBSL is cleared or PRBSIE is set to zero.
Bit 3: PRBS Detector Bit Error Latched (PBERL). This latched status bit is set to one when the PRBS detector is
in sync and a bit error has been detected. PBERL is cleared when the host processor writes a one to it and is not
set again until another bit error is detected. When PBERL is set, it can cause a hardware interrupt to occur if the
PBERIE interrupt-enable bit is set to one. The interrupt is cleared when PBERL is cleared or PBERIE is set to zero.
Bit 2: Receiver Code Violation Latched (RCVL). This latched status bit is set to one when the RCV status bit
goes high. RCVL is cleared when the host processor writes a one to it and is not set again until RCV goes high
again. When RCVL is set, it can cause a hardware interrupt to occur if the RCVIE interrupt-enable bit is set to one.
The interrupt is cleared when RCVL is cleared or RCVIE is set to zero.
Bit 1: Receiver Loss-of-Clock Lock Latched (RLOLL). This latched status bit is set to one when the RLOL status
bit changes state (low to high or high to low). RLOLL is cleared when the host processor writes a one to it and is
not set again until RLOL changes state again. When RLOLL is set, it can cause a hardware interrupt to occur if the
RLOLIE interrupt-enable bit is set to one. The interrupt is cleared when RLOLL is cleared or RLOLIE is set to zero.
Bit 0: Receiver Loss-of-Signal Latched (RLOSL). This latched status bit is set to one when the RLOS status bit
changes state (low to high or high to low). RLOSL is cleared when the host processor writes a one to it and is not
set again until RLOS changes state again. When RLOSL is set, it can cause a hardware interrupt to occur if the
RLOSIE interrupt-enable bit is set to one. The interrupt is cleared when RLOSL is cleared or RLOSIE is set to zero.
20 of 60
DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
SRIEn
Status Register Interrupt Enable
05h, 15h, 25h, 35h
Register Name:
Register Description:
Register Address:
Bit
Name
Default
7
—
—
6
—
—
5
TDMIE
0
4
PRBSIE
0
3
PBERIE
0
2
RCVIE
0
1
RLOLIE
0
0
RLOSIE
0
1
RCV[1]
0
0
RCV[0]
0
1
RCV[9]
0
0
RCV[8]
0
Bit 5: Transmitter Driver Monitor Interrupt Enable (TDMIE)
0 = mask TDML interrupt
1 = enable TDML interrupt
Bit 4: PRBS Detector Interrupt Enable (PRBSIE)
0 = mask PRBSL interrupt
1 = enable PRBSL interrupt
Bit 3: PRBS Detector Bit-Error Interrupt Enable (PBERIE)
0 = mask PBERL interrupt
1 = enable PBERL interrupt
Bit 2: Receiver Line-Code Violation Interrupt Enable (RCVIE)
0 = mask RCVL interrupt
1 = enable RCVL interrupt
Bit 1: Receiver Loss-of-Clock Lock Interrupt Enable (RLOLIE)
0 = mask RLOLL interrupt
1 = enable RLOLL interrupt
Bit 0: Receiver Loss-of-Signal Interrupt Enable (RLOSIE)
0 = mask RLOSL interrupt
1 = enable RLOSL interrupt
Register Name:
Register Description:
Register Address:
Bit
Name
Default
7
RCV[7]
0
Register Name:
Register Description:
Register Address:
Bit
Name
Default
7
RCV[15]
0
RCVLn
Receiver Code-Violation Count Register (Low Byte)
06h, 16h, 26h, 36h
6
RCV[6]
0
5
RCV[5]
0
4
RCV[4]
0
3
RCV[3]
0
2
RCV[2]
0
RCVHn
Receiver Code-Violation Count Register (High Byte)
07h, 17h, 27h, 37h
6
RCV[14]
0
5
RCV[13]
0
4
RCV[12]
0
3
RCV[11]
0
2
RCV[10]
0
Bits 15 to 0: Receiver Code-Violation Counter Register (RCV[15:0]). The RCV registers form a 16-bit register
for reading the line-code violation counter value. The registers are updated with the line-code violation counter
value when the RCVUD control bit is toggled low to high. After the RCV registers are updated, the line-code
violation counter is cleared. The counter operates in two modes, depending on the setting of the ITU bit in the RCR
register. See the RCR register description for details about the ITU control bit.
21 of 60
DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
6. RECEIVER
Interfacing to the Line. The receiver can be transformer-coupled or capacitor-coupled to the line. Typically, the
receiver interfaces to the incoming coaxial cable (75W) through a 1:2 step-up transformer. Figure 1-1 shows the
arrangement of the transformer and other recommended interface components. Table 11-A specifies the required
characteristics of the transformer. The receiver expects the incoming signal to be in B3ZS- or HDB3-coded AMI
format.
Optional Preamp. The receiver can be used in monitoring applications, which typically have series resistors with a
resistive loss of approximately 20dB. When the RMON input pin is high, the receiver compensates for this resistive
loss by applying approximately 14dB of flat gain to the incoming signal before sending the signal to the
AGC/equalizer block where additional flat gain is applied as needed.
Automatic Gain Control (AGC) and Adaptive Equalizer. The AGC circuitry applies flat (frequency independent)
gain to the incoming signal to compensate for flat losses in the transmission channel and variations in transmission
power. Since the incoming signal also experiences frequency-dependent losses as it passes through the coaxial
cable, the adaptive equalizer circuitry applies frequency-dependent gain to offset line losses and restore the signal.
The AGC/equalizer circuitry automatically adapts to coaxial cable losses from 0 to 15dB, which translates into 0 to
380 meters (DS3), 0 to 440 meters (E3), or 0 to 360 meters (STS-1) of coaxial cable (AT&T 734A or equivalent).
The AGC and the equalizer work simultaneously but independently to supply a signal of nominal amplitude and
pulse shape to the clock and data recovery block. The AGC/equalizer block automatically handles direct (0 meters)
monitoring of the transmitter output signal.
Clock and Data Recovery (CDR). The CDR block takes the amplified, equalized signal from the AGC/equalizer
block and produces separate clock, positive data, and negative data signals. The CDR requires a master clock. If
the signal on the appropriate MCLK pin is toggling, the LIU selects the MCLK signal as its master clock. If the
appropriate MCLK pin is wired high, the LIU uses the signal on the TCLK pin as the master clock. The appropriate
MCLK is selected based on the settings of the E3M and STS mode pins or register bits.
The receiver locks onto the incoming signal using a clock recovery PLL. The status of the PLL lock is indicated in
the RLOL status bit. The RLOL bit is set when the difference between recovered clock frequency and MCLK
frequency is greater than 7900ppm and cleared when the difference is less than 7700ppm. A change of state of the
RLOL status bit can cause an interrupt on the INT pin if enabled to do so by the RLOLIE interrupt-enable bit. Note
that if MCLK is not present, or MCLK is high and TCLK is not present, RLOL is not set.
Loss-of-Signal (LOS) Detector. The receiver contains analog and digital LOS detectors. The analog LOS detector
resides in the AGC/equalizer block. If the incoming signal level is less than a signal level approximately 24dB below
nominal, analog LOS (ALOS) is declared. The ALOS signal cannot be directly examined, but when ALOS occurs
the AGC/equalizer mutes the recovered data, forcing all zeros out of the data recovery circuitry and causing digital
LOS (DLOS), which is indicated by the RLOS pin and the RLOS status bit. ALOS clears when the incoming signal
level is greater than or equal to a signal level approximately 18dB below nominal.
The digital LOS detector declares DLOS when it detects 175 ±75 consecutive zeros in the recovered data stream.
When DLOS occurs, the receiver asserts the RLOS pin (hardware mode) or the RLOS status bit (CPU bus mode).
DLOS is cleared when there are no EXZ occurrences over a span of 175 ±75 clock periods. An EXZ occurrence is
defined as three or more consecutive zeros in the DS3 and STS-1 modes and four or more consecutive zeros in
the E3 mode. The RLOS pin goes inactive (high) when the DLOS condition is cleared. In CPU bus mode, a change
of the RLOS status bit can cause an interrupt on the INT pin if enabled to do so by the RLOSIE interrupt-enable bit.
The requirements of ANSI T1.231 and ITU-T G.775 for DS3 LOS defects are met by the DLOS detector, which
asserts RLOS when it counts 175 ±75 consecutive zeros coming out of the CDR block and clears RLOS when it
counts 175 ±75 consecutive pulse intervals without excessive zero occurrences.
The requirements of ITU-T G.775 for E3 LOS defects are met by a combination of the ALOS detector and the
DLOS detector, as follows:
22 of 60
DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
For E3 RLOS Assertion:
1) The ALOS detector in the AGC/equalizer block detects that the incoming signal is less than or equal to a signal
level approximately 24dB below nominal, and mutes the data coming out of the clock and data recovery block.
(24dB below nominal in the “tolerance range” of G.775, where LOS may or may not be declared.)
2) The DLOS detector counts 175 ±75 consecutive zeros coming out of the CDR block and asserts RLOS. (175
±75 meets the 10 £ N £ 255 pulse-interval duration requirement of G.775.)
For E3 RLOS Clear:
1) The ALOS detector in the AGC/equalizer block detects that the incoming signal is greater than or equal to a
signal level approximately 18dB below nominal, and enables data to come out of the CDR block. (18dB is in
the “tolerance range” of G.775, where LOS may or may not be declared.)
2) The DLOS detector counts 175 ±75 consecutive pulse intervals without EXZ occurrences and deasserts
RLOS. (175 ±75 meets the 10 £ N £ 255 pulse-interval duration requirement of G.775.)
The DLOS detector supports the requirements of ANSI T1.231 for STS-1 LOS defects. At STS-1 rates, the time
required for the DLOS detector to count 175 ±75 consecutive zeros falls in the range of 2.3£ T£ 100ms required by
ANSI T1.231 for declaring an LOS defect. Although the time required for the DLOS detector to count 175 ±75
consecutive pulse intervals with no excessive zeros is less than the 125ms–250ms period required by ANSI T1.231
for clearing an LOS defect, a period of this length where LOS is inactive can easily be timed in software.
During LOS, the RCLK output pin is derived from the LIU’s master clock. The ALOS detector has a longer time
constant than the DLOS detector. Thus, when the incoming signal is lost, the DLOS detector activates first
(asserting the RLOS pin or bit), followed by the ALOS detector. When a signal is restored, the DLOS detector does
not get a valid signal that it can qualify for no EXZ occurrences until the ALOS detector has seen the signal rise
above a signal level approximately 18dB below nominal.
Framer Interface Format and the B3ZS/HDB3 Decoder. The recovered data can be output in either binary or
bipolar format. To select the bipolar interface format, pull the RBIN pin low (hardware mode) or clear the RBIN
configuration bit (CPU bus mode). In bipolar format, the B3ZS/HDB3 decoder is disabled and the recovered data is
buffered and output on the RPOS and RNEG outputs. Received positive-polarity pulses are indicated by RPOS =
1, while negative-polarity pulses are indicated by RNEG = 1. In bipolar interface format, the receiver simply passes
on the received data and does not check it for BPV or EXZ occurrences.
To select the binary interface format, pull the RBIN pin high (hardware mode) or set the RBIN configuration bit
(CPU bus mode). In binary format, the B3ZS/HBD3 decoder is enabled, and the recovered data is decoded and
output as a binary value on the RDAT pin. Code violations are flagged on the RLCV pin. In the discussion that
follows, a valid pulse that conforms to the AMI rule is denoted as B. A BPV pulse that violates the AMI rule is
denoted as V.
In DS3 and STS-1 modes, B3ZS decoding is performed. RLCV is asserted during any RCLK cycle where the data
on RDAT causes ones of the following code violations:
§
Hardware mode or ITU bit set to 0
– A BPV immediately preceded by a valid pulse (B, V).
– A BPV with the same polarity as the last BPV.
– The third zero in an EXZ occurrence.
§
ITU bit set to 1
– A BPV immediately preceded by a valid pulse (B, V).
– A BPV with the same polarity as the last BPV.
In E3 mode, HDB3 decoding is performed. RLCV is asserted during any RCLK cycle where the data on RDAT
causes one of the following code violations:
§
Hardware mode or ITU bit set to 0
– A BPV immediately preceded by a valid pulse (B, V) or by a valid pulse and a zero (B, 0, V).
– A BPV with the same polarity as the last BPV.
– The fourth zero in an EXZ occurrence (only in hardware mode or when ITU = 0).
23 of 60
DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
§
ITU bit set to 1
– A BPV with the same polarity as the last BPV.
When RLCV is asserted to flag a BPV, the RDAT pin outputs a one. The state bit that tracks the polarity of the last
BPV is toggled on every BPV, whether part of a valid B3ZS/HDB3 codeword or not.
To support a glueless interface to a variety of neighboring components, the polarity of RCLK can be inverted.
Normally, data is output on the RPOS/RDAT and RNEG/RLCV pins on the falling edge of RCLK. To output data on
these pins on the rising edge of RCLK, pull the RCINV pin high (hardware mode) or set the RCINV configuration bit
(CPU bus mode).
The RCLK, RPOS/RDAT, and RNEG/RLCV pins can be tri-stated to support protection switching and redundantLIU applications. This tri-stating capability supports system configurations where two or more LIUs are wire-ORed
together and a system processor selects one to be active. To tri-state RCLK, RPOS/RDAT, and RNEG/RLCV,
assert the RTS pin or the RTS configuration bit.
Receive Line-Code Violation Counter. The line-code violation counter is always enabled regardless of the
settings of the RBIN pin or the RBIN configuration bit. The receiver has an internal 16-bit saturating counter and a
16-bit latch, which the CPU can read as registers RCVH and RCVL. The value of the internal counter is latched into
the RCVH/RCVL register and cleared when the receive code-violation counter update bit, RCVUD, is changed from
a zero to a one. The RCVUD bit must be cleared back to a zero before a new update can occur. If there is an LCV
increment pulse and an update pulse in the same clock period, the counter is preset to a one rather than cleared
so that the LCV is not missed. The counter is incremented when the RLCV pin flags a code violation as described
in the Framer Interface Format and the B3ZS/HDB3 Decoder section. The counter saturates at 65,535 (0FFFFh)
and does not roll over.
Receiver Power-Down. To minimize power consumption when the receiver is not being used, assert the RPD
configuration bit (CPU bus mode). When the receiver is powered down, the RCLK, RPOS/RDAT, and RNEG/RLCV
pins are tri-stated. In addition, the RXP and RXN pins become high impedance.
Receiver Jitter Tolerance. The receiver exceeds the input jitter tolerance requirements of all applicable
telecommunication standards in Table 1-A. See Figure 6-1.
Figure 6-1. Receiver Jitter Tolerance
JITTER TOLERANCE (UIP-P)
15
10
STS-1 GR253
DS3 GR-499 Cat II
10
DS3 GR-499 Cat I
5
DS315x JITTER TOLERANCE
1.5
E3 G.823
1.0
0.3
0.15
0.1
0.1
30
10
300
100
669
2.3k
1k
FREQUENCY (Hz)
24 of 60
22.3k
10k
60k
300k
100k
800k
1M
DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
7. TRANSMITTER
Transmit Clock. The clock applied at the TCLK input clocks in data on the TPOS/TDAT and TNEG pins. If the jitter
attenuator is not enabled in the transmit path, the signal on TCLK is the transmit line clock and must be
transmission quality (i.e., ±20ppm frequency accuracy and low jitter). If the jitter attenuator is enabled in the
transmit path, the signal on TCLK can be jittery and/or periodically gapped (not exceeding 8UI), but must still have
an average frequency within ±20ppm of the nominal line rate. When enabled in the transmit path, the jitter
attenuator generates the transmit line clock from the signal applied on the appropriate MCLK pin. The signal on the
MCLK pin must, therefore, be a transmission-quality clock (±20ppm frequency accuracy and low jitter).
The polarity of TCLK can be inverted to support glueless interfacing to a variety of neighboring components.
Normally data is sampled on the TPOS/TDAT and TNEG pins on the rising edge of TCLK. To sample data on the
falling edge of TCLK, pull the TCINV pin high (hardware mode) or set the TCINV configuration bit (CPU bus mode).
Framer Interface Format and the B3ZS/HDB3 Encoder. Data to be transmitted can be input in either binary or
bipolar format. To select the binary interface format, pull the TBIN pin high (hardware mode) or set the TBIN
configuration bit (CPU bus mode). In binary format, the B3ZS/HBD3 encoder is enabled, and the data to be
transmitted is sampled on the TDAT pin. The TNEG pin is ignored in binary interface mode and should be wired
low. In DS3 and STS-1 modes, the B3ZS/HDB3 encoder operates in the B3ZS mode. In E3 mode the encoder
operates in HDB3 mode.
To select the bipolar interface format, pull the TBIN pin low (hardware mode) or clear the TBIN configuration bit
(CPU bus mode). In bipolar format, the B3ZS/HDB3 encoder is disabled and the data to be transmitted is sampled
on the TPOS and TNEG pins. Positive-polarity pulses are indicated by TPOS = 1, while negative-polarity pulses
are indicated by TNEG = 1.
Pattern Generation. The transmitter can generate several patterns internally, including unframed all ones (E3
AIS), 100100…, and DS3 AIS. See Figure 7-2 for the structure of the DS3 AIS signal. The TDSA and TDSB input
pins (hardware mode) or the TDSA and TDSB control bits (CPU bus mode) are used to select these patterns.
Table 4-F indicates the possible selections.
Waveshaping, Line Build-Out, Line Driver. The waveshaping block converts the transmit clock, positive data,
and negative data signals into a single AMI signal with the waveshape required for interfacing to DS3/E3/STS-1
lines. Table 7-A through Table 7-E and Figure 7-1 show the waveform template specifications and test parameters.
Because DS3 and STS-1 signals must meet the waveform templates at the cross-connect through any cable length
from 0 to 450ft, the waveshaping circuitry includes a selectable LBO feature. For cable lengths of 225ft or greater,
the TLBO pin (hardware mode) or the TLBO configuration bit (CPU bus mode) should be low. When TLBO is low,
output pulses are driven onto the coaxial cable without any preattenuation. For cable lengths less than 225ft, TLBO
should be high to enable the LBO circuitry. When TLBO is high, pulses are preattenuated by the LBO circuitry
before being driven onto the coaxial cable. The LBO circuitry provides attenuation that mimics the attenuation of
225ft of coaxial cable.
The transmitter line driver can be disabled and the TXP and TXN outputs tri-stated by asserting the TTS input or
the TTS configuration bit. Powering down the transmitter through the TPD configuration bit (CPU bus mode) also
tri-states the TXP and TXN outputs.
Interfacing to the Line. The transmitter interfaces to the outgoing DS3/E3/STS-1 coaxial cable (75W) through a
2:1 step-down transformer connected to the TXP and TXN pins. Figure 1-1 shows the arrangement of the
transformer and other recommended interface components. Table 11-A specifies the required characteristics of the
transformer.
Transmit Driver Monitor. If the transmit driver monitor detects a faulty transmitter, it activates the TDM output
(hardware mode or CPU bus mode) or sets the TDM status bit and optionally activates the INT output (CPU bus
mode). When the transmitter is tri-stated, the transmit driver monitor is also disabled. The transmitter is declared to
be faulty when the transmitter outputs see a load of less than ~25W.
25 of 60
DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
Transmitter Power-Down. To minimize power consumption when the transmitter is not being used, assert the
TPD configuration bit (CPU bus mode only). When the transmitter is powered down, the TXP and TXN pins are put
in a high-impedance state and the transmit amplifiers are powered down.
Transmitter Jitter Generation (Intrinsic). The transmitter meets the jitter generation requirements of all
applicable standards, with or without the jitter attenuator enabled.
Transmitter Jitter Transfer. Without the jitter attenuator enabled in the transmit side, the transmitter passes jitter
through unchanged. With the jitter attenuator enabled in the transmit side, the transmitter meets the jitter transfer
requirements of all applicable telecommunication standards in Table 1-A. See Figure 9-1.
Table 7-A. DS3 Waveform Template
TIME (IN UNIT INTERVALS)
NORMALIZED AMPLITUDE EQUATION
UPPER CURVE
-0.85 £ T £ -0.68
-0.68 £ T £ +0.36
0.36 £ T £ 1.4
-0.85 £ T £ -0.36
-0.36 £ T £ +0.36
0.36 £ T £ 1.4
0.03
0.5 {1 + sin[(p / 2)(1 + T / 0.34)]} + 0.03
-1.84(T - 0.36)
0.08 + 0.407e
LOWER CURVE
-0.03
0.5 {1 + sin[(p / 2)(1 + T / 0.18)]} - 0.03
-0.03
Governing Specifications: ANSI T1.102 and Bellcore GR-499.
Table 7-B. DS3 Waveform Test Parameters and Limits
PARAMETER
Rate
Line Code
Transmission Medium
Test Measurement Point
Test Termination
SPECIFICATION
44.736Mbps (±20ppm)
B3ZS
Coaxial cable (AT&T 734A or equivalent)
At the end of 0 to 450ft of coaxial cable
75W (±1%) resistive
Pulse Amplitude
Between 0.36V and 0.85V
Pulse Shape
An isolated pulse (preceded by two zeros and
followed by one or more zeros) falls within the
curves listed in Table 7-A.
Unframed All-Ones Power Level at
22.368MHz
Unframed All-Ones Power Level at
44.736MHz
Pulse Imbalance of Isolated Pulses
Between -1.8dBm and +5.7dBm
At least 20dB less than the power measured at
22.368MHz
Ratio of positive and negative pulses must be
between 0.90 and 1.10.
Table 7-C. STS-1 Waveform Template
TIME (IN UNIT INTERVALS)
-0.85 £ T £ -0.68
-0.68 £ T £ +0.26
0.26 £ T £ 1.4
-0.85 £ T £ -0.36
-0.36 £ T £ +0.36
0.36 £ T £ 1.4
NORMALIZED AMPLITUDE EQUATIONS
UPPER CURVE
0.03
0.5 {1 + sin[(p / 2)(1 + T / 0.34)]} + 0.03
-2.4(T - 0.26)
0.1 + 0.61e
LOWER CURVE
-0.03
0.5 {1 + sin[(p / 2)(1 + T / 0.18)]} - 0.03
-0.03
Governing Specifications: Bellcore GR-253 and Bellcore GR-499 and ANSI T1.102.
26 of 60
DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
Table 7-D. STS-1 Waveform Test Parameters and Limits
PARAMETER
Rate
Line Code
Transmission Medium
Test Measurement Point
Test Termination
Pulse Amplitude
Pulse Shape
Unframed All-Ones Power Level at 25.92MHz
Unframed All-Ones Power Level at 51.84MHz
SPECIFICATION
51.840Mbps (±20ppm)
B3ZS
Coaxial cable (AT&T 734A or equivalent)
At the end of 0 to 450ft of coaxial cable
75W (±1%) resistive
0.800V nominal (not covered in specs)
An isolated pulse (preceded by two zeros and followed by one
or more zeros) falls within the curved listed in Table 7-C.
Between -1.8dBm and +5.7dBm
At least 20dB less than the power measured at 25.92MHz.
Table 7-E. E3 Waveform Test Parameters and Limits
PARAMETER
Rate
Line Code
Transmission Medium
Test Measurement Point
Test Termination
Pulse Amplitude
Pulse Shape
Ratio of the Amplitudes of Positive and Negative
Pulses at the Center of the Pulse Interval
Ratio of the Widths of Positive and Negative
Pulses at the Nominal Half Amplitude
SPECIFICATION
34.368Mbps (±20ppm)
HDB3
Coaxial cable (AT&T 734A or equivalent)
At the transmitter
75W (±1%) resistive
1.0V (nominal)
An isolated pulse (preceded by two zeros and followed by one
or more zeros) falls within the template shown in Figure 7-1.
0.95 to 1.05
0.95 to 1.05
Figure 7-1. E3 Waveform Template
1.2
1.1
17
1.0
OUTPUT LEVEL (V)
0.9
0.8
8.65
0.7
G.703
E3
TEMPLATE
0.6
0.5
0.4
12.1
0.3
0.2
0.1
24.5
0
-0.1
29.1
-0.2
TIME (ns)
27 of 60
DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
Figure 7-2. DS3 AIS Structure
M1 Subframe
84
X1
Info F1
(1)
Bits (1)
84
Info
Bits
C1
(0)
84
Info
Bits
F2
(0)
84
Info
Bits
C2
(0)
84
Info
Bits
F3
(0)
84
Info
Bits
C3
(0)
84
Info
Bits
F4
(1)
84
Info
Bits
M2 Subframe
84
Info F1
X2
Bits (1)
(1)
84
Info
Bits
C1
(0)
84
Info
Bits
F2
(0)
84
Info
Bits
C2
(0)
84
Info
Bits
F3
(0)
84
Info
Bits
C3
(0)
84
Info
Bits
F4
(1)
84
Info
Bits
M3 Subframe
84
Info F1
P1
Bits (1)
(0)
84
Info
Bits
C1
(0)
84
Info
Bits
F2
(0)
84
Info
Bits
C2
(0)
84
Info
Bits
F3
(0)
84
Info
Bits
C3
(0)
84
Info
Bits
F4
(1)
84
Info
Bits
M4 Subframe
84
Info F1
P2
Bits (1)
(0)
84
Info
Bits
C1
(0)
84
Info
Bits
F2
(0)
84
Info
Bits
C2
(0)
84
Info
Bits
F3
(0)
84
Info
Bits
C3
(0)
84
Info
Bits
F4
(1)
84
Info
Bits
M5 Subframe
84
M1
Info F1
(0)
Bits (1)
84
Info
Bits
C1
(0)
84
Info
Bits
F2
(0)
84
Info
Bits
C2
(0)
84
Info
Bits
F3
(0)
84
Info
Bits
C3
(0)
84
Info
Bits
F4
(1)
84
Info
Bits
M6 Subframe
84
Info F1
M2
Bits (1)
(1)
84
Info
Bits
C1
(0)
84
Info
Bits
F2
(0)
84
Info
Bits
C2
(0)
84
Info
Bits
F3
(0)
84
Info
Bits
C3
(0)
84
Info
Bits
F4
(1)
84
Info
Bits
M7 Subframe
84
M3
Info F1
(0)
Bits (1)
84
Info
Bits
C1
(0)
84
Info
Bits
F2
(0)
84
Info
Bits
C2
(0)
84
Info
Bits
F3
(0)
84
Info
Bits
C3
(0)
84
Info
Bits
F4
(1)
84
Info
Bits
Note 1: X1 is transmitted first.
Note 2: The 84 info bits contain the repetitive sequence 1010…, where the first 1 in the sequence immediately follows each X, P, F, C, or M bit.
8. DIAGNOSTICS
PRBS Generator and Detector. Each LIU has built-in pseudorandom bit sequence (PRBS) generator and detector
15
23
circuitry for physical layer testing. The device generates and detects unframed 2 - 1 (DS3 or STS-1) or 2 - 1
PRBS, according to the ITU O.151 specification. To transmit a PRBS pattern, pull the TDSA and TDSB pins high
(hardware mode) or set configuration bits TDSA and TDSB (CPU bus mode). As Table 4-F shows, the PRBS
15
23
generator automatically generates 2 - 1 for DS3 and STS-1 modes and 2 - 1 for E3 mode.
The PRBS detector, which is always enabled (Table 4-G), reports its status through the PRBS output pin (hardware
and CPU bus modes) or through the PRBS and PBER status bits (CPU bus mode). When the PRBS detector is out
of synchronization, the PRBS pin is forced high. When the detector syncs to an incoming PRBS pattern, the PRBS
pin is driven low, then pulses high, synchronous with RCLK, for each bit error detected. See Figure 8-1 and Figure
8-2 for details. In CPU bus mode, the PRBS status bit is set to one when the detector is out of synchronization and
set to zero when the detector syncs to an incoming PRBS pattern. A change of state of the PRBS bit can cause an
interrupt on the INT pin if the PRBSIE interrupt-enable bit is set to one. A pattern bit error can also cause an
interrupt if the PBERIE interrupt-enable bit is set to one. The PRBS detector also declares sync in the presence of
an incoming all-ones pattern.
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DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
Loopbacks. Each LIU has three internal loopbacks. See Figure 3-1 and Figure 3-2. The LLB and RLB pins
(hardware mode) or LLB and RLB control bits (CPU bus mode) enable these loopbacks. When LLB = RLB = 0,
loopbacks are disabled. Setting RLB = 1 with LLB = 0 enables remote loopback, which loops recovered clock and
data back through the LIU transmitter. During remote loopback, recovered clock and data are output on RCLK,
RPOS/RDAT, and RNEG/RLCV, but the TPOS/TDAT and TNEG pins are ignored. Setting LLB = 1 with RLB = 0
enables analog local loopback, which loops the outgoing transmit signal back to the receiver’s analog front end.
Setting LLB = RLB = 1 enables digital local loopback, which loops digital transmit clock and data back to the
receiver’s digital circuitry, including the LOS detector, the B3ZS/HDB3 decoder, and the PRBS detector. When
either of the local loopbacks is enabled, the transmit signal is output normally on TXP/TXN, but the received signal
on RXP/RXN is ignored.
Figure 8-1. PRBS Output with Normal RCLK Operation
RCINV = 0
RCLK
PRBS
PRBS DETECTOR
IS NOT IN SYNC
PRBS DETECTOR IS IN SYNC; THE
PRBS PIN PULSES HIGH FOR EACH BIT
ERROR DETECTED
Figure 8-2. PRBS Output with Inverted RCLK Operation
RCINV = 1
RCLK
PRBS
PRBS DETECTOR
IS NOT IN SYNC
PRBS DETECTOR IS IN SYNC; THE
PRBS PIN PULSES HIGH FOR EACH BIT
ERROR DETECTED
9. JITTER ATTENUATOR
Each LIU contains an on-board jitter attenuator that can be placed in the receive path or the transmit path or can
be disabled. The TJA and RJA pins (hardware mode) or the TJA and RJA control bits (CPU bus mode) specify how
the jitter attenuator is used. Setting TJA = RJA = 0 disables the jitter attenuator. To use the jitter attenuator in the
receive path, set RJA = 1 (with TJA = 0). To use it in the transmit path, set TJA = 1. Figure 9-1 shows the minimum
jitter attenuation for the device when the jitter attenuator is enabled. Figure 9-1 also shows the receive jitter transfer
when the jitter attenuator is disabled.
The jitter attenuator consists of a narrowband PLL to retime the selected clock, a 16 x 2-bit FIFO to buffer the
associated data while the clock is being retimed, and logic to prevent FIFO over/underflow in the presence of very
large jitter amplitudes.
The jitter attenuator requires a transmission-quality master clock (i.e., ±20ppm frequency accuracy and low jitter).
When enabled in the receive path, the JA can obtain its master clock from the appropriate MCLK pin or the TCLK
pin. If the signal on the MCLK pin is toggling, the JA uses the signal on the MCLK pin as its master clock. If the
MCLK pin is high, the JA uses the signal on the TCLK pin as its master clock. When enabled in the transmit path,
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DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
the JA must take its master clock from the MCLK pin. The clock and data recovery block also uses the selected
master clock.
The JA has a loop bandwidth of master_clock / 2,058,874 (see corner frequencies in Figure 9-1). The JA
attenuates jitter at frequencies higher than the loop bandwidth, while allowing jitter (and wander) at lower
frequencies to pass through relatively unaffected.
Figure 9-1. Jitter Attenuation/Jitter Transfer
21.7Hz (DS3)
16.7Hz (E3)
25.2Hz (STS-1)
27Hz
40Hz
1k
40k 59.6k
>150k
0
DS3 [GR-253 (1999)]
CATEGORY I
DS3 [GR-499 (1995)]
CATEGORY I
DS315x TYPICAL RECEIVER
JITTER TRANSFER WITH JITTER
ATTENUATOR DISABLED
JITTER ATTENUATION (dB)
STS-1 [GR-253
(1999)]
CATEGORY II
-10
-20
E3 [TBR24 (1997)]
DS315x
DS3/E3/STS-1
MINIMUM
JITTER
ATTENUATION
WITH JITTER
ATTENUATOR
ENABLED
DS3 [GR-499 (1999)]
CATEGORY II
-30
10
100
10k
1k
100k
1M
FREQUENCY (Hz)
10.
RESET LOGIC
There are four sources for reset: an internal power-on reset (POR) circuit, the reset pin RST, the JTAG reset pin
JTRST, and the RST bit in each LIU’s global configuration register (GCR). The chip is divided into three zones for
reset: the digital logic, the analog circuits, and the JTAG logic. The digital logic includes the status and control
registers, the B3ZS/HDB3 encoder and decoder, the PRBS generator and detector, and the LOS detect logic. The
analog circuits include clock and data recovery, jitter attenuator, and transmit waveform generation. The JTAG
logic consists of the common boundary scan controller and the boundary scan cells at each pin.
The POR circuit resets the digital logic, analog circuits, and JTAG logic zones. The RST pin resets the digital logic
and the analog circuits but not the JTAG logic. The JTRST pin resets only the JTAG logic. Each LIU’s RST register
bit resets the digital logic for that LIU, including resetting the LIU’s registers to the default state (except for the RST
bit).
The POR signal and RST pin require an active master clock source for the LIU to properly reset.
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DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
11.
TRANSFORMERS
Table 11-A. Transformer Characteristics
PARAMETER
Turns Ratio
Bandwidth 75W
Primary Inductance
Leakage Inductance
Interwinding Capacitance
Isolation Voltage
VALUE
1:2ct ±2%
0.250MHz to 500MHz (typ)
19mH (min)
0.150mH (max)
10pF (max)
1500VRMS (min)
Table 11-B. Recommended Transformers
MANUFACTURER
Pulse Engineering
NO. OF
TRANSFORMERS
PART
TEMP RANGE
1
PE-65968
0°C to +70°C
1
PE-65969
0°C to +70°C
8
T3049
0°C to +70°C
1
TG07-0206NS
0°C to +70°C
1
TD07-0206NE
0°C to +70°C
Halo Electronics
PIN-PACKAGE/
SCHEMATIC
6 SMT
LS-1/C
6 Thru-Hole
LC-1/C
32 SMT
YB/1
6 SMT
SMD/B
6 DIP
DIP/B
Note: Table subject to change. Industrial temperature range and other multiples (dual, quad) are also available. Contact the manufacturers for
details at www.pulseeng.com and www.haloelectronics.com.
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DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
12.
JTAG TEST ACCESS PORT AND BOUNDARY SCAN
12.1
JTAG Description
The DS315x LIUs support the standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional
public instructions included are HIGHZ, CLAMP, and IDCODE. Figure 12-1 features a block diagram. The LIUs
contain the following items, which meet the requirements set by the IEEE 1149.1 Standard Test Access Port and
Boundary Scan Architecture:
Test Access Port (TAP)
TAP Controller
Instruction Register
Bypass Register
Boundary Scan Register
Device Identification Register
The TAP has the necessary interface pins, namely JTCLK, JTRST, JTDI, JTDO, and JTMS. Details on these pins
can be found in Section 4. Details about the boundary scan architecture and the TAP can be found in IEEE 1149.11990, IEEE 1149.1a-1993, and IEEE 1149.1b-1994.
Figure 12-1. JTAG Block Diagram
BOUNDARY
SCAN
REGISTER
MUX
IDENTIFICATION
REGISTER
BYPASS
REGISTER
INSTRUCTION
REGISTER
SELECT
TEST ACCESS PORT
CONTROLLER
10k
JTDI
10k
JTMS
TRI-STATE
10k
JTCLK
JTRST
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JTDO
DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
12.2
JTAG TAP Controller State Machine Description
This section discusses the operation of the TAP controller state machine. The TAP controller is a finite state
machine that responds to the logic level at JTMS on the rising edge of JTCLK. Each of the states denoted in Figure
12-2 are described in the following pages.
Figure 12-2. JTAG TAP Controller State Machine
Test-Logic-Reset
1
0
Run-Test/Idle
1
Select
DR-Scan
1
0
1
Select
IR-Scan
0
0
1
1
Capture-DR
Capture-IR
0
0
Shift-DR
Shift-IR
0
0
1
1
1
Exit1- DR
0
0
Pause-DR
Pause-IR
0
1
0
0
1
0
Exit2-DR
Exit2-IR
1
1
Update-DR
1
1
Exit1-IR
0
Update-IR
1
0
Test-Logic-Reset. Upon device power-up, the TAP controller starts in the Test-Logic-Reset state. The instruction
register contains the IDCODE instruction. All system logic on the device operates normally.
Run-Test-Idle. Run-Test-Idle is used between scan operations or during specific tests. The instruction and test
registers remain idle.
Select-DR-Scan. All test registers retain their previous state. With JTMS low, a rising edge of JTCLK moves the
controller into the Capture-DR state and initiates a scan sequence. JTMS high moves the controller to the SelectIR-SCAN state.
Capture-DR. Data can be parallel loaded into the test data registers selected by the current instruction. If the
instruction does not call for a parallel load or the selected register does not allow parallel loads, the test register
remains at its current value. On the rising edge of JTCLK, the controller goes to the Shift-DR state if JTMS is low or
to the Exit1-DR state if JTMS is high.
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DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
Shift-DR. The test data register selected by the current instruction is connected between JTDI and JTDO and shifts
data one stage toward its serial output on each rising edge of JTCLK. If a test register selected by the current
instruction is not placed in the serial path, it maintains its previous state.
Exit1-DR. While in this state, a rising edge on JTCLK with JTMS high puts the controller in the Update-DR state,
which terminates the scanning process. A rising edge on JTCLK with JTMS low puts the controller in the Pause-DR
state.
Pause-DR. Shifting of the test registers is halted while in this state. All test registers selected by the current
instruction retain their previous state. The controller remains in this state while JTMS is low. A rising edge on
JTCLK with JTMS high puts the controller in the Exit2-DR state.
Exit2-DR. While in this state, a rising edge on JTCLK with JTMS high puts the controller in the Update-DR state
and terminates the scanning process. A rising edge on JTCLK with JTMS low puts the controller in the Shift-DR
state.
Update-DR. A falling edge on JTCLK while in the Update-DR state latches the data from the shift register path of
the test registers into the data output latches. This prevents changes at the parallel output because of changes in
the shift register. A rising edge on JTCLK with JTMS low puts the controller in the Run-Test-Idle state. With JTMS
high, the controller enters the Select-DR-Scan state.
Select-IR-Scan. All test registers retain their previous state. The instruction register remains unchanged during this
state. With JTMS low, a rising edge on JTCLK moves the controller into the Capture-IR state and initiates a scan
sequence for the instruction register. JTMS high during a rising edge on JTCLK puts the controller back into the
Test-Logic-Reset state.
Capture-IR. The Capture-IR state is used to load the shift register in the instruction register with a fixed value. This
value is loaded on the rising edge of JTCLK. If JTMS is high on the rising edge of JTCLK, the controller enters the
Exit1-IR state. If JTMS is low on the rising edge of JTCLK, the controller enters the Shift-IR state.
Shift-IR. In this state, the instruction register’s shift register is connected between JTDI and JTDO and shifts data
one stage for every rising edge of JTCLK toward the serial output. The parallel register and the test registers
remain at their previous states. A rising edge on JTCLK with JTMS high moves the controller to the Exit1-IR state.
A rising edge on JTCLK with JTMS low keeps the controller in the Shift-IR state, while moving data one stage
through the instruction shift register.
Exit1-IR. A rising edge on JTCLK with JTMS low puts the controller in the Pause-IR state. If JTMS is high on the
rising edge of JTCLK, the controller enters the Update-IR state and terminates the scanning process.
Pause-IR. Shifting of the instruction register is halted temporarily. With JTMS high, a rising edge on JTCLK puts
the controller in the Exit2-IR state. The controller remains in the Pause-IR state if JTMS is low during a rising edge
on JTCLK.
Exit2-IR. A rising edge on JTCLK with JTMS high puts the controller in the Update-IR state. The controller loops
back to the Shift-IR state if JTMS is low during a rising edge of JTCLK in this state.
Update-IR. The instruction shifted into the instruction shift register is latched into the parallel output on the falling
edge of JTCLK as the controller enters this state. Once latched, this instruction becomes the current instruction. A
rising edge on JTCLK with JTMS low puts the controller in the Run-Test-Idle state. With JTMS high, the controller
enters the Select-DR-Scan state.
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DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
12.3
JTAG Instruction Register and Instructions
The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When the
TAP controller enters the Shift-IR state, the instruction shift register is connected between JTDI and JTDO. While in
the Shift-IR state, a rising edge on JTCLK with JTMS low shifts data one stage toward the serial output at JTDO. A
rising edge on JTCLK in the Exit1-IR state or the Exit2-IR state with JTMS high moves the controller to the UpdateIR state. The falling edge of that same JTCLK latches the data in the instruction shift register to the instruction
parallel output. Table 12-A shows the instructions supported by the DS315x and their respective operational binary
codes.
Table 12-A. JTAG Instruction Codes
INSTRUCTIONS
SAMPLE/PRELOAD
BYPASS
EXTEST
CLAMP
HIGHZ
IDCODE
SELECTED REGISTER
Boundary Scan
Bypass
Boundary Scan
Bypass
Bypass
Device Identification
INSTRUCTION CODES
010
111
000
011
100
001
SAMPLE/PRELOAD. SAMPLE/RELOAD is a mandatory instruction for the IEEE 1149.1 specification. This
instruction supports two functions. The digital I/Os of the device can be sampled at the boundary scan register
without interfering with the device’s normal operation by using the Capture-DR state. SAMPLE/PRELOAD also
allows the DS315x to shift data into the boundary scan register through JTDI using the Shift-DR state.
EXTEST. EXTEST allows testing of the interconnections to the device. When the EXTEST instruction is latched in
the instruction register, the following actions occur. Once enabled through the Update-IR state, the parallel outputs
of the digital output pins are driven. The boundary scan register is connected between JTDI and JTDO. The
Capture-DR samples all digital inputs into the boundary scan register.
BYPASS. When the BYPASS instruction is latched into the parallel instruction register, JTDI connects to JTDO
through the 1-bit bypass test register. This allows data to pass from JTDI to JTDO without affecting the device’s
normal operation.
IDCODE. When the IDCODE instruction is latched into the parallel instruction register, the identification test
register is selected. The device identification code is loaded into the identification register on the rising edge of
JTCLK, following entry into the Capture-DR state. Shift-DR can be used to shift the identification code out serially
through JTDO. During Test-Logic-Reset, the identification code is forced into the instruction register’s parallel
output.
HIGHZ. All digital outputs are placed into a high-impedance state. The bypass register is connected between JTDI
and JTDO.
CLAMP. All digital output pins output data from the boundary scan parallel output while connecting the bypass
register between JTDI and JTDO. The outputs do not change during the CLAMP instruction.
Table 12-B. JTAG ID Code
PART
DS3154
DS3153
DS3152
DS3151
REVISION
Consult factory
Consult factory
Consult factory
Consult factory
DEVICE CODE
0000000000110011
0000000000110010
0000000000110000
0000000000100000
MANUFACTURER CODE
00010100001
00010100001
00010100001
00010100001
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REQUIRED
1
1
1
1
DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
12.4
JTAG Test Registers
IEEE 1149.1 requires a minimum of two test registers—the bypass register and the boundary scan register. An
optional test register, the identification register, has been included in the device design. It is used with the IDCODE
instruction and the Test-Logic-Reset state of the TAP controller.
Bypass Register. This single 1-bit shift register, used with the BYPASS, CLAMP, and HIGHZ instructions,
provides a short path between JTDI and JTDO.
Boundary Scan Register. This register contains a shift register path and a latched parallel output for control cells
and digital I/O cells. DS315x BSDL files are available at www.maxim-ic.com/TechSupport/telecom/bsdl.htm.
Identification Register. This register contains a 32-bit shift register and a 32-bit latched parallel output. It is
selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-Reset state.
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13.
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Lead with Respect to VSS (except VDD)
Supply Voltage Range (VDD) with Respect to VSS
Ambient Operating Temperature Range
Junction Operating Temperature Range
Storage Temperature Range
Soldering Temperature
-0.3V to +5.5V
-0.3V to +3.63V
-40°C to +85°C
-40°C to +125°C
-55°C to +125°C
See IPC/JEDEC J-STD-020A Specification
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device. Ambient operating temperature range
when device is mounted on a four-layer JEDEC test board with no airflow.
Note: The typical values listed in Tables 13-A through 13-I are not production tested.
Table 13-A. Recommended DC Operating Conditions
(TA = -40°C to +85°C)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Logic 1
VIH
2.0
5.5
V
Logic 0
VIL
-0.3
+0.8
V
Supply Voltage
VDD
3.135
3.3
3.465
V
MIN
TYP
MAX
100
200
300
400
80
150
225
300
UNITS
70
mA
Table 13-B. DC Characteristics
(VDD = 3.3V ±5%, TA = -40°C to +85°C.)
PARAMETER
Supply Current (Note 1)
SYMBOL
IDD
Supply Current, Transmitters Tri-Stated
(All TTSn Low) (Note 2)
IDDTTS
Power-Down Current (All TPD, RPD
Control Bits High)
IDDPD
Lead Capacitance
CONDITIONS
DS3151
DS3152
DS3153
DS3154
DS3151
DS3152
DS3153
DS3154
DS315x (Note 2)
55
CIO
7
mA
mA
pF
Input Leakage
IIL
(Note 3)
-50
+10
mA
Output Leakage (when High-Z)
ILO
(Note 3)
-10
+10
mA
Output Voltage (IO = -4.0mA)
VOH
2.4
VDD
V
Output Voltage (IO = +4.0mA)
VOL
0
0.4
V
Note 1: TCLKn = STMCLK = 51.84MHz; TXPn/TXNn driving all ones into 75W resistive loads; analog loopback enabled; all other inputs at VDD
or grounded; all other outputs open.
Note 2: TCLKn = STMCLK = 51.84MHz; other inputs at VDD or grounded; digital outputs left open circuited.
Note 3: 0V < VIN < VDD.
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DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
Table 13-C. Framer Interface Timing
(VDD = 3.3V ±5%, TA = -40°C to +85°C.) (Figure 13-1 and Figure 13-2)
PARAMETER
SYMBOL
CONDITIONS
(Note 4)
(Note 5)
RCLK/TCLK Clock Period
t1
(Note 6)
MIN
TYP
22.4
29.1
19.3
MAX
UNITS
50
55
%
ns
RCLK Duty Cycle
t2/t1, t3/t1
(Notes 7, 8)
45
TCLK Duty Cycle
t2/t1, t3/t1
(Note 8)
30
70
%
MCLK Duty Cycle
t2/t1, t3/t1
(Note 8)
30
70
%
TPOS/TDAT, TNEG to TCLK Setup
Time
t4
(Notes 8, 9)
2
ns
TPOS/TDAT, TNEG Hold Time
t5
(Notes 8, 9)
2
ns
RCLK to RPOS/RDAT, RNEG/RLCV,
and PRBS Value Change
t6
(Notes 7, 8, 10)
2
RCLK Rise and Fall Time
t7
(Notes 8, 11)
TCLK Rise and Fall Time
t8
(Notes 8, 12)
6
5
ns
ns
5
ns
Note 4: DS3 mode.
Note 5: E3 mode.
Note 6: STS-1 mode.
Note 7: Outputs loaded with 25pF, measured at 50% threshold.
Note 8: Not tested during production test.
Note 9: When TCINV = 0, TPOS/TDAT and TNEG are sampled on the rising edge of TCLK. When TCINV = 1, TPOS/TDAT and TNEG are
sampled on the falling edge of TCLK.
Note 10: When RCINV = 0, RPOS/RDAT and RNEG/RLCV are updated on the falling edge of RCLK. When RCINV = 1, RPOS/RDAT and
RNEG/RLCV are updated on the rising edge of RCLK.
Note 11: Outputs loaded with 25pF, measured between VOL (max) and VOH (min).
Note 12: Measured between VIL (max) and VIH (min).
Figure 13-1. Transmitter Framer Interface Timing Diagram
t1
t2
t3
TCLK (NORMAL)
TCLK (INVERTED)
t8
t4
t5
TPOS/TDAT,
TNEG
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DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
Figure 13-2. Receiver Framer Interface Timing Diagram
t1
t2
t3
RCLK (NORMAL)
RCLK (INVERTED)
t6
t7
RPOS/RDAT,
RNEG/RLCV
Table 13-D. Receiver Input Characteristics—DS3 and STS-1 Modes
(VDD = 3.3V ±5%, TA = -40°C to +85°C.)
PARAMETER
Receive Sensitivity (Length of Cable)
Signal-to-Noise Ratio, Interfering Signal Test (Notes 13, 14)
Input Pulse Amplitude, RMON = 0 (Notes 14, 15)
Input Pulse Amplitude, RMON = 1 (Note 14, 15)
Analog LOS Declare, RMON = 0 (Note 16)
Analog LOS Clear, RMON = 0 (Note 16)
Analog LOS Declare, RMON = 1 (Note 16)
Analog LOS Clear, RMON = 1 (Note 16)
Intrinsic Jitter Generation (Note 14)
MIN
900
TYP
1200
10
MAX
UNITS
ft
1000
200
-24
mVpk
mVpk
dB
dB
dB
dB
UIP-P
-17
-38
-29
0.03
Table 13-E. Receiver Input Characteristics—E3 Mode
(VDD = 3.3V ±5%, TA = -40°C to +85°C.)
PARAMETER
Receive Sensitivity (Length of Cable)
Signal-to-Noise Ratio, Interfering Signal Test (Notes 13, 14)
Input Pulse Amplitude, RMON = 0 (Notes 14, 15)
Input Pulse Amplitude, RMON = 1 (Notes 14, 15)
Analog LOS Declare, RMON = 0 (Note 16)
Analog LOS Clear, RMON = 0 (Note 16)
Analog LOS Declare, RMON = 1 (Note 16)
Analog LOS Clear, RMON = 1 (Note 16)
Intrinsic Jitter Generation (Note 14)
15
23
MIN
900
TYP
1200
12
MAX
UNITS
ft
1300
260
-24
mVpk
mVpk
dB
dB
dB
dB
UIP-P
-17
-38
-29
0.03
Note 13: An interfering signal (2 - 1 PRBS for DS3/STS-1, 2 - 1 PRBS for E3, B3ZS/HDB3 encoded, compliant waveshape, nominal bit rate)
is added to the wanted signal. The combined signal is passed through 0 to 900ft of coaxial cable and presented to the DS3154
receiver. This spec indicates the lowest signal-to-noise ratio that results in a bit error ratio <10-9.
Note 14: Not tested during production test.
Note 15: Measured on the line side (i.e., the BNC connector side) of the 1:2 receive transformer (Figure 1-1). During measurement, incoming
data traffic is unframed 215 - 1 PRBS for DS3/STS-1 and unframed 223 - 1 PRBS for E3.
Note 16: With respect to nominal 800mVpk signal for DS3/STS-1 and nominal 1000mVpk signal for E3.
39 of 60
DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
Table 13-F. Transmitter Output Characteristics—DS3 and STS-1 Modes
(VDD = 3.3V ±5%, TA = -40°C to +85°C.)
PARAMETER
DS3 Output Pulse Amplitude, TLBO = 0 (Note 17)
DS3 Output Pulse Amplitude, TLBO = 1 (Note 17)
STS-1 Output Pulse Amplitude, TLBO = 0 (Note 17)
STS-1 Output Pulse Amplitude, TLBO = 1 (Note 17)
Ratio of Positive and Negative Pulse-Peak Amplitudes
DS3 Unframed All-Ones Power Level at 22.368MHz, 3kHz Bandwidth
DS3 Unframed All-Ones Power Level at 44.736MHz vs. Power Level at
22.368MHz, 3kHz Bandwidth
Intrinsic Jitter Generation (Note 18)
MIN
700
520
700
520
0.9
-1.8
TYP
800
700
800
700
MAX
900
800
1100
850
1.1
+5.7
UNITS
mVpk
mVpk
mVpk
mVpk
-20
dB
0.02
0.05
UIP-P
TYP
1000
14.55
MAX
1100
UNITS
mVpk
ns
dBm
Table 13-G. Transmitter Output Characteristics—E3 Mode
(VDD = 3.3V ±5%, TA = -40°C to +85°C.)
PARAMETER
Output Pulse Amplitude (Note 17)
Pulse Width
Ratio of Positive and Negative Pulse Amplitudes (at Centers of Pulses)
Ratio of Positive and Negative Pulse Widths (at Nominal Half Amplitude)
Intrinsic Jitter Generation (Note 18)
MIN
900
0.95
0.95
0.02
1.05
1.05
0.05
UIP-P
Note 17: Measured on the line side (i.e., the BNC connector side) of the 2:1 transmit transformer (Figure 1-1).
Note 18: Measured with jitter-free clock applied to TCLK and a bandpass jitter filter with 10Hz and 800kHz cutoff frequencies. Not tested during
production test.
Table 13-H. CPU Bus Timing
(VDD = 3.3V ±5%, TA = -40°C to +85°C.) (Figure 13-3 and Figure 13-4)
PARAMETER
Setup Time for A[5:0] Valid to CS Active (Notes 19, 20)
Setup Time for CS Active to RD, WR, or DS Active
Delay Time from RD or DS Active to D[7:0] Valid
Hold Time from RD or WR or DS Inactive to CS Inactive
Delay from CS or RD or DS Inactive to D[7:0] Invalid or Tri-State
(Note 21)
Wait Time from WR or DS Active to Latch D[7:0]
D[7:0] Setup Time to WR or DS Inactive
D[7:0] Hold Time from WR or DS Inactive
A[5:0] Hold Time from WR or RD or DS Inactive
RD, WR, or DS Inactive Time
Muxed Address Valid to ALE Falling (Note 22)
Muxed Address Hold Time (Note 22)
ALE Pulse Width (Note 22)
Setup Time for ALE High or Muxed Address Valid to CS Active
(Note 22)
SYMBOL
t1
t2
t3
t4
MIN
0
0
TYP
MAX
t5
2
t6
t7
t8
t9
t10
t11
t12
t13
65
10
2
5
75
10
10
30
ns
ns
ns
ns
ns
ns
ns
ns
t14
0
ns
65
0
20
UNITS
ns
ns
ns
ns
ns
Note 19: D[7:0] loaded with 50pF when tested as outputs.
Note 20: If a gapped clock is applied on TCLK and diagnostic loopback is enabled, read cycle time must be extended by the length of the
largest TCLK gap.
Note 21: Not tested during production test.
Note 22: In nonmultiplexed bus applications (Figure 13-3), ALE should be wired high. In multiplexed bus applications (Figure 13-4), A[5:0]
should be wired to D[5:0] and the falling edge of ALE latches the address.
40 of 60
DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
Figure 13-3. CPU Bus Timing Diagram (Nonmultiplexed)
INTEL READ CYCLE
t9
A[5:0]
ADDRESS VALID
D[7:0]
DATA VALID
t5
WR
t1
CS
t2
t3
t4
t10
RD
INTEL WRITE CYCLE
t9
A[5:0]
ADDRESS VALID
D[7:0]
t7
t8
RD
t1
CS
t2
t6
t4
t10
WR
41 of 60
DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
Figure 13-3. CPU Bus Timing Diagram (Nonmultiplexed)(continued)
MOTOROLA READ CYCLE
t9
A[5:0]
ADDRESS VALID
D[7:0]
DATA VALID
t5
R/W
t1
CS
t2
t3
t4
t10
DS
MOTOROLA WRITE CYCLE
t9
A[5:0]
ADDRESS VALID
D[7:0]
t7
t8
R/W
t1
CS
t2
t6
t4
t10
DS
42 of 60
DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
Figure 13-4. CPU Bus Timing Diagram (Multiplexed)
INTEL READ CYCLE
t13
ALE
t12
t11
ADDRESS
A[5:0]
VALID
t14
D[7:0]
DATA VALID
t14
t5
WR
CS
t2
t3
t4
t10
RD
NOTE: t14 STARTS ON THE OCCURRENCE OF EITHER THE RISING EDGE OF ALE OR A VALID ADDRESS, WHICHEVER OCCURS LAST.
INTEL WRITE CYCLE
t13
ALE
t12
t11
A[5:0]
ADDRESS
VALID
t14
D[7:0]
t14
t7
t8
RD
CS
t2
t6
t4
t10
WR
NOTE: t14 STARTS ON THE OCCURRENCE OF EITHER THE RISING EDGE OF ALE OR A VALID ADDRESS, WHICHEVER OCCURS LAST.
43 of 60
DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
Figure 13-4. CPU Bus Timing Diagram (Multiplexed) (continued)
MOTOROLA READ CYCLE
t13
ALE
t12
t11
ADDRESS
VALID
A[5:0]
t14
D[7:0]
DATA VALID
t14
t5
R/W
CS
t2
t4
t3
t10
DS
NOTE: t14 STARTS ON THE OCCURRENCE OF EITHER THE RISING EDGE OF ALE OR A VALID ADDRESS, WHICHEVER OCCURS LAST.
MOTOROLA WRITE CYCLE
t13
ALE
A[5:0]
t12
t11
ADDRESS
VALID
t14
D[7:0]
t14
t7
R/W
t8
CS
t2
t6
t4
t10
DS
NOTE: t14 STARTS ON THE OCCURRENCE OF EITHER THE RISING EDGE OF ALE OR A VALID ADDRESS, WHICHEVER OCCURS LAST.
44 of 60
DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
Table 13-I. JTAG Interface Timing
(VDD = 3.3V ±5%, TA = -40°C to +85°C.) (Figure 13-5)
PARAMETER
SYMBOL
JTCLK Clock Period
t1
JTCLK Clock High/Low Time (Note 23)
t2/t3
JTCLK to JTDI, JTMS Setup Time
t4
JTCLK to JTDI, JTMS Hold Time
t5
JTCLK to JTDO Delay
t6
JTCLK to JTDO High-Z Delay (Note 24)
t7
t8
JTRST Width Low Time
MIN
50
50
50
2
2
100
Figure 13-5. JTAG Timing Diagram
t1
t3
JTCLK
t4
t5
JTDI, JTMS, JTRST
t6
t7
JTDO
t8
JTRST
45 of 60
MAX
50
50
Note 23: Clock can be stopped high or low.
Note 24: Not tested during production test.
t2
TYP
1000
500
UNITS
ns
ns
ns
ns
ns
ns
ns
DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
14.
PIN ASSIGNMENTS
Table 14-A lists pin assignments sorted by signal name. Table 14-B lists pin assignments sorted by pin number.
DS3154 has all four LIUs. DS3153 has only LIUs 1, 2, and 3. DS3152 has only LIUs 1 and 2. DS3151 has only LIU
1. Figure 14-1 through Figure 14-8 show pinouts for the four devices in both hardware and CPU bus modes.
Table 14-A. Pin Assignments Sorted by Signal Name
PIN
NAME
HARDWARE
MODE
CPU BUS
MODE
A[0]
N
Y
K6
A[1]
N
Y
L6
A[2]
N
Y
K7
A[3]
N
Y
L7
A[4]
N
Y
K8
LIU 1
LIU 2
A[5]
N
Y
L8
ALE
N
Y
C7
CS
N
Y
B7
D[0]
N
Y
E3
D[1]
N
Y
F2
D[2]
N
Y
F3
D[3]
N
Y
G2
D[4]
N
Y
G3
D[5]
N
Y
H2
D[6]
N
Y
H3
D[7]
N
Y
J3
E3MCLK
Y
Y
E12
E3Mn
Y
N
HIZ
Y
Y
J8
HW
Y
Y
E9
INT
N
Y
C5
JTCLK
Y
Y
E4
JTDI
Y
Y
H4
JTDO
Y
Y
J4
JTMS
Y
Y
D5
JTRST
Y
Y
D4
LLBn
Y
N
MOT
N
Y
PRBSn
Y
Y
F3
B5
G10
L8
LIU 3
LIU 4
C7
K6
E11
H2
A11
M2
A10
M3
C6
B1
L12
RBIN
Y
N
D9
RCINV
Y
N
J9
RCLKn
Y
Y
RD
N
Y
RJAn
Y
N
B4
L9
D11
J2
RLBn
Y
N
C5
K8
E10
H3
RLOSn
Y
Y
A1
M12
A12
M1
C1
K12
B6
46 of 60
DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
Table 14-A. Pin Assignments Sorted by Signal Name (continued)
PIN
NAME
HARDWARE
MODE
CPU
MODE
LIU 1
LIU 2
LIU 3
LIU 4
RNEGn
Y
Y
C3
K10
C10
K3
RPOSn
Y
Y
C2
K11
B10
L3
RST
Y
Y
RTSn
Y
Y
B2
L11
B11
L2
RXNn
Y
Y
A2
M11
B12
L1
RXPn
Y
Y
A3
M10
C12
K1
STMCLK
Y
Y
B7
L6
H1
M8
STSn
Y
N
T3MCLK
Y
Y
F2
G11
A5
TBIN
Y
N
D8
TCINV
Y
N
H9
TCLKn
Y
Y
E1
H12
A8
M5
TDMn
Y
Y
D3
J10
C9
K4
TDSAn
Y
N
G2
F11
B6
L7
TDSBn
Y
N
G3
F10
C6
K7
TEST
Y
Y
TJAn
Y
N
C4
K9
D10
J3
TLBOn
Y
N
E3
H10
C8
K5
TNEGn
Y
Y
D2
J11
B9
L4
TPOSn
Y
Y
D1
J12
A9
M4
TTSn
Y
Y
E2
H11
B8
L5
TXNn
Y
Y
G1
F12
A6
M7
F1
G12
A7
M6
J5
TXPn
Y
Y
VDD
Y
Y
D6, E5, E6, F4, F5, F6, G7, G8, G9, H7, H8, J7
VSS
Y
Y
D7, E7, E8, F7, F8, F9, G4, G5, G6, H5, H6, J6
WR
N
Y
B5
47 of 60
DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
Table 14-B. Pin Assignments Sorted by Pin Number
PIN
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
E1
E2
E3
E4
E5
E6
E7
E8
DS3154
HARDWARE CPU BUS
MODE
MODE
RLOS1
RLOS1
RXN1
RXN1
RXP1
RXP1
RMON1
N.C.
T3MCLK
T3MCLK
TXN3
TXN3
TXP3
TXP3
TCLK3
TCLK3
TPOS3
TPOS3
RCLK3
RCLK3
PRBS3
PRBS3
RLOS3
RLOS3
PRBS1
PRBS1
RTS1
RTS1
N.C.
N.C.
RJA1
N.C.
LLB1
WR
TDSA3
RD
STS3
CS
TTS3
TTS3
TNEG3
TNEG3
RPOS3
RPOS3
RTS3
RTS3
RXN3
RXN3
RCLK1
RCLK1
RPOS1
RPOS1
RNEG1
RNEG1
TJA1
N.C.
RLB1
INT
TDSB3
MOT
E3M3
ALE
TLBO3
N.C.
TDM3
TDM3
RNEG3
RNEG3
N.C.
N.C.
RXP3
RXP3
TPOS1
TPOS1
TNEG1
TNEG1
TDM1
TDM1
JTRST
JTRST
JTMS
JTMS
VDD
VDD
VSS
VSS
TBIN
N.C.
RBIN
N.C.
TJA3
N.C.
RJA3
N.C.
RMON3
N.C.
TCLK1
TCLK1
TTS1
TTS1
TLBO1
D0
JTCLK
JTCLK
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
DS3153
HARDWARE
CPU BUS
MODE
MODE
RLOS1
RLOS1
RXN1
RXN1
RXP1
RXP1
RMON1
N.C.
T3MCLK
T3MCLK
TXN3
TXN3
TXP3
TXP3
TCLK3
TCLK3
TPOS3
TPOS3
RCLK3
RCLK3
PRBS3
PRBS3
RLOS3
RLOS3
PRBS1
PRBS1
RTS1
RTS1
N.C.
N.C.
RJA1
N.C.
LLB1
WR
TDSA3
RD
STS3
CS
TTS3
TTS3
TNEG3
TNEG3
RPOS3
RPOS3
RTS3
RTS3
RXN3
RXN3
RCLK1
RCLK1
RPOS1
RPOS1
RNEG1
RNEG1
TJA1
N.C.
RLB1
INT
TDSB3
MOT
E3M3
ALE
TLBO3
N.C.
TDM3
TDM3
RNEG3
RNEG3
N.C.
N.C.
RXP3
RXP3
TPOS1
TPOS1
TNEG1
TNEG1
TDM1
TDM1
JTRST
JTRST
JTMS
JTMS
VDD
VDD
VSS
VSS
TBIN
N.C.
RBIN
N.C.
TJA3
N.C.
RJA3
N.C.
RMON3
N.C.
TCLK1
TCLK1
TTS1
TTS1
TLBO1
D0
JTCLK
JTCLK
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
48 of 60
DS3152
HARDWARE CPU BUS
MODE
MODE
RLOS1
RLOS1
RXN1
RXN1
RXP1
RXP1
RMON1
N.C.
T3MCLK
T3MCLK
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
PRBS1
PRBS1
RTS1
RTS1
N.C.
N.C.
RJA1
N.C.
LLB1
WR
N.C.
RD
N.C.
CS
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
RCLK1
RCLK1
RPOS1
RPOS1
RNEG1
RNEG1
TJA1
N.C.
RLB1
INT
N.C.
MOT
N.C.
ALE
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
TPOS1
TPOS1
TNEG1
TNEG1
TDM1
TDM1
JTRST
JTRST
JTMS
JTMS
VDD
VDD
VSS
VSS
TBIN
N.C.
RBIN
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
TCLK1
TCLK1
TTS1
TTS1
TLBO1
D0
JTCLK
JTCLK
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
DS3151
HARDWARE CPU BUS
MODE
MODE
RLOS1
RLOS1
RXN1
RXN1
RXP1
RXP1
RMON1
N.C.
T3MCLK
T3MCLK
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
PRBS1
PRBS1
RTS1
RTS1
N.C.
N.C.
RJA1
N.C.
LLB1
WR
N.C.
RD
N.C.
CS
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
RCLK1
RCLK1
RPOS1
RPOS1
RNEG1
RNEG1
TJA1
N.C.
RLB1
INT
N.C.
MOT
N.C.
ALE
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
TPOS1
TPOS1
TNEG1
TNEG1
TDM1
TDM1
JTRST
JTRST
JTMS
JTMS
VDD
VDD
VSS
VSS
TBIN
N.C.
RBIN
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
TCLK1
TCLK1
TTS1
TTS1
TLBO1
D0
JTCLK
JTCLK
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
PIN
E9
E10
E11
E12
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
J11
J12
K1
K2
K3
K4
K5
K6
DS3154
HARDWARE CPU BUS
MODE
MODE
HW
HW
RLB3
N.C.
LLB3
N.C.
E3MCLK
E3MCLK
TXP1
TXP1
STS1
D1
E3M1
D2
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
TDSB2
N.C.
TDSA2
N.C.
TXN2
TXN2
TXN1
TxN1
TDSA1
D3
TDSB1
D4
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
E3M2
N.C.
STS2
N.C.
TXP2
TXP2
RST
RST
LLB4
D5
RLB4
D6
JTDI
JTDI
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
TCINV
N.C.
TLBO2
N.C.
TTS2
TTS2
TCLK2
TCLK2
RMON4
N.C.
RJA4
N.C.
TJA4
D7
JTDO
JTDO
TEST
TEST
VSS
VSS
VDD
VDD
HIZ
HIZ
RCINV
N.C
TDM2
TDM2
TNEG2
TNEG2
TPOS2
TPOS2
RXP4
RXP4
N.C.
N.C.
RNEG4
RNEG4
TDM4
TDM4
TLBO4
N.C.
E3M4
A0
DS3153
HARDWARE
CPU BUS
MODE
MODE
HW
HW
RLB3
N.C.
LLB3
N.C.
E3MCLK
E3MCLK
TXP1
TXP1
STS1
D1
E3M1
D2
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
TDSB2
N.C.
TDSA2
N.C.
TXN2
TXN2
TXN1
TXN1
TDSA1
D3
TDSB1
D4
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
E3M2
N.C.
STS2
N.C.
TXP2
TXP2
RST
RST
N.C.
D5
N.C.
D6
JTDI
JTDI
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
TCINV
N.C.
TLBO2
N.C.
TTS2
TTS2
TCLK2
TCLK2
N.C.
N.C.
N.C.
N.C.
N.C.
D7
JTDO
JTDO
TEST
TEST
VSS
VSS
VDD
VDD
HIZ
HIZ
RCINV
N.C
TDM2
TDM2
TNEG2
TNEG2
TPOS2
TPOS2
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
A0
49 of 60
DS3152
HARDWARE CPU BUS
MODE
MODE
HW
HW
N.C.
N.C.
N.C.
N.C.
E3MCLK
E3MCLK
TXP1
TXP1
STS1
D1
E3M1
D2
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
TDSB2
N.C.
TDSA2
N.C.
TXN2
TXN2
TXN1
TXN1
TDSA1
D3
TDSB1
D4
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
E3M2
N.C.
STS2
N.C.
TXP2
TXP2
RST
RST
N.C.
D5
N.C.
D6
JTDI
JTDI
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
TCINV
N.C.
TLBO2
N.C.
TTS2
TTS2
TCLK2
TCLK2
N.C.
N.C.
N.C.
N.C.
N.C.
D7
JTDO
JTDO
TEST
TEST
VSS
VSS
VDD
VDD
HIZ
HIZ
RCINV
N.C
TDM2
TDM2
TNEG2
TNEG2
TPOS2
TPOS2
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
A0
DS3151
HARDWARE CPU BUS
MODE
MODE
HW
HW
N.C.
N.C.
N.C.
N.C.
E3MCLK
E3MCLK
TXP1
TXP1
STS1
D1
E3M1
D2
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
TXN1
TXN1
TDSA1
D3
TDSB1
D4
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
RST
RST
N.C.
D5
N.C.
D6
JTDI
JTDI
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
TCINV
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
D7
JTDO
JTDO
TEST
TEST
VSS
VSS
VDD
VDD
HIZ
HIZ
RCINV
N.C
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
A0
DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
PIN
K7
K8
K9
K10
K11
K12
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
L12
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
DS3154
HARDWARE CPU BUS
MODE
MODE
TDSB4
A2
RLB2
A4
TJA2
N.C.
RNEG2
RNEG2
RPOS2
RPOS2
RCLK2
RCLK2
RXN4
RXN4
RTS4
RTS4
RPOS4
RPOS4
TNEG4
TNEG4
TTS4
TTS4
STS4
A1
TDSA4
A3
LLB2
A5
RJA2
N.C.
N.C.
N.C.
RTS2
RTS2
PRBS2
PRBS2
RLOS4
RLOS4
PRBS4
PRBS4
RCLK4
RCLK4
TPOS4
TPOS4
TCLK4
TCLK4
TXP4
TXP4
TXN4
TXN4
STMCLK
STMCLK
RMON2
N.C.
RXP2
RXP2
RXN2
RXN2
RLOS2
RLOS2
DS3153
HARDWARE
CPU BUS
MODE
MODE
N.C.
A2
RLB2
A4
TJA2
N.C.
RNEG2
RNEG2
RPOS2
RPOS2
RCLK2
RCLK2
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
A1
N.C.
A3
LLB2
A5
RJA2
N.C.
N.C.
N.C.
RTS2
RTS2
PRBS2
PRBS2
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
STMCLK
STMCLK
RMON2
N.C.
RXP2
RXP2
RXN2
RXN2
RLOS2
RLOS2
50 of 60
DS3152
HARDWARE CPU BUS
MODE
MODE
N.C.
A2
RLB2
A4
TJA2
N.C.
RNEG2
RNEG2
RPOS2
RPOS2
RCLK2
RCLK2
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
A1
N.C.
A3
LLB2
N.C.
RJA2
N.C.
N.C.
N.C.
RTS2
RTS2
PRBS2
PRBS2
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
STMCLK
STMCLK
RMON2
N.C.
RXP2
RXP2
RXN2
RXN2
RLOS2
RLOS2
DS3151
HARDWARE CPU BUS
MODE
MODE
N.C.
A2
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
A1
N.C.
A3
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
STMCLK
STMCLK
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
Figure 14-1. DS3151 Hardware Mode Pin Assignment
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
RLOS1
B1
RXN1
B2
RXP1
B3
RMON1
B4
T3MCLK
B5
N.C.
B6
N.C.
B7
N.C.
B8
N.C.
B9
N.C.
B10
N.C.
B11
N.C.
B12
PRBS1
C1
RTS1
C2
N.C.
C3
RJA1
C4
LLB1
C5
N.C.
C6
N.C.
C7
N.C.
C8
N.C.
C9
N.C.
C10
N.C.
C11
N.C.
C12
RCLK1
D1
RPOS1
D2
RNEG1
D3
TJA1
D4
RLB1
D5
N.C.
D6
N.C.
D7
N.C.
D8
N.C.
D9
N.C.
D10
N.C.
D11
N.C.
D12
TPOS1
E1
TNEG1
E2
TDM1
E3
JTRST
E4
JTMS
E5
VDD
E6
VSS
E7
TBIN
E8
RBIN
E9
N.C.
E10
N.C.
E11
N.C.
E12
TCLK1
F1
TTS1
F2
TLBO1
F3
JTCLK
F4
VDD
F5
VDD
F6
VSS
F7
VSS
F8
HW
F9
N.C.
F10
N.C.
F11
E3MCLK
F12
TXP1
G1
STS1
G2
E3M1
G3
VDD
G4
VDD
G5
VDD
G6
VSS
G7
VSS
G8
VSS
G9
N.C.
G10
N.C.
G11
N.C.
G12
TXN1
H1
TDSA1
H2
TDSB1
H3
VSS
H4
VSS
H5
VSS
H6
VDD
H7
VDD
H8
VDD
H9
N.C.
H10
N.C.
H11
N.C.
H12
RST
J1
N.C.
J2
N.C.
J3
JTDI
J4
VSS
J5
VSS
J6
VDD
J7
VDD
J8
TCINV
J9
N.C.
J10
N.C.
J11
N.C.
J12
N.C.
K1
N.C.
K2
N.C.
K3
JTDO
K4
TEST
K5
VSS
K6
VDD
K7
HIZ
K8
RCINV
K9
N.C.
K10
N.C.
K11
N.C.
K12
N.C.
L1
N.C.
L2
N.C.
L3
N.C.
L4
N.C.
L5
N.C.
L6
N.C.
L7
N.C.
L8
N.C.
L9
N.C.
L10
N.C.
L11
N.C.
L12
N.C.
M1
N.C.
M2
N.C.
M3
N.C.
M4
N.C.
M5
N.C.
M6
N.C.
M7
N.C.
M8
N.C.
M9
N.C.
M10
N.C.
M11
N.C.
M12
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
STMCLK
N.C.
N.C.
N.C.
N.C.
High-Speed Analog
High-Speed Digital
Low-Speed Digital
VDD
VSS
51 of 60
DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
Figure 14-2. DS3151 CPU Bus Mode Pin Assignment
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
RLOS1
B1
RXN1
B2
RXP1
B3
N.C.
B4
T3MCLK
B5
N.C.
B6
N.C.
B7
N.C.
B8
N.C.
B9
N.C.
B10
N.C.
B11
N.C.
B12
PRBS1
C1
RTS1
C2
N.C.
C3
N.C.
C4
WR
C5
RD
C6
CS
C7
N.C.
C8
N.C.
C9
N.C.
C10
N.C.
C11
N.C.
C12
RCLK1
D1
RPOS1
D2
RNEG1
D3
N.C.
D4
INT
D5
MOT
D6
ALE
D7
N.C.
D8
N.C.
D9
N.C.
D10
N.C.
D11
N.C.
D12
TPOS1
E1
TNEG1
E2
TDM1
E3
JTRST
E4
JTMS
E5
VDD
E6
VSS
E7
N.C.
E8
N.C.
E9
N.C.
E10
N.C.
E11
N.C.
E12
TCLK1
F1
TTS1
F2
D0
F3
JTCLK
F4
VDD
F5
VDD
F6
VSS
F7
VSS
F8
HW
F9
N.C.
F10
N.C.
F11
E3MCLK
F12
TXP1
G1
D1
G2
D2
G3
VDD
G4
VDD
G5
VDD
G6
VSS
G7
VSS
G8
VSS
G9
N.C.
G10
N.C.
G11
N.C.
G12
TXN1
H1
D3
H2
D4
H3
VSS
H4
VSS
H5
VSS
H6
VDD
H7
VDD
H8
VDD
H9
N.C.
H10
N.C.
H11
N.C.
H12
RST
J1
D5
J2
D6
J3
JTDI
J4
VSS
J5
VSS
J6
VDD
J7
VDD
J8
N.C.
J9
N.C.
J10
N.C.
J11
N.C.
J12
N.C.
K1
N.C.
K2
D7
K3
JTDO
K4
TEST
K5
VSS
K6
VDD
K7
HIZ
K8
N.C.
K9
N.C.
K10
N.C.
K11
N.C.
K12
N.C.
L1
N.C.
L2
N.C.
L3
N.C.
L4
N.C.
L5
A0
L6
A2
L7
N.C.
L8
N.C.
L9
N.C.
L10
N.C.
L11
N.C.
L12
N.C.
M1
N.C.
M2
N.C.
M3
N.C.
M4
N.C.
M5
A1
M6
A3
M7
N.C.
M8
N.C.
M9
N.C.
M10
N.C.
M11
N.C.
M12
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
STMCLK
N.C.
N.C.
N.C.
N.C.
High-Speed Analog
High-Speed Digital
Low-Speed Digital
VDD
VSS
52 of 60
DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
Figure 14-3. DS3152 Hardware Mode Pin Assignment
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
RLOS1
B1
RXN1
B2
RXP1
B3
RMON1
B4
T3MCLK
B5
N.C.
B6
N.C.
B7
N.C.
B8
N.C.
B9
N.C.
B10
N.C.
B11
N.C.
B12
PRBS1
C1
RTS1
C2
N.C.
C3
RJA1
C4
LLB1
C5
N.C.
C6
N.C.
C7
N.C.
C8
N.C.
C9
N.C.
C10
N.C.
C11
N.C.
C12
RCLK1
D1
RPOS1
D2
RNEG1
D3
TJA1
D4
RLB1
D5
N.C.
D6
N.C.
D7
N.C.
D8
N.C.
D9
N.C.
D10
N.C.
D11
N.C.
D12
TPOS1
E1
TNEG1
E2
TDM1
E3
JTRST
E4
JTMS
E5
VDD
E6
VSS
E7
TBIN
E8
RBIN
E9
N.C.
E10
N.C.
E11
N.C.
E12
TCLK1
F1
TTS1
F2
TLBO1
F3
JTCLK
F4
VDD
F5
VDD
F6
VSS
F7
VSS
F8
HW
F9
N.C.
F10
N.C.
F11
E3MCLK
F12
TXP1
G1
STS1
G2
E3M1
G3
VDD
G4
VDD
G5
VDD
G6
VSS
G7
VSS
G8
VSS
G9
TDSB2
G10
TDSA2
G11
TXN2
G12
TXN1
H1
TDSA1
H2
TDSB1
H3
VSS
H4
VSS
H5
VSS
H6
VDD
H7
VDD
H8
VDD
H9
E3M2
H10
STS2
H11
TXP2
H12
RST
J1
N.C.
J2
N.C.
J3
JTDI
J4
VSS
J5
VSS
J6
VDD
J7
VDD
J8
TCINV
J9
TLBO2
J10
TTS2
J11
TCLK2
J12
N.C.
K1
N.C.
K2
N.C.
K3
JTDO
K4
TEST
K5
VSS
K6
VDD
K7
HIZ
K8
RCINV
K9
TDM2
K10
TNEG2
K11
TPOS2
K12
N.C.
L1
N.C.
L2
N.C.
L3
N.C.
L4
N.C.
L5
N.C.
L6
N.C.
L7
RLB2
L8
TJA2
L9
RNEG2
L10
RPOS2
L11
RCLK2
L12
N.C.
M1
N.C.
M2
N.C.
M3
N.C.
M4
N.C.
M5
N.C.
M6
N.C.
M7
LLB2
M8
RJA2
M9
N.C.
M10
RTS2
M11
PRBS2
M12
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
RXP2
RXN2
RLOS2
High-Speed Analog
High-Speed Digital
Low-Speed Digital
VDD
VSS
53 of 60
STMCLK RMON2
DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
Figure 14-4. DS3152 CPU Bus Mode Pin Assignment
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
RLOS1
B1
RXN1
B2
RXP1
B3
N.C.
B4
T3MCLK
B5
N.C.
B6
N.C.
B7
N.C.
B8
N.C.
B9
N.C.
B10
N.C.
B11
N.C.
B12
PRBS1
C1
RTS1
C2
N.C.
C3
N.C.
C4
WR
C5
RD
C6
CS
C7
N.C.
C8
N.C.
C9
N.C.
C10
N.C.
C11
N.C.
C12
RCLK1
D1
RPOS1
D2
RNEG1
D3
N.C.
D4
INT
D5
MOT
D6
ALE
D7
N.C.
D8
N.C.
D9
N.C.
D10
N.C.
D11
N.C.
D12
TPOS1
E1
TNEG1
E2
TDM1
E3
JTRST
E4
JTMS
E5
VDD
E6
VSS
E7
N.C.
E8
N.C.
E9
N.C.
E10
N.C.
E11
N.C.
E12
TCLK1
F1
TTS1
F2
D0
F3
JTCLK
F4
VDD
F5
VDD
F6
VSS
F7
VSS
F8
HW
F9
N.C.
F10
N.C.
F11
E3MCLK
F12
TXP1
G1
D1
G2
D2
G3
VDD
G4
VDD
G5
VDD
G6
VSS
G7
VSS
G8
VSS
G9
N.C.
G10
N.C.
G11
TXN2
G12
TXN1
H1
D3
H2
D4
H3
VSS
H4
VSS
H5
VSS
H6
VDD
H7
VDD
H8
VDD
H9
N.C.
H10
N.C.
H11
TXP2
H12
RST
J1
D5
J2
D6
J3
JTDI
J4
VSS
J5
VSS
J6
VDD
J7
VDD
J8
N.C.
J9
N.C.
J10
TTS2
J11
TCLK2
J12
N.C.
K1
N.C.
K2
D7
K3
JTDO
K4
TEST
K5
VSS
K6
VDD
K7
HIZ
K8
N.C.
K9
TDM2
K10
TNEG2
K11
TPOS2
K12
N.C.
L1
N.C.
L2
N.C.
L3
N.C.
L4
N.C.
L5
A0
L6
A2
L7
A4
L8
N.C.
L9
RNEG2
L10
RPOS2
L11
RCLK2
L12
N.C.
M1
N.C.
M2
N.C.
M3
N.C.
M4
N.C.
M5
A1
M6
A3
M7
N.C.
M8
N.C.
M9
N.C.
M10
RTS2
M11
PRBS2
M12
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
STMCLK
N.C.
RXP2
RXN2
RLOS2
High-Speed Analog
High-Speed Digital
Low-Speed Digital
VDD
VSS
54 of 60
DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
Figure 14-5. DS3153 Hardware Mode Pin Assignment
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
RLOS1
B1
RXN1
B2
RXP1
B3
RMON1
B4
T3MCLK
B5
TXN3
B6
TXP3
B7
TCLK3
B8
TPOS3
B9
RCLK3
B10
PRBS3
B11
RLOS3
B12
PRBS1
C1
RTS1
C2
N.C.
C3
RJA1
C4
LLB1
C5
TDSA3
C6
STS3
C7
TTS3
C8
TNEG3
C9
RPOS3
C10
RTS3
C11
RXN3
C12
RCLK1
D1
RPOS1
D2
RNEG1
D3
TJA1
D4
RLB1
D5
TDSB3
D6
E3M3
D7
TLBO3
D8
TDM3
D9
RNEG3
D10
N.C.
D11
RXP3
D12
TPOS1
E1
TNEG1
E2
TDM1
E3
JTRST
E4
JTMS
E5
VDD
E6
VSS
E7
TBIN
E8
RBIN
E9
TJA3
E10
RJA3
E11
RMON3
E12
TCLK1
F1
TTS1
F2
TLBO1
F3
JTCLK
F4
VDD
F5
VDD
F6
VSS
F7
VSS
F8
HW
F9
RLB3
F10
LLB3
F11
E3MCLK
F12
TXP1
G1
STS1
G2
E3M1
G3
VDD
G4
VDD
G5
VDD
G6
VSS
G7
VSS
G8
VSS
G9
TDSB2
G10
TDSA2
G11
TXN2
G12
TXN1
H1
TDSA1
H2
TDSB1
H3
VSS
H4
VSS
H5
VSS
H6
VDD
H7
VDD
H8
VDD
H9
E3M2
H10
STS2
H11
TXP2
H12
RST
J1
N.C.
J2
N.C.
J3
JTDI
J4
VSS
J5
VSS
J6
VDD
J7
VDD
J8
TCINV
J9
TLBO2
J10
TTS2
J11
TCLK2
J12
N.C.
K1
N.C.
K2
N.C.
K3
JTDO
K4
TEST
K5
VSS
K6
VDD
K7
HIZ
K8
RCINV
K9
TDM2
K10
TNEG2
K11
TPOS2
K12
N.C.
L1
N.C.
L2
N.C.
L3
N.C.
L4
N.C.
L5
N.C.
L6
N.C.
L7
RLB2
L8
TJA2
L9
RNEG2
L10
RPOS2
L11
RCLK2
L12
N.C.
M1
N.C.
M2
N.C.
M3
N.C.
M4
N.C.
M5
N.C.
M6
N.C.
M7
LLB2
M8
RJA2
M9
N.C.
M10
RTS2
M11
PRBS2
M12
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
RXP2
RXN2
RLOS2
High-Speed Analog
High-Speed Digital
Low-Speed Digital
VDD
VSS
55 of 60
STMCLK RMON2
DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
Figure 14-6. DS3153 CPU Bus Mode Pin Assignment
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
RLOS1
B1
RXN1
B2
RXP1
B3
N.C.
B4
T3MCLK
B5
TXN3
B6
TXP3
B7
TCLK3
B8
TPOS3
B9
RCLK3
B10
PRBS3
B11
RLOS3
B12
PRBS1
C1
RTS1
C2
N.C.
C3
N.C.
C4
WR
C5
RD
C6
CS
C7
TTS3
C8
TNEG3
C9
RPOS3
C10
RTS3
C11
RXN3
C12
RCLK1
D1
RPOS1
D2
RNEG1
D3
N.C.
D4
INT
D5
MOT
D6
ALE
D7
N.C.
D8
TDM3
D9
RNEG3
D10
N.C.
D11
RXP3
D12
TPOS1
E1
TNEG1
E2
TDM1
E3
JTRST
E4
JTMS
E5
VDD
E6
VSS
E7
N.C.
E8
N.C.
E9
N.C.
E10
N.C.
E11
N.C.
E12
TCLK1
F1
TTS1
F2
D0
F3
JTCLK
F4
VDD
F5
VDD
F6
VSS
F7
VSS
F8
HW
F9
N.C.
F10
N.C.
F11
E3MCLK
F12
TXP1
G1
D1
G2
D2
G3
VDD
G4
VDD
G5
VDD
G6
VSS
G7
VSS
G8
VSS
G9
N.C.
G10
N.C.
G11
TXN2
G12
TXN1
H1
D3
H2
D4
H3
VSS
H4
VSS
H5
VSS
H6
VDD
H7
VDD
H8
VDD
H9
N.C.
H10
N.C.
H11
TXP2
H12
RST
J1
D5
J2
D6
J3
JTDI
J4
VSS
J5
VSS
J6
VDD
J7
VDD
J8
N.C.
J9
N.C.
J10
TTS2
J11
TCLK2
J12
N.C.
K1
N.C.
K2
D7
K3
JTDO
K4
TEST
K5
VSS
K6
VDD
K7
HIZ
K8
N.C.
K9
TDM2
K10
TNEG2
K11
TPOS2
K12
N.C.
L1
N.C.
L2
N.C.
L3
N.C.
L4
N.C.
L5
A0
L6
A2
L7
A4
L8
N.C.
L9
RNEG2
L10
RPOS2
L11
RCLK2
L12
N.C.
M1
N.C.
M2
N.C.
M3
N.C.
M4
N.C.
M5
A1
M6
A3
M7
A5
M8
N.C.
M9
N.C.
M10
RTS2
M11
PRBS2
M12
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
STMCLK
N.C.
RXP2
RXN2
RLOS2
High-Speed Analog
High-Speed Digital
Low-Speed Digital
VDD
VSS
56 of 60
DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
Figure 14-7. DS3154 Hardware Mode Pin Assignment
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
RLOS1
B1
RXN1
B2
RXP1
B3
RMON1
B4
T3MCLK
B5
TXN3
B6
TXP3
B7
TCLK3
B8
TPOS3
B9
RCLK3
B10
PRBS3
B11
RLOS3
B12
PRBS1
C1
RTS1
C2
N.C.
C3
RJA1
C4
LLB1
C5
TDSA3
C6
STS3
C7
TTS3
C8
TNEG3
C9
RPOS3
C10
RTS3
C11
RXN3
C12
RCLK1
D1
RPOS1
D2
RNEG1
D3
TJA1
D4
RLB1
D5
TDSB3
D6
E3M3
D7
TLBO3
D8
TDM3
D9
RNEG3
D10
N.C.
D11
RXP3
D12
TPOS1
E1
TNEG1
E2
TDM1
E3
JTRST
E4
JTMS
E5
VDD
E6
VSS
E7
TBIN
E8
RBIN
E9
TJA3
E10
RJA3
E11
RMON3
E12
TCLK1
F1
TTS1
F2
TLBO1
F3
JTCLK
F4
VDD
F5
VDD
F6
VSS
F7
VSS
F8
HW
F9
RLB3
F10
LLB3
F11
E3MCLK
F12
TXP1
G1
STS1
G2
E3M1
G3
VDD
G4
VDD
G5
VDD
G6
VSS
G7
VSS
G8
VSS
G9
TDSB2
G10
TDSA2
G11
TXN2
G12
TXN1
H1
TDSA1
H2
TDSB1
H3
VSS
H4
VSS
H5
VSS
H6
VDD
H7
VDD
H8
VDD
H9
E3M2
H10
STS2
H11
TXP2
H12
RST
J1
LLB4
J2
RLB4
J3
JTDI
J4
VSS
J5
VSS
J6
VDD
J7
VDD
J8
TCINV
J9
TLBO2
J10
TTS2
J11
TCLK2
J12
RMON4
K1
RJA4
K2
TJA4
K3
JTDO
K4
TEST
K5
VSS
K6
VDD
K7
HIZ
K8
RCINV
K9
TDM2
K10
TNEG2
K11
TPOS2
K12
RXP4
L1
N.C.
L2
RNEG4
L3
TDM4
L4
TLBO4
L5
E3M4
L6
TDSB4
L7
RLB2
L8
TJA2
L9
RNEG2
L10
RPOS2
L11
RCLK2
L12
RXN4
M1
RTS4
M2
RPOS4
M3
TNEG4
M4
TTS4
M5
STS4
M6
TDSA4
M7
LLB2
M8
RJA2
M9
N.C.
M10
RTS2
M11
PRBS2
M12
RLOS4
PRBS4
RCLK4
TPOS4
TCLK4
TXP4
TXN4
RXP2
RXN2
RLOS2
High-Speed Analog
High-Speed Digital
Low-Speed Digital
VDD
VSS
57 of 60
STMCLK RMON2
DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
Figure 14-8. DS3154 CPU Bus Mode Pin Assignment
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
RLOS1
B1
RXN1
B2
RXP1
B3
N.C.
B4
T3MCLK
B5
TXN3
B6
TXP3
B7
TCLK3
B8
TPOS3
B9
RCLK3
B10
PRBS3
B11
RLOS3
B12
PRBS1
C1
RTS1
C2
N.C.
C3
N.C.
C4
WR
C5
RD
C6
CS
C7
TTS3
C8
TNEG3
C9
RPOS3
C10
RTS3
C11
RXN3
C12
RCLK1
D1
RPOS1
D2
RNEG1
D3
N.C.
D4
INT
D5
MOT
D6
ALE
D7
N.C.
D8
TDM3
D9
RNEG3
D10
N.C.
D11
RXP3
D12
TPOS1
E1
TNEG1
E2
TDM1
E3
JTRST
E4
JTMS
E5
VDD
E6
VSS
E7
N.C.
E8
N.C.
E9
N.C.
E10
N.C.
E11
N.C.
E12
TCLK1
F1
TTS1
F2
D0
F3
JTCLK
F4
VDD
F5
VDD
F6
VSS
F7
VSS
F8
HW
F9
N.C.
F10
N.C.
F11
E3MCLK
F12
TXP1
G1
D1
G2
D2
G3
VDD
G4
VDD
G5
VDD
G6
VSS
G7
VSS
G8
VSS
G9
N.C.
G10
N.C.
G11
TXN2
G12
TXN1
H1
D3
H2
D4
H3
VSS
H4
VSS
H5
VSS
H6
VDD
H7
VDD
H8
VDD
H9
N.C.
H10
N.C.
H11
TXP2
H12
RST
J1
D5
J2
D6
J3
JTDI
J4
VSS
J5
VSS
J6
VDD
J7
VDD
J8
N.C.
J9
N.C.
J10
TTS2
J11
TCLK2
J12
N.C.
K1
N.C.
K2
D7
K3
JTDO
K4
TEST
K5
VSS
K6
VDD
K7
HIZ
K8
N.C.
K9
TDM2
K10
TNEG2
K11
TPOS2
K12
RXP4
L1
N.C.
L2
RNEG4
L3
TDM4
L4
N.C.
L5
A0
L6
A2
L7
A4
L8
N.C.
L9
RNEG2
L10
RPOS2
L11
RCLK2
L12
RXN4
M1
RTS4
M2
RPOS4
M3
TNEG4
M4
TTS4
M5
A1
M6
A3
M7
A5
M8
N.C.
M9
N.C.
M10
RTS2
M11
PRBS2
M12
RLOS4
PRBS4
RCLK4
TPOS4
TCLK4
TXP4
TXN4
STMCLK
N.C.
RXP2
RXN2
RLOS2
High-Speed Analog
High-Speed Digital
Low-Speed Digital
VDD
VSS
58 of 60
DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
15.
PACKAGE INFORMATION
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to
www.maxim-ic.com/DallasPackInfo.)
Note: All dimensions in millimeters.
A1 BALL PAD CORNER
13.00
12
11
10
9
8
7
6
5
4
3
2
1
A
B
1.00
C
D
E
F
13.00
G
H
J
K
(1.00)
L
M
(1.00)
1.00
BOTTOM VIEW
59 of 60
DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
16.
THERMAL INFORMATION
Table 16-A. Thermal Properties, Natural Convection
PARAMETER
Ambient Temperature (Note 1)
Junction Temperature
Theta-JA (qJA), Still Air (Note 2)
Psi-JB
Psi-JT
MIN
-40
-40
TYP
MAX
+85
+125
22.4
9.2
1.6
UNITS
°C
°C
°C/W
°C/W
°C/W
Note 1: The package is mounted on a four-layer JEDEC standard test board with no airflow and dissipating maximum power.
Note 2: Theta-JA (qJA) is the junction-to-ambient thermal resistance, when the package is mounted on a four-layer JEDEC standard test board
with no airflow and dissipating maximum power.
Table 16-B. Theta-JA (qJA) vs. Airflow
FORCED AIR (m/s)
0
1
2.5
17.
THETA-JA (qJA)
22.4°C/W
19.0°C/W
17.2°C/W
REVISION HISTORY
REVISION
012103
DESCRIPTION
DS3154 new product release
DS3151/DS3152/DS3153 new product releases.
Electrical Characteristics section, Notes 1 and 2: Changed 44.73MHz to 51.84MHz; added indication that
specs are lower for rev A2; “all ones driven into RXPn/RXNn (1.0V square wave)” changed to “analog
loopback enabled” to match production test methodology.
040403
Table 13-B, Input leakage, IIL: -10mA min changed to -50mA min.
Table 13-B: Replaced TBD values for IDD, IDDTS, and IDDPD (DS3151/DS3152/DS3153); changed IDDPD
spec from 38 typ and 50 max to 45 typ and 70 max.
Table 14-A and Table 14-B: Changed pins RBIN, RCINV, TBIN, and TCINV to “N.C.” to reflect they are
not available in CPU bus mode.
Figure 1-1: Labeled capacitors connected to transformer center taps as “(optional)”.
Section 6, Optional Pre-Amp Paragraph: Clarified that the pre-amp contributes +14dB of flat gain.
072303
120303
Table 11-A: Changed leakage inductance to 0.150mH max.
Table 11-B: Reformatted table and added row for Pulse Engineering’s T3049 octal transformer.
Table 13-H: Reworded Note 20.
GCR Register Definition (page 16): Clarified that RST bit holds the digital logic of the LIU in reset rather
than the whole LIU.
Table 13-B: Changed DS3151 IDD from 130mA (max) to 100mA (max). Changed DS3151 IDDTTS from
105mA (max) to 80mA (max). Removed sentences in Notes 1 and 2 that labeled IDD and IDDTTS specs for
rev A1 devices.
Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product.
No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2003 Maxim Integrated Products · Printed USA
60 of 60