DP8212/DP8212M 8-Bit Input/Output Port General Description Features The DP8212/DP8212M is an 8-bit input/output port contained in a standard 24-pin dual-in-line package. The device, which is fabricated using Schottky Bipolar technology, is part of National Semiconductor’s 8080A support family. The DP8212/DP8212M can be used to implement latches, gated buffers, or multiplexers. Thus, all of the major peripheral and input/output functions of a microcomputer system can be implemented with this device. The DP8212/DP8212M includes an 8-bit latch with TRI-STATEÉ output buffers, and device selection and control logic. Also included is a service request flip-flop for the generation and control of interrupts to the microprocessor. Y Y Y Y Y Y Y Y 8-Bit data latch and buffer Service request flip-flop for generation and control of interrupts 0.25 mA input load current TRI-STATE TTL output drive capability Outputs sink 15 mA Asynchronous latch clear 3.65V output for direct interface to INS8080A Reduces system package count by replacing buffers, latches, and multiplexers in microcomputer systems 8080A Microcomputer Family Block Diagram TL/F/6824 – 1 TRI-STATEÉ is a registered trademark of National Semiconductor Corp. C1995 National Semiconductor Corporation TL/F/6824 RRD-B30M105/Printed in U. S. A. DP8212/DP8212M 8-Bit Input/Output Port June 1988 Absolute Maximum Ratings Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Min Max Units Supply Voltage (VCC) DP8212M 4.50 5.50 VDC DP8212 4.75 5.25 VDC Operating Temperaure (TA) b 55 a 125 DP8212M §C a 75 DP8212 0 §C Note: Maximum ratings indicate limits beyond which permanent damage may occur. Continuous operation at these limits is not intended and should be limited to those conditions specified under DC electrical characteristics. Storage Temperature b 65§ C to a 160§ C All Output or Supply Voltages All Input Voltages Output Currents Maximum Power Dissipation* at 25§ C Cavity Package Molded Package b 0.5V to a 7V b 1.0V to 5.5V 125 mA 1903 mW 2005 mW *Derate cavity package 12.7 mW/§ C above 25§ C; derate molded package 16.0 mW/§ C above 25§ C. Electrical Characteristics Min s TA s Max, Min s VCC s Max, unless otherwise noted Symbol Parameter Conditions Max Units b 0.25 mA VF e 0.45V b 0.75 mA VF e 0.45V b 1.0 mA VR e VCC Max 10 mA Input Leakage Current, MD Input VR e VCC Max 30 mA Input Leakage Current, DS1 Input VR e VCC Max 40 mA VC Input Forward Voltage Clamp IC e b5 mA b1 V VIL Input ‘‘Low’’ Voltage IF Input Load Current, STB, DS2, CLR, DI1 – DI8 Inputs IF Input Load Current, MD Input IF Input Load Current, DS1 Input IR Input Leakage Current STB, DS2, CLR, DI1 – DI8 Inputs IR IR VIH VOL VOH Min Typ VF e 0.45V DP8212M 0.08 V DP8212 0.85 V Input ‘‘High’’ Voltage 2.0 Output ‘‘Low’’ Voltage Output ‘‘High’’ Voltage V IOL e 10 mA DP8212M 0.45 V IOL e 15 mA DP8212 0.45 V IOH e 0.5 mA DP8212M 3.40 4.0 IOH e 1.0 mA DP8212 3.65 4.0 ISC Short-Circuit Output Current VO e 0V, VCC e 5V l IO l Output Leakage Current, High Impedance State VO e 0.45V/VCC Max ICC Power Supply Current V V b 15 b 75 mA 20 mA DP8212M 90 145 mA DP8212 90 130 mA Capacitance* F e 1 MHz, VBIAS e 2.5V, VCC e 5V, TA e 25§ C Typ Max CIN Symbol DS1, MD Input Capacitance Parameter Min 9 12 pF CIN DS2, CLR, STB, DI1 – DI8 Input Capacitance 5 9 pF COUT DO1–DO8 Output Capacitance 8 12 pF *This parameter is sampled and not 100% tested. 2 Units Switching Characteristics Min s TA s Max, Min s VCC s Max Symbol Parameter Conditions DP8212M Min Max 40 DP8212 Min Units Max tPW Pulse Width tPD Data to Output Delay (Note 1) 30 30 30 ns ns tWE Write Enable to Output Delay (Note 1) 50 40 ns tSET Data Set-Up Time 20 15 tH Data Hold Time 30 20 tR Reset to Output Delay (Note 1) 55 40 ns tS Set to Output Delay (Note 1) 35 30 ns tE Output Enable/Disable Time (Note 2) 50 45 ns tC Clear to Output Delay (Note 1) 65 55 ns ns ns Note 1: CL e 30 pF Note 2: CL e 30 pF except for DP8212M tE (DISABLE) CL e 5 pF Switching Conditions 1. Input Pulse Amplitude e 2.5V. 2. Input Rise and Fall Times e 5 ns. 3. Between 1V and 2V Measurements made at 1.5V with 15 mA & 30 pF Test Load. 4. CL includes jig and probe capacitance. 5. CL e 30 pF. 6. CL e 30 pF except for DP8212M tE (DISABLE) CL e 5 pF Alternate Test Load (Refer to Timing Diagram) Test Load TL/F/6824 – 2 TL/F/6824 – 3 3 Timing Diagram TL/F/6824 – 4 4 Logic Diagram TL/F/6824 – 5 5 Data In (DI1 –DI8): Eight-bit data input to the data latch, which consists of eight D-type flip-flops. Incorporating a level sensitive clock while the data latch clock input is high, the Q output of each flip-flop follows the data input. When the clock input returns low, the data latch stores the data input. The clock input high overrides the clear (CLR) input data latch reset. Clear (CLR): When low, asynchronously resets (clears) the data latch and the service request flip-flop. The service request flip-flop is in the non-interrupting state when reset. Logic Tables Logic Table A STB MD (DS1 # DS2) Data Out Equals 0 0 0 TRI-STATE 1 0 0 TRI-STATE 0 1 0 DATA LATCH 1 1 0 DATA LATCH 0 0 1 DATA LATCH 1 0 1 DATA IN 0 1 1 DATA IN 1 1 1 DATA IN OUTPUT SIGNALS Interrupt (INT): Goes low (interrupting state) when either the service request flip-flop is synchronously set by the strobe (STB) input or the device is selected. Data Out (DO1 –DO8): Eight-bit data output of data buffers, which are TRI-STATE, non-inverting stages. These buffers have a common control line that either enables the buffers to transmit the data from the data latch outputs or disables the buffers by placing them in the high-impedance state. CLR K resets data latch to the output low state. The data latch clock is level sensitive, a low level clock latches the data. Logic Table B Connection Diagram CLR (DS1 # DS2) STB Q* INT 0 RESET 0 0 0 1 1 0 0 0 1 1 0 K 1 0 1 1 RESET 0 0 0 1 0 0 0 1 Dual-In-Line Package *Internal Service Request flip-flop. Functional Pin Definitions The following describes the function of all the DP8212/ DP8212M input/output pins. Some of these descriptions reference internal circuits. INPUT SIGNALS Device Select (DS1, DS2): When DS1 is low and DS2 is high, the device is selected. The output buffers are enabled and the service request flip-flop is asynchronously reset (cleared) when the device is selected. Mode (MD): When high (output mode), the output buffers are enabled and the source of the data latch clock input is the device selection logic (DS1 # DS2). When low (input mode), the state of the output buffers is determined by the device selection logic (DS1 # DS2) and the source of the data latch clock input is the strobe (STB) input. Strobe (STB): Used as data latch clock input when the mode (MD) input is low (input mode). Also used to synchronously set the service request flip-flop, which is negative edge triggered. TL/F/6824 – 6 Top View Order Number DP8212J, DP8212N or DP8212MJ See NS Package Number J24A or N24A 6 Applications in Microcomputer Systems Gated Buffer (TRI-STATE) TL/F/6824 – 7 TL/F/6824 – 8 Interrupting Input Port Interrupt Instruction Port TL/F/6824 – 10 TL/F/6824 – 9 7 Applications in Microcomputer Systems (Continued) Output Port (with Hand-Shanking) TL/F/6824 – 11 INS8080A Status Latch TL/F/6824 – 12 8 Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (J) Order Number DP8212J or DP8212MJ NS Package Number J24A 9 DP8212/DP8212M 8-Bit Input/Output Port Physical Dimensions inches (millimeters) (Continued) Molded Dual-In-Line Package (N) Order Number DP8212N NS Package Number N24A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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