ICST ICS950211YGLF-T Programmable timing control hub for p4 Datasheet

ICS950211
Integrated
Circuit
Systems, Inc.
Programmable Timing Control Hub™ for P4™
Pin Configuration
VDDREF
X1
X2
GND
1
PCICLK_F0
1
PCICLK_F1
PCICLK_F2
VDDPCI
GND
1
*WDEN/PCICLK0
PCICLK1
PCICLK2
PCICLK3
VDDPCI
GND
PCICLK4
PCICLK5
PCICLK6
VDD3V66
GND
3V66_2
3V66_3
3V66_4
3V66_5
*PD#
VDDA
GND
*Vtt_PWRGD#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
ICS950211
Recommended Application:
Brookdale and Brookdale -G chipset with P4 processor.
Output Features:
•
3 - Pairs of differential CPU clocks (differential current mode)
•
5 - 3V66 @ 3.3V
•
10 - PCI @ 3.3V
•
2 - 48MHz @ 3.3V fixed
•
1 - REF @ 3.3V, 14.318MHz
•
1 - VCH/3V66 @ 3.3V, 48 MHz or 66.6 MHz
Features/Benefits:
•
Programmable output frequency.
•
Programmable output divider ratios.
•
Programmable output rise/fall time.
•
Programmable output skew.
•
Programmable spread percentage for EMI control.
•
Watchdog timer technology to reset system
if system malfunctions.
•
Programmable watch dog safe frequency.
•
Support I2C Index read/write and block read/write operations.
•
Uses external 14.318MHz crystal.
1. These outputs have 2X drive strength.
* Internal Pull-up resistor of 120K to VDD
** these inputs have 120K internal pull-down
to GND
Frequency Table
Block Diagram
FS4 FS3 FS2 FS1 FS0
PLL2
48MHz_USB
48MHz_DOT
XTAL
OSC
3V66_1/VCH_CLK
REF
PLL1
Spread
Spectrum
WDEN
PD#
CPU_STOP#
PCI_STOP#
MULTSEL0
FS (4:0)
SDATA
SCLK
Vtt_PWRGD#
CPU
DIVDER
Reg.
3
Stop
7
3
Control
Config.
Stop
3
PCI
DIVDER
Logic
1
REF
FS1
FS0
CPU_STOP#*
CPUCLKT0
CPUCLKC0
VDDCPU
CPUCLKT1
CPUCLKC1
GND
VDDCPU
CPUCLKT2
CPUCLKC2
MULTSEL0*
I REF
GND
FS2
48MHz_USB/FS3**
48MHz_DOT
AVDD48
GND
3V66_1/VCH_CLK/FS4**
PCI_STOP#*
3V66_0
VDD
GND
SCLK
SDATA
56-Pin 300-mil SSOP & 240-mil TSSOP
Key Specifications:
•
CPU Output Jitter <150ps
•
3V66 Output Jitter <250ps
•
CPU Output Skew <100ps
X1
X2
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
3V66
DIVDER
5
CPUCLKT (2:0)
CPUCLKC (2:0)
PCICLK (6:0)
PCICLK_F (2:0)
3V66 (5:2, 0)
I REF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CPUCLK
MHz
3V66
MHz
PCICLK
MHz
66.66*
100.00
200.00
133.33
100.90
105.00
109.00
114.00
117.00
127.00
130.00
132.50
205.00
170.00
180.00
190.00
66.66
66.66
66.66
66.66
67.27
70.00
72.67
76.00
78.00
72.86
74.29
75.71
70.00
56.67
60.00
63.33
33.33
33.33
33.33
33.33
33.63
35.00
36.33
38.00
39.00
36.43
37.14
37.89
35.00
28.33
30.00
31.67
For additional frequency selections please refer to Byte 0.
* For 950211BF version, this frequency is 166.66MHz.
Power Groups
0465E—05/17/05
VDDA = Analog Core PLL
VDDREF = REF, Xtal
AVDD48 = 48MHz
Integrated
Circuit
Systems, Inc.
ICS950211
General Description
The ICS950211 is a single chip clock solution for desktop designs using the Intel Brookdale chipset with PC133 or DDR
memory. It provides all necessary clock signals for such a system.
The ICS950211 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). This part
incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a
serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the output
divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each
individual output clock. M/N control can configure output frequency with resolution up to 0.1MHz increment.
Pin Description
PIN NUMBER
1, 8, 14, 19,
32, 46, 50
PIN NAME
VDD
TYPE
PWR
DESCRIPTION
3.3V power supply.
Cr ystal input, has inter nal load cap (33pF) and feedback resistor from X2.
2
X1
IN
3
X2
OUT
Cr ystal output, nominally 14.318MHz. Has inter nal load cap (33pF).
GND
PWR
Ground pins for 3.3V supply.
3V66 (5:2, 0)
OUT
3.3V Fixed 66MHz clock outputs for HUB.
PCICLK_F(2:0)
OUT
3.3V PCI clock output
4, 9, 15, 20, 27, 31,
36, 41, 47
24, 23, 22, 21, 33
7,6,5
10
WDEN
PCICLK0
18, 17, 16, 13, 12, 11 PCICLK (6:1)
IN
3.3V PCI clock output.
OUT
3.3V PCI clock outputs.
25
PD#
26
VDDA
28
Vtt_PWRGD#
IN
30
29
SCLK
SDATA
IN
I/O
34
PCI_STOP#
IN
IN
PWR
3V66_1/VCH_CLK
OUT
FS4
AVDD48
48MHz_DOT
FS3
48MHz_USB
IN
PWR
OUT
IN
OUT
42
I REF
OUT
43
MULTSEL0
35
37
38
39
Hardware enable of watch dog circuit. Enabled when latched high.
OUT
IN
44, 48, 51
CPUCLKC (2:0)
OUT
45, 49, 52
CPUCLKT (2:0)
OUT
40, 55, 54
FS (2:0)
IN
53
CPU_STOP#
IN
56
REF
OUT
Asynchronous active low input pin used to power down the device into a low
power state. The inter nal clocks are disabled and the VCO and the cr ystal are
s t o p p e d . T h e l a t e n c y o f t h e p ow e r d ow n w i l l n o t b e g r e a t e r t h a n 3 m s.
Analog power 3.3V.
This 3.3V LVTTL input is a level sensitive strobe used to determine when FS (4:0)
inputs are valid and are ready to be sampled (active low).
Clock pin for I2C circuitr y 5V tolerant.
Data pin for I2C circuitr y 5V tolerant.
Halts PCICLK clocks at logic 0 level, when input low except PCICLK_F which are
free running.
3.3V output selectable through I2C to be 66MHz from internal VCO or
48MHz (non-SSC).
L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n .
Analog power 3.3V.
3.3V Fixed 48MHz clock output for DOT.
L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n .
3.3V Fixed 48MHz clock output for USB.
This pin establishes the reference current for the CPUCLK pairs. This pin requires
a fixed precision resistor tied to ground in order to establish the appropriate
current.
3.3V LVTTL input for selecting the current multiplier for CPU outputs
"Complementor y" clocks of differential pair CPU outputs. These are current
outputs and external resistors are required for voltage bias.
"True" clocks of differential pair CPU outputs. These are current outputs and
external resistors are required for voltage bias.
L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n .
Halts CPUCLK clocks at logic 0 level, when input low except CPUCLK_F which
are free running.
3.3V, 14.318MHz reference clock output.
0465E—05/17/05
2
Integrated
Circuit
Systems, Inc.
ICS950211
Maximum Allowed Current
Condition
Max 3.3V supply consumption
Max discrete cap loads,
Vdd = 3.465V
All static inputs = Vdd or GND
Powerdown Mode
(PWRDWN# = 0)
40mA
Full Active
360mA
Host Swing Select Functions
MULTISEL0
Board Target
Trace/Term Z
Reference R,
Iref =
VDD/(3*Rr)
Output
Current
Voh @ Z
0
50 ohms
Rr = 221 1%,
Iref = 5.00mA
Ioh = 4* I REF
1.0V @ 50
1
50 ohms
Rr = 475 1%,
Iref = 2.32mA
Ioh = 6* I REF
0.7V @ 50
0465E—05/17/05
3
Integrated
Circuit
Systems, Inc.
ICS950211
General I2C serial interface information
How to Write:
How to Read:
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends the begining byte location = N
ICS clock will acknowledge
Controller (host) sends the data byte count = X
ICS clock will acknowledge
Controller (host) starts sending Byte N through
Byte N + X -1
(see Note 2)
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) will send start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
ICS clock will send the data byte count = X
ICS clock sends Byte N + X -1
ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Read Operation
Index Block Write Operation
Controller (Host)
starT bit
T
Slave Address D2(H)
WR
WRite
Controller (Host)
T
starT bit
Slave Address D2(H)
WR
WRite
ICS (Slave/Receiver)
ICS (Slave/Receiver)
ACK
ACK
Beginning Byte = N
Beginning Byte = N
ACK
ACK
RT
Repeat starT
Slave Address D3(H)
RD
ReaD
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
ACK
Data Byte Count = X
ACK
Beginning Byte N
Byte N + X - 1
ACK
X Byte
ACK
P
stoP bit
Byte N + X - 1
N
P
*See notes on the following page.
0465E—05/17/05
4
Not acknowledge
stoP bit
Integrated
Circuit
Systems, Inc.
ICS950211
Byte 0: Functionality and frequency select register (Default=0)
Bit
Description
Bit2 Bit7 Bit6 Bit5 Bit4 CPUCLK
MHz
FS4 FS3 FS2 FS1 FS0
Bit
(2,7:4)
Bit 3
Bit 1
Bit 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
010101-
3V66
MHz
PWD
PCICLK
MHz
Spread %
0
0
0
0
66.662
66.66
33.33
0 to -0.5% down spread
0
0
0
1
100.00
66.66
33.33
0 to -0.5% down spread
0
0
1
0
200.00
66.66
33.33
0 to -0.5% down spread
33.33
0 to -0.5% down spread
0
0
1
1
133.33
66.66
0
1
0
0
100.90
67.27
33.63
+/-0.35% center spread
0
1
0
1
105.00
70.00
35.00
+/-0.35% center spread
+/-0.35% center spread
0
1
1
0
109.00
72.67
36.33
0
1
1
1
114.00
76.00
38.00
+/-0.35% center spread
1
0
0
0
117.00
78.00
39.00
+/-0.35% center spread
+/-0.35% center spread
1
0
0
1
127.00
72.86
36.43
1
0
1
0
130.00
74.29
37.14
+/-0.35% center spread
1
0
1
1
132.50
75.71
37.89
+/-0.35% center spread
+/-0.35% center spread
1
1
0
0
205.00
70.00
35.00
1
1
0
1
170.00
56.67
28.33
+/-0.35% center spread
1
1
1
0
180.00
60.00
30.00
+/-0.35% center spread
+/-0.35% center spread
1
1
1
1
190.00
63.33
31.67
0
0
0
0
133.90
66.95
33.48
+/-0.35% center spread
0
0
0
1
133.33
66.67
33.33
+/-0.35% center spread
+/-0.35% center spread
0
0
1
0
120.00
60.00
30.00
0
0
1
1
125.00
62.50
31.25
+/-0.35% center spread
0
1
0
0
134.90
67.45
33.73
+/-0.35% center spread
+/-0.35% center spread
0
1
0
1
137.00
68.50
34.25
0
1
1
0
139.00
69.50
34.75
+/-0.35% center spread
0
1
1
1
141.00
70.50
35.25
+/-0.35% center spread
+/-0.35% center spread
1
0
0
0
143.00
71.50
35.75
1
0
0
1
145.00
72.50
36.25
+/-0.35% center spread
1
0
1
0
150.00
75.00
37.50
+/-0.35% center spread
+/-0.35% center spread
1
0
1
1
155.00
77.50
38.75
1
1
0
0
160.00
80.00
40.00
+/-0.35% center spread
1
1
0
1
150.00
64.29
32.14
+/-0.35% center spread
1
1
1
0
160.00
68.57
34.29
+/-0.35% center spread
1
1
1
1
170.00
72.86
36.43
+/-0.35% center spread
Frequency is selected by hardware select, latched inputs
Frequency is selected by Bit 2,7:4
Normal
Spread spectrum enable
Watch dog safe frequency will be selected by latch inputs
Watch dog safe frequency will be programmed by Byte 10 bit (4:0)
Notes:
1. Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
2. For 950211BF version, this frequency is 166.66MHz.
0465E—05/17/05
5
Note 1
0
1
0
Integrated
Circuit
Systems, Inc.
ICS950211
Byte 1: Output Control Register
(1 = enable, 0 = disable)
Bit
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Pin#
44, 45
48, 49
51, 52
-
PWD
1
1
1
X
X
X
X
X
Description
CPUT/C2
CPUT/C1
CPUT/C0
FS4 Read
FS3 Read
FS2 Read
FS1 Read
FS0 Read
b a ck
b a ck
b a ck
b a ck
b a ck
Byte 2: Output Control Register
(1 = enable, 0 = disable)
Bit
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Pin#
18
17
16
13
12
11
10
PWD
X
1
1
1
1
1
1
1
Description
MULTSEL (Read back)
PCICLK_6
PCICLK_5
PCICLK_4
PCICLK_3
PCICLK_2
PCICLK_1
PCICLK_0
Byte 3: Output Control Register
(1 = enable, 0 = disable)
Bit
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Pin#
38
39
35
7
6
5
PWD
1
1
1
0
0
1
1
1
Description
48MHZ_DOT
48MHz_USB
Reset gear shift detect 1 = Enable, 0 = Disable
Async freq. control bit 0 (See Async Freq. Control Table)
3V66_1/VCH_CLK, (default) = 66.66MHz, 1=48MHz
PCICLK_F2
PCICLK_F1
PCICLK_F0
Byte 4: Output Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
33
35
24
23
22
21
PWD
1
X
1
1
1
1
1
1
Description
Async. freq. control bit 1 (See Async. Freq. Control Table)
Reserved
3V66_0
3V66_1/VCH_CLK
3V66_5
3V66_4
3V66_3
3V66_2
Notes:
1. PWD = Power on Default
2. For disabled clocks, they stop low for single ended clocks. Differential CPU clocks stop with CPUCLKT at high,
CPUCLKC off, and external resistor termination will bring CPUCLKC low.
0465E—05/17/05
6
Integrated
Circuit
Systems, Inc.
ICS950211
Asynchronous Frequency Control Table
Byte 4
Bit 7
Byte 3
Bit 4
3V66 [0:3]
PCI_F [1:2]
PCICK [0:6]
0
0
66.01 MHz
33.005 MHz
0
1
75.44 MHz
37.72 MHz
1
0
66.66 MHz
33.33 MHz
1
1
88.01 MHz
44.005 MHz
Note
From Fix PLL (no
spread)
From Fix PLL (no
spread)
From main PLL
(Default)
From Fix PLL (no
spread)
Byte 5: Programming Edge Rate
(1 = enable, 0 = disable)
Bit
Pin#
PWD
Description
Bi t 7
X
1
CPUCLK T/C0 Free Running Control, 0=Free Running; 1=Stoppable*
Bi t 6
X
1
CPUCLK T/C1 Free Running Control, 0=Free Running; 1=Stoppable*
Bi t 5
X
1
CPUCLK T/C2 Free Running Control, 0=Free Running; 1=Stoppable*
(Reserved)
Bi t 4
X
1
Bi t 3
X
1
(Reserved)
Bi t 2
X
1
(Reserved)
Bi t 1
X
1
(Reserved)
Bi t 0
X
1
(Reserved)
* This functionality is only available in BF version.
Byte 6: Vendor ID Register
(1 = enable, 0 = disable)
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
Revision ID Bit3
Revision ID Bit2
Revision ID Bit1
Revision ID Bit0
Vendor ID Bit3
Vendor ID Bit2
Vendor ID Bit1
Vendor ID Bit0
PWD
X
X
X
X
0
0
0
1
Description
Revision ID values will be based on individual device's revision
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Byte 7: Revision ID and Device ID Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Device ID7
Device ID6
Device ID5
Device ID4
Device ID3
Device ID2
Device ID1
Device ID0
PWD
Description
0
0
0
Device ID values will be based on individual device
0
"01H" in this case.
0
0
0
1
0465E—05/17/05
7
Integrated
Circuit
Systems, Inc.
ICS950211
Byte 8: Byte Count Read Back Register
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
Byte7
Byte6
Byte5
Byte4
Byte3
Byte2
Byte1
Byte0
PWD
Description
0
0
0
Note: Writing to this register will configure byte count and how
0
many bytes will be read back, default is 0FH = 15 bytes.
1
1
1
1
Byte 9: Watchdog Timer Count Register
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
WD7
WD6
WD5
WD4
WD3
WD2
WD1
WD0
PWD
Description
0
0
0
The decimal representation of these 8 bits correspond to X •
0
290ms the watchdog timer will wait before it goes to alarm mode
and reset the frequency to the safe setting. Default at power up is
1
8 • 290ms = 2.3 seconds.
0
0
0
Byte 10: Programming Enable bit 8 Watchdog Control Register
Bit
Name
PWD
Bit 7
Program
Enable
0
Bit 6
WD Enable
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WD Alarm
SF4
SF3
SF2
SF1
SF0
0
0
0
0
0
0
Description
Programming Enable bit
0 = no programming. Frequencies are selected by HW latches or Byte0 1
= enable all I2C programing.
Watchdog Enable bit.
This bit will over write WDEN latched value. 0 = disable, 1 = Enable.
Watchdog Alarm Status 0 = normal 1= alarm status
Watchdog safe frequency bits. Writing to these bits will configure the safe
frequency corrsponding to Byte 0 Bit 2, 7:4 table
Byte 11: VCO Frequency M Divider (Reference divider) Control Register
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
Ndiv 8
Mdiv 6
Mdiv 5
Mdiv 4
Mdiv 3
Mdiv 2
Mdiv 1
Mdiv 0
PWD
X
X
X
X
X
X
X
X
Description
N divider bit 8
The decimal respresentation of Mdiv (6:0) corresposd to the
reference divider value. Default at power up is equal to the
latched inputs selection.
0465E—05/17/05
8
Integrated
Circuit
Systems, Inc.
ICS950211
Byte 12: VCO Frequency N Divider (VCO divider) Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Ndiv 7
Ndiv 6
Ndiv 5
Ndiv 4
Ndiv 3
Ndiv 2
Ndiv 1
Ndiv 0
PWD
Description
X
X
X
The decimal representation of Ndiv (8:0) correspond to the
X
VCO divider value. Default at power up is equal to the
latched inputs selecton. Notice Ndiv 8 is located in Byte 11.
X
X
X
X
Byte 13: Spread Spectrum Control Register
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
SS 7
SS 6
SS 5
SS 4
SS 3
SS 2
SS 1
SS 0
PWD
Description
X
X
X
The Spread Spectrum (12:0) bit will program the spread
X
precentage. Spread precent needs to be calculated based on the
VCO frequency, spreading profile, spreading amount and spread
X
frequency. Default power on is latched FS divider.
X
X
X
Byte 14: Spread Spectrum Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Reserved
Reserved
Reserved
SS 12
SS 11
SS 10
SS 9
SS 8
PWD
X
X
X
X
X
X
X
X
Description
Reserved
Reserved
Reserved
Spread Spectrum Bit 12
Spread Spectrum Bit 11
Spread Spectrum Bit 10
Spread Spectrum Bit 9
Spread Spectrum Bit 8
Byte 15: Output Divider Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
B it 1
Bit 0
Name
CPU Div 3
CPU Div 2
CPU Div 1
CPU Div 0
CPU Div 3
CPU Div 2
CPU Div 1
CPU Div 0
PWD
X
X
X
X
X
X
X
X
Description
CPU2 clock divider ratio can be configured via these 4
bits individually. For divider selection table refer to
Table 1. Default at power up is latched FS divider.
CPU [1:0] clock divider ratio can be configured via
these 4 bits individually. For divider selection table refer
to Table 1. Default at power up is latched FS divider.
0465E—05/17/05
9
Integrated
Circuit
Systems, Inc.
ICS950211
Byte 16: Output Divider Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
PCI Div 3
PCI Div 2
PCI Div 1
PCI Div 0
3V66 Div 3
3V66 Div 2
3V66 Div 1
3V66 Div 0
PWD
X
X
X
X
X
X
X
X
Description
3V66 [3:2] clock divider ratio can be configured via
these 4 bits individually. For divider selection table refer
to Table 1. Default at power up is latched FS divider.
3V66 [1:0] clock divider ratio can be configured via
these 4 bits individually. For divider selection table refer
to Table 1. Default at power up is latched FS divider.
Byte 17: Output Divider Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
3V66_INV
3V66_INV
CPU_INV
CPU_INV
Reserved
Reserved
Reserved
Reserved
PWD
X
X
X
X
X
X
X
X
Description
3V66 [3:2] Phase Inversion bit
3V66 Phase Inversion bit
CPUCLK2 Phase Inversion bit
CPUCLK [1:0] Phase Inversion bit
3V66 [1:0] clock divider ratio can be configured via these 4
bits individually. For divider selection table refer to Table 1.
Default at power up is latched FS divider.
Table 1
Div (3:2)
Div (1:0)
Table 2
00
01
10
11
Div (3:2)
Div (1:0)
00
01
10
11
/8
/16
/32
00
/2
/4
/8
/16
00
/4
01
/3
/6
/12
/24
01
/3
/6
/12
/24
10
/5
/10
/20
/40
10
/5
/10
/20
/40
11
/7
/14
/28
/56
11
/7
/14
/28
/56
Byte 18: Group Skew Control Register
Bit
Name
PWD
Bi t 7
CPU_Skew 1
0
Bi t 6
Bi t 5
Bi t 4
Bi t 3
CPU_Skew 0
Reserved
Reserved
CPU_Skew 1
1
0
0
0
Bi t 2
Bi t 1
Bi t 0
CPU_Skew 0
Reserved
Reserved
1
0
0
Description
These 2 bits delay the CPUCLKC/T2 with respect to
CPUCLKC/T (1:0)
00 = 0ps 01 = 250ps 10 = 500ps 11 =750ps
Reserved
Reserved
These 2 bits delay the CPUCLKC/T (1:0) clock with respect to
CPUCLKC/T2
00 = 0ps 01 = 250ps 10 = 500ps 11 = 750ps
Reserved
Reserved
Byte 19: Group Skew Control Register
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
These 4bits control
CPU-3V66(3:1)
These 4 bits control
CPU-3V66_0
PWD
1
1
1
1
1
1
1
1
Programming Sequence
0
0
1
1
1
1
0
1
0
1
1
1
0
0
0
0
0
1
0
0
0
0
1
0
0ps
150ps
300ps
450ps
600ps
750ps
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1 1 1 1 900ps Reserved
Reserved
Reserved
0465E—05/17/05
10
Integrated
Circuit
Systems, Inc.
ICS950211
Byte 20: Group Skew Control Register
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
PWD
These 4bits control
CPU-PCI(6:0)
These 4 bits control
CPU-PCIF(1:0)
1
1
1
1
1
1
1
1
Programming Sequence
0
0
1
1
1
1
0
1
0
1
1
1
0
0
0
0
0
1
0
0
0
0
1
0
0ps
150ps
300ps
450ps
600ps
750ps
1 1 1 1 900ps Reserved
Reserved
Reserved
Byte 21: Slew Rate Control Register
Bit
Name
PWD
Bit 7
PCIF Slew 1
1
Bit 6
PCIF Slew 0
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PCIF Slew 1
PCIF Slew 0
3V66 (3:2)_Slew 1
3V66 (3:2)_Slew 1
3V66 (1:0)_Slew 1
3V66 (1:0)_Slew 0
1
0
1
0
1
0
Description
PCIF2(1:0) clock slew rate control bits.
01 = strong: 11 = normal; 10 = weak
PCIF1(1:0) clock slew rate control bits.
01 = strong: 11 = normal; 10 = weak
PCIF(1:0) clock slew rate control bits.
01 = strong: 11 = normal; 10 = weak
3V66 (3:2) clock slew rate control bits.
01 = strong: 11 = normal; 10 = weak
3V66 (1:0) clock slew rate control bits.
01 = strong: 11 = normal; 10 = weak
Byte 22: Slew Rate Control Register
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
REF Slew 1
REF Slew 0
PCI (6:4) Slew 1
PCI (6:4) Slew 0
PCI (3:1) Slew 1
PCI (3:1) Slew 0
PCI0 Slew 1
PCI0 Slew 0
PWD
1
0
1
0
1
0
1
0
Description
REF clock slew rate control bits.
01 = strong: 11 = normal; 10 = weak
PCI (6:4) clock slew rate control bits.
01 = strong: 11 = normal; 10 = weak
PCI (3:1) clock slew rate control bits.
01 = strong: 11 = normal; 10 = weak
PCI0 clock slew rate control bits.
01 = strong: 11 = normal; 10 = weak
Byte 23: Slew Rate Control Register
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
Reserved
Reserved
VCH Slew 1
VCH Slew 0
48USB Slew 1
48USB Slew 0
48DOT Slew 1
48DOT Slew 0
PWD
X
X
1
0
1
0
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Description
Reserved
VCH clock slew rate control bits.
01 = strong: 11 = normal; 10 = weakk
48USB clock slew rate control bits.
01 = strong: 11 = normal; 10 = weakk
48DOT clock slew rate control bits.
01 = strong: 11 = normal; 10 = weak
0465E—05/17/05
11
Integrated
Circuit
Systems, Inc.
ICS950211
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +5%
PARAMETER
Input High Voltage
Input Low Voltage
SYMBOL
VIH
VIL
Input High Current
Input Low Current
Input Low Current
IIH
IIL1
IIL2
Operating
Supply Current
Power Down
Supply Current
IDD3.3OP
IDD3.3PD
CONDITIONS
VIN = VDD
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
Fi
Lpin
VDD = 3.3 V;
Input Capacitance
CIN
Cout
CINX
Logic Inputs
Out put pin capacitance
X1 & X2 pins
Ttrans
Transition Time
1
Settling Time1
Clk Stabilization
Delay
1
TYP
-5
-5
-200
C L = 0 pF; Select @ 66M
C L = Full load
IREF=2.32
IREF= 5mA
Input frequency
Pin Inductance
1
MIN
2
VSS - 0.3
MAX
UNITS
VDD + 0.3
V
0.8
V
5
mA
mA
mA
100
360
25
45
mA
mA
mA
mA
7
MHz
nH
5
6
45
pF
pF
pF
14.318
27
36
To 1st crossing of target Freq.
3
mS
Ts
From 1st crossing to 1% target Freq.
3
mS
TSTAB
tPZH,tPZH
tPLZ,tPZH
From VDD = 3.3 V to 1% target Freq.
output enable delay (all outputs)
output disable delay (all outputs)
3
10
10
mS
nS
nS
1
Guaranteed by design, not 100% tested in production.
0465E—05/17/05
12
1
1
Integrated
Circuit
Systems, Inc.
ICS950211
Electrical Characteristics - CPUCLK
TA = 0 - 70°C; VDD = 3.3 V +/-5%; (unless otherwise stated)
PARAMETER
Current Source
Output Impedance
Output High Voltage
SYMBOL
Output High Current
IOH
Rise Time 1
Differential Crossover
ZO
CONDITIONS
VO = VX
VOH
MIN
MAX
VOL = 20%, VOH = 80%
UNITS
Ω
3000
0.71
VR = 475W +1%; IREF = 2.32mA; IOH = 6*IREF
tr
TYP
1.2
-13.92
175
V
mA
700
ps
VX
Note 3
45
50
55
%
dt
VT = 50%
45
49.4
55
%
Skew , CPU to CPU
tsk
VT = 50%
40
100
ps
Jitter, Cycle-to-cycle1
tjcyc-cyc
VT = VX
90
150
ps
TYP
MAX
UNITS
55
MHz
Ω
V
0.55
-33
38
V
mA
mA
2
ns
Voltage1
Duty Cycle1
1
Notes:
1 - Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
1
Output Frequency
Output Impedance
Output High Voltage
F0
RDSN11
VOH1
Output Low Voltage
Output High Current
Output Low Current
VOL1
IOH1
IOL1
Rise Time
Fall Time
33.33
VO = VDD*(0.5)
IOH = -1 mA
12
2.4
IOL = 1 mA
VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V
VOL@ MIN = 1.95 V, VOL@ MAX= 0.4
-33
30
tr11
VOL = 0.4 V, VOH = 2.4 V
0.5
VOH = 2.4 V, VOL = 0.4 V
0.5
1.45
2
ns
VT = 1.5 V
45
51.5
55
%
Skew
tf11
d t11
1
tsk1
Jitter
tjcyc-cyc
Duty Cycle
1
VT = 1.5 V
VT = 1.5 V
1
Guaranteed by design, not 100% tested in production.
0465E—05/17/05
13
1.52
155
500
ps
123
250
ps
Integrated
Circuit
Systems, Inc.
ICS950211
Electrical Characteristics - 3V66
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =10-30 pF (unless otherwise stated)
PARAMETER
Output Frequency
SYMBOL
FO1
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
R DSP11
VOH1
VOL1
IOH1
IOL1
Rise Time
Fall Time
CONDITIONS
MIN
TYP
66.66
MAX
UNITS
MHz
55
0.4
-33
38
Ω
V
V
mA
mA
2
ns
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V
VOL@ MIN = 1.95 V, VOL@ MAX= 0.4
-33
30
tr11
VOL = 0.4 V, VOH = 2.4 V
0.5
3
VOH = 2.4 V, VOL = 0.4 V
0.5
1.3
2
ns
VT = 1.5 V
45
52
55
%
Skew
1
tf1
1
d t1
tsk11
155
500
ps
Jitter
tjcyc-cyc1
150
250
ps
Duty Cycle
12
2.4
VT = 1.5 V
VT = 1.5 V
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - VCH, 48MHz DOT, 48MHz, USB
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise stated)
PARAMETER
Output Frequency
SYMBOL
FO1
VO = VDD*(0.5)
Output Impedance
Output High Voltage
RDSN11
VOH1
VO = VDD*(0.5)
IOH = -1 mA
12
2.4
Output Low Voltage
Output High Current
Output Low Current
VOL1
IOH1
IOL1
IOL = 1 mA
VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V
VOL@ MIN = 1.95 V, VOL@ MAX= 0.4
-29
29
48DOT Rise Time
tr11
VOL = 0.4 V, VOH = 2.4 V
0.5
48DOT Fall Time
VCH 48 USB
Rise Time
VCH 48 USB
Fall Time
48 DOT to 48 USB
Skew
Duty Cycle
tf11
VOH = 2.4 V, VOL = 0.4 V
1
tf1
Jitter
tr
tskew
1
1
d t1
1
tjcyc-cyc
CONDITIONS
MIN
TYP
48
MAX
UNITS
MHz
55
Ω
V
0.55
-23
27
V
mA
mA
0.6
1
ns
0.5
0.7
1
ns
VOL = 0.4 V, VOH = 2.4 V
1
1.1
2
ns
VOH = 2.4 V, VOL = 0.4 V
1
1.2
2
ns
1
ns
50.1
55
%
130
350
ps
VT=1.5V
VT = 1.5 V
VT = 1.5 V
45
1
Guaranteed by design, not 100% tested in production.
0465E—05/17/05
14
Integrated
Circuit
Systems, Inc.
ICS950211
Electrical Characteristics - REF
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =10-20 pF (unless otherwise stated)
PARAMETER
Output Frequency
SYMBOL
FO1
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
RDSP11
VOH1
VOL1
IOH1
IOL1
Rise Time
tr1
1
VOL = 0.4 V, VOH = 2.4 V
Fall Time
tf11
d t11
VOH = 2.4 V, VOL = 0.4 V
Duty Cycle
Jitter
tjcyc-cyc
CONDITIONS
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V
VOL@ MIN = 1.95 V, VOL@ MAX= 0.4
VT = 1.5 V
VT = 1.5 V
MIN
Guaranteed by design, not 100% tested in production.
0465E—05/17/05
15
MAX
UNITS
MHz
60
-29
29
0.4
-23
27
Ω
V
V
mA
mA
1
4
ns
4
ns
55
500
%
ps
20
2.4
1
45
1
TYP
53
Integrated
Circuit
Systems, Inc.
ICS950211
Shared Pin Operation Input/Output Pins
Figure 1 shows a means of implementing this function
when a switch or 2 pin header is used. With no jumper is
installed the pin will be pulled high. With the jumper in
place the pin will be pulled low. If programmability is not
necessary, than only a single resistor is necessary. The
programming resistors should be located close to the series
termination resistor to minimize the current loop area. It is
more important to locate the series termination resistor
close to the driver than the programming resistor.
The I/O pins designated by (input/output) serve as dual
signal functions to the device. During initial power-up, they
act as input pins. The logic level (voltage) that is present on
these pins at this time is read and stored into a 5-bit internal
data latch. At the end of Power-On reset, (see AC
characteristics for timing values), the device changes the
mode of operations for these pins to an output function. In
this mode the pins produce the specified buffered clocks to
external loads.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD (logic 1)
power supply or the GND (logic 0) voltage potential. A 10
Kilohm (10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
0465E—05/17/05
16
Integrated
Circuit
Systems, Inc.
ICS950211
Un-Buffered Mode 3V66 & PCI Phase Relationship
All 3V66 clocks are to be in pphase with each other. In the case where 3V66_1 is configured as 48MHz VCH clock, there is no
defined phase relationship between 3V66_1/VCH and other 3V66 clocks. The PCI group should lag 3V66 by the standard
skew described below as Tpci.
3V66
Tpci
PCICLK_F and PCICLK
Group Skews at Common Transition Edges: (Un-Buffered Mode)
GROUP
3V66
PCI
3V66 to PCI
1
SYMBOL
3V66
PCI
S3V66-PCI
CONDITIONS
3V66 pin to pin skew
PCI_F and PCI pin to pin skew
3V66 leads 33MHz PCI
MIN
0
0
1.5
TYP
155
302
1.7
MAX UNITS
500
ps
500
ps
3.5
ns
Guaranteed by design, not 100% tested in production.
PD# Functionality
CPU_STOP#
CPUT
CPUC
3V66
66MHz_OUT
PCICLK_F
PCICLK
PCICLK
USB/DOT
48MHz
1
Normal
Normal
66MHz
66MHz_IN
66MHz_IN
66MHz_IN
48MHz
0
iref * Mult
Float
Low
Low
Low
Low
Low
0465E—05/17/05
17
Integrated
Circuit
Systems, Inc.
ICS950211
PCI_STOP# - Assertion (transition from logic "1" to logic "0")
The impact of asserting the PCI_STOP# signal will be the following. All PCI[6:0] and stoppable PCI_F[2,0] clocks will latch low
in their next high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the next rising
edge.
Assertion of PCI_STOP# Waveforms
PCI_STOP#
PCI_F[2:0] 33MHz
PCI[6:0] 33MHz
tsu
CPU_STOP# - Assertion (transition from logic "1" to logic "0")
The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I2C configuration to be stoppable via
assertion of CPU_STOP# are to be stopped after their next transition following the two CPU clock edge sampling as shown.
The final state of the stopped CPU signals is CPUT=High and CPUC=Low. There is to be no change to the output drive current
values. The CPUT will be driven high with a current value equal to (MULTSEL0) X (I REF), the CPUC signal will not be driven.
Assertion of CPU_STOP# Waveforms
CPU_STOP#
CPUT
CPUC
CPU_STOP# Functionality
CPU_STOP#
CPUT
CPUC
1
Normal
Normal
0
iref * Mult
Float
0465E—05/17/05
18
Integrated
Circuit
Systems, Inc.
ICS950211
c
N
In Millimeters
SYMBOL COMMON DIMENSIONS
MIN
MAX
A
2.41
2.80
A1
0.20
0.40
b
0.20
0.34
c
0.13
0.25
D
SEE VARIATIONS
E
10.03
10.68
E1
7.40
7.60
e
0.635 BASIC
h
0.38
0.64
L
0.50
1.02
N
SEE VARIATIONS
0°
8°
α
L
E1
INDEX
AREA
E
1 2
a
h x 45°
D
A
In Inches
COMMON DIMENSIONS
MIN
MAX
.095
.110
.008
.016
.008
.0135
.005
.010
SEE VARIATIONS
.395
.420
.291
.299
0.025 BASIC
.015
.025
.020
.040
SEE VARIATIONS
0°
8°
A1
-Ce
SEATING
PLANE
b
N
.10 (.004) C
56
VARIATIONS
D mm.
MIN
MAX
18.31
18.55
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
300 mil SSOP Package
Ordering Information
ICS950211yFLF-T
Example:
ICS XXXX y F LF- T
Designation for tape and reel packaging
RoHS Compliant
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0465E—05/17/05
19
D (inch)
MIN
.720
MAX
.730
Integrated
Circuit
Systems, Inc.
ICS950211
c
N
L
E1
INDEX
AREA
E
1 2
a
D
A
A2
A1
56-Lead 6.10 mm. Body, 0.50 mm. Pitch TSSOP
(240 mil)
(20 mil)
In Millimeters
In Inches
SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS
MIN
MAX
MIN
MAX
A
-1.20
-.047
A1
0.05
0.15
.002
.006
A2
0.80
1.05
.032
.041
b
0.17
0.27
.007
.011
c
0.09
0.20
.0035
.008
SEE VARIATIONS
SEE VARIATIONS
D
8.10 BASIC
0.319 BASIC
E
E1
6.00
6.20
.236
.244
0.50 BASIC
0.020 BASIC
e
L
0.45
0.75
.018
.030
SEE VARIATIONS
SEE VARIATIONS
N
a
0°
8°
0°
8°
aaa
-0.10
-.004
-Ce
SEATING
PLANE
b
VARIATIONS
N
aaa C
56
D mm.
MIN
13.90
D (inch)
MAX
14.10
Reference Doc.: JEDEC Publication 95, MO-153
240 mil TSSOP Package
10-0039
Ordering Information
ICS950211yGLF-T
Example:
ICS XXXX y G LF- T
Designation for tape and reel packaging
RoHS Compliant
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0465E—05/17/05
20
MIN
.547
MAX
.555
Integrated
Circuit
Systems, Inc.
ICS950211
Revision History
Rev.
E
Issue Date Description
1. Updated Description on Byte 13.
5/17/2005 2. Updated LF Ordering Information from "Lead Free" to "RoHS Compliant".
0465E—05/17/05
21
Page #
9,19-20