CPC7508 Line Card Access Switch Features Description • • • • • • The CPC7508 is a member of Clare’s next generation Line Card Access Switch family. When used with ringing SLICs it provides the necessary functions to replace the two 2-Form-C electromechanical test relays used in contemporary Fiber To The Home (FTTH) and Optical Network Unit (ONU) deployments as well as Voice over IP (VoIP) telephony terminals. TTL logic level inputs for 3.3V logic interfaces Smart logic for power up / hot plug state control Monolithic IC reliability Low matched RON Clean, bounce-free switching Tertiary protection consisting of integrated current limiting and thermal shutdown for SLIC protection • +12.5V operation with power consumption ≤25mW • Latched logic level inputs, no external drive circuitry required • Small 16-pin SOIC Solid state switches provide the mechanism for tip and ring line break, drop test, and channel test while requiring only a single +12V supply for operation. Interface compatibility with 3.3V or 5V logic for switch state control is provided by the TTL logic level inputs. The CPC7508 is designed for fiber access units where EMR’s are used for test access and line monitoring functions but solid-state switches are desired due to reduced operating noise, lower power consumption and longer lifetimes. Applications • • • • • • Fiber to the Home (FTTH) Fiber in the Loop (FITL) VoIP Gateways PBX Systems Digitally Added Main Line (DAML) Hybrid Fiber Coax (HFC) This monolithic 8-pole solid-state switch is available in a 16-pin SOIC package. Ordering Information Part Number Description CPC7508B CPC7508BTR 8-pole LCAS, 16-pin SOIC in tubes (50/tube) 8-pole LCAS, 16-pin SOIC in reels (1000/reel) Figure 1. CPC7508 Block Diagram TTEST_IN (TCHAN_TEST) CPC7508 +12VDC TTEST_OUT (TDROP_TEST) 1 VDD 8 7 X SW7 X SW3 Tip TLINE 6 X SW5 5 TBAT X SW1 Secondary Protection Ring Ringing SLIC SW2 RLINE 11 12 RBAT X X SW4 X SW6 SW8 X RTEST_OUT (RDROP_TEST) 10 L A T C H Switch Control Logic 9 2 GND 16 INA 15 INB 14 13 INC LATCH 3 TSD RTEST_IN (RCHAN_TEST) Pb DS-CPC7508 - R04 www.clare.com RoHS 2002/95/EC e3 1 CPC7508 1. Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 General Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6 Switch Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6.1 Break Switches, SW1 and SW2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6.2 TEST_OUT Switches SW3 & SW4 and TEST BRIDGE Switches SW7 & SW8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6.3 TEST_IN Switches, SW5 and SW6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7 Digital I/O Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8 Voltage and Power Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.9 Protection Circuitry Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.10 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 3 3 3 3 4 4 5 6 7 7 7 8 2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2.2 Logic States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 Switch Logic and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3.2 Under Voltage Detection and Switch Lock Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3.2.1 Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3.2.2 Hot Plug and Power Up Circuit Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3.2.3 Power Loss Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3.3 Data Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.4 TSD Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.5 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.6 Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.6.1 Current Limiting function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.6.2 Thermal Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.7 External Protection Elements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3. Manufacturing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Mechanical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Printed-Circuit Board Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Tape and Reel Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.1 Moisture Reflow Sensitivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.2 Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 Washing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 www.clare.com 13 13 13 14 14 14 14 14 R04 CPC7508 1. Specifications 1.1 Package Pinout 1.2 Pin Description CPC7508 Pin Name VDD 1 16 INA 1 VDD +12.5VDC supply GND 2 15 INB 2 GND Ground 3 TSD I/O, All Off control, Thermal shutdown flag 4 N/C No Connect - Do not use 5 TBAT Tip lead to the SLIC 6 TLINE Tip lead of the line side TSD 3 14 INC Description N/C 4 13 LATCH TBAT 5 12 RBAT TLINE 6 11 RLINE 8 TTEST_IN Tip lead of the Test In (Channel Test) bus TTEST_OUT 7 10 RTEST_OUT 9 RTEST_IN Ring lead of the Test In (Channel Test) bus TTEST_IN 8 9 RTEST_IN 7 10 TTEST_OUT Tip lead of the Test Out (Drop Test) bus RTEST_OUT Ring lead of the Test Out (Drop Test) bus 11 RLINE Ring lead of the line side 12 RBAT Ring lead to the SLIC 13 LATCH 14 INC Input, Logic control 15 INB Input, Logic control 16 INA Input, Logic control Input, Data latch enable 1.3 Absolute Maximum Ratings 1.4 ESD Rating Parameter Minimum Maximum Unit +12 V power supply (VDD) -0.3 15 V Logic input voltage -0.3 6 V Logic input to switch output isolation - 225 V Switch open-contact to ground isolation - 225 V Switch open, contact to contact isolation - 320 V Operating relative humidity 5 95 % Operating temperature -40 +110 °C Storage temperature -40 +150 °C 1000 V 1.5 General Conditions Unless otherwise specified, minimum and maximum values are guaranteed by production testing requirements. Absolute maximum electrical ratings are at 25°C. Absolute Maximum Ratings are stress ratings. Stresses in excess of these ratings can cause permanent damage to the device. Functional operation of the device at conditions beyond those indicated in the operational sections of this data sheet is not implied. R04 ESD Rating (Human Body Model) Typical values are characteristic of the device at 25° C and are the result of engineering evaluations. They are provided for information purposes only and are not part of the testing requirements. Specifications cover the operating temperature range TA = -40° C to +85° C. Also, unless otherwise specified all testing is performed with VDD = 12.5 Vdc, logic low input voltage is 0 Vdc and logic high voltage is 3.3 Vdc. www.clare.com 3 CPC7508 1.6 Switch Specifications 1.6.1 Break Switches, SW1 and SW2 Parameter Off-State Leakage Current Test Conditions Symbol Minimum Typical Maximum Unit 1 μA VSW1 (differential) = TLINE to TBAT VSW2 (differential) = RLINE to RBAT Applied voltage maximum ±225 V to ground All-Off state. +25° C, VSW (differential) = ±320 V +85° C, VSW (differential) = ±330 V 0.1 ISW - -40° C, VSW (differential) = ±310 V 0.3 0.1 ISW(on) = ±10 mA, ±40 mA On Resistance +25° C RON +85° C -40° C On Resistance Matching Per SW1 & SW2 On Resistance test conditions. ΔRON VSW (on) = ±10 V, +25° C DC current limit VSW (on) = ±10 V, +85° C ISW VSW (on) = ±10 V, -40° C Dynamic current limit (t ≤ 0.5 μs) Break switches on, all other switches off. Apply ±1 kV 10x1000 μs pulse with appropriate protection in place. ISW +25° C, Logic inputs = gnd, VSW (TLINE, RLINE) = ±225 V VSW (TBAT, RBAT) = ±225 V Logic input to switch output isolation +85° C, Logic inputs = gnd, VSW (TLINE, RLINE) = ±225 V VSW (TBAT, RBAT) = ±225 V ISW -40° C, Logic inputs = gnd, VSW (TLINE, RLINE) = ±225 V VSW (TBAT, RBAT) = ±225 V dv/dt sensitivity 4 - - www.clare.com 14.7 Ω 21.1 28 8 10.7 - - 0.15 0.8 - 300 80 160 - 400 425 - 1.0 - A - 0.1 - 0.3 1 μA - 0.1 - 500 - V/μs - Ω mA R04 CPC7508 1.6.2 TEST_OUT Switches SW3 & SW4 and TEST BRIDGE Switches SW7 & SW8 Parameter Off-State Leakage Current Test Conditions Symbol Minimum Typical Maximum Unit 1 μA 60 - 85 110 Ω 30 50 - - 0.5 2 - 135 70 85 - 210 250 - 0.7 - A 1 μA - V/μs VSW3 (differential) = TLINE to TTEST_OUT VSW4 (differential) = RLINE to RTEST_OUT VSW7 (differential) = TTEST_OUT to TTEST_IN VSW8 (differential) = RTEST_OUT to RTEST_IN Applied voltage maximum ±225 V to ground All-Off state. +25° C, VSW (differential) = ±320 V +85° C, VSW (differential) = ±330 V 0.1 ISW - -40° C, VSW (differential) = ±310 V 0.3 0.1 ISW(on) = ±0 mA, ±10 mA, On Resistance +25° C RON +85° C -40° C On Resistance Matching Per On Resistance test conditions. SW3 & SW4 ΔRON SW7 & SW8 VSW (on) = ± 10 V, +25° C DC current limit VSW (on) = ± 10 V, +85° C ISW VSW (on) = ± 10 V, -40° C Dynamic current limit (t ≤ 0.5 μs) Test_OUT switches on, all other switches off. Apply ±1 kV 10x1000 μs pulse with appropriate protection in place. ISW +25° C, Logic inputs = gnd, VSW3 (TTEST_OUT) = ±225 V VSW4 (RTEST_OUT) = ±225 V Logic input to switch output isolation +85° C, Logic inputs = gnd, VSW3 (TTEST_OUT) = ±225 V VSW4 (RTEST_OUT) = ±225 V R04 - mA 0.1 ISW - -40° C, Logic inputs = gnd, VSW3 (TTEST_OUT) = ±225 V VSW4 (RTEST_OUT) = ±225 V dv/dt sensitivity - Ω 0.3 0.1 - www.clare.com - 500 5 CPC7508 1.6.3 TEST_IN Switches, SW5 and SW6 Parameter Off-State Leakage Current Test Conditions Symbol Minimum Typical Maximum Unit 1 μA VSW5 (differential) = TTEST_IN to TBAT VSW6 (differential) = RTEST_IN to RBAT Applied voltage maximum ±225 V to ground All-Off state. +25° C, VSW (differential) = ±320 V +85° C, VSW (differential) = ±330 V 0.1 ISW - -40° C, VSW (differential) = ±310 V 0.2 0.1 ISW(on) = ±10 mA, ±40 mA On Resistance Per SW5 & SW6 On Resistance test conditions. ΔRON VSW (on) = ±10 V, +25° C DC current limit ISW VSW (on) = ±10 V, +85° C VSW (on) = ±10 V, -40° C Dynamic current limit (t ≤ 0.5 μs) Break switches on, all other switches off. Apply ±1 kV 10x1000 μs pulse with appropriate protection in place. ISW +25° C, Logic inputs = gnd, VSW5 (TTEST_IN) = ±225 V VSW6 (RTEST_IN) = ±225 V Logic input to switch output isolation +85° C, Logic inputs = gnd, VSW5 (TTEST_IN) = ±225 V VSW6 (RTEST_IN) = ±225 V ISW -40° C, Logic inputs = gnd, VSW5 (TTEST_IN) = ±225 V VSW6 (RTEST_IN) = ±225 V dv/dt sensitivity 6 - 46 70 20 28 - - 0.35 1.4 - 125 80 95 - 165 250 - 1 - A - 0.1 - 0.3 1 μA - 0.1 - 500 - V/μs RON +85° C -40° C On Resistance Matching 38 +25° C - - www.clare.com - Ω Ω mA R04 CPC7508 1.7 Digital I/O Electrical Specifications Parameter Test Conditions Symbol Minimum Typical Maximum Input voltage, Logic low Input voltage falling VIL 0.8 1.0 - Input voltage, Logic high Input voltage rising VIH - 1.7 2.0 Unit Input Characteristics V Input leakage current, Logic high VDD = 13.4 V, VHI = 2.4 V IIH - 0.1 1 μA Input leakage current, Logic low VDD = 13.4 V, VIL = 0.4 V IIL - 0.1 1 μA VDD = 13.4 V, ITSD = 1mA VTSD_on - 0 0.4 V Test Conditions Symbol Minimum Typical Maximum Unit - VDD 11.4 12.5 13.4 V IDD - 1.67 2 mA P - 20 25 mW Symbol Minimum Typical Maximum Unit TTSD_on 110 125 150 °C TTSD_off 10 - 25 °C Output Characteristics Output voltage, TSD Logic low 1.8 Voltage and Power Specifications Parameter Voltage Requirements VDD Power Specifications VDD current VDD = 12.5 V, All states Power consumption VDD = 12.5 V, All states, Measure IDD 1.9 Protection Circuitry Specifications Parameter Conditions Thermal Shutdown Specifications Shutdown activation temperature Shutdown circuit hysteresis R04 Not production tested - limits are guaranteed by design and Quality Control sampling audits. www.clare.com 7 CPC7508 1.10 Truth Table State Talk INA INB INC 0 0 0 LATCH TSD Break Switches TEST_OUT Switches TEST BRIDGE Switches TEST_IN Switches On Off Off Off TEST_IN 0 0 1 Off Off Off On TEST_OUT 0 1 0 Off On Off Off TEST_IN Monitor 0 1 1 On Off Off On On On Off Off TEST_OUT Monitor 1 0 0 0 Z1 TEST_IN & OUT 1 0 1 Off On Off On All-Off 1 1 0 Off Off Off Off TEST_IN Bridge 1 1 1 Off Off On On Latched X X X 1 All-Off X X X X Off Off 1 Unchanged 0 Off Off Z = High Impedance. Because TSD has a high impedance output for a logic high it needs to be pulled up to the logic supply through an external resistor. Break Switches: SW1 and SW2 TEST_OUT Switches: SW3 and SW4 TEST_IN Switches: SW5 and SW6 TEST BRIDGE Switches: SW7 and SW8 8 www.clare.com R04 CPC7508 2. Functional Description 2.1 Introduction The CPC7508 LCAS provides the necessary test access functions for line card interfaces supported by ringing SLICs in contemporary Fiber In The Loop (FITL), Fiber To The Home (FTTH) applications and Voice over Internet Protocol (VoIP). These applications have a different working environment than standard traditional Digital Loop Carrier (DLC) equipment and therefore have unique requirements. Two significant differences are the diverse supply voltages and the interface to ringing SLICs. The once common 5V supply is generally not available in the modern short loop products made feasible with the advent of broadband services. To support applications where a 5V supply is not available but a 12V supply is, the VDD input power specification for the CPC7508 has been set accordingly. Ringing SLICs have replaced the customary standard SLIC and ringing relay configuration and for the LCAS to be compatible with a ringing SLIC. the LCAS internal protection circuits have been removed. This was essential so as not to clip the ringing waveform output from the ringing SLIC. Traditional test access is provided by two pair of test access switches, TEST_IN and TEST_OUT, employing the TEST_IN & OUT state. Supplementing the traditional test access switches is the TEST BRIDGE switch pair capable of cross connecting the test busses thereby providing the means to validate the status of SW1 and SW2, the Break Switches. Integrated into the CPC7508 is a dynamic active current limit, a DC current limit and a thermal shutdown mechanism to provide protection for the SLIC during a fault condition. Positive and negative lightning surge currents are reduced by the dynamic current limiting circuitry and excess power-cross potentials are restricted by the DC current limit and thermal shutdown circuits. To protect the CPC7508 from an over-voltage fault condition, use of a secondary protector is required. The secondary protector must limit the voltage seen at it’s tip and ring line terminals to a level below the maximum breakdown voltage of the switches. With proper selection of the secondary protector, a line interface circuit using the CPC7508 will meet all relevant ITU, LSSGR, TIA/EIA and IEC protection requirements. The CPC7508 operates from a single +12.5 V supply giving the device extremely low power consumption in any state. State control is via TTL logic-level compatible inputs so no additional driver circuitry or level translators are required. TTL compatible inputs make state control of the CPC7508 with low voltage logic devices possible. 2.2.2 Logic States The CPC7508 provides eight distinct states enabling sufficient configurations to satisfy most design requirements. They are defined below. 2.2 Description 2.2.1 Overview Because the CPC7508 LCAS utilizes solid-state switch construction to implement the switching functions this means no impulse noise is generated when switching large line potentials. To ensure proper voice performance the linear break switches SW1 and SW2 have exceptionally low RON and excellent matching characteristics. The switches have a R04 minimum open contact breakdown voltage of 320 V and a minimum contact to ground breakdown voltage of 225 V at +25°C, sufficiently high with proper protection to prevent breakdown in the presence of a transient fault condition. • Talk. Break switches SW1 and SW2 closed, all other switches open. This provides a path between the ringing SLIC and the drop allowing communication and signalling to pass between the subscriber and the network. • Test_IN. Test switches SW5 and SW6 closed, all other switches open. In this state the SLIC, CODEC and digital carrier performance can be tested via the Test In or Channel Test bus • Test_OUT. Test switches SW3 and SW4 closed and all other switches open. This state provides the www.clare.com 9 CPC7508 • • • • • means to test the drop without the loading effects of the line feed circuitry. Test_IN Monitor. Break switches SW1 and SW2 plus the TEST_IN switches SW5 and SW6 closed, all other switches open. With this state it is possible to monitor the SLIC output while the SLIC is driving the line. Test_OUT Monitor. Break switches SW1 and SW2 plus the TEST_OUT switches SW3 and SW4 closed, all other switches open. With this state it is possible to monitor the LCAS output while the SLIC is driving the line. Test_IN & OUT. TEST_IN switches SW5 and SW6 plus the TEST_OUT switches SW3 and SW4 closed, all other switches open. This state allows simultaneous testing of the transmission channel and the drop. Test_IN BRIDGE. TEST_IN switches SW5 and SW6 plus TEST BRIDGE switches SW7 and SW8 closed, all other switches open. This state allows connecting the SLIC output to the Test Out bus to compare the on-hook TEST_OUT Monitor evaluation. This makes it possible to determine if there is a failure with the Break Switches. All-Off. All switches open. Activation of this state can be accomplished by setting the appropriate INX pattern or by pulling the TSD input/output low. 2.3 Switch Logic and Control 2.3.1 Introduction The CPC7508 uses a three input transparent latch as the interface between the externally controlled inputs, INA, INB and INC and the switch logic. Control of the transparent latch is by means of the LATCH input. Data output from the latch is fed into the switch control logic which decodes the inputs and drives the appropriate switches. To prevent undesirable switch activity during both start-up and power down the switch control logic also contains under voltage lock out detection circuitry to manage the behavior of the CPC7508. The under voltage lock out release threshold is internally set to ensure all internal logic is properly biased before accepting external switch commands from the INx inputs to control the switch states. Prior to release of the under voltage lock out, the switch control logic is conditioned to the All-Off state 10 2.3.2 Under Voltage Detection and Switch Lock Out Under voltage detection circuitry in the CPC7508 consists of an internal detector to evaluate the VDD supply and smart logic to provide for switch state control during both power up and power loss transitions. Any time an unsatisfactory condition causes the VDD supply to fall below the internally set under voltage lockout threshold, the smart logic overrides user switch control by blocking the information at the INx input pins and conditions the switch control logic to place the switches into the All-Off state. 2.3.2.1 Power Up Sequence Upon power up, the under voltage detector and smart logic become active before the switch driver circuits and the switch control logic can activate any of the switches. As the VDD supply starts up, the rising supply voltage is evaluated by the under voltage detector to determine when to de-assert the under voltage switch lock out command. Prior to release of the lock out command, the smart logic preconditions the switch control logic for the All-Off state. The All_Off state is sustained by holding the LATCH input at a logic high level. This is accomplished by an external resistor at the LATCH pin which pulls the input to the supply voltage used by the on-board logic. The LATCH logic high secures the switch control logic and the CPC7508 remains in the All-Off state until the LATCH input is pulled down to a logic low. Prior to the assertion of a logic low at the LATCH pin, the control inputs INA, INB and INC must be properly conditioned. 2.3.2.2 Hot Plug and Power Up Circuit Design Considerations To facilitate hot plug insertion and power up control the LATCH pin has an external pull up resistor to the local logic power rail that will hold a non-driven LATCH pin at a logic high state. This enables board designers to use the CPC7508 with FPGAs and other devices that provide high impedance outputs during power up and configuration. www.clare.com R04 CPC7508 2.3.3 Data Latch There are six possible start up scenarios that can occur during power up. They are: 1. 2. 3. 4. 5. 6. All inputs defined at power up & LATCH = 0 All inputs defined at power up & LATCH = 1 All inputs defined at power up & LATCH = Z All inputs not defined at power up & LATCH = 0 All inputs not defined at power up & LATCH = 1 All inputs not defined at power up & LATCH = Z Under all of the start up situations listed above the CPC7508 will hold all of it’s switches in the all-off state during power up. When VDD requirements have been satisfied the LCAS will complete it’s start up procedure in one of three conditions. For start up scenario 1 the CPC7508 will transition from the all-off state to the state defined by the inputs when VDD is valid. For start up scenarios 2, 3, 5, and 6 the CPC7508 will power up in the all-off state and remain there until the LATCH pin is pulled low. This allows for an indefinite all-off state for boards inserted into a powered system but are not configured for service or boards that need to wait for other devices to be configured first. Start up scenario 4 will start up with all switches in the all-off state but upon the acceptance of a valid VDD the LCAS will revert to one of the legitimate states listed in the truth tables and there after may randomly change states based on input pin leakage currents and loading. Because the LCAS state after power up can not be predicted with this start up condition it should never be utilized. On designs that do not wish to individually control the LATCH pins of multi-port cards it is possible to bus many (or all) of the LATCH pins together to create a single board level input enable control. 2.3.2.3 Power Loss Sequence For a falling VDD event, the under voltage lock out detector monitors the supply voltage and upon reaching the internally set threshold point asserts the under voltage lock out command. This feature protects the integrity of the application during power dropouts by assuring proper logic and switch behavior up to the moment the switches are forced off and external inputs are suppressed. Upon assertion of the under voltage lock out command the switch control logic is conditioned into the All_Off state where it will remain until VDD recovers and the LATCH input is pulled low. R04 The CPC7508 has an integrated transparent data latch controlled by the LATCH input which can be used as an enable or a chip select function when the INx inputs of multiple LCAS devices are connected to common busses. The latch enable operation is controlled by TTL input logic levels at the LATCH pin. Control data is input to the latch via the input pins INA, INB and INC while the output of the data latch are internal nodes used for state control. When the LATCH enable input control pin is a logic 0 (low) the data latch is transparent and any change to the inputs will flow directly through the latch to the state control circuitry and be reflected by a change in the switches status. Whenever the LATCH enable control pin is at logic 1, the data latch is active and data is locked. Subsequent changes to the input controls INA, INB and INC will not result in a change to the control logic or affect the existing switch state. 2.4 TSD Pin Description The TSD pin is a bi-directional I/O structure used as an output to indicate a thermal shutdown event is in effect and as an input to condition the device into the All-Off state. As an output, this pin indicates the status of the thermal shutdown circuitry. During normal operation the output will be pulled up to a logic high by an external resistor tied to the local logic supply voltage. Under a line fault situation that creates excess thermal loading, the CPC7508 will enter thermal shutdown and a logic low will be output. As an input, the TSD pin is utilized to place the CPC7508 into the “All-Off” state by simply pulling the input to a logic low. Clare recommends the use of an open-collector or an open-drain type output from the control logic to manage the All-Off state using the TSD pin. Forcing TSD to a logic 1 or tying this pin to VCC will not prevent normal operation of the thermal shutdown circuitry inside the CPC7508. It will however prevent the user from detecting a thermal shutdown condition and is therefore not recommended. www.clare.com 11 CPC7508 Neither the TSD input control nor the TSD output functions are affected by the latch function. Since internal thermal shutdown control and external “All-off” control is not affected by the state of the LATCH enable input, TSD will override state control. 2.5 Power Supplies Only a +12 V supply and ground are connected to the CPC7508. Switch state control is powered exclusively by the +12 V supply while internal level shifters provide the necessary translation from the low voltage inputs to the switch driver circuitry. 2.6 Protection The CPC7508 uses a combination of current limiting and a thermal shutdown mechanism to protect the SLIC device and itself from damage during transient line faults such as lightning. For power induction or power-cross fault conditions the DC current limit function restricts the maximum current through the switches. Excess power dissipation during current limiting events will trigger the thermal shutdown circuit to shut down all of the switches. 2.6.1 Current Limiting function If a lightning strike transient occurs when any of the devices switches are operating, the current will be restricted by the dynamic current limit response of the active switches. For instance, during the talk state, when a 1000V 10x1000 μs lightning pulse (GR-1089-CORE) is applied to the line though a properly clamped external protector, the current seen at TLINE and RLINE will be a pulse with a typical magnitude of 2.5 A and a duration less than 0.5 μs. If a power-cross fault occurs with the device in the talk state, the current is passed though the break switches SW1 and SW2 but is limited by the DC current limit response of the two break switches. The DC current limit specified over temperature is between 80 mA and 425 mA and the circuitry has a negative temperature coefficient. As a result, if the device is subjected to extended heating due to a power cross fault condition, the measured current at TLINE and RLINE will decrease as the device temperature increases. If the device temperature rises sufficiently, the temperature shutdown mechanism will activate and the device will enter the all-off state. 12 2.6.2 Thermal Shutdown The thermal shutdown mechanism activates when the device die temperature reaches a minimum of 110° C, placing the device in the all-off state regardless of logic input. During thermal shutdown events the TSD pin will output a logic low with a nominal 0 V level. A logic high is output from the TSD pin during normal operation with a typical output level equal to VDD. If presented with a short duration transient such as a lightning event, the thermal shutdown feature will typically not activate. But in an extended power-cross event, the device temperature will rise and the thermal shutdown mechanism will activate forcing the switches to the all-off state. At this point the current measured into TLINE or RLINE will drop to zero. Once the device enters thermal shutdown it will remain in the all-off state until the temperature of the device drops below the de-activation level of the thermal shutdown circuit. This permits the device to autonomously return to normal operation. If the transient has not passed, current will again flow up to the value allowed by the dynamic DC current limiting of the switches and heating will resume, reactivating the thermal shutdown mechanism. This cycle of entering and exiting the thermal shutdown mode will continue as long as the fault condition persists. If the magnitude of the fault condition is great enough, the external secondary protector will activate shunting the fault current to ground. 2.7 External Protection Elements The CPC7508 requires only the over voltage secondary protector normally used to protect the ringing SLIC placed on the line side of the LCAS. The secondary protector must limit voltage transients to levels that do not exceed the breakdown voltage or input-output isolation barrier of the CPC7508. Use of a foldback or crowbar type protector is recommended to minimize stresses on the LCAS. Consult Clare’s application note, AN-100, “Designing Surge and Power Fault Protection Circuits for Solid State Subscriber Line Interfaces” for equations related to the specifications of external secondary protectors, fused resistors and PTCs. www.clare.com R04 CPC7508 3. Manufacturing Information 3.1 Mechanical Dimensions NOTES: 1. Coplanarity = 0.1016 (0.004) max. 2. Leadframe thickness does not include solder plating (1000 microinch maximum). 10.211 ± 0.254 (0.402 ± 0.010) PIN 16 10.312 ± 0.381 (0.406 ± 0.015) 7.493 ± 0.127 (0.295 ± 0.005) DIMENSIONS mm (inches) PIN 1 0.406 ± 0.076 (0.016 ± 0.003) 1.270 TYP (0.050 TYP) 2.540 ± 0.152 (0.100 ± 0.006) 2.337 ± 0.051 (0.092 ± 0.002) 0.649 ± 0.102 (0.026 ± 0.004) 0.203 ± 0.102 (0.008 ± 0.004) 0.889 ± 0.178 (0.035 ± 0.007) 0.254 MIN / 0.737 MAX X 45° (0.010 MIN / 0.029 MAX X 45°) 0.2311 MIN / 0.3175 MAX (0.0091 MIN / 0.0125 MAX) 3.2 Printed-Circuit Board Land Pattern 1.27 (0.050) 9.40 (0.370) 2.00 (0.079) 0.60 (0.024) R04 DIMENSIONS mm (inches) www.clare.com 13 CPC7508 3.3 Tape and Reel Packaging 330.2 Dia (13.00 Dia) B0=10.70 + 0.15 (0.421 + 0.01) Pin 1 Top Cover Tape Thickness 0.102 Max (0.004 Max) W=16.00 + 0.30 (0.630 + 0.010) Top Cover Tape K0=3.20 + 0.15 (0.193 + 0.01) K1=2.70 + 0.15 (0.106 + 0.01) Embossed Carrier Embossment P=12.00 (0.47) A0=10.90 + 0.15 (0.429 + 0.010) Dimensions mm (inches) User Direction of Feed NOTE: Tape dimensions not shown comply with JEDEC Standard EIA-481-2 3.4.2 Reflow Profile 3.4 Soldering 3.4.1 Moisture Reflow Sensitivity Clare has characterized the moisture reflow sensitivity for this package using IPC/JEDEC standard J-STD-020. The CPC7508B 16-pin SOIC package conforms to with the IPC/JEDEC standard J-STD-033 moisture sensitivity level (MSL) level 1. For proper assembly, this component must be processed in accordance with the current revision of IPC/JEDEC standard J-STD-020. Failure to follow the recommended guidelines may cause permanent damage to the device resulting in impaired performance and/or a reduced lifetime expectancy. 3.5 Washing Clare does not recommend ultrasonic cleaning of this part. Pb RoHS 2002/95/EC e3 For additional information please visit www.clare.com Clare, Inc. makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses or indemnity are expressed or implied. Except as set forth in Clare’s Standard Terms and Conditions of Sale, Clare, Inc. assumes no liability whatsoever, and disclaims any express or implied warranty relating to its products, including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. The products described in this document are not designed, intended, authorized, or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or where malfunction of Clare’s product may result in direct physical harm, injury, or death to a person or severe property or environmental damage. Clare, Inc. reserves the right to discontinue or make changes to its products at any time without notice. Specification: DS-DS-CPC7508-R04 © Copyright 2009, Clare, Inc. All rights reserved. Printed in USA. 10/14/09 14 www.clare.com R04