LSI/CSI LS7166 UL (631) 271-0400 FAX (631) 271-0405 ® LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 A3800 December 2002 24-BIT QUADRATURE COUNTER REGISTER DESCRIPTION: Internal hardware registers are accessible through the I/O bus (D0 - D7) for READ or WRITE when CS = 0. The C/D input selects between the control registers (C/D = 1) and the data registers (C/D = 0) during a READ or WRITE operation. (See Table 1) 7166-120902-1 *(Contact factory for 24-Pin TSSOP Package Pinout) (Write Input) WR 1 (Chip Select Input) CS 20 VSS (GND) 2 19 RD (Read Input) (Load Counter/Load Latch) LCTR/LLTC 3 18 C/D (Control/ Data Input) (A, B Gate/Reset Counter)ABGT/RCTR 4 17 BW (Borrow Output) VDD (+5V) 5 16 CY (Carry Output) (Count Input) A 6 15 D7 (Count Input) B 7 14 D6 D0 8 13 D5 D1 9 12 D4 D2 10 11 D3 LS7166 GENERAL DESCRIPTION: The LS7166 is a CMOS, 24-bit counter that can be programmed to operate in several different modes. The operating mode is set up by writing control words into internal control registers (see Figure 8). There are three 6-bit and one 2-bit control registers for setting up the circuit functional characteristics. In addition to the control registers, there is a 5-bit output status register (OSR) that indicates the current counter status. The IC communicates with external circuits through an 8-bit three state I/O bus. Control and data words are written into the LS7166 through the bus. In addition to the I/O bus, there are a number of discrete inputs and outputs to facilitate instantaneous hardware based control functions and instantaneous status indication. 20-Pin Package PIN ASSIGNMENT - Top View LSI FEATURES: • Programmable modes are: Up/Down, Binary, BCD, 24 Hour Clock, Divide-by-N, x1 or x2 or x4 Quadrature and Single Cycle. • DC to 20 MHz Count Frequency. • 8-Bit I/O Bus for Microprocessor Communication and Control. • 24-Bit comparator for pre-set count comparison. • Readable status register. • Input/Output TTL and CMOS compatible. • 5 Volt operation (Vdd - Vss). • LS7166 (DIP); LS7166-S (SOIC); LS7166-TS24 (24-Pin TSSOP)* - See Fig. 1 FIGURE 1 The information included herein is believed to be accurate and reliable. However, LSI Computer Systems, Inc. assumes no responsibilities for inaccuracies, nor for any infringements of patent rights of others which may result from its use. TABLE 1 - Register Addressing Modes D7 D6 C/D RD WR CS X X X X X 1 0 0 1 1 0 COMMENT Disable Chip for READ/WRITE Write to Master Control Register (MCR) 0 1 1 1 0 Write to input control register (ICR) 1 0 1 1 0 Write to output/counter control register (OCCR) 1 X 1 X 1 0 1 1 0 0 Write to quadrature register (QR) Write to preset register (PR) and increment register address counter. X X 0 1 0 Read output latch (OL) and increment register address counter X X 1 1 0 Read output status register (OSR). X = Don't Care OSR (Output Status Register). Indicates CNTR status: Accessed by: READ when C/D = 1, CS = 0. Bit # 7 6 5 4 3 2 1 0 U U U 0/1 0/1 0/1 0/1 0/1 BWT. Borrow Toggle Flip-Flop. Toggles everytime CNTR underflows generating a borrow. CYT. Carry Toggle Flip-Flop. Toggles everytime CNTR overflows generating a carry. COMPT. Compare Toggle Flip-Flop. Toggles everytime CNTR equals PR SIGN. Sign bit. Reset ( = 0) when CNTR underflows Set ( = 1) when CNTR overflows UP/DOWN. Count direction indicatior in quadrature mode. Reset ( = 0) when counting down Set ( = 1) when counting up (Forced to 1 in non-quadrature mode) U = Undefined OL(Output latch). The OL is the output port for the CNTR. The 24 bit CNTR Value at any instant can be accessed by performing a CNTR to OL transfer and then reading the OL in 3 READ cycle sequence of Byte 0 (OL0), Byte 1 (OL1) and Byte 2 (OL2). The address pointer for OL0/OL1/OL2 is automatically incremented with each READ cycle. Accessed by: READ when C/D = 0, CS = 0. Bit # 7 OL2 (BYTE 2) 0 7 0 OL1 (BYTE 1) 7 0 OL0 (BYTE 0) Standard Sequence for Loading and Reading OL: 3 MCR ; Reset OL address pointer and Transfer CNTR to OL READ OL ; Read Byte 0 and increment address READ OL ; Read Byte 1 and increment address READ OL ; Read Byte 2 and increment address 7166-062394-3 PR (Preset register). The PR is the input port for the CNTR. The CNTR is loaded with a 24 bit data via the PR. The data is first written into the PR in 3 WRITE cycle sequence of Byte 0 (PR0), Byte 1 (PR1) and Byte 2 (PR2). The address pointer for PR0/PR1/PR2 is automatically incremented with each write cycle. Accessed by: WRITE when C/D = 0, CS = 0. Bit # 7----------0 PR2 (BYTE 2) 7---------- 0 PR1 (BYTE 1) 7----------0 PR0 (BYTE 0) Standard Sequence for Loading PR and Reading CNTR: 1 MCR ; Reset PR address pointer WRITE PR ; Load Byte 0 and into PR0 increment address WRITE PR ; Load Byte 1 and into PR1 increment address WRITE PR ; Load Byte 2 and into PR3 increment address 8 MCR ; Transfer PR to CNTR MCR (Master Control Register). Performs register reset and load operations. Writing a "non-zero” word to MCR does not require a follow-up write of an “all-zero” word to terminate a designated operation. Accessed by: WRITE when C/D = 1, CS = 0. Bit # 7 6 5 0 0 4 3 2 1 0 1: Reset PR/OL address pointer 1: Transfer CNTR to OL (24 bits) 1: Reset CNTR, BWT and CYT. Set SIGN bit. (CNTR=0, BWT=0, CYT=0, SIGN=1) 1: Transfer PR to CNTR (24 bits) 1: Reset COMPT (COMPT = 0) 1: Master reset. Reset CNTR, ICR, OCCR, QR, BWT, CYT, OL COMPT, and PR/OL address pointer. Set PR (PR=FFFFFF) and SIGN. 0: Select MCR 0: NOTE: Control functions may be combined. ICR (Input Control Register). Initializes counter input operating modes. Accessed by: WRITE when C/D = 1, CS = 0. Bit # 7 6 5 4 3 2 1 0 0 1 0: Input A = Up count input, Input B = Down count input 1: Input A = Count input, Input B = Count direction input (overridden in quadrature mode) where B = 0 selects up count mode and B =1 selects Down count mode. (NOTE: During counting operation B may switch only when A = 1.) 0: NOP 1: Increment CNTR once (A/B = 1, if enabled) 0: NOP 1: Decrement CNTR once (A/B = 1, if enabled) 0: Disable inputs A/B 1: Enable inputs A/B 0: Initialize Pin 4 as CNTR Reset input (Pin 4 = RCTR) 1: Initialize Pin 4 as Enable/Disable gate for A/B inputs (Pin 4 = ABGT) 0: Initialize Pin 3 as CNTR load input (Pin 3 = LCTR) 1: Initialize Pin 3 as OL load input (Pin 3 = LLTC) 1: Select ICR 0: NOTE: Control functions may be combined. 7166-062394-2 OCCR (Output Control Register) Initializes CNTR and output operating modes. Accessed by : WRITE when C/D = 1, CS = 0. Bit # 7 6 5 4 3 2 1 0 1 0 0: 1: 0: 1: Binary count mode (Overridden by D3 = 1). BCD count mode (Overridden by D3 = 1) Normal count mode Non-Recycle count mode. (CNTR enabled with a Load or Reset CNTR and disabled with generation of Carry or Borrow. In this mode no external CY or BW is generated. Instead CYT or BWT should be used as cycle completion indicator.) 0: Normal count mode 1: Divide by N count mode (CNTR is reloaded with PR data upon Carry or Borrow). 0: Binary or BCD count mode (see D0) 1: 24 Hour Clock mode with Byte 0 = Sec, Byte 1 = Min and Byte 2 = Hr. (Overrides BCD/Binary Modes) 0 Pin 16 = CY, Pin 17 = BW. (Active Low) 0 1 Pin 16 = CYT, Pin 17 = BWT 0 0 Pin 16 = CY, Pin 17 = BW. (Active high) 1 1 Pin 16 = COMP, Pin 17 = COMPT 1 0 Select OCCR 1 QR (Quadrature Register). Selects quadrature count mode (See Fig. 7) Accessed by: WRITE when C/D = 1, CS = 0. Bit # 7 6 5 4 3 2 1 0 1 1 X X X X 0 Disable quadrature mode 0 1 Enable x1 quadrature mode 0 0 Enable x2 quadrature mode 1 1 Enable x4 quadrature mode 1 1 1 X = Don’t Care 7166-062394-4 Select QR I/O DESCRIPTION: (See REGISTER DESCRIPTION for I/O Prgramming.) Data-Bus (D0-D7) (Pin 8-Pin 15). The 8-line data bus is a three-state I/O bus for interfacing with the system bus. CS (Chip Select Input) (Pin 2). A logical "0" at this input enables the chip for Read and Write. RD (Read Input) (Pin 19). A logical "0" at this input enables the OSR and the OL to be read on the data bus. WR (Write Input) (Pin 1) A logical "0" at this input enables the data bus to be written into the control and data registers. C/D (Control/Data Input) (Pin 18). A logical "1" at this input enables a control word to be written into one of the four control registers or the OSR to be read on the I/O bus. A logical "0" enables a data word to be written into the PR, or the OL to be read on the I/O bus. A (Pin 6). Input A is a programmable count input capable of functioning in three different modes, such as up count input, down count input and quadrature input. B (Pin 7). Input B is also a programmable count input that can be programmed to function either as down count input, or count direction control gate for input A, or quadrature input. When B is programmed as count direction control gate, B = 0 enables A as the Up Count input and B = 1 enables A as the Down Count input. When programmed as the direction input, B can switch state only when A is high. ABGT/RCTR (PIN 4). This input can be programmed to function as either inputs A and B enable gate or as external counter reset input. A logical "0" is the active level on this input. Absolute Maximum Ratings: Parameter Symbol Voltage at any input VIN Operating Temperature TA Storage Temperature TSTG Supply Voltage VDD - VSS In non-quadrature mode, if Pin 4 is programmed as A and B enable gate input, it may switch state only when A is high (if A is clock and B is direction) or when both A and B are high (if A and B are clocks. In quadrature mode, if Pin 4 is programmed as A and B enable gate, it may switch state only when either A or B switches. LCTR/LLTC (PIN 3). This input can be programmed to function as the external load command input for either the CNTR or the OL. When programmed as counter load input, the counter is loaded with the data contained in the PR. When programmed as the OL load input, the OL is loaded with data contained in the CNTR. A logical "0" is the active level on this input. CY (Pin 16). This output can be programmed to serve as one of the following: A. CY. Complemented Carry out (active "0"). B. CY. True Carry out (active "1"). C. CYT. Carry Toggle flip-flop out. D. COMP. Comparator out (active "0") BW (Pin 17). This output can be programmed to serve as one of the following: A. BW. Complemented Borrow out (active "0"). B. BW. True Borrow out (active "1"). C. BWT. Borrow Toggle flip-flop out. D. COMPT. Comparator Toggle output. VDD (Pin 5). Supply voltage positive terminal. VSS (Pin 20). Supply voltage negative terminal. Values VSS - 0.3 to VDD + 0 .3 0 to +70 -65 to +150 +7.0 Unit Volts oC oC Volts DC Electrical Characteristics. (All voltages referenced to VSS. TA = 0˚ to 70˚C, VDD = 4.5V to 5.5V, fc = 0, unless otherwise specified) Parameter Supply Voltage Supply Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input Current Output Source Current Output Sink Current Data Bus Off-State Leakage Current 7166-111299-5 Symbol VDD IDD VIL VIH VOL VOH ISRC ISINK - Min. Value 4.5 0 2.0 2.5 - Max.Value 5.5 350 0.8 VDD 0.4 15 Unit Volts µA Volts Volts Volts Volts nA 200 4 - µA mA - 15 nA Remarks Outputs open 4mA Sink 200µA Source Leakage Current VOH = 2.5V VOL = 0.4V - TRANSIENT CHARACTERISTICS (See Timing Diagrams in Fig. 2 thru Fig. 7, VDD = 4.5V to 5.5V, TA = 0˚ to 70˚C, unless otherwise specified) Parameter Clock A/B "Low” Clock A/B "High" Clock A/B Frequency (See NOTE 1) Clock UP/DN Reversal Delay LCTR Positive edge to the next A/B positive or negative edge delay Clock A/B to CY/BW/COMP "low" propagation delay Clock A/B to CY/BW/COMP "high" propagation delay LCTR and LLTC pulse width Clock A/B to CYT, BWT and COMPT "high" propagation delay Clock A/B to CYT, BWT and COMPT "low" progagation delay WR pulse width RD to data out delay (CL = 20pF) CS, RD Terminate to Data-Bus Tri-State Data-Bus set-up time for WR Data-Bus hold time for WR C/D, CS set-up time for RD C/D, CS hold time for RD C/D set-up time for WR C/D hold time for WR CS set-up time for WR CS holdtime for WR Quadrature Mode: Clock A/B Validation delay (See NOTE 2) A and B phase delay Clock A/B frequency CY, BW, COMP pulse width Symbol TCL TCH fc Min.Value 20 30 0 Max.Value No Limit No Limit 20 Unit ns ns MHz TUDD 100 - ns TLC 100 - ns TCBL - 65 ns TCBH - 85 ns TLCW 60 - ns TTFH - 100 ns TTFL - 100 ns TWW TR 60 - 110 ns ns TRT - 30 ns TDS 15 - ns (see Note 3) TDH TCRS TCRH TCWS TCWH TSWS TSWH 30 0 0 15 30 15 0 - ns (see Note 3) ns ns ns (see Note 3) ns (see Note 3) ns (see Note 3) ns (see Note 3) TCQV - 160 ns TPH fCQ TCBW 208 75 1.2 180 ns MHz ns NOTE 1: A) In Divide by N mode, the maximum clock frequency is 10 MHz. B) The maximum frequency for valid CY, BW, CYT, BWT, COMP, COMPT is 10 MHz. NOTE 2: In quadrature mode A/B inputs are filtered and required to be stable for at least TCQV length to be valid. NOTE 3: All WR specifications are critical for proper operation of LS7166 7166-120902-6 TLCW LTCR TLC TCL UP CLK (A) TCH TUDD TCH DN CLK (B) TCL Q0 (Internal) Q1 (Internal) Q2-Q23 (Internal) CNTR=FFFFFD (PR=CNTR) COMP CNTR=FFFFFE CNTR=FFFFFF CNTR=000000 CNTR=0000001 CNTR=000000 CNTR=FFFFFF CNTR=FFFFFE CNTR=FFFFFD (PR=CNTR) NOTE 2 CY BW FIGURE 2 . LOAD COUNTER, UP CLOCK, DOWN CLOCK, COMPARE OUT, CARRY, BORROW NOTE 1: The counter in this example is assumed to be operating in the binary mode. NOTE 2: No COMP output is generated here, although PR = CNTR. COMP output is disabled with a counter load command and enabled with the rising edge of the next clock, thus eliminating invalid COMP outputs whenever the CNTR is loaded from the PR. NOTE 3: When UP Clock is active, the DN Clock should be held "HIGH" and vice versa. UP CLK OR DN CLK TCBH TCBL CY TTFH TTFL CYT TCBL BW TCBH TTFL TTFH BWT TCBL TCBH COMP TTFH COMPT SIGN (INTERNAL) FIGURE 3. CLOCK TO CY/BW OUTPUT PROPAGATION DELAYS 7166-030192-7 TTFL CS, C/D TCRS TCRH RD TRD TRT DATA BUS VALID OUTPUT CS, C/D TWW TCWS TCWH WR TSWH TSWS TDS TDH VALID DATA DATA BUS FIGURE 4. READ/WRITE CYCLES LCTR DN CLK Q0 (INTERNAL) Q1 (INTERNAL) Q2-Q23 (INTERNAL) CNTR=3 =2 =1 =0 =3 =2 =1 =0 CNTR LD (INTERNAL) BW NOTE: EXAMPLE OF DIVIDE BY 4 IN DOWN COUNT MODE FIGURE 5. DIVIDE BY N MODE CNTR LOAD (LCTR or MCR BASED) UP CLK OR DN CLK CY or BW CNTR DISABLED CNTR ENABLED FIGURE 6 . CYCLE ONCE MODE 7166-030494-8 CNTR DISABLED =3 FORWARD REVERSE A TPH TPH B UPCLK (X1) (Internal) TCQV DNCLK (X1) (Internal) UPCLK (X2) (Internal) DNCLK (X2) (Internal) TCQV UPCLK (X4) (Internal) DNCLK (X4) (Internal) UP/DN(OSR Bit 4) CY TCBW TCBW BW FIGURE 7. QUADRATURE MODE INTERNAL CLOCKS 7166-030392-9 (DATA-BUS) I/O BUFFER 8-15 D0 - D7 D0 -D4 D0, D6,D7 (CHIP SELECT INPUT) CS QR 2 (READ INPUT) RD 19 (WRITE INPUT) WR 1 (CONTROL /DATA INPUT) C/D 18 (COUNT INPUT) A 6 (COUNT INPUT) B 7 (AB GATE/LOAD LATCH) ABGT/RCTR 4 INPUT BUFFER AND DECODE LOGIC INTERNAL DATA BUS D0 - D7 (LOAD CTR/LOAD LATCH) LCTR/LLTC OSR D0 - D7 OCCR CONTROL LOGIC ICR STATUS LOGIC D0 - D7 16 CY (CARRY OUT) 17 BW (BORROW OUT) MCR 3 COMPARATOR N1=N2 N1 N2 PR/OL ADDRESS PR0 (+5V) VDD (GND) V SS B0 - B7 PR1 5 20 D0 -D7 B0 - B23 OL0 CNTR B8 - B15 Q0 -Q23 OL1 PR2 B16 - B23 PR/OL ADDRESS FIGURE 8. LS7166 BLOCK DIAGRAM D0 - D7 UP CLOCK DN CLOCK 7166-03392-10 OL2 LS7166 INTERFACE EXAMPLES ADDRESS BUS DECODE CS 7166 A0 8080 C/D DATA BUS D0 - D7 WR WR DBIN RD DATA ADRS/ DATA D0 - D7 ADDRESS 8282 ALE S0 - S2 STB 7166 A0 I/O DECODE RD (Minimum Mode) C/D RD +V 8086/8088 CLK CS DECODE D WR S S74 CK Q R WR IORC 8288 IOWC ALE S0 -S2 8086/8088 (Maximum Mode) ADRS/DATA RD WR 7166 STB ADDRESS DECODE 8282 A0 CS C/D DATA D0 - D7 7166-03392-11 LS7166 INTERFACE EXAMPLES A0 C/D ADDRESS BUS CS DECODE IORQ 7166 Z80 DATA BUS D0 - D7 RD RD WR WR DATA ADRS/ DATA D0 - D7 A0 D AS Q LS373 C/D ADDRESS CS CK DECODE I/O DECODE ST0-ST3 7166 Z8000 R/W RD DS WR DATA BUS ADDRESS D Q D0 - D7 A0 C/D LS373 CK DECODE CS R/W RD +V LDS/UDS S 7166 D 68000 68008 68010 S74 CK R Q WR +V AS S D DTACK CLK CLOCK 7166-03392-12 Q S74 CK R Q S D S74 CK R